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1/*2 * AMD 10Gb Ethernet driver3 *4 * This file is available to you under your choice of the following two5 * licenses:6 *7 * License 1: GPLv28 *9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.10 *11 * This file is free software; you may copy, redistribute and/or modify12 * it under the terms of the GNU General Public License as published by13 * the Free Software Foundation, either version 2 of the License, or (at14 * your option) any later version.15 *16 * This file is distributed in the hope that it will be useful, but17 * WITHOUT ANY WARRANTY; without even the implied warranty of18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU19 * General Public License for more details.20 *21 * You should have received a copy of the GNU General Public License22 * along with this program. If not, see <http://www.gnu.org/licenses/>.23 *24 * This file incorporates work covered by the following copyright and25 * permission notice:26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,28 * Inc. unless otherwise expressly agreed to in writing between Synopsys29 * and you.30 *31 * The Software IS NOT an item of Licensed Software or Licensed Product32 * under any End User Software License Agreement or Agreement for Licensed33 * Product with Synopsys or any supplement thereto. Permission is hereby34 * granted, free of charge, to any person obtaining a copy of this software35 * annotated with this license and the Software, to deal in the Software36 * without restriction, including without limitation the rights to use,37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies38 * of the Software, and to permit persons to whom the Software is furnished39 * to do so, subject to the following conditions:40 *41 * The above copyright notice and this permission notice shall be included42 * in all copies or substantial portions of the Software.43 *44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF54 * THE POSSIBILITY OF SUCH DAMAGE.55 *56 *57 * License 2: Modified BSD58 *59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.60 * All rights reserved.61 *62 * Redistribution and use in source and binary forms, with or without63 * modification, are permitted provided that the following conditions are met:64 * * Redistributions of source code must retain the above copyright65 * notice, this list of conditions and the following disclaimer.66 * * Redistributions in binary form must reproduce the above copyright67 * notice, this list of conditions and the following disclaimer in the68 * documentation and/or other materials provided with the distribution.69 * * Neither the name of Advanced Micro Devices, Inc. nor the70 * names of its contributors may be used to endorse or promote products71 * derived from this software without specific prior written permission.72 *73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.83 *84 * This file incorporates work covered by the following copyright and85 * permission notice:86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,88 * Inc. unless otherwise expressly agreed to in writing between Synopsys89 * and you.90 *91 * The Software IS NOT an item of Licensed Software or Licensed Product92 * under any End User Software License Agreement or Agreement for Licensed93 * Product with Synopsys or any supplement thereto. Permission is hereby94 * granted, free of charge, to any person obtaining a copy of this software95 * annotated with this license and the Software, to deal in the Software96 * without restriction, including without limitation the rights to use,97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies98 * of the Software, and to permit persons to whom the Software is furnished99 * to do so, subject to the following conditions:100 *101 * The above copyright notice and this permission notice shall be included102 * in all copies or substantial portions of the Software.103 *104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF114 * THE POSSIBILITY OF SUCH DAMAGE.115 */116 117#ifndef __XGBE_COMMON_H__118#define __XGBE_COMMON_H__119 120/* DMA register offsets */121#define DMA_MR 0x3000122#define DMA_SBMR 0x3004123#define DMA_ISR 0x3008124#define DMA_AXIARCR 0x3010125#define DMA_AXIAWCR 0x3018126#define DMA_AXIAWARCR 0x301c127#define DMA_DSR0 0x3020128#define DMA_DSR1 0x3024129#define DMA_TXEDMACR 0x3040130#define DMA_RXEDMACR 0x3044131 132/* DMA register entry bit positions and sizes */133#define DMA_ISR_MACIS_INDEX 17134#define DMA_ISR_MACIS_WIDTH 1135#define DMA_ISR_MTLIS_INDEX 16136#define DMA_ISR_MTLIS_WIDTH 1137#define DMA_MR_INTM_INDEX 12138#define DMA_MR_INTM_WIDTH 2139#define DMA_MR_SWR_INDEX 0140#define DMA_MR_SWR_WIDTH 1141#define DMA_RXEDMACR_RDPS_INDEX 0142#define DMA_RXEDMACR_RDPS_WIDTH 3143#define DMA_SBMR_AAL_INDEX 12144#define DMA_SBMR_AAL_WIDTH 1145#define DMA_SBMR_EAME_INDEX 11146#define DMA_SBMR_EAME_WIDTH 1147#define DMA_SBMR_BLEN_INDEX 1148#define DMA_SBMR_BLEN_WIDTH 7149#define DMA_SBMR_RD_OSR_LMT_INDEX 16150#define DMA_SBMR_RD_OSR_LMT_WIDTH 6151#define DMA_SBMR_UNDEF_INDEX 0152#define DMA_SBMR_UNDEF_WIDTH 1153#define DMA_SBMR_WR_OSR_LMT_INDEX 24154#define DMA_SBMR_WR_OSR_LMT_WIDTH 6155#define DMA_TXEDMACR_TDPS_INDEX 0156#define DMA_TXEDMACR_TDPS_WIDTH 3157 158/* DMA register values */159#define DMA_SBMR_BLEN_256 256160#define DMA_SBMR_BLEN_128 128161#define DMA_SBMR_BLEN_64 64162#define DMA_SBMR_BLEN_32 32163#define DMA_SBMR_BLEN_16 16164#define DMA_SBMR_BLEN_8 8165#define DMA_SBMR_BLEN_4 4166#define DMA_DSR_RPS_WIDTH 4167#define DMA_DSR_TPS_WIDTH 4168#define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)169#define DMA_DSR0_RPS_START 8170#define DMA_DSR0_TPS_START 12171#define DMA_DSRX_FIRST_QUEUE 3172#define DMA_DSRX_INC 4173#define DMA_DSRX_QPR 4174#define DMA_DSRX_RPS_START 0175#define DMA_DSRX_TPS_START 4176#define DMA_TPS_STOPPED 0x00177#define DMA_TPS_SUSPENDED 0x06178 179/* DMA channel register offsets180 * Multiple channels can be active. The first channel has registers181 * that begin at 0x3100. Each subsequent channel has registers that182 * are accessed using an offset of 0x80 from the previous channel.183 */184#define DMA_CH_BASE 0x3100185#define DMA_CH_INC 0x80186 187#define DMA_CH_CR 0x00188#define DMA_CH_TCR 0x04189#define DMA_CH_RCR 0x08190#define DMA_CH_TDLR_HI 0x10191#define DMA_CH_TDLR_LO 0x14192#define DMA_CH_RDLR_HI 0x18193#define DMA_CH_RDLR_LO 0x1c194#define DMA_CH_TDTR_LO 0x24195#define DMA_CH_RDTR_LO 0x2c196#define DMA_CH_TDRLR 0x30197#define DMA_CH_RDRLR 0x34198#define DMA_CH_IER 0x38199#define DMA_CH_RIWT 0x3c200#define DMA_CH_CATDR_LO 0x44201#define DMA_CH_CARDR_LO 0x4c202#define DMA_CH_CATBR_HI 0x50203#define DMA_CH_CATBR_LO 0x54204#define DMA_CH_CARBR_HI 0x58205#define DMA_CH_CARBR_LO 0x5c206#define DMA_CH_SR 0x60207 208/* DMA channel register entry bit positions and sizes */209#define DMA_CH_CR_PBLX8_INDEX 16210#define DMA_CH_CR_PBLX8_WIDTH 1211#define DMA_CH_CR_SPH_INDEX 24212#define DMA_CH_CR_SPH_WIDTH 1213#define DMA_CH_IER_AIE20_INDEX 15214#define DMA_CH_IER_AIE20_WIDTH 1215#define DMA_CH_IER_AIE_INDEX 14216#define DMA_CH_IER_AIE_WIDTH 1217#define DMA_CH_IER_FBEE_INDEX 12218#define DMA_CH_IER_FBEE_WIDTH 1219#define DMA_CH_IER_NIE20_INDEX 16220#define DMA_CH_IER_NIE20_WIDTH 1221#define DMA_CH_IER_NIE_INDEX 15222#define DMA_CH_IER_NIE_WIDTH 1223#define DMA_CH_IER_RBUE_INDEX 7224#define DMA_CH_IER_RBUE_WIDTH 1225#define DMA_CH_IER_RIE_INDEX 6226#define DMA_CH_IER_RIE_WIDTH 1227#define DMA_CH_IER_RSE_INDEX 8228#define DMA_CH_IER_RSE_WIDTH 1229#define DMA_CH_IER_TBUE_INDEX 2230#define DMA_CH_IER_TBUE_WIDTH 1231#define DMA_CH_IER_TIE_INDEX 0232#define DMA_CH_IER_TIE_WIDTH 1233#define DMA_CH_IER_TXSE_INDEX 1234#define DMA_CH_IER_TXSE_WIDTH 1235#define DMA_CH_RCR_PBL_INDEX 16236#define DMA_CH_RCR_PBL_WIDTH 6237#define DMA_CH_RCR_RBSZ_INDEX 1238#define DMA_CH_RCR_RBSZ_WIDTH 14239#define DMA_CH_RCR_SR_INDEX 0240#define DMA_CH_RCR_SR_WIDTH 1241#define DMA_CH_RIWT_RWT_INDEX 0242#define DMA_CH_RIWT_RWT_WIDTH 8243#define DMA_CH_SR_FBE_INDEX 12244#define DMA_CH_SR_FBE_WIDTH 1245#define DMA_CH_SR_RBU_INDEX 7246#define DMA_CH_SR_RBU_WIDTH 1247#define DMA_CH_SR_RI_INDEX 6248#define DMA_CH_SR_RI_WIDTH 1249#define DMA_CH_SR_RPS_INDEX 8250#define DMA_CH_SR_RPS_WIDTH 1251#define DMA_CH_SR_TBU_INDEX 2252#define DMA_CH_SR_TBU_WIDTH 1253#define DMA_CH_SR_TI_INDEX 0254#define DMA_CH_SR_TI_WIDTH 1255#define DMA_CH_SR_TPS_INDEX 1256#define DMA_CH_SR_TPS_WIDTH 1257#define DMA_CH_TCR_OSP_INDEX 4258#define DMA_CH_TCR_OSP_WIDTH 1259#define DMA_CH_TCR_PBL_INDEX 16260#define DMA_CH_TCR_PBL_WIDTH 6261#define DMA_CH_TCR_ST_INDEX 0262#define DMA_CH_TCR_ST_WIDTH 1263#define DMA_CH_TCR_TSE_INDEX 12264#define DMA_CH_TCR_TSE_WIDTH 1265 266/* DMA channel register values */267#define DMA_OSP_DISABLE 0x00268#define DMA_OSP_ENABLE 0x01269#define DMA_PBL_1 1270#define DMA_PBL_2 2271#define DMA_PBL_4 4272#define DMA_PBL_8 8273#define DMA_PBL_16 16274#define DMA_PBL_32 32275#define DMA_PBL_64 64 /* 8 x 8 */276#define DMA_PBL_128 128 /* 8 x 16 */277#define DMA_PBL_256 256 /* 8 x 32 */278#define DMA_PBL_X8_DISABLE 0x00279#define DMA_PBL_X8_ENABLE 0x01280 281/* MAC register offsets */282#define MAC_TCR 0x0000283#define MAC_RCR 0x0004284#define MAC_PFR 0x0008285#define MAC_WTR 0x000c286#define MAC_HTR0 0x0010287#define MAC_VLANTR 0x0050288#define MAC_VLANHTR 0x0058289#define MAC_VLANIR 0x0060290#define MAC_IVLANIR 0x0064291#define MAC_RETMR 0x006c292#define MAC_Q0TFCR 0x0070293#define MAC_RFCR 0x0090294#define MAC_RQC0R 0x00a0295#define MAC_RQC1R 0x00a4296#define MAC_RQC2R 0x00a8297#define MAC_RQC3R 0x00ac298#define MAC_ISR 0x00b0299#define MAC_IER 0x00b4300#define MAC_RTSR 0x00b8301#define MAC_PMTCSR 0x00c0302#define MAC_RWKPFR 0x00c4303#define MAC_LPICSR 0x00d0304#define MAC_LPITCR 0x00d4305#define MAC_TIR 0x00e0306#define MAC_VR 0x0110307#define MAC_DR 0x0114308#define MAC_HWF0R 0x011c309#define MAC_HWF1R 0x0120310#define MAC_HWF2R 0x0124311#define MAC_MDIOSCAR 0x0200312#define MAC_MDIOSCCDR 0x0204313#define MAC_MDIOISR 0x0214314#define MAC_MDIOIER 0x0218315#define MAC_MDIOCL22R 0x0220316#define MAC_GPIOCR 0x0278317#define MAC_GPIOSR 0x027c318#define MAC_MACA0HR 0x0300319#define MAC_MACA0LR 0x0304320#define MAC_MACA1HR 0x0308321#define MAC_MACA1LR 0x030c322#define MAC_RSSCR 0x0c80323#define MAC_RSSAR 0x0c88324#define MAC_RSSDR 0x0c8c325#define MAC_TSCR 0x0d00326#define MAC_SSIR 0x0d04327#define MAC_STSR 0x0d08328#define MAC_STNR 0x0d0c329#define MAC_STSUR 0x0d10330#define MAC_STNUR 0x0d14331#define MAC_TSAR 0x0d18332#define MAC_TSSR 0x0d20333#define MAC_TXSNR 0x0d30334#define MAC_TXSSR 0x0d34335 336#define MAC_QTFCR_INC 4337#define MAC_MACA_INC 4338#define MAC_HTR_INC 4339 340#define MAC_RQC2_INC 4341#define MAC_RQC2_Q_PER_REG 4342 343/* MAC register entry bit positions and sizes */344#define MAC_HWF0R_ADDMACADRSEL_INDEX 18345#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5346#define MAC_HWF0R_ARPOFFSEL_INDEX 9347#define MAC_HWF0R_ARPOFFSEL_WIDTH 1348#define MAC_HWF0R_EEESEL_INDEX 13349#define MAC_HWF0R_EEESEL_WIDTH 1350#define MAC_HWF0R_GMIISEL_INDEX 1351#define MAC_HWF0R_GMIISEL_WIDTH 1352#define MAC_HWF0R_MGKSEL_INDEX 7353#define MAC_HWF0R_MGKSEL_WIDTH 1354#define MAC_HWF0R_MMCSEL_INDEX 8355#define MAC_HWF0R_MMCSEL_WIDTH 1356#define MAC_HWF0R_RWKSEL_INDEX 6357#define MAC_HWF0R_RWKSEL_WIDTH 1358#define MAC_HWF0R_RXCOESEL_INDEX 16359#define MAC_HWF0R_RXCOESEL_WIDTH 1360#define MAC_HWF0R_SAVLANINS_INDEX 27361#define MAC_HWF0R_SAVLANINS_WIDTH 1362#define MAC_HWF0R_SMASEL_INDEX 5363#define MAC_HWF0R_SMASEL_WIDTH 1364#define MAC_HWF0R_TSSEL_INDEX 12365#define MAC_HWF0R_TSSEL_WIDTH 1366#define MAC_HWF0R_TSSTSSEL_INDEX 25367#define MAC_HWF0R_TSSTSSEL_WIDTH 2368#define MAC_HWF0R_TXCOESEL_INDEX 14369#define MAC_HWF0R_TXCOESEL_WIDTH 1370#define MAC_HWF0R_VLHASH_INDEX 4371#define MAC_HWF0R_VLHASH_WIDTH 1372#define MAC_HWF0R_VXN_INDEX 29373#define MAC_HWF0R_VXN_WIDTH 1374#define MAC_HWF1R_ADDR64_INDEX 14375#define MAC_HWF1R_ADDR64_WIDTH 2376#define MAC_HWF1R_ADVTHWORD_INDEX 13377#define MAC_HWF1R_ADVTHWORD_WIDTH 1378#define MAC_HWF1R_DBGMEMA_INDEX 19379#define MAC_HWF1R_DBGMEMA_WIDTH 1380#define MAC_HWF1R_DCBEN_INDEX 16381#define MAC_HWF1R_DCBEN_WIDTH 1382#define MAC_HWF1R_HASHTBLSZ_INDEX 24383#define MAC_HWF1R_HASHTBLSZ_WIDTH 3384#define MAC_HWF1R_L3L4FNUM_INDEX 27385#define MAC_HWF1R_L3L4FNUM_WIDTH 4386#define MAC_HWF1R_NUMTC_INDEX 21387#define MAC_HWF1R_NUMTC_WIDTH 3388#define MAC_HWF1R_RSSEN_INDEX 20389#define MAC_HWF1R_RSSEN_WIDTH 1390#define MAC_HWF1R_RXFIFOSIZE_INDEX 0391#define MAC_HWF1R_RXFIFOSIZE_WIDTH 5392#define MAC_HWF1R_SPHEN_INDEX 17393#define MAC_HWF1R_SPHEN_WIDTH 1394#define MAC_HWF1R_TSOEN_INDEX 18395#define MAC_HWF1R_TSOEN_WIDTH 1396#define MAC_HWF1R_TXFIFOSIZE_INDEX 6397#define MAC_HWF1R_TXFIFOSIZE_WIDTH 5398#define MAC_HWF2R_AUXSNAPNUM_INDEX 28399#define MAC_HWF2R_AUXSNAPNUM_WIDTH 3400#define MAC_HWF2R_PPSOUTNUM_INDEX 24401#define MAC_HWF2R_PPSOUTNUM_WIDTH 3402#define MAC_HWF2R_RXCHCNT_INDEX 12403#define MAC_HWF2R_RXCHCNT_WIDTH 4404#define MAC_HWF2R_RXQCNT_INDEX 0405#define MAC_HWF2R_RXQCNT_WIDTH 4406#define MAC_HWF2R_TXCHCNT_INDEX 18407#define MAC_HWF2R_TXCHCNT_WIDTH 4408#define MAC_HWF2R_TXQCNT_INDEX 6409#define MAC_HWF2R_TXQCNT_WIDTH 4410#define MAC_IER_TSIE_INDEX 12411#define MAC_IER_TSIE_WIDTH 1412#define MAC_ISR_MMCRXIS_INDEX 9413#define MAC_ISR_MMCRXIS_WIDTH 1414#define MAC_ISR_MMCTXIS_INDEX 10415#define MAC_ISR_MMCTXIS_WIDTH 1416#define MAC_ISR_PMTIS_INDEX 4417#define MAC_ISR_PMTIS_WIDTH 1418#define MAC_ISR_SMI_INDEX 1419#define MAC_ISR_SMI_WIDTH 1420#define MAC_ISR_TSIS_INDEX 12421#define MAC_ISR_TSIS_WIDTH 1422#define MAC_MACA1HR_AE_INDEX 31423#define MAC_MACA1HR_AE_WIDTH 1424#define MAC_MDIOIER_SNGLCOMPIE_INDEX 12425#define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1426#define MAC_MDIOISR_SNGLCOMPINT_INDEX 12427#define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1428#define MAC_MDIOSCAR_DA_INDEX 21429#define MAC_MDIOSCAR_DA_WIDTH 5430#define MAC_MDIOSCAR_PA_INDEX 16431#define MAC_MDIOSCAR_PA_WIDTH 5432#define MAC_MDIOSCAR_RA_INDEX 0433#define MAC_MDIOSCAR_RA_WIDTH 16434#define MAC_MDIOSCCDR_BUSY_INDEX 22435#define MAC_MDIOSCCDR_BUSY_WIDTH 1436#define MAC_MDIOSCCDR_CMD_INDEX 16437#define MAC_MDIOSCCDR_CMD_WIDTH 2438#define MAC_MDIOSCCDR_CR_INDEX 19439#define MAC_MDIOSCCDR_CR_WIDTH 3440#define MAC_MDIOSCCDR_DATA_INDEX 0441#define MAC_MDIOSCCDR_DATA_WIDTH 16442#define MAC_MDIOSCCDR_SADDR_INDEX 18443#define MAC_MDIOSCCDR_SADDR_WIDTH 1444#define MAC_PFR_HMC_INDEX 2445#define MAC_PFR_HMC_WIDTH 1446#define MAC_PFR_HPF_INDEX 10447#define MAC_PFR_HPF_WIDTH 1448#define MAC_PFR_HUC_INDEX 1449#define MAC_PFR_HUC_WIDTH 1450#define MAC_PFR_PM_INDEX 4451#define MAC_PFR_PM_WIDTH 1452#define MAC_PFR_PR_INDEX 0453#define MAC_PFR_PR_WIDTH 1454#define MAC_PFR_VTFE_INDEX 16455#define MAC_PFR_VTFE_WIDTH 1456#define MAC_PFR_VUCC_INDEX 22457#define MAC_PFR_VUCC_WIDTH 1458#define MAC_PMTCSR_MGKPKTEN_INDEX 1459#define MAC_PMTCSR_MGKPKTEN_WIDTH 1460#define MAC_PMTCSR_PWRDWN_INDEX 0461#define MAC_PMTCSR_PWRDWN_WIDTH 1462#define MAC_PMTCSR_RWKFILTRST_INDEX 31463#define MAC_PMTCSR_RWKFILTRST_WIDTH 1464#define MAC_PMTCSR_RWKPKTEN_INDEX 2465#define MAC_PMTCSR_RWKPKTEN_WIDTH 1466#define MAC_Q0TFCR_PT_INDEX 16467#define MAC_Q0TFCR_PT_WIDTH 16468#define MAC_Q0TFCR_TFE_INDEX 1469#define MAC_Q0TFCR_TFE_WIDTH 1470#define MAC_RCR_ACS_INDEX 1471#define MAC_RCR_ACS_WIDTH 1472#define MAC_RCR_CST_INDEX 2473#define MAC_RCR_CST_WIDTH 1474#define MAC_RCR_DCRCC_INDEX 3475#define MAC_RCR_DCRCC_WIDTH 1476#define MAC_RCR_HDSMS_INDEX 12477#define MAC_RCR_HDSMS_WIDTH 3478#define MAC_RCR_IPC_INDEX 9479#define MAC_RCR_IPC_WIDTH 1480#define MAC_RCR_JE_INDEX 8481#define MAC_RCR_JE_WIDTH 1482#define MAC_RCR_LM_INDEX 10483#define MAC_RCR_LM_WIDTH 1484#define MAC_RCR_RE_INDEX 0485#define MAC_RCR_RE_WIDTH 1486#define MAC_RFCR_PFCE_INDEX 8487#define MAC_RFCR_PFCE_WIDTH 1488#define MAC_RFCR_RFE_INDEX 0489#define MAC_RFCR_RFE_WIDTH 1490#define MAC_RFCR_UP_INDEX 1491#define MAC_RFCR_UP_WIDTH 1492#define MAC_RQC0R_RXQ0EN_INDEX 0493#define MAC_RQC0R_RXQ0EN_WIDTH 2494#define MAC_RSSAR_ADDRT_INDEX 2495#define MAC_RSSAR_ADDRT_WIDTH 1496#define MAC_RSSAR_CT_INDEX 1497#define MAC_RSSAR_CT_WIDTH 1498#define MAC_RSSAR_OB_INDEX 0499#define MAC_RSSAR_OB_WIDTH 1500#define MAC_RSSAR_RSSIA_INDEX 8501#define MAC_RSSAR_RSSIA_WIDTH 8502#define MAC_RSSCR_IP2TE_INDEX 1503#define MAC_RSSCR_IP2TE_WIDTH 1504#define MAC_RSSCR_RSSE_INDEX 0505#define MAC_RSSCR_RSSE_WIDTH 1506#define MAC_RSSCR_TCP4TE_INDEX 2507#define MAC_RSSCR_TCP4TE_WIDTH 1508#define MAC_RSSCR_UDP4TE_INDEX 3509#define MAC_RSSCR_UDP4TE_WIDTH 1510#define MAC_RSSDR_DMCH_INDEX 0511#define MAC_RSSDR_DMCH_WIDTH 4512#define MAC_SSIR_SNSINC_INDEX 8513#define MAC_SSIR_SNSINC_WIDTH 8514#define MAC_SSIR_SSINC_INDEX 16515#define MAC_SSIR_SSINC_WIDTH 8516#define MAC_TCR_SS_INDEX 29517#define MAC_TCR_SS_WIDTH 2518#define MAC_TCR_TE_INDEX 0519#define MAC_TCR_TE_WIDTH 1520#define MAC_TCR_VNE_INDEX 24521#define MAC_TCR_VNE_WIDTH 1522#define MAC_TCR_VNM_INDEX 25523#define MAC_TCR_VNM_WIDTH 1524#define MAC_TIR_TNID_INDEX 0525#define MAC_TIR_TNID_WIDTH 16526#define MAC_TSCR_AV8021ASMEN_INDEX 28527#define MAC_TSCR_AV8021ASMEN_WIDTH 1528#define MAC_TSCR_SNAPTYPSEL_INDEX 16529#define MAC_TSCR_SNAPTYPSEL_WIDTH 2530#define MAC_TSCR_TSADDREG_INDEX 5531#define MAC_TSCR_TSADDREG_WIDTH 1532#define MAC_TSCR_TSCFUPDT_INDEX 1533#define MAC_TSCR_TSCFUPDT_WIDTH 1534#define MAC_TSCR_TSCTRLSSR_INDEX 9535#define MAC_TSCR_TSCTRLSSR_WIDTH 1536#define MAC_TSCR_TSENA_INDEX 0537#define MAC_TSCR_TSENA_WIDTH 1538#define MAC_TSCR_TSENALL_INDEX 8539#define MAC_TSCR_TSENALL_WIDTH 1540#define MAC_TSCR_TSEVNTENA_INDEX 14541#define MAC_TSCR_TSEVNTENA_WIDTH 1542#define MAC_TSCR_TSINIT_INDEX 2543#define MAC_TSCR_TSINIT_WIDTH 1544#define MAC_TSCR_TSIPENA_INDEX 11545#define MAC_TSCR_TSIPENA_WIDTH 1546#define MAC_TSCR_TSIPV4ENA_INDEX 13547#define MAC_TSCR_TSIPV4ENA_WIDTH 1548#define MAC_TSCR_TSIPV6ENA_INDEX 12549#define MAC_TSCR_TSIPV6ENA_WIDTH 1550#define MAC_TSCR_TSMSTRENA_INDEX 15551#define MAC_TSCR_TSMSTRENA_WIDTH 1552#define MAC_TSCR_TSVER2ENA_INDEX 10553#define MAC_TSCR_TSVER2ENA_WIDTH 1554#define MAC_TSCR_TXTSSTSM_INDEX 24555#define MAC_TSCR_TXTSSTSM_WIDTH 1556#define MAC_TSSR_TXTSC_INDEX 15557#define MAC_TSSR_TXTSC_WIDTH 1558#define MAC_TXSNR_TXTSSTSMIS_INDEX 31559#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1560#define MAC_VLANHTR_VLHT_INDEX 0561#define MAC_VLANHTR_VLHT_WIDTH 16562#define MAC_VLANIR_VLTI_INDEX 20563#define MAC_VLANIR_VLTI_WIDTH 1564#define MAC_VLANIR_CSVL_INDEX 19565#define MAC_VLANIR_CSVL_WIDTH 1566#define MAC_VLANTR_DOVLTC_INDEX 20567#define MAC_VLANTR_DOVLTC_WIDTH 1568#define MAC_VLANTR_ERSVLM_INDEX 19569#define MAC_VLANTR_ERSVLM_WIDTH 1570#define MAC_VLANTR_ESVL_INDEX 18571#define MAC_VLANTR_ESVL_WIDTH 1572#define MAC_VLANTR_ETV_INDEX 16573#define MAC_VLANTR_ETV_WIDTH 1574#define MAC_VLANTR_EVLS_INDEX 21575#define MAC_VLANTR_EVLS_WIDTH 2576#define MAC_VLANTR_EVLRXS_INDEX 24577#define MAC_VLANTR_EVLRXS_WIDTH 1578#define MAC_VLANTR_VL_INDEX 0579#define MAC_VLANTR_VL_WIDTH 16580#define MAC_VLANTR_VTHM_INDEX 25581#define MAC_VLANTR_VTHM_WIDTH 1582#define MAC_VLANTR_VTIM_INDEX 17583#define MAC_VLANTR_VTIM_WIDTH 1584#define MAC_VR_DEVID_INDEX 8585#define MAC_VR_DEVID_WIDTH 8586#define MAC_VR_SNPSVER_INDEX 0587#define MAC_VR_SNPSVER_WIDTH 8588#define MAC_VR_USERVER_INDEX 16589#define MAC_VR_USERVER_WIDTH 8590 591/* MMC register offsets */592#define MMC_CR 0x0800593#define MMC_RISR 0x0804594#define MMC_TISR 0x0808595#define MMC_RIER 0x080c596#define MMC_TIER 0x0810597#define MMC_TXOCTETCOUNT_GB_LO 0x0814598#define MMC_TXOCTETCOUNT_GB_HI 0x0818599#define MMC_TXFRAMECOUNT_GB_LO 0x081c600#define MMC_TXFRAMECOUNT_GB_HI 0x0820601#define MMC_TXBROADCASTFRAMES_G_LO 0x0824602#define MMC_TXBROADCASTFRAMES_G_HI 0x0828603#define MMC_TXMULTICASTFRAMES_G_LO 0x082c604#define MMC_TXMULTICASTFRAMES_G_HI 0x0830605#define MMC_TX64OCTETS_GB_LO 0x0834606#define MMC_TX64OCTETS_GB_HI 0x0838607#define MMC_TX65TO127OCTETS_GB_LO 0x083c608#define MMC_TX65TO127OCTETS_GB_HI 0x0840609#define MMC_TX128TO255OCTETS_GB_LO 0x0844610#define MMC_TX128TO255OCTETS_GB_HI 0x0848611#define MMC_TX256TO511OCTETS_GB_LO 0x084c612#define MMC_TX256TO511OCTETS_GB_HI 0x0850613#define MMC_TX512TO1023OCTETS_GB_LO 0x0854614#define MMC_TX512TO1023OCTETS_GB_HI 0x0858615#define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c616#define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860617#define MMC_TXUNICASTFRAMES_GB_LO 0x0864618#define MMC_TXUNICASTFRAMES_GB_HI 0x0868619#define MMC_TXMULTICASTFRAMES_GB_LO 0x086c620#define MMC_TXMULTICASTFRAMES_GB_HI 0x0870621#define MMC_TXBROADCASTFRAMES_GB_LO 0x0874622#define MMC_TXBROADCASTFRAMES_GB_HI 0x0878623#define MMC_TXUNDERFLOWERROR_LO 0x087c624#define MMC_TXUNDERFLOWERROR_HI 0x0880625#define MMC_TXOCTETCOUNT_G_LO 0x0884626#define MMC_TXOCTETCOUNT_G_HI 0x0888627#define MMC_TXFRAMECOUNT_G_LO 0x088c628#define MMC_TXFRAMECOUNT_G_HI 0x0890629#define MMC_TXPAUSEFRAMES_LO 0x0894630#define MMC_TXPAUSEFRAMES_HI 0x0898631#define MMC_TXVLANFRAMES_G_LO 0x089c632#define MMC_TXVLANFRAMES_G_HI 0x08a0633#define MMC_RXFRAMECOUNT_GB_LO 0x0900634#define MMC_RXFRAMECOUNT_GB_HI 0x0904635#define MMC_RXOCTETCOUNT_GB_LO 0x0908636#define MMC_RXOCTETCOUNT_GB_HI 0x090c637#define MMC_RXOCTETCOUNT_G_LO 0x0910638#define MMC_RXOCTETCOUNT_G_HI 0x0914639#define MMC_RXBROADCASTFRAMES_G_LO 0x0918640#define MMC_RXBROADCASTFRAMES_G_HI 0x091c641#define MMC_RXMULTICASTFRAMES_G_LO 0x0920642#define MMC_RXMULTICASTFRAMES_G_HI 0x0924643#define MMC_RXCRCERROR_LO 0x0928644#define MMC_RXCRCERROR_HI 0x092c645#define MMC_RXRUNTERROR 0x0930646#define MMC_RXJABBERERROR 0x0934647#define MMC_RXUNDERSIZE_G 0x0938648#define MMC_RXOVERSIZE_G 0x093c649#define MMC_RX64OCTETS_GB_LO 0x0940650#define MMC_RX64OCTETS_GB_HI 0x0944651#define MMC_RX65TO127OCTETS_GB_LO 0x0948652#define MMC_RX65TO127OCTETS_GB_HI 0x094c653#define MMC_RX128TO255OCTETS_GB_LO 0x0950654#define MMC_RX128TO255OCTETS_GB_HI 0x0954655#define MMC_RX256TO511OCTETS_GB_LO 0x0958656#define MMC_RX256TO511OCTETS_GB_HI 0x095c657#define MMC_RX512TO1023OCTETS_GB_LO 0x0960658#define MMC_RX512TO1023OCTETS_GB_HI 0x0964659#define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968660#define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c661#define MMC_RXUNICASTFRAMES_G_LO 0x0970662#define MMC_RXUNICASTFRAMES_G_HI 0x0974663#define MMC_RXLENGTHERROR_LO 0x0978664#define MMC_RXLENGTHERROR_HI 0x097c665#define MMC_RXOUTOFRANGETYPE_LO 0x0980666#define MMC_RXOUTOFRANGETYPE_HI 0x0984667#define MMC_RXPAUSEFRAMES_LO 0x0988668#define MMC_RXPAUSEFRAMES_HI 0x098c669#define MMC_RXFIFOOVERFLOW_LO 0x0990670#define MMC_RXFIFOOVERFLOW_HI 0x0994671#define MMC_RXVLANFRAMES_GB_LO 0x0998672#define MMC_RXVLANFRAMES_GB_HI 0x099c673#define MMC_RXWATCHDOGERROR 0x09a0674 675/* MMC register entry bit positions and sizes */676#define MMC_CR_CR_INDEX 0677#define MMC_CR_CR_WIDTH 1678#define MMC_CR_CSR_INDEX 1679#define MMC_CR_CSR_WIDTH 1680#define MMC_CR_ROR_INDEX 2681#define MMC_CR_ROR_WIDTH 1682#define MMC_CR_MCF_INDEX 3683#define MMC_CR_MCF_WIDTH 1684#define MMC_CR_MCT_INDEX 4685#define MMC_CR_MCT_WIDTH 2686#define MMC_RIER_ALL_INTERRUPTS_INDEX 0687#define MMC_RIER_ALL_INTERRUPTS_WIDTH 23688#define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0689#define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1690#define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1691#define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1692#define MMC_RISR_RXOCTETCOUNT_G_INDEX 2693#define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1694#define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3695#define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1696#define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4697#define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1698#define MMC_RISR_RXCRCERROR_INDEX 5699#define MMC_RISR_RXCRCERROR_WIDTH 1700#define MMC_RISR_RXRUNTERROR_INDEX 6701#define MMC_RISR_RXRUNTERROR_WIDTH 1702#define MMC_RISR_RXJABBERERROR_INDEX 7703#define MMC_RISR_RXJABBERERROR_WIDTH 1704#define MMC_RISR_RXUNDERSIZE_G_INDEX 8705#define MMC_RISR_RXUNDERSIZE_G_WIDTH 1706#define MMC_RISR_RXOVERSIZE_G_INDEX 9707#define MMC_RISR_RXOVERSIZE_G_WIDTH 1708#define MMC_RISR_RX64OCTETS_GB_INDEX 10709#define MMC_RISR_RX64OCTETS_GB_WIDTH 1710#define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11711#define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1712#define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12713#define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1714#define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13715#define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1716#define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14717#define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1718#define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15719#define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1720#define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16721#define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1722#define MMC_RISR_RXLENGTHERROR_INDEX 17723#define MMC_RISR_RXLENGTHERROR_WIDTH 1724#define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18725#define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1726#define MMC_RISR_RXPAUSEFRAMES_INDEX 19727#define MMC_RISR_RXPAUSEFRAMES_WIDTH 1728#define MMC_RISR_RXFIFOOVERFLOW_INDEX 20729#define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1730#define MMC_RISR_RXVLANFRAMES_GB_INDEX 21731#define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1732#define MMC_RISR_RXWATCHDOGERROR_INDEX 22733#define MMC_RISR_RXWATCHDOGERROR_WIDTH 1734#define MMC_TIER_ALL_INTERRUPTS_INDEX 0735#define MMC_TIER_ALL_INTERRUPTS_WIDTH 18736#define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0737#define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1738#define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1739#define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1740#define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2741#define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1742#define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3743#define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1744#define MMC_TISR_TX64OCTETS_GB_INDEX 4745#define MMC_TISR_TX64OCTETS_GB_WIDTH 1746#define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5747#define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1748#define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6749#define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1750#define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7751#define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1752#define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8753#define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1754#define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9755#define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1756#define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10757#define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1758#define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11759#define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1760#define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12761#define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1762#define MMC_TISR_TXUNDERFLOWERROR_INDEX 13763#define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1764#define MMC_TISR_TXOCTETCOUNT_G_INDEX 14765#define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1766#define MMC_TISR_TXFRAMECOUNT_G_INDEX 15767#define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1768#define MMC_TISR_TXPAUSEFRAMES_INDEX 16769#define MMC_TISR_TXPAUSEFRAMES_WIDTH 1770#define MMC_TISR_TXVLANFRAMES_G_INDEX 17771#define MMC_TISR_TXVLANFRAMES_G_WIDTH 1772 773/* MTL register offsets */774#define MTL_OMR 0x1000775#define MTL_FDCR 0x1008776#define MTL_FDSR 0x100c777#define MTL_FDDR 0x1010778#define MTL_ISR 0x1020779#define MTL_RQDCM0R 0x1030780#define MTL_TCPM0R 0x1040781#define MTL_TCPM1R 0x1044782 783#define MTL_RQDCM_INC 4784#define MTL_RQDCM_Q_PER_REG 4785#define MTL_TCPM_INC 4786#define MTL_TCPM_TC_PER_REG 4787 788/* MTL register entry bit positions and sizes */789#define MTL_OMR_ETSALG_INDEX 5790#define MTL_OMR_ETSALG_WIDTH 2791#define MTL_OMR_RAA_INDEX 2792#define MTL_OMR_RAA_WIDTH 1793 794/* MTL queue register offsets795 * Multiple queues can be active. The first queue has registers796 * that begin at 0x1100. Each subsequent queue has registers that797 * are accessed using an offset of 0x80 from the previous queue.798 */799#define MTL_Q_BASE 0x1100800#define MTL_Q_INC 0x80801 802#define MTL_Q_TQOMR 0x00803#define MTL_Q_TQUR 0x04804#define MTL_Q_TQDR 0x08805#define MTL_Q_RQOMR 0x40806#define MTL_Q_RQMPOCR 0x44807#define MTL_Q_RQDR 0x48808#define MTL_Q_RQFCR 0x50809#define MTL_Q_IER 0x70810#define MTL_Q_ISR 0x74811 812/* MTL queue register entry bit positions and sizes */813#define MTL_Q_RQDR_PRXQ_INDEX 16814#define MTL_Q_RQDR_PRXQ_WIDTH 14815#define MTL_Q_RQDR_RXQSTS_INDEX 4816#define MTL_Q_RQDR_RXQSTS_WIDTH 2817#define MTL_Q_RQFCR_RFA_INDEX 1818#define MTL_Q_RQFCR_RFA_WIDTH 6819#define MTL_Q_RQFCR_RFD_INDEX 17820#define MTL_Q_RQFCR_RFD_WIDTH 6821#define MTL_Q_RQOMR_EHFC_INDEX 7822#define MTL_Q_RQOMR_EHFC_WIDTH 1823#define MTL_Q_RQOMR_RQS_INDEX 16824#define MTL_Q_RQOMR_RQS_WIDTH 9825#define MTL_Q_RQOMR_RSF_INDEX 5826#define MTL_Q_RQOMR_RSF_WIDTH 1827#define MTL_Q_RQOMR_RTC_INDEX 0828#define MTL_Q_RQOMR_RTC_WIDTH 2829#define MTL_Q_TQDR_TRCSTS_INDEX 1830#define MTL_Q_TQDR_TRCSTS_WIDTH 2831#define MTL_Q_TQDR_TXQSTS_INDEX 4832#define MTL_Q_TQDR_TXQSTS_WIDTH 1833#define MTL_Q_TQOMR_FTQ_INDEX 0834#define MTL_Q_TQOMR_FTQ_WIDTH 1835#define MTL_Q_TQOMR_Q2TCMAP_INDEX 8836#define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3837#define MTL_Q_TQOMR_TQS_INDEX 16838#define MTL_Q_TQOMR_TQS_WIDTH 10839#define MTL_Q_TQOMR_TSF_INDEX 1840#define MTL_Q_TQOMR_TSF_WIDTH 1841#define MTL_Q_TQOMR_TTC_INDEX 4842#define MTL_Q_TQOMR_TTC_WIDTH 3843#define MTL_Q_TQOMR_TXQEN_INDEX 2844#define MTL_Q_TQOMR_TXQEN_WIDTH 2845 846/* MTL queue register value */847#define MTL_RSF_DISABLE 0x00848#define MTL_RSF_ENABLE 0x01849#define MTL_TSF_DISABLE 0x00850#define MTL_TSF_ENABLE 0x01851 852#define MTL_RX_THRESHOLD_64 0x00853#define MTL_RX_THRESHOLD_96 0x02854#define MTL_RX_THRESHOLD_128 0x03855#define MTL_TX_THRESHOLD_32 0x01856#define MTL_TX_THRESHOLD_64 0x00857#define MTL_TX_THRESHOLD_96 0x02858#define MTL_TX_THRESHOLD_128 0x03859#define MTL_TX_THRESHOLD_192 0x04860#define MTL_TX_THRESHOLD_256 0x05861#define MTL_TX_THRESHOLD_384 0x06862#define MTL_TX_THRESHOLD_512 0x07863 864#define MTL_ETSALG_WRR 0x00865#define MTL_ETSALG_WFQ 0x01866#define MTL_ETSALG_DWRR 0x02867#define MTL_RAA_SP 0x00868#define MTL_RAA_WSP 0x01869 870#define MTL_Q_DISABLED 0x00871#define MTL_Q_ENABLED 0x02872 873/* MTL traffic class register offsets874 * Multiple traffic classes can be active. The first class has registers875 * that begin at 0x1100. Each subsequent queue has registers that876 * are accessed using an offset of 0x80 from the previous queue.877 */878#define MTL_TC_BASE MTL_Q_BASE879#define MTL_TC_INC MTL_Q_INC880 881#define MTL_TC_ETSCR 0x10882#define MTL_TC_ETSSR 0x14883#define MTL_TC_QWR 0x18884 885/* MTL traffic class register entry bit positions and sizes */886#define MTL_TC_ETSCR_TSA_INDEX 0887#define MTL_TC_ETSCR_TSA_WIDTH 2888#define MTL_TC_QWR_QW_INDEX 0889#define MTL_TC_QWR_QW_WIDTH 21890 891/* MTL traffic class register value */892#define MTL_TSA_SP 0x00893#define MTL_TSA_ETS 0x02894 895/* PCS register offsets */896#define PCS_V1_WINDOW_SELECT 0x03fc897#define PCS_V2_WINDOW_DEF 0x9060898#define PCS_V2_WINDOW_SELECT 0x9064899#define PCS_V2_RV_WINDOW_DEF 0x1060900#define PCS_V2_RV_WINDOW_SELECT 0x1064901#define PCS_V2_YC_WINDOW_DEF 0x18060902#define PCS_V2_YC_WINDOW_SELECT 0x18064903 904/* PCS register entry bit positions and sizes */905#define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6906#define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14907#define PCS_V2_WINDOW_DEF_SIZE_INDEX 2908#define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4909 910/* SerDes integration register offsets */911#define SIR0_KR_RT_1 0x002c912#define SIR0_STATUS 0x0040913#define SIR1_SPEED 0x0000914 915/* SerDes integration register entry bit positions and sizes */916#define SIR0_KR_RT_1_RESET_INDEX 11917#define SIR0_KR_RT_1_RESET_WIDTH 1918#define SIR0_STATUS_RX_READY_INDEX 0919#define SIR0_STATUS_RX_READY_WIDTH 1920#define SIR0_STATUS_TX_READY_INDEX 8921#define SIR0_STATUS_TX_READY_WIDTH 1922#define SIR1_SPEED_CDR_RATE_INDEX 12923#define SIR1_SPEED_CDR_RATE_WIDTH 4924#define SIR1_SPEED_DATARATE_INDEX 4925#define SIR1_SPEED_DATARATE_WIDTH 2926#define SIR1_SPEED_PLLSEL_INDEX 3927#define SIR1_SPEED_PLLSEL_WIDTH 1928#define SIR1_SPEED_RATECHANGE_INDEX 6929#define SIR1_SPEED_RATECHANGE_WIDTH 1930#define SIR1_SPEED_TXAMP_INDEX 8931#define SIR1_SPEED_TXAMP_WIDTH 4932#define SIR1_SPEED_WORDMODE_INDEX 0933#define SIR1_SPEED_WORDMODE_WIDTH 3934 935/* SerDes RxTx register offsets */936#define RXTX_REG6 0x0018937#define RXTX_REG20 0x0050938#define RXTX_REG22 0x0058939#define RXTX_REG114 0x01c8940#define RXTX_REG129 0x0204941 942/* SerDes RxTx register entry bit positions and sizes */943#define RXTX_REG6_RESETB_RXD_INDEX 8944#define RXTX_REG6_RESETB_RXD_WIDTH 1945#define RXTX_REG20_BLWC_ENA_INDEX 2946#define RXTX_REG20_BLWC_ENA_WIDTH 1947#define RXTX_REG114_PQ_REG_INDEX 9948#define RXTX_REG114_PQ_REG_WIDTH 7949#define RXTX_REG129_RXDFE_CONFIG_INDEX 14950#define RXTX_REG129_RXDFE_CONFIG_WIDTH 2951 952/* MAC Control register offsets */953#define XP_PROP_0 0x0000954#define XP_PROP_1 0x0004955#define XP_PROP_2 0x0008956#define XP_PROP_3 0x000c957#define XP_PROP_4 0x0010958#define XP_PROP_5 0x0014959#define XP_MAC_ADDR_LO 0x0020960#define XP_MAC_ADDR_HI 0x0024961#define XP_ECC_ISR 0x0030962#define XP_ECC_IER 0x0034963#define XP_ECC_CNT0 0x003c964#define XP_ECC_CNT1 0x0040965#define XP_DRIVER_INT_REQ 0x0060966#define XP_DRIVER_INT_RO 0x0064967#define XP_DRIVER_SCRATCH_0 0x0068968#define XP_DRIVER_SCRATCH_1 0x006c969#define XP_INT_REISSUE_EN 0x0074970#define XP_INT_EN 0x0078971#define XP_I2C_MUTEX 0x0080972#define XP_MDIO_MUTEX 0x0084973 974/* MAC Control register entry bit positions and sizes */975#define XP_DRIVER_INT_REQ_REQUEST_INDEX 0976#define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1977#define XP_DRIVER_INT_RO_STATUS_INDEX 0978#define XP_DRIVER_INT_RO_STATUS_WIDTH 1979#define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0980#define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8981#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8982#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8983#define XP_ECC_CNT0_RX_DED_INDEX 24984#define XP_ECC_CNT0_RX_DED_WIDTH 8985#define XP_ECC_CNT0_RX_SEC_INDEX 16986#define XP_ECC_CNT0_RX_SEC_WIDTH 8987#define XP_ECC_CNT0_TX_DED_INDEX 8988#define XP_ECC_CNT0_TX_DED_WIDTH 8989#define XP_ECC_CNT0_TX_SEC_INDEX 0990#define XP_ECC_CNT0_TX_SEC_WIDTH 8991#define XP_ECC_CNT1_DESC_DED_INDEX 8992#define XP_ECC_CNT1_DESC_DED_WIDTH 8993#define XP_ECC_CNT1_DESC_SEC_INDEX 0994#define XP_ECC_CNT1_DESC_SEC_WIDTH 8995#define XP_ECC_IER_DESC_DED_INDEX 5996#define XP_ECC_IER_DESC_DED_WIDTH 1997#define XP_ECC_IER_DESC_SEC_INDEX 4998#define XP_ECC_IER_DESC_SEC_WIDTH 1999#define XP_ECC_IER_RX_DED_INDEX 31000#define XP_ECC_IER_RX_DED_WIDTH 11001#define XP_ECC_IER_RX_SEC_INDEX 21002#define XP_ECC_IER_RX_SEC_WIDTH 11003#define XP_ECC_IER_TX_DED_INDEX 11004#define XP_ECC_IER_TX_DED_WIDTH 11005#define XP_ECC_IER_TX_SEC_INDEX 01006#define XP_ECC_IER_TX_SEC_WIDTH 11007#define XP_ECC_ISR_DESC_DED_INDEX 51008#define XP_ECC_ISR_DESC_DED_WIDTH 11009#define XP_ECC_ISR_DESC_SEC_INDEX 41010#define XP_ECC_ISR_DESC_SEC_WIDTH 11011#define XP_ECC_ISR_RX_DED_INDEX 31012#define XP_ECC_ISR_RX_DED_WIDTH 11013#define XP_ECC_ISR_RX_SEC_INDEX 21014#define XP_ECC_ISR_RX_SEC_WIDTH 11015#define XP_ECC_ISR_TX_DED_INDEX 11016#define XP_ECC_ISR_TX_DED_WIDTH 11017#define XP_ECC_ISR_TX_SEC_INDEX 01018#define XP_ECC_ISR_TX_SEC_WIDTH 11019#define XP_I2C_MUTEX_BUSY_INDEX 311020#define XP_I2C_MUTEX_BUSY_WIDTH 11021#define XP_I2C_MUTEX_ID_INDEX 291022#define XP_I2C_MUTEX_ID_WIDTH 21023#define XP_I2C_MUTEX_ACTIVE_INDEX 01024#define XP_I2C_MUTEX_ACTIVE_WIDTH 11025#define XP_MAC_ADDR_HI_VALID_INDEX 311026#define XP_MAC_ADDR_HI_VALID_WIDTH 11027#define XP_PROP_0_CONN_TYPE_INDEX 281028#define XP_PROP_0_CONN_TYPE_WIDTH 31029#define XP_PROP_0_MDIO_ADDR_INDEX 161030#define XP_PROP_0_MDIO_ADDR_WIDTH 51031#define XP_PROP_0_PORT_ID_INDEX 01032#define XP_PROP_0_PORT_ID_WIDTH 81033#define XP_PROP_0_PORT_MODE_INDEX 81034#define XP_PROP_0_PORT_MODE_WIDTH 41035#define XP_PROP_0_PORT_SPEEDS_INDEX 221036#define XP_PROP_0_PORT_SPEEDS_WIDTH 51037#define XP_PROP_1_MAX_RX_DMA_INDEX 241038#define XP_PROP_1_MAX_RX_DMA_WIDTH 51039#define XP_PROP_1_MAX_RX_QUEUES_INDEX 81040#define XP_PROP_1_MAX_RX_QUEUES_WIDTH 51041#define XP_PROP_1_MAX_TX_DMA_INDEX 161042#define XP_PROP_1_MAX_TX_DMA_WIDTH 51043#define XP_PROP_1_MAX_TX_QUEUES_INDEX 01044#define XP_PROP_1_MAX_TX_QUEUES_WIDTH 51045#define XP_PROP_2_RX_FIFO_SIZE_INDEX 161046#define XP_PROP_2_RX_FIFO_SIZE_WIDTH 161047#define XP_PROP_2_TX_FIFO_SIZE_INDEX 01048#define XP_PROP_2_TX_FIFO_SIZE_WIDTH 161049#define XP_PROP_3_GPIO_MASK_INDEX 281050#define XP_PROP_3_GPIO_MASK_WIDTH 41051#define XP_PROP_3_GPIO_MOD_ABS_INDEX 201052#define XP_PROP_3_GPIO_MOD_ABS_WIDTH 41053#define XP_PROP_3_GPIO_RATE_SELECT_INDEX 161054#define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 41055#define XP_PROP_3_GPIO_RX_LOS_INDEX 241056#define XP_PROP_3_GPIO_RX_LOS_WIDTH 41057#define XP_PROP_3_GPIO_TX_FAULT_INDEX 121058#define XP_PROP_3_GPIO_TX_FAULT_WIDTH 41059#define XP_PROP_3_GPIO_ADDR_INDEX 81060#define XP_PROP_3_GPIO_ADDR_WIDTH 31061#define XP_PROP_3_MDIO_RESET_INDEX 01062#define XP_PROP_3_MDIO_RESET_WIDTH 21063#define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 81064#define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 31065#define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 121066#define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 41067#define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 41068#define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 21069#define XP_PROP_4_MUX_ADDR_HI_INDEX 81070#define XP_PROP_4_MUX_ADDR_HI_WIDTH 51071#define XP_PROP_4_MUX_ADDR_LO_INDEX 01072#define XP_PROP_4_MUX_ADDR_LO_WIDTH 31073#define XP_PROP_4_MUX_CHAN_INDEX 41074#define XP_PROP_4_MUX_CHAN_WIDTH 31075#define XP_PROP_4_REDRV_ADDR_INDEX 161076#define XP_PROP_4_REDRV_ADDR_WIDTH 71077#define XP_PROP_4_REDRV_IF_INDEX 231078#define XP_PROP_4_REDRV_IF_WIDTH 11079#define XP_PROP_4_REDRV_LANE_INDEX 241080#define XP_PROP_4_REDRV_LANE_WIDTH 31081#define XP_PROP_4_REDRV_MODEL_INDEX 281082#define XP_PROP_4_REDRV_MODEL_WIDTH 31083#define XP_PROP_4_REDRV_PRESENT_INDEX 311084#define XP_PROP_4_REDRV_PRESENT_WIDTH 11085 1086/* I2C Control register offsets */1087#define IC_CON 0x00001088#define IC_TAR 0x00041089#define IC_DATA_CMD 0x00101090#define IC_INTR_STAT 0x002c1091#define IC_INTR_MASK 0x00301092#define IC_RAW_INTR_STAT 0x00341093#define IC_CLR_INTR 0x00401094#define IC_CLR_TX_ABRT 0x00541095#define IC_CLR_STOP_DET 0x00601096#define IC_ENABLE 0x006c1097#define IC_TXFLR 0x00741098#define IC_RXFLR 0x00781099#define IC_TX_ABRT_SOURCE 0x00801100#define IC_ENABLE_STATUS 0x009c1101#define IC_COMP_PARAM_1 0x00f41102 1103/* I2C Control register entry bit positions and sizes */1104#define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 21105#define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 21106#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 81107#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 81108#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 161109#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 81110#define IC_CON_MASTER_MODE_INDEX 01111#define IC_CON_MASTER_MODE_WIDTH 11112#define IC_CON_RESTART_EN_INDEX 51113#define IC_CON_RESTART_EN_WIDTH 11114#define IC_CON_RX_FIFO_FULL_HOLD_INDEX 91115#define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 11116#define IC_CON_SLAVE_DISABLE_INDEX 61117#define IC_CON_SLAVE_DISABLE_WIDTH 11118#define IC_CON_SPEED_INDEX 11119#define IC_CON_SPEED_WIDTH 21120#define IC_DATA_CMD_CMD_INDEX 81121#define IC_DATA_CMD_CMD_WIDTH 11122#define IC_DATA_CMD_STOP_INDEX 91123#define IC_DATA_CMD_STOP_WIDTH 11124#define IC_ENABLE_ABORT_INDEX 11125#define IC_ENABLE_ABORT_WIDTH 11126#define IC_ENABLE_EN_INDEX 01127#define IC_ENABLE_EN_WIDTH 11128#define IC_ENABLE_STATUS_EN_INDEX 01129#define IC_ENABLE_STATUS_EN_WIDTH 11130#define IC_INTR_MASK_TX_EMPTY_INDEX 41131#define IC_INTR_MASK_TX_EMPTY_WIDTH 11132#define IC_RAW_INTR_STAT_RX_FULL_INDEX 21133#define IC_RAW_INTR_STAT_RX_FULL_WIDTH 11134#define IC_RAW_INTR_STAT_STOP_DET_INDEX 91135#define IC_RAW_INTR_STAT_STOP_DET_WIDTH 11136#define IC_RAW_INTR_STAT_TX_ABRT_INDEX 61137#define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 11138#define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 41139#define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 11140 1141/* I2C Control register value */1142#define IC_TX_ABRT_7B_ADDR_NOACK 0x00011143#define IC_TX_ABRT_ARB_LOST 0x10001144 1145/* Descriptor/Packet entry bit positions and sizes */1146#define RX_PACKET_ERRORS_CRC_INDEX 21147#define RX_PACKET_ERRORS_CRC_WIDTH 11148#define RX_PACKET_ERRORS_FRAME_INDEX 31149#define RX_PACKET_ERRORS_FRAME_WIDTH 11150#define RX_PACKET_ERRORS_LENGTH_INDEX 01151#define RX_PACKET_ERRORS_LENGTH_WIDTH 11152#define RX_PACKET_ERRORS_OVERRUN_INDEX 11153#define RX_PACKET_ERRORS_OVERRUN_WIDTH 11154 1155#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 01156#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 11157#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 11158#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 11159#define RX_PACKET_ATTRIBUTES_LAST_INDEX 21160#define RX_PACKET_ATTRIBUTES_LAST_WIDTH 11161#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 31162#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 11163#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 41164#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 11165#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 51166#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 11167#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 61168#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 11169#define RX_PACKET_ATTRIBUTES_FIRST_INDEX 71170#define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 11171#define RX_PACKET_ATTRIBUTES_TNP_INDEX 81172#define RX_PACKET_ATTRIBUTES_TNP_WIDTH 11173#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX 91174#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH 11175 1176#define RX_NORMAL_DESC0_OVT_INDEX 01177#define RX_NORMAL_DESC0_OVT_WIDTH 161178#define RX_NORMAL_DESC2_HL_INDEX 01179#define RX_NORMAL_DESC2_HL_WIDTH 101180#define RX_NORMAL_DESC2_TNP_INDEX 111181#define RX_NORMAL_DESC2_TNP_WIDTH 11182#define RX_NORMAL_DESC3_CDA_INDEX 271183#define RX_NORMAL_DESC3_CDA_WIDTH 11184#define RX_NORMAL_DESC3_CTXT_INDEX 301185#define RX_NORMAL_DESC3_CTXT_WIDTH 11186#define RX_NORMAL_DESC3_ES_INDEX 151187#define RX_NORMAL_DESC3_ES_WIDTH 11188#define RX_NORMAL_DESC3_ETLT_INDEX 161189#define RX_NORMAL_DESC3_ETLT_WIDTH 41190#define RX_NORMAL_DESC3_FD_INDEX 291191#define RX_NORMAL_DESC3_FD_WIDTH 11192#define RX_NORMAL_DESC3_INTE_INDEX 301193#define RX_NORMAL_DESC3_INTE_WIDTH 11194#define RX_NORMAL_DESC3_L34T_INDEX 201195#define RX_NORMAL_DESC3_L34T_WIDTH 41196#define RX_NORMAL_DESC3_LD_INDEX 281197#define RX_NORMAL_DESC3_LD_WIDTH 11198#define RX_NORMAL_DESC3_OWN_INDEX 311199#define RX_NORMAL_DESC3_OWN_WIDTH 11200#define RX_NORMAL_DESC3_PL_INDEX 01201#define RX_NORMAL_DESC3_PL_WIDTH 141202#define RX_NORMAL_DESC3_RSV_INDEX 261203#define RX_NORMAL_DESC3_RSV_WIDTH 11204 1205#define RX_DESC3_L34T_IPV4_TCP 11206#define RX_DESC3_L34T_IPV4_UDP 21207#define RX_DESC3_L34T_IPV4_ICMP 31208#define RX_DESC3_L34T_IPV4_UNKNOWN 71209#define RX_DESC3_L34T_IPV6_TCP 91210#define RX_DESC3_L34T_IPV6_UDP 101211#define RX_DESC3_L34T_IPV6_ICMP 111212#define RX_DESC3_L34T_IPV6_UNKNOWN 151213 1214#define RX_CONTEXT_DESC3_TSA_INDEX 41215#define RX_CONTEXT_DESC3_TSA_WIDTH 11216#define RX_CONTEXT_DESC3_TSD_INDEX 61217#define RX_CONTEXT_DESC3_TSD_WIDTH 11218 1219#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 01220#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 11221#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 11222#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 11223#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 21224#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 11225#define TX_PACKET_ATTRIBUTES_PTP_INDEX 31226#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 11227#define TX_PACKET_ATTRIBUTES_VXLAN_INDEX 41228#define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH 11229 1230#define TX_CONTEXT_DESC2_MSS_INDEX 01231#define TX_CONTEXT_DESC2_MSS_WIDTH 151232#define TX_CONTEXT_DESC3_CTXT_INDEX 301233#define TX_CONTEXT_DESC3_CTXT_WIDTH 11234#define TX_CONTEXT_DESC3_TCMSSV_INDEX 261235#define TX_CONTEXT_DESC3_TCMSSV_WIDTH 11236#define TX_CONTEXT_DESC3_VLTV_INDEX 161237#define TX_CONTEXT_DESC3_VLTV_WIDTH 11238#define TX_CONTEXT_DESC3_VT_INDEX 01239#define TX_CONTEXT_DESC3_VT_WIDTH 161240 1241#define TX_NORMAL_DESC2_HL_B1L_INDEX 01242#define TX_NORMAL_DESC2_HL_B1L_WIDTH 141243#define TX_NORMAL_DESC2_IC_INDEX 311244#define TX_NORMAL_DESC2_IC_WIDTH 11245#define TX_NORMAL_DESC2_TTSE_INDEX 301246#define TX_NORMAL_DESC2_TTSE_WIDTH 11247#define TX_NORMAL_DESC2_VTIR_INDEX 141248#define TX_NORMAL_DESC2_VTIR_WIDTH 21249#define TX_NORMAL_DESC3_CIC_INDEX 161250#define TX_NORMAL_DESC3_CIC_WIDTH 21251#define TX_NORMAL_DESC3_CPC_INDEX 261252#define TX_NORMAL_DESC3_CPC_WIDTH 21253#define TX_NORMAL_DESC3_CTXT_INDEX 301254#define TX_NORMAL_DESC3_CTXT_WIDTH 11255#define TX_NORMAL_DESC3_FD_INDEX 291256#define TX_NORMAL_DESC3_FD_WIDTH 11257#define TX_NORMAL_DESC3_FL_INDEX 01258#define TX_NORMAL_DESC3_FL_WIDTH 151259#define TX_NORMAL_DESC3_LD_INDEX 281260#define TX_NORMAL_DESC3_LD_WIDTH 11261#define TX_NORMAL_DESC3_OWN_INDEX 311262#define TX_NORMAL_DESC3_OWN_WIDTH 11263#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 191264#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 41265#define TX_NORMAL_DESC3_TCPPL_INDEX 01266#define TX_NORMAL_DESC3_TCPPL_WIDTH 181267#define TX_NORMAL_DESC3_TSE_INDEX 181268#define TX_NORMAL_DESC3_TSE_WIDTH 11269#define TX_NORMAL_DESC3_VNP_INDEX 231270#define TX_NORMAL_DESC3_VNP_WIDTH 31271 1272#define TX_NORMAL_DESC2_VLAN_INSERT 0x21273#define TX_NORMAL_DESC3_VXLAN_PACKET 0x31274 1275/* MDIO undefined or vendor specific registers */1276#ifndef MDIO_PMA_10GBR_PMD_CTRL1277#define MDIO_PMA_10GBR_PMD_CTRL 0x00961278#endif1279 1280#ifndef MDIO_PMA_10GBR_FECCTRL1281#define MDIO_PMA_10GBR_FECCTRL 0x00ab1282#endif1283 1284#ifndef MDIO_PMA_RX_CTRL11285#define MDIO_PMA_RX_CTRL1 0x80511286#endif1287 1288#ifndef MDIO_PMA_RX_LSTS1289#define MDIO_PMA_RX_LSTS 0x0180201290#endif1291 1292#ifndef MDIO_PMA_RX_EQ_CTRL41293#define MDIO_PMA_RX_EQ_CTRL4 0x0001805C1294#endif1295 1296#ifndef MDIO_PMA_MP_MISC_STS1297#define MDIO_PMA_MP_MISC_STS 0x00781298#endif1299 1300#ifndef MDIO_PMA_PHY_RX_EQ_CEU1301#define MDIO_PMA_PHY_RX_EQ_CEU 0x1800E1302#endif1303 1304#ifndef MDIO_PCS_DIG_CTRL1305#define MDIO_PCS_DIG_CTRL 0x80001306#endif1307 1308#ifndef MDIO_PCS_DIGITAL_STAT1309#define MDIO_PCS_DIGITAL_STAT 0x80101310#endif1311 1312#ifndef MDIO_AN_XNP1313#define MDIO_AN_XNP 0x00161314#endif1315 1316#ifndef MDIO_AN_LPX1317#define MDIO_AN_LPX 0x00191318#endif1319 1320#ifndef MDIO_AN_COMP_STAT1321#define MDIO_AN_COMP_STAT 0x00301322#endif1323 1324#ifndef MDIO_AN_INTMASK1325#define MDIO_AN_INTMASK 0x80011326#endif1327 1328#ifndef MDIO_AN_INT1329#define MDIO_AN_INT 0x80021330#endif1331 1332#ifndef MDIO_VEND2_AN_ADVERTISE1333#define MDIO_VEND2_AN_ADVERTISE 0x00041334#endif1335 1336#ifndef MDIO_VEND2_AN_LP_ABILITY1337#define MDIO_VEND2_AN_LP_ABILITY 0x00051338#endif1339 1340#ifndef MDIO_VEND2_AN_CTRL1341#define MDIO_VEND2_AN_CTRL 0x80011342#endif1343 1344#ifndef MDIO_VEND2_AN_STAT1345#define MDIO_VEND2_AN_STAT 0x80021346#endif1347 1348#ifndef MDIO_VEND2_PMA_CDR_CONTROL1349#define MDIO_VEND2_PMA_CDR_CONTROL 0x80561350#endif1351 1352#ifndef MDIO_VEND2_PMA_MISC_CTRL01353#define MDIO_VEND2_PMA_MISC_CTRL0 0x80901354#endif1355 1356#ifndef MDIO_CTRL1_SPEED1G1357#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)1358#endif1359 1360#ifndef MDIO_VEND2_CTRL1_AN_ENABLE1361#define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)1362#endif1363 1364#ifndef MDIO_VEND2_CTRL1_AN_RESTART1365#define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)1366#endif1367 1368#ifndef MDIO_VEND2_CTRL1_SS61369#define MDIO_VEND2_CTRL1_SS6 BIT(6)1370#endif1371 1372#ifndef MDIO_VEND2_CTRL1_SS131373#define MDIO_VEND2_CTRL1_SS13 BIT(13)1374#endif1375 1376/* MDIO mask values */1377#define XGBE_AN_CL73_INT_CMPLT BIT(0)1378#define XGBE_AN_CL73_INC_LINK BIT(1)1379#define XGBE_AN_CL73_PG_RCV BIT(2)1380#define XGBE_AN_CL73_INT_MASK 0x071381 1382#define XGBE_XNP_MCF_NULL_MESSAGE 0x0011383#define XGBE_XNP_ACK_PROCESSED BIT(12)1384#define XGBE_XNP_MP_FORMATTED BIT(13)1385#define XGBE_XNP_NP_EXCHANGE BIT(15)1386 1387#define XGBE_KR_TRAINING_START BIT(0)1388#define XGBE_KR_TRAINING_ENABLE BIT(1)1389 1390#define XGBE_PCS_CL37_BP BIT(12)1391#define XGBE_PCS_PSEQ_STATE_MASK 0x1c1392#define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x101393 1394#define XGBE_AN_CL37_INT_CMPLT BIT(0)1395#define XGBE_AN_CL37_INT_MASK 0x011396 1397#define XGBE_AN_CL37_HD_MASK 0x401398#define XGBE_AN_CL37_FD_MASK 0x201399 1400#define XGBE_AN_CL37_PCS_MODE_MASK 0x061401#define XGBE_AN_CL37_PCS_MODE_BASEX 0x001402#define XGBE_AN_CL37_PCS_MODE_SGMII 0x041403#define XGBE_AN_CL37_TX_CONFIG_MASK 0x081404#define XGBE_AN_CL37_MII_CTRL_8BIT 0x01001405 1406#define XGBE_PMA_CDR_TRACK_EN_MASK 0x011407#define XGBE_PMA_CDR_TRACK_EN_OFF 0x001408#define XGBE_PMA_CDR_TRACK_EN_ON 0x011409 1410#define XGBE_PMA_RX_RST_0_MASK BIT(4)1411#define XGBE_PMA_RX_RST_0_RESET_ON 0x101412#define XGBE_PMA_RX_RST_0_RESET_OFF 0x001413 1414#define XGBE_PMA_RX_SIG_DET_0_MASK BIT(4)1415#define XGBE_PMA_RX_SIG_DET_0_ENABLE BIT(4)1416#define XGBE_PMA_RX_SIG_DET_0_DISABLE 0x00001417 1418#define XGBE_PMA_RX_VALID_0_MASK BIT(12)1419#define XGBE_PMA_RX_VALID_0_ENABLE BIT(12)1420#define XGBE_PMA_RX_VALID_0_DISABLE 0x00001421 1422#define XGBE_PMA_RX_AD_REQ_MASK BIT(12)1423#define XGBE_PMA_RX_AD_REQ_ENABLE BIT(12)1424#define XGBE_PMA_RX_AD_REQ_DISABLE 0x00001425 1426#define XGBE_PMA_RX_ADPT_ACK_MASK BIT(12)1427#define XGBE_PMA_RX_ADPT_ACK BIT(12)1428 1429#define XGBE_PMA_CFF_UPDTM1_VLD BIT(8)1430#define XGBE_PMA_CFF_UPDT0_VLD BIT(9)1431#define XGBE_PMA_CFF_UPDT1_VLD BIT(10)1432#define XGBE_PMA_CFF_UPDT_MASK (XGBE_PMA_CFF_UPDTM1_VLD |\1433 XGBE_PMA_CFF_UPDT0_VLD | \1434 XGBE_PMA_CFF_UPDT1_VLD)1435 1436#define XGBE_PMA_PLL_CTRL_MASK BIT(15)1437#define XGBE_PMA_PLL_CTRL_ENABLE BIT(15)1438#define XGBE_PMA_PLL_CTRL_DISABLE 0x00001439 1440/* Bit setting and getting macros1441 * The get macro will extract the current bit field value from within1442 * the variable1443 *1444 * The set macro will clear the current bit field value within the1445 * variable and then set the bit field of the variable to the1446 * specified value1447 */1448#define GET_BITS(_var, _index, _width) \1449 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))1450 1451#define SET_BITS(_var, _index, _width, _val) \1452do { \1453 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \1454 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \1455} while (0)1456 1457#define GET_BITS_LE(_var, _index, _width) \1458 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))1459 1460#define SET_BITS_LE(_var, _index, _width, _val) \1461do { \1462 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \1463 (_var) |= cpu_to_le32((((_val) & \1464 ((0x1 << (_width)) - 1)) << (_index))); \1465} while (0)1466 1467/* Bit setting and getting macros based on register fields1468 * The get macro uses the bit field definitions formed using the input1469 * names to extract the current bit field value from within the1470 * variable1471 *1472 * The set macro uses the bit field definitions formed using the input1473 * names to set the bit field of the variable to the specified value1474 */1475#define XGMAC_GET_BITS(_var, _prefix, _field) \1476 GET_BITS((_var), \1477 _prefix##_##_field##_INDEX, \1478 _prefix##_##_field##_WIDTH)1479 1480#define XGMAC_SET_BITS(_var, _prefix, _field, _val) \1481 SET_BITS((_var), \1482 _prefix##_##_field##_INDEX, \1483 _prefix##_##_field##_WIDTH, (_val))1484 1485#define XGMAC_GET_BITS_LE(_var, _prefix, _field) \1486 GET_BITS_LE((_var), \1487 _prefix##_##_field##_INDEX, \1488 _prefix##_##_field##_WIDTH)1489 1490#define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \1491 SET_BITS_LE((_var), \1492 _prefix##_##_field##_INDEX, \1493 _prefix##_##_field##_WIDTH, (_val))1494 1495/* Macros for reading or writing registers1496 * The ioread macros will get bit fields or full values using the1497 * register definitions formed using the input names1498 *1499 * The iowrite macros will set bit fields or full values using the1500 * register definitions formed using the input names1501 */1502#define XGMAC_IOREAD(_pdata, _reg) \1503 ioread32((_pdata)->xgmac_regs + _reg)1504 1505#define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \1506 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \1507 _reg##_##_field##_INDEX, \1508 _reg##_##_field##_WIDTH)1509 1510#define XGMAC_IOWRITE(_pdata, _reg, _val) \1511 iowrite32((_val), (_pdata)->xgmac_regs + _reg)1512 1513#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \1514do { \1515 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \1516 SET_BITS(reg_val, \1517 _reg##_##_field##_INDEX, \1518 _reg##_##_field##_WIDTH, (_val)); \1519 XGMAC_IOWRITE((_pdata), _reg, reg_val); \1520} while (0)1521 1522/* Macros for reading or writing MTL queue or traffic class registers1523 * Similar to the standard read and write macros except that the1524 * base register value is calculated by the queue or traffic class number1525 */1526#define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \1527 ioread32((_pdata)->xgmac_regs + \1528 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)1529 1530#define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \1531 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \1532 _reg##_##_field##_INDEX, \1533 _reg##_##_field##_WIDTH)1534 1535#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \1536 iowrite32((_val), (_pdata)->xgmac_regs + \1537 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)1538 1539#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \1540do { \1541 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \1542 SET_BITS(reg_val, \1543 _reg##_##_field##_INDEX, \1544 _reg##_##_field##_WIDTH, (_val)); \1545 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \1546} while (0)1547 1548/* Macros for reading or writing DMA channel registers1549 * Similar to the standard read and write macros except that the1550 * base register value is obtained from the ring1551 */1552#define XGMAC_DMA_IOREAD(_channel, _reg) \1553 ioread32((_channel)->dma_regs + _reg)1554 1555#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \1556 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \1557 _reg##_##_field##_INDEX, \1558 _reg##_##_field##_WIDTH)1559 1560#define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \1561 iowrite32((_val), (_channel)->dma_regs + _reg)1562 1563#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \1564do { \1565 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \1566 SET_BITS(reg_val, \1567 _reg##_##_field##_INDEX, \1568 _reg##_##_field##_WIDTH, (_val)); \1569 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \1570} while (0)1571 1572/* Macros for building, reading or writing register values or bits1573 * within the register values of XPCS registers.1574 */1575#define XPCS_GET_BITS(_var, _prefix, _field) \1576 GET_BITS((_var), \1577 _prefix##_##_field##_INDEX, \1578 _prefix##_##_field##_WIDTH)1579 1580#define XPCS_SET_BITS(_var, _prefix, _field, _val) \1581 SET_BITS((_var), \1582 _prefix##_##_field##_INDEX, \1583 _prefix##_##_field##_WIDTH, (_val))1584 1585#define XPCS32_IOWRITE(_pdata, _off, _val) \1586 iowrite32(_val, (_pdata)->xpcs_regs + (_off))1587 1588#define XPCS32_IOREAD(_pdata, _off) \1589 ioread32((_pdata)->xpcs_regs + (_off))1590 1591#define XPCS16_IOWRITE(_pdata, _off, _val) \1592 iowrite16(_val, (_pdata)->xpcs_regs + (_off))1593 1594#define XPCS16_IOREAD(_pdata, _off) \1595 ioread16((_pdata)->xpcs_regs + (_off))1596 1597/* Macros for building, reading or writing register values or bits1598 * within the register values of SerDes integration registers.1599 */1600#define XSIR_GET_BITS(_var, _prefix, _field) \1601 GET_BITS((_var), \1602 _prefix##_##_field##_INDEX, \1603 _prefix##_##_field##_WIDTH)1604 1605#define XSIR_SET_BITS(_var, _prefix, _field, _val) \1606 SET_BITS((_var), \1607 _prefix##_##_field##_INDEX, \1608 _prefix##_##_field##_WIDTH, (_val))1609 1610#define XSIR0_IOREAD(_pdata, _reg) \1611 ioread16((_pdata)->sir0_regs + _reg)1612 1613#define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \1614 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \1615 _reg##_##_field##_INDEX, \1616 _reg##_##_field##_WIDTH)1617 1618#define XSIR0_IOWRITE(_pdata, _reg, _val) \1619 iowrite16((_val), (_pdata)->sir0_regs + _reg)1620 1621#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \1622do { \1623 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \1624 SET_BITS(reg_val, \1625 _reg##_##_field##_INDEX, \1626 _reg##_##_field##_WIDTH, (_val)); \1627 XSIR0_IOWRITE((_pdata), _reg, reg_val); \1628} while (0)1629 1630#define XSIR1_IOREAD(_pdata, _reg) \1631 ioread16((_pdata)->sir1_regs + _reg)1632 1633#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \1634 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \1635 _reg##_##_field##_INDEX, \1636 _reg##_##_field##_WIDTH)1637 1638#define XSIR1_IOWRITE(_pdata, _reg, _val) \1639 iowrite16((_val), (_pdata)->sir1_regs + _reg)1640 1641#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \1642do { \1643 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \1644 SET_BITS(reg_val, \1645 _reg##_##_field##_INDEX, \1646 _reg##_##_field##_WIDTH, (_val)); \1647 XSIR1_IOWRITE((_pdata), _reg, reg_val); \1648} while (0)1649 1650/* Macros for building, reading or writing register values or bits1651 * within the register values of SerDes RxTx registers.1652 */1653#define XRXTX_IOREAD(_pdata, _reg) \1654 ioread16((_pdata)->rxtx_regs + _reg)1655 1656#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \1657 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \1658 _reg##_##_field##_INDEX, \1659 _reg##_##_field##_WIDTH)1660 1661#define XRXTX_IOWRITE(_pdata, _reg, _val) \1662 iowrite16((_val), (_pdata)->rxtx_regs + _reg)1663 1664#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \1665do { \1666 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \1667 SET_BITS(reg_val, \1668 _reg##_##_field##_INDEX, \1669 _reg##_##_field##_WIDTH, (_val)); \1670 XRXTX_IOWRITE((_pdata), _reg, reg_val); \1671} while (0)1672 1673/* Macros for building, reading or writing register values or bits1674 * within the register values of MAC Control registers.1675 */1676#define XP_GET_BITS(_var, _prefix, _field) \1677 GET_BITS((_var), \1678 _prefix##_##_field##_INDEX, \1679 _prefix##_##_field##_WIDTH)1680 1681#define XP_SET_BITS(_var, _prefix, _field, _val) \1682 SET_BITS((_var), \1683 _prefix##_##_field##_INDEX, \1684 _prefix##_##_field##_WIDTH, (_val))1685 1686#define XP_IOREAD(_pdata, _reg) \1687 ioread32((_pdata)->xprop_regs + (_reg))1688 1689#define XP_IOREAD_BITS(_pdata, _reg, _field) \1690 GET_BITS(XP_IOREAD((_pdata), (_reg)), \1691 _reg##_##_field##_INDEX, \1692 _reg##_##_field##_WIDTH)1693 1694#define XP_IOWRITE(_pdata, _reg, _val) \1695 iowrite32((_val), (_pdata)->xprop_regs + (_reg))1696 1697#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \1698do { \1699 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \1700 SET_BITS(reg_val, \1701 _reg##_##_field##_INDEX, \1702 _reg##_##_field##_WIDTH, (_val)); \1703 XP_IOWRITE((_pdata), (_reg), reg_val); \1704} while (0)1705 1706/* Macros for building, reading or writing register values or bits1707 * within the register values of I2C Control registers.1708 */1709#define XI2C_GET_BITS(_var, _prefix, _field) \1710 GET_BITS((_var), \1711 _prefix##_##_field##_INDEX, \1712 _prefix##_##_field##_WIDTH)1713 1714#define XI2C_SET_BITS(_var, _prefix, _field, _val) \1715 SET_BITS((_var), \1716 _prefix##_##_field##_INDEX, \1717 _prefix##_##_field##_WIDTH, (_val))1718 1719#define XI2C_IOREAD(_pdata, _reg) \1720 ioread32((_pdata)->xi2c_regs + (_reg))1721 1722#define XI2C_IOREAD_BITS(_pdata, _reg, _field) \1723 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \1724 _reg##_##_field##_INDEX, \1725 _reg##_##_field##_WIDTH)1726 1727#define XI2C_IOWRITE(_pdata, _reg, _val) \1728 iowrite32((_val), (_pdata)->xi2c_regs + (_reg))1729 1730#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \1731do { \1732 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \1733 SET_BITS(reg_val, \1734 _reg##_##_field##_INDEX, \1735 _reg##_##_field##_WIDTH, (_val)); \1736 XI2C_IOWRITE((_pdata), (_reg), reg_val); \1737} while (0)1738 1739/* Macros for building, reading or writing register values or bits1740 * using MDIO.1741 */1742 1743#define XGBE_ADDR_C45 BIT(30)1744 1745#define XMDIO_READ(_pdata, _mmd, _reg) \1746 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \1747 XGBE_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))1748 1749#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \1750 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)1751 1752#define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \1753 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \1754 XGBE_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))1755 1756#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \1757do { \1758 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \1759 mmd_val &= ~_mask; \1760 mmd_val |= (_val); \1761 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \1762} while (0)1763 1764#endif1765