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1/*2 * AMD 10Gb Ethernet driver3 *4 * This file is available to you under your choice of the following two5 * licenses:6 *7 * License 1: GPLv28 *9 * Copyright (c) 2016 Advanced Micro Devices, Inc.10 *11 * This file is free software; you may copy, redistribute and/or modify12 * it under the terms of the GNU General Public License as published by13 * the Free Software Foundation, either version 2 of the License, or (at14 * your option) any later version.15 *16 * This file is distributed in the hope that it will be useful, but17 * WITHOUT ANY WARRANTY; without even the implied warranty of18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU19 * General Public License for more details.20 *21 * You should have received a copy of the GNU General Public License22 * along with this program. If not, see <http://www.gnu.org/licenses/>.23 *24 * This file incorporates work covered by the following copyright and25 * permission notice:26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,28 * Inc. unless otherwise expressly agreed to in writing between Synopsys29 * and you.30 *31 * The Software IS NOT an item of Licensed Software or Licensed Product32 * under any End User Software License Agreement or Agreement for Licensed33 * Product with Synopsys or any supplement thereto. Permission is hereby34 * granted, free of charge, to any person obtaining a copy of this software35 * annotated with this license and the Software, to deal in the Software36 * without restriction, including without limitation the rights to use,37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies38 * of the Software, and to permit persons to whom the Software is furnished39 * to do so, subject to the following conditions:40 *41 * The above copyright notice and this permission notice shall be included42 * in all copies or substantial portions of the Software.43 *44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF54 * THE POSSIBILITY OF SUCH DAMAGE.55 *56 *57 * License 2: Modified BSD58 *59 * Copyright (c) 2016 Advanced Micro Devices, Inc.60 * All rights reserved.61 *62 * Redistribution and use in source and binary forms, with or without63 * modification, are permitted provided that the following conditions are met:64 * * Redistributions of source code must retain the above copyright65 * notice, this list of conditions and the following disclaimer.66 * * Redistributions in binary form must reproduce the above copyright67 * notice, this list of conditions and the following disclaimer in the68 * documentation and/or other materials provided with the distribution.69 * * Neither the name of Advanced Micro Devices, Inc. nor the70 * names of its contributors may be used to endorse or promote products71 * derived from this software without specific prior written permission.72 *73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.83 *84 * This file incorporates work covered by the following copyright and85 * permission notice:86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,88 * Inc. unless otherwise expressly agreed to in writing between Synopsys89 * and you.90 *91 * The Software IS NOT an item of Licensed Software or Licensed Product92 * under any End User Software License Agreement or Agreement for Licensed93 * Product with Synopsys or any supplement thereto. Permission is hereby94 * granted, free of charge, to any person obtaining a copy of this software95 * annotated with this license and the Software, to deal in the Software96 * without restriction, including without limitation the rights to use,97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies98 * of the Software, and to permit persons to whom the Software is furnished99 * to do so, subject to the following conditions:100 *101 * The above copyright notice and this permission notice shall be included102 * in all copies or substantial portions of the Software.103 *104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF114 * THE POSSIBILITY OF SUCH DAMAGE.115 */116 117#include <linux/module.h>118#include <linux/device.h>119#include <linux/pci.h>120#include <linux/log2.h>121 122#include "xgbe.h"123#include "xgbe-common.h"124 125static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)126{127 unsigned int vector_count;128 unsigned int i, j;129 int ret;130 131 vector_count = XGBE_MSI_BASE_COUNT;132 vector_count += max(pdata->rx_ring_count,133 pdata->tx_ring_count);134 135 ret = pci_alloc_irq_vectors(pdata->pcidev, XGBE_MSI_MIN_COUNT,136 vector_count, PCI_IRQ_MSI | PCI_IRQ_MSIX);137 if (ret < 0) {138 dev_info(pdata->dev, "multi MSI/MSI-X enablement failed\n");139 return ret;140 }141 142 pdata->isr_as_bh_work = 1;143 pdata->irq_count = ret;144 145 pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);146 pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 1);147 pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 2);148 pdata->an_irq = pci_irq_vector(pdata->pcidev, 3);149 150 for (i = XGBE_MSI_BASE_COUNT, j = 0; i < ret; i++, j++)151 pdata->channel_irq[j] = pci_irq_vector(pdata->pcidev, i);152 pdata->channel_irq_count = j;153 154 pdata->per_channel_irq = 1;155 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;156 157 if (netif_msg_probe(pdata))158 dev_dbg(pdata->dev, "multi %s interrupts enabled\n",159 pdata->pcidev->msix_enabled ? "MSI-X" : "MSI");160 161 return 0;162}163 164static int xgbe_config_irqs(struct xgbe_prv_data *pdata)165{166 int ret;167 168 ret = xgbe_config_multi_msi(pdata);169 if (!ret)170 goto out;171 172 ret = pci_alloc_irq_vectors(pdata->pcidev, 1, 1,173 PCI_IRQ_INTX | PCI_IRQ_MSI);174 if (ret < 0) {175 dev_info(pdata->dev, "single IRQ enablement failed\n");176 return ret;177 }178 179 pdata->isr_as_bh_work = pdata->pcidev->msi_enabled ? 1 : 0;180 pdata->irq_count = 1;181 pdata->channel_irq_count = 1;182 183 pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);184 pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 0);185 pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 0);186 pdata->an_irq = pci_irq_vector(pdata->pcidev, 0);187 188 if (netif_msg_probe(pdata))189 dev_dbg(pdata->dev, "single %s interrupt enabled\n",190 pdata->pcidev->msi_enabled ? "MSI" : "legacy");191 192out:193 if (netif_msg_probe(pdata)) {194 unsigned int i;195 196 dev_dbg(pdata->dev, " dev irq=%d\n", pdata->dev_irq);197 dev_dbg(pdata->dev, " ecc irq=%d\n", pdata->ecc_irq);198 dev_dbg(pdata->dev, " i2c irq=%d\n", pdata->i2c_irq);199 dev_dbg(pdata->dev, " an irq=%d\n", pdata->an_irq);200 for (i = 0; i < pdata->channel_irq_count; i++)201 dev_dbg(pdata->dev, " dma%u irq=%d\n",202 i, pdata->channel_irq[i]);203 }204 205 return 0;206}207 208static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)209{210 struct xgbe_prv_data *pdata;211 struct device *dev = &pdev->dev;212 void __iomem * const *iomap_table;213 struct pci_dev *rdev;214 unsigned int ma_lo, ma_hi;215 unsigned int reg;216 int bar_mask;217 int ret;218 219 pdata = xgbe_alloc_pdata(dev);220 if (IS_ERR(pdata)) {221 ret = PTR_ERR(pdata);222 goto err_alloc;223 }224 225 pdata->pcidev = pdev;226 pci_set_drvdata(pdev, pdata);227 228 /* Get the version data */229 pdata->vdata = (struct xgbe_version_data *)id->driver_data;230 231 ret = pcim_enable_device(pdev);232 if (ret) {233 dev_err(dev, "pcim_enable_device failed\n");234 goto err_pci_enable;235 }236 237 /* Obtain the mmio areas for the device */238 bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);239 ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME);240 if (ret) {241 dev_err(dev, "pcim_iomap_regions failed\n");242 goto err_pci_enable;243 }244 245 iomap_table = pcim_iomap_table(pdev);246 if (!iomap_table) {247 dev_err(dev, "pcim_iomap_table failed\n");248 ret = -ENOMEM;249 goto err_pci_enable;250 }251 252 pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR];253 if (!pdata->xgmac_regs) {254 dev_err(dev, "xgmac ioremap failed\n");255 ret = -ENOMEM;256 goto err_pci_enable;257 }258 pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET;259 pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET;260 if (netif_msg_probe(pdata)) {261 dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);262 dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);263 dev_dbg(dev, "xi2c_regs = %p\n", pdata->xi2c_regs);264 }265 266 pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR];267 if (!pdata->xpcs_regs) {268 dev_err(dev, "xpcs ioremap failed\n");269 ret = -ENOMEM;270 goto err_pci_enable;271 }272 if (netif_msg_probe(pdata))273 dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs);274 275 /* Set the PCS indirect addressing definition registers */276 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));277 if (rdev &&278 (rdev->vendor == PCI_VENDOR_ID_AMD) && (rdev->device == 0x15d0)) {279 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;280 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;281 } else if (rdev && (rdev->vendor == PCI_VENDOR_ID_AMD) &&282 (rdev->device == 0x14b5)) {283 pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;284 pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;285 286 /* Yellow Carp devices do not need cdr workaround */287 pdata->vdata->an_cdr_workaround = 0;288 289 /* Yellow Carp devices do not need rrc */290 pdata->vdata->enable_rrc = 0;291 } else {292 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;293 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;294 }295 pci_dev_put(rdev);296 297 /* Configure the PCS indirect addressing support */298 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);299 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);300 pdata->xpcs_window <<= 6;301 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);302 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);303 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;304 if (netif_msg_probe(pdata)) {305 dev_dbg(dev, "xpcs window def = %#010x\n",306 pdata->xpcs_window_def_reg);307 dev_dbg(dev, "xpcs window sel = %#010x\n",308 pdata->xpcs_window_sel_reg);309 dev_dbg(dev, "xpcs window = %#010x\n",310 pdata->xpcs_window);311 dev_dbg(dev, "xpcs window size = %#010x\n",312 pdata->xpcs_window_size);313 dev_dbg(dev, "xpcs window mask = %#010x\n",314 pdata->xpcs_window_mask);315 }316 317 pci_set_master(pdev);318 319 /* Enable all interrupts in the hardware */320 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);321 322 /* Retrieve the MAC address */323 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);324 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);325 pdata->mac_addr[0] = ma_lo & 0xff;326 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;327 pdata->mac_addr[2] = (ma_lo >> 16) & 0xff;328 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;329 pdata->mac_addr[4] = ma_hi & 0xff;330 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;331 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) ||332 !is_valid_ether_addr(pdata->mac_addr)) {333 dev_err(dev, "invalid mac address\n");334 ret = -EINVAL;335 goto err_pci_enable;336 }337 338 /* Clock settings */339 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;340 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;341 342 /* Set the DMA coherency values */343 pdata->coherent = 1;344 pdata->arcr = XGBE_DMA_PCI_ARCR;345 pdata->awcr = XGBE_DMA_PCI_AWCR;346 pdata->awarcr = XGBE_DMA_PCI_AWARCR;347 348 /* Read the port property registers */349 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);350 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);351 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);352 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);353 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);354 if (netif_msg_probe(pdata)) {355 dev_dbg(dev, "port property 0 = %#010x\n", pdata->pp0);356 dev_dbg(dev, "port property 1 = %#010x\n", pdata->pp1);357 dev_dbg(dev, "port property 2 = %#010x\n", pdata->pp2);358 dev_dbg(dev, "port property 3 = %#010x\n", pdata->pp3);359 dev_dbg(dev, "port property 4 = %#010x\n", pdata->pp4);360 }361 362 /* Set the maximum channels and queues */363 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,364 MAX_TX_DMA);365 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,366 MAX_RX_DMA);367 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,368 MAX_TX_QUEUES);369 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,370 MAX_RX_QUEUES);371 if (netif_msg_probe(pdata)) {372 dev_dbg(dev, "max tx/rx channel count = %u/%u\n",373 pdata->tx_max_channel_count,374 pdata->rx_max_channel_count);375 dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n",376 pdata->tx_max_q_count, pdata->rx_max_q_count);377 }378 379 /* Set the hardware channel and queue counts */380 xgbe_set_counts(pdata);381 382 /* Set the maximum fifo amounts */383 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,384 TX_FIFO_SIZE);385 pdata->tx_max_fifo_size *= 16384;386 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,387 pdata->vdata->tx_max_fifo_size);388 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,389 RX_FIFO_SIZE);390 pdata->rx_max_fifo_size *= 16384;391 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,392 pdata->vdata->rx_max_fifo_size);393 if (netif_msg_probe(pdata))394 dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n",395 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);396 397 /* Configure interrupt support */398 ret = xgbe_config_irqs(pdata);399 if (ret)400 goto err_pci_enable;401 402 /* Configure the netdev resource */403 ret = xgbe_config_netdev(pdata);404 if (ret)405 goto err_irq_vectors;406 407 netdev_notice(pdata->netdev, "net device enabled\n");408 409 return 0;410 411err_irq_vectors:412 pci_free_irq_vectors(pdata->pcidev);413 414err_pci_enable:415 xgbe_free_pdata(pdata);416 417err_alloc:418 dev_notice(dev, "net device not enabled\n");419 420 return ret;421}422 423static void xgbe_pci_remove(struct pci_dev *pdev)424{425 struct xgbe_prv_data *pdata = pci_get_drvdata(pdev);426 427 xgbe_deconfig_netdev(pdata);428 429 pci_free_irq_vectors(pdata->pcidev);430 431 /* Disable all interrupts in the hardware */432 XP_IOWRITE(pdata, XP_INT_EN, 0x0);433 434 xgbe_free_pdata(pdata);435}436 437static int __maybe_unused xgbe_pci_suspend(struct device *dev)438{439 struct xgbe_prv_data *pdata = dev_get_drvdata(dev);440 struct net_device *netdev = pdata->netdev;441 int ret = 0;442 443 if (netif_running(netdev))444 ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT);445 446 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);447 pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER;448 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);449 450 return ret;451}452 453static int __maybe_unused xgbe_pci_resume(struct device *dev)454{455 struct xgbe_prv_data *pdata = dev_get_drvdata(dev);456 struct net_device *netdev = pdata->netdev;457 int ret = 0;458 459 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);460 461 pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;462 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);463 464 if (netif_running(netdev)) {465 ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT);466 467 /* Schedule a restart in case the link or phy state changed468 * while we were powered down.469 */470 schedule_work(&pdata->restart_work);471 }472 473 return ret;474}475 476static struct xgbe_version_data xgbe_v2a = {477 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,478 .xpcs_access = XGBE_XPCS_ACCESS_V2,479 .mmc_64bit = 1,480 .tx_max_fifo_size = 229376,481 .rx_max_fifo_size = 229376,482 .tx_tstamp_workaround = 1,483 .ecc_support = 1,484 .i2c_support = 1,485 .irq_reissue_support = 1,486 .tx_desc_prefetch = 5,487 .rx_desc_prefetch = 5,488 .an_cdr_workaround = 1,489 .enable_rrc = 1,490};491 492static struct xgbe_version_data xgbe_v2b = {493 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,494 .xpcs_access = XGBE_XPCS_ACCESS_V2,495 .mmc_64bit = 1,496 .tx_max_fifo_size = 65536,497 .rx_max_fifo_size = 65536,498 .tx_tstamp_workaround = 1,499 .ecc_support = 1,500 .i2c_support = 1,501 .irq_reissue_support = 1,502 .tx_desc_prefetch = 5,503 .rx_desc_prefetch = 5,504 .an_cdr_workaround = 1,505 .enable_rrc = 1,506};507 508static const struct pci_device_id xgbe_pci_table[] = {509 { PCI_VDEVICE(AMD, 0x1458),510 .driver_data = (kernel_ulong_t)&xgbe_v2a },511 { PCI_VDEVICE(AMD, 0x1459),512 .driver_data = (kernel_ulong_t)&xgbe_v2b },513 /* Last entry must be zero */514 { 0, }515};516MODULE_DEVICE_TABLE(pci, xgbe_pci_table);517 518static SIMPLE_DEV_PM_OPS(xgbe_pci_pm_ops, xgbe_pci_suspend, xgbe_pci_resume);519 520static struct pci_driver xgbe_driver = {521 .name = XGBE_DRV_NAME,522 .id_table = xgbe_pci_table,523 .probe = xgbe_pci_probe,524 .remove = xgbe_pci_remove,525 .driver = {526 .pm = &xgbe_pci_pm_ops,527 }528};529 530int xgbe_pci_init(void)531{532 return pci_register_driver(&xgbe_driver);533}534 535void xgbe_pci_exit(void)536{537 pci_unregister_driver(&xgbe_driver);538}539