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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Applied Micro X-Gene SoC Ethernet v2 Driver4 *5 * Copyright (c) 2017, Applied Micro Circuits Corporation6 * Author(s): Iyappan Subramanian <isubramanian@apm.com>7 * Keyur Chudgar <kchudgar@apm.com>8 */9 10#ifndef __XGENE_ENET_V2_MAC_H__11#define __XGENE_ENET_V2_MAC_H__12 13/* Register offsets */14#define MAC_CONFIG_1 0xa00015#define MAC_CONFIG_2 0xa00416#define MII_MGMT_CONFIG 0xa02017#define MII_MGMT_COMMAND 0xa02418#define MII_MGMT_ADDRESS 0xa02819#define MII_MGMT_CONTROL 0xa02c20#define MII_MGMT_STATUS 0xa03021#define MII_MGMT_INDICATORS 0xa03422#define INTERFACE_CONTROL 0xa03823#define STATION_ADDR0 0xa04024#define STATION_ADDR1 0xa04425 26#define RGMII_REG_0 0x27e027#define ICM_CONFIG0_REG_0 0x2c0028#define ICM_CONFIG2_REG_0 0x2c0829#define ECM_CONFIG0_REG_0 0x2d0030 31/* Register fields */32#define SOFT_RESET BIT(31)33#define TX_EN BIT(0)34#define RX_EN BIT(2)35#define PAD_CRC BIT(2)36#define CRC_EN BIT(1)37#define FULL_DUPLEX BIT(0)38 39#define INTF_MODE_POS 840#define INTF_MODE_LEN 241#define HD_MODE_POS 2542#define HD_MODE_LEN 243#define CFG_MACMODE_POS 1844#define CFG_MACMODE_LEN 245#define CFG_WAITASYNCRD_POS 046#define CFG_WAITASYNCRD_LEN 1647#define CFG_SPEED_125_POS 2448#define CFG_WFIFOFULLTHR_POS 049#define CFG_WFIFOFULLTHR_LEN 750#define MGMT_CLOCK_SEL_POS 051#define MGMT_CLOCK_SEL_LEN 352#define PHY_ADDR_POS 853#define PHY_ADDR_LEN 554#define REG_ADDR_POS 055#define REG_ADDR_LEN 556#define MII_MGMT_BUSY BIT(0)57#define MII_READ_CYCLE BIT(0)58#define CFG_WAITASYNCRD_EN BIT(16)59 60static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)61{62 u32 mask = GENMASK(pos + len, pos);63 64 *var &= ~mask;65 *var |= ((val << pos) & mask);66}67 68static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)69{70 u32 mask = GENMASK(pos + len, pos);71 72 return (var & mask) >> pos;73}74 75#define SET_REG_BITS(var, field, val) \76 xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)77 78#define SET_REG_BIT(var, field, val) \79 xgene_set_reg_bits(var, field ## _POS, 1, val)80 81#define GET_REG_BITS(var, field) \82 xgene_get_reg_bits(var, field ## _POS, field ## _LEN)83 84#define GET_REG_BIT(var, field) ((var) & (field))85 86struct xge_pdata;87 88void xge_mac_reset(struct xge_pdata *pdata);89void xge_mac_set_speed(struct xge_pdata *pdata);90void xge_mac_enable(struct xge_pdata *pdata);91void xge_mac_disable(struct xge_pdata *pdata);92void xge_mac_init(struct xge_pdata *pdata);93void xge_mac_set_station_addr(struct xge_pdata *pdata);94 95#endif /* __XGENE_ENET_V2_MAC_H__ */96