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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/* Applied Micro X-Gene SoC Ethernet Driver3 *4 * Copyright (c) 2014, Applied Micro Circuits Corporation5 * Authors: Iyappan Subramanian <isubramanian@apm.com>6 * Ravi Patel <rapatel@apm.com>7 * Keyur Chudgar <kchudgar@apm.com>8 */9 10#ifndef __XGENE_ENET_HW_H__11#define __XGENE_ENET_HW_H__12 13#include "xgene_enet_main.h"14 15struct xgene_enet_pdata;16struct xgene_enet_stats;17struct xgene_enet_desc_ring;18 19/* clears and then set bits */20static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)21{22 u32 end = start + len - 1;23 u32 mask = GENMASK(end, start);24 25 *dst &= ~mask;26 *dst |= (val << start) & mask;27}28 29static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)30{31 return (val & GENMASK(end, start)) >> start;32}33 34enum xgene_enet_rm {35 RM0,36 RM1,37 RM3 = 338};39 40#define CSR_RING_ID 0x000841#define OVERWRITE BIT(31)42#define IS_BUFFER_POOL BIT(20)43#define PREFETCH_BUF_EN BIT(21)44#define CSR_RING_ID_BUF 0x000c45#define CSR_PBM_COAL 0x001446#define CSR_PBM_CTICK0 0x001847#define CSR_PBM_CTICK1 0x001c48#define CSR_PBM_CTICK2 0x002049#define CSR_PBM_CTICK3 0x002450#define CSR_THRESHOLD0_SET1 0x003051#define CSR_THRESHOLD1_SET1 0x003452#define CSR_RING_NE_INT_MODE 0x017c53#define CSR_RING_CONFIG 0x006c54#define CSR_RING_WR_BASE 0x007055#define NUM_RING_CONFIG 556#define BUFPOOL_MODE 357#define INC_DEC_CMD_ADDR 0x002c58#define UDP_HDR_SIZE 259#define BUF_LEN_CODE_2K 0x500060 61#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))62#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))63 64/* Empty slot soft signature */65#define EMPTY_SLOT_INDEX 166#define EMPTY_SLOT ~0ULL67 68#define WORK_DESC_SIZE 3269#define BUFPOOL_DESC_SIZE 1670 71#define RING_OWNER_MASK GENMASK(9, 6)72#define RING_BUFNUM_MASK GENMASK(5, 0)73 74#define SELTHRSH_POS 375#define SELTHRSH_LEN 376#define RINGADDRL_POS 577#define RINGADDRL_LEN 2778#define RINGADDRH_POS 079#define RINGADDRH_LEN 780#define RINGSIZE_POS 2381#define RINGSIZE_LEN 382#define RINGTYPE_POS 1983#define RINGTYPE_LEN 284#define RINGMODE_POS 2085#define RINGMODE_LEN 386#define RECOMTIMEOUTL_POS 2887#define RECOMTIMEOUTL_LEN 488#define RECOMTIMEOUTH_POS 089#define RECOMTIMEOUTH_LEN 390#define NUMMSGSINQ_POS 191#define NUMMSGSINQ_LEN 1692#define ACCEPTLERR BIT(19)93#define QCOHERENT BIT(4)94#define RECOMBBUF BIT(27)95 96#define MAC_OFFSET 0x3097#define OFFSET_4 0x0498#define OFFSET_8 0x0899 100#define BLOCK_ETH_CSR_OFFSET 0x2000101#define BLOCK_ETH_CLE_CSR_OFFSET 0x6000102#define BLOCK_ETH_RING_IF_OFFSET 0x9000103#define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000104#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000105#define BLOCK_ETH_MAC_OFFSET 0x0000106#define BLOCK_ETH_STATS_OFFSET 0x0000107#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800108 109#define CLKEN_ADDR 0xc208110#define SRST_ADDR 0xc200111 112#define MAC_ADDR_REG_OFFSET 0x00113#define MAC_COMMAND_REG_OFFSET 0x04114#define MAC_WRITE_REG_OFFSET 0x08115#define MAC_READ_REG_OFFSET 0x0c116#define MAC_COMMAND_DONE_REG_OFFSET 0x10117 118#define STAT_ADDR_REG_OFFSET 0x14119#define STAT_COMMAND_REG_OFFSET 0x18120#define STAT_WRITE_REG_OFFSET 0x1c121#define STAT_READ_REG_OFFSET 0x20122#define STAT_COMMAND_DONE_REG_OFFSET 0x24123 124#define PCS_ADDR_REG_OFFSET 0x00125#define PCS_COMMAND_REG_OFFSET 0x04126#define PCS_WRITE_REG_OFFSET 0x08127#define PCS_READ_REG_OFFSET 0x0c128#define PCS_COMMAND_DONE_REG_OFFSET 0x10129 130#define MII_MGMT_CONFIG_ADDR 0x20131#define MII_MGMT_COMMAND_ADDR 0x24132#define MII_MGMT_ADDRESS_ADDR 0x28133#define MII_MGMT_CONTROL_ADDR 0x2c134#define MII_MGMT_STATUS_ADDR 0x30135#define MII_MGMT_INDICATORS_ADDR 0x34136 137#define BUSY_MASK BIT(0)138#define READ_CYCLE_MASK BIT(0)139#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)140 141#define ENET_SPARE_CFG_REG_ADDR 0x0750142#define RSIF_CONFIG_REG_ADDR 0x0010143#define RSIF_RAM_DBG_REG0_ADDR 0x0048144#define RGMII_REG_0_ADDR 0x07e0145#define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8146#define DEBUG_REG_ADDR 0x0700147#define CFG_BYPASS_ADDR 0x0294148#define CLE_BYPASS_REG0_0_ADDR 0x0490149#define CLE_BYPASS_REG1_0_ADDR 0x0494150#define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)151#define RESUME_TX BIT(0)152#define CFG_SPEED_1250 BIT(24)153#define TX_PORT0 BIT(0)154#define CFG_BYPASS_UNISEC_TX BIT(2)155#define CFG_BYPASS_UNISEC_RX BIT(1)156#define CFG_CLE_BYPASS_EN0 BIT(31)157#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)158#define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)159 160#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)161#define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5)162#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)163#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)164#define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4)165#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)166#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)167#define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0))168#define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16))169#define CSR_ECM_CFG_0_ADDR 0x0220170#define CSR_ECM_CFG_1_ADDR 0x0224171#define CSR_MULTI_DPF0_ADDR 0x0230172#define RXBUF_PAUSE_THRESH 0x0534173#define RXBUF_PAUSE_OFF_THRESH 0x0540174#define DEF_PAUSE_THRES 0x7d175#define DEF_PAUSE_OFF_THRES 0x6d176#define DEF_QUANTA 0x8000177#define NORM_PAUSE_OPCODE 0x0001178#define PAUSE_XON_EN BIT(30)179#define MULTI_DPF_AUTOCTRL BIT(28)180#define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20))181#define ICM_CONFIG0_REG_0_ADDR 0x0400182#define ICM_CONFIG2_REG_0_ADDR 0x0410183#define ECM_CONFIG0_REG_0_ADDR 0x0500184#define ECM_CONFIG0_REG_1_ADDR 0x0504185#define ICM_ECM_DROP_COUNT_REG0_ADDR 0x0508186#define ICM_ECM_DROP_COUNT_REG1_ADDR 0x050c187#define RX_DV_GATE_REG_0_ADDR 0x05fc188#define TX_DV_GATE_EN0 BIT(2)189#define RX_DV_GATE_EN0 BIT(1)190#define RESUME_RX0 BIT(0)191#define ENET_CFGSSQMIFPRESET_ADDR 0x14192#define ENET_CFGSSQMIWQRESET_ADDR 0x1c193#define ENET_CFGSSQMIWQASSOC_ADDR 0xe0194#define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc195#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0196#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4197#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70198#define ENET_BLOCK_MEM_RDY_ADDR 0x74199#define MAC_CONFIG_1_ADDR 0x00200#define MAC_CONFIG_2_ADDR 0x04201#define MAX_FRAME_LEN_ADDR 0x10202#define INTERFACE_CONTROL_ADDR 0x38203#define STATION_ADDR0_ADDR 0x40204#define STATION_ADDR1_ADDR 0x44205#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)206#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)207#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)208#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)209#define SOFT_RESET1 BIT(31)210#define TX_EN BIT(0)211#define RX_EN BIT(2)212#define TX_FLOW_EN BIT(4)213#define RX_FLOW_EN BIT(5)214#define ENET_LHD_MODE BIT(25)215#define ENET_GHD_MODE BIT(26)216#define FULL_DUPLEX2 BIT(0)217#define PAD_CRC BIT(2)218#define LENGTH_CHK BIT(4)219 220#define TR64_ADDR 0x20221#define TR127_ADDR 0x21222#define TR255_ADDR 0x22223#define TR511_ADDR 0x23224#define TR1K_ADDR 0x24225#define TRMAX_ADDR 0x25226#define TRMGV_ADDR 0x26227 228#define RFCS_ADDR 0x29229#define RMCA_ADDR 0x2a230#define RBCA_ADDR 0x2b231#define RXCF_ADDR 0x2c232#define RXPF_ADDR 0x2d233#define RXUO_ADDR 0x2e234#define RALN_ADDR 0x2f235#define RFLR_ADDR 0x30236#define RCDE_ADDR 0x31237#define RCSE_ADDR 0x32238#define RUND_ADDR 0x33239#define ROVR_ADDR 0x34240#define RFRG_ADDR 0x35241#define RJBR_ADDR 0x36242#define RDRP_ADDR 0x37243 244#define TMCA_ADDR 0x3a245#define TBCA_ADDR 0x3b246#define TXPF_ADDR 0x3c247#define TDFR_ADDR 0x3d248#define TEDF_ADDR 0x3e249#define TSCL_ADDR 0x3f250#define TMCL_ADDR 0x40251#define TLCL_ADDR 0x41252#define TXCL_ADDR 0x42253#define TNCL_ADDR 0x43254#define TPFH_ADDR 0x44255#define TDRP_ADDR 0x45256#define TJBR_ADDR 0x46257#define TFCS_ADDR 0x47258#define TXCF_ADDR 0x48259#define TOVR_ADDR 0x49260#define TUND_ADDR 0x4a261#define TFRG_ADDR 0x4b262#define DUMP_ADDR 0x27263 264#define ECM_DROP_COUNT(src) xgene_get_bits(src, 0, 15)265#define ICM_DROP_COUNT(src) xgene_get_bits(src, 16, 31)266 267#define TSO_IPPROTO_TCP 1268 269#define USERINFO_POS 0270#define USERINFO_LEN 32271#define FPQNUM_POS 32272#define FPQNUM_LEN 12273#define ELERR_POS 46274#define ELERR_LEN 2275#define NV_POS 50276#define NV_LEN 1277#define LL_POS 51278#define LL_LEN 1279#define LERR_POS 60280#define LERR_LEN 3281#define STASH_POS 52282#define STASH_LEN 2283#define BUFDATALEN_POS 48284#define BUFDATALEN_LEN 15285#define DATAADDR_POS 0286#define DATAADDR_LEN 42287#define COHERENT_POS 63288#define HENQNUM_POS 48289#define HENQNUM_LEN 12290#define TYPESEL_POS 44291#define TYPESEL_LEN 4292#define ETHHDR_POS 12293#define ETHHDR_LEN 8294#define IC_POS 35 /* Insert CRC */295#define TCPHDR_POS 0296#define TCPHDR_LEN 6297#define IPHDR_POS 6298#define IPHDR_LEN 6299#define MSS_POS 20300#define MSS_LEN 2301#define EC_POS 22 /* Enable checksum */302#define EC_LEN 1303#define ET_POS 23 /* Enable TSO */304#define IS_POS 24 /* IP protocol select */305#define IS_LEN 1306#define TYPE_ETH_WORK_MESSAGE_POS 44307#define LL_BYTES_MSB_POS 56308#define LL_BYTES_MSB_LEN 8309#define LL_BYTES_LSB_POS 48310#define LL_BYTES_LSB_LEN 12311#define LL_LEN_POS 48312#define LL_LEN_LEN 8313#define DATALEN_MASK GENMASK(11, 0)314 315#define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS)316 317#define TSO_MSS0_POS 0318#define TSO_MSS0_LEN 14319#define TSO_MSS1_POS 16320#define TSO_MSS1_LEN 14321 322struct xgene_enet_raw_desc {323 __le64 m0;324 __le64 m1;325 __le64 m2;326 __le64 m3;327};328 329struct xgene_enet_raw_desc16 {330 __le64 m0;331 __le64 m1;332};333 334static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)335{336 __le64 *desc_slot = desc_slot_ptr;337 338 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);339}340 341static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)342{343 __le64 *desc_slot = desc_slot_ptr;344 345 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));346}347 348enum xgene_enet_ring_cfgsize {349 RING_CFGSIZE_512B,350 RING_CFGSIZE_2KB,351 RING_CFGSIZE_16KB,352 RING_CFGSIZE_64KB,353 RING_CFGSIZE_512KB,354 RING_CFGSIZE_INVALID355};356 357enum xgene_enet_ring_type {358 RING_DISABLED,359 RING_REGULAR,360 RING_BUFPOOL361};362 363enum xgene_ring_owner {364 RING_OWNER_ETH0,365 RING_OWNER_ETH1,366 RING_OWNER_CPU = 15,367 RING_OWNER_INVALID368};369 370enum xgene_enet_ring_bufnum {371 RING_BUFNUM_REGULAR = 0x0,372 RING_BUFNUM_BUFPOOL = 0x20,373 RING_BUFNUM_INVALID374};375 376enum xgene_enet_err_code {377 HBF_READ_DATA = 3,378 HBF_LL_READ = 4,379 BAD_WORK_MSG = 6,380 BUFPOOL_TIMEOUT = 15,381 INGRESS_CRC = 16,382 INGRESS_CHECKSUM = 17,383 INGRESS_TRUNC_FRAME = 18,384 INGRESS_PKT_LEN = 19,385 INGRESS_PKT_UNDER = 20,386 INGRESS_FIFO_OVERRUN = 21,387 INGRESS_CHECKSUM_COMPUTE = 26,388 ERR_CODE_INVALID389};390 391static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)392{393 return (id & RING_OWNER_MASK) >> 6;394}395 396static inline u8 xgene_enet_ring_bufnum(u16 id)397{398 return id & RING_BUFNUM_MASK;399}400 401static inline bool xgene_enet_is_bufpool(u16 id)402{403 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;404}405 406static inline u8 xgene_enet_get_fpsel(u16 id)407{408 if (xgene_enet_is_bufpool(id))409 return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL;410 411 return 0;412}413 414static inline u16 xgene_enet_get_numslots(u16 id, u32 size)415{416 bool is_bufpool = xgene_enet_is_bufpool(id);417 418 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :419 size / WORK_DESC_SIZE;420}421 422void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,423 enum xgene_enet_err_code status);424int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);425void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);426bool xgene_ring_mgr_init(struct xgene_enet_pdata *p);427int xgene_enet_phy_connect(struct net_device *ndev);428void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata);429u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr);430void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr,431 u32 wr_data);432u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr);433 434extern const struct xgene_mac_ops xgene_gmac_ops;435extern const struct xgene_port_ops xgene_gport_ops;436extern struct xgene_ring_ops xgene_ring1_ops;437 438#endif /* __XGENE_ENET_HW_H__ */439