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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Atlantic Network Driver3 *4 * Copyright (C) 2014-2019 aQuantia Corporation5 * Copyright (C) 2019-2020 Marvell International Ltd.6 */7 8/* File aq_hw.h: Declaration of abstract interface for NIC hardware specific9 * functions.10 */11 12#ifndef AQ_HW_H13#define AQ_HW_H14 15#include "aq_common.h"16#include "aq_rss.h"17#include "hw_atl/hw_atl_utils.h"18 19#define AQ_HW_MAC_COUNTER_HZ 312500000ll20#define AQ_HW_PHY_COUNTER_HZ 160000000ll21 22enum aq_tc_mode {23 AQ_TC_MODE_INVALID = -1,24 AQ_TC_MODE_8TCS,25 AQ_TC_MODE_4TCS,26};27 28#define AQ_RX_FIRST_LOC_FVLANID 0U29#define AQ_RX_LAST_LOC_FVLANID 15U30#define AQ_RX_FIRST_LOC_FETHERT 16U31#define AQ_RX_LAST_LOC_FETHERT 31U32#define AQ_RX_FIRST_LOC_FL3L4 32U33#define AQ_RX_LAST_LOC_FL3L4 39U34#define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L435#define AQ_VLAN_MAX_FILTERS \36 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U)37#define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU38 39#define AQ_FRAC_PER_NS 0x100000000LL40 41/* Used for rate to Mbps conversion */42#define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */43 44/* NIC H/W capabilities */45struct aq_hw_caps_s {46 u64 hw_features;47 u64 link_speed_msk;48 unsigned int hw_priv_flags;49 u32 media_type;50 u32 rxds_max;51 u32 txds_max;52 u32 rxds_min;53 u32 txds_min;54 u32 txhwb_alignment;55 u32 irq_mask;56 u32 vecs;57 u32 mtu;58 u32 mac_regs_count;59 u32 hw_alive_check_addr;60 u8 msix_irqs;61 u8 tcs_max;62 u8 rxd_alignment;63 u8 rxd_size;64 u8 txd_alignment;65 u8 txd_size;66 u8 tx_rings;67 u8 rx_rings;68 bool flow_control;69 bool is_64_dma;70 bool op64bit;71 u32 quirks;72 u32 priv_data_len;73};74 75struct aq_hw_link_status_s {76 unsigned int mbps;77 bool full_duplex;78 u32 lp_link_speed_msk;79 u32 lp_flow_control;80};81 82struct aq_stats_s {83 u64 brc;84 u64 btc;85 u64 uprc;86 u64 mprc;87 u64 bprc;88 u64 erpt;89 u64 uptc;90 u64 mptc;91 u64 bptc;92 u64 erpr;93 u64 mbtc;94 u64 bbtc;95 u64 mbrc;96 u64 bbrc;97 u64 ubrc;98 u64 ubtc;99 u64 dpc;100 u64 dma_pkt_rc;101 u64 dma_pkt_tc;102 u64 dma_oct_rc;103 u64 dma_oct_tc;104};105 106#define AQ_HW_IRQ_INVALID 0U107#define AQ_HW_IRQ_INTX 1U108#define AQ_HW_IRQ_MSI 2U109#define AQ_HW_IRQ_MSIX 3U110 111#define AQ_HW_SERVICE_IRQS 1U112 113#define AQ_HW_POWER_STATE_D0 0U114#define AQ_HW_POWER_STATE_D3 3U115 116#define AQ_HW_FLAG_STARTED 0x00000004U117#define AQ_HW_FLAG_STOPPING 0x00000008U118#define AQ_HW_FLAG_RESETTING 0x00000010U119#define AQ_HW_FLAG_CLOSING 0x00000020U120#define AQ_HW_PTP_AVAILABLE 0x01000000U121#define AQ_HW_LINK_DOWN 0x04000000U122#define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U123#define AQ_HW_FLAG_ERR_HW 0x80000000U124 125#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)126 127#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \128 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \129 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)130 131#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \132 AQ_NIC_LINK_DOWN)133 134#define AQ_HW_MEDIA_TYPE_TP 1U135#define AQ_HW_MEDIA_TYPE_FIBRE 2U136 137#define AQ_HW_TXD_MULTIPLE 8U138#define AQ_HW_RXD_MULTIPLE 8U139 140#define AQ_HW_QUEUES_MAX 32U141#define AQ_HW_MULTICAST_ADDRESS_MAX 32U142 143#define AQ_HW_PTP_TC 2U144 145#define AQ_HW_LED_BLINK 0x2U146#define AQ_HW_LED_DEFAULT 0x0U147 148#define AQ_HW_MEDIA_DETECT_CNT 6000149 150enum aq_priv_flags {151 AQ_HW_LOOPBACK_DMA_SYS,152 AQ_HW_LOOPBACK_PKT_SYS,153 AQ_HW_LOOPBACK_DMA_NET,154 AQ_HW_LOOPBACK_PHYINT_SYS,155 AQ_HW_LOOPBACK_PHYEXT_SYS,156};157 158#define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\159 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\160 BIT(AQ_HW_LOOPBACK_DMA_NET) |\161 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\162 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS))163 164#define ATL_HW_CHIP_MIPS 0x00000001U165#define ATL_HW_CHIP_TPO2 0x00000002U166#define ATL_HW_CHIP_RPF2 0x00000004U167#define ATL_HW_CHIP_MPI_AQ 0x00000010U168#define ATL_HW_CHIP_ATLANTIC 0x00800000U169#define ATL_HW_CHIP_REVISION_A0 0x01000000U170#define ATL_HW_CHIP_REVISION_B0 0x02000000U171#define ATL_HW_CHIP_REVISION_B1 0x04000000U172#define ATL_HW_CHIP_ANTIGUA 0x08000000U173 174#define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \175 (_HW_)->chip_features))176 177struct aq_hw_s {178 atomic_t flags;179 u8 rbl_enabled:1;180 struct aq_nic_cfg_s *aq_nic_cfg;181 const struct aq_fw_ops *aq_fw_ops;182 void __iomem *mmio;183 struct aq_hw_link_status_s aq_link_status;184 struct hw_atl_utils_mbox mbox;185 struct hw_atl_stats_s last_stats;186 struct aq_stats_s curr_stats;187 u64 speed;188 u32 itr_tx;189 u32 itr_rx;190 unsigned int chip_features;191 u32 fw_ver_actual;192 atomic_t dpc;193 u32 mbox_addr;194 u32 rpc_addr;195 u32 settings_addr;196 u32 rpc_tid;197 struct hw_atl_utils_fw_rpc rpc;198 s64 ptp_clk_offset;199 u16 phy_id;200 void *priv;201};202 203struct aq_ring_s;204struct aq_ring_param_s;205struct sk_buff;206struct aq_rx_filter_l3l4;207 208struct aq_hw_ops {209 210 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,211 unsigned int frags);212 213 int (*hw_ring_rx_receive)(struct aq_hw_s *self,214 struct aq_ring_s *aq_ring);215 216 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,217 unsigned int sw_tail_old);218 219 int (*hw_ring_tx_head_update)(struct aq_hw_s *self,220 struct aq_ring_s *aq_ring);221 222 int (*hw_set_mac_address)(struct aq_hw_s *self, const u8 *mac_addr);223 224 int (*hw_soft_reset)(struct aq_hw_s *self);225 226 int (*hw_prepare)(struct aq_hw_s *self,227 const struct aq_fw_ops **fw_ops);228 229 int (*hw_reset)(struct aq_hw_s *self);230 231 int (*hw_init)(struct aq_hw_s *self, const u8 *mac_addr);232 233 int (*hw_start)(struct aq_hw_s *self);234 235 int (*hw_stop)(struct aq_hw_s *self);236 237 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,238 struct aq_ring_param_s *aq_ring_param);239 240 int (*hw_ring_tx_start)(struct aq_hw_s *self,241 struct aq_ring_s *aq_ring);242 243 int (*hw_ring_tx_stop)(struct aq_hw_s *self,244 struct aq_ring_s *aq_ring);245 246 int (*hw_ring_rx_init)(struct aq_hw_s *self,247 struct aq_ring_s *aq_ring,248 struct aq_ring_param_s *aq_ring_param);249 250 int (*hw_ring_rx_start)(struct aq_hw_s *self,251 struct aq_ring_s *aq_ring);252 253 int (*hw_ring_rx_stop)(struct aq_hw_s *self,254 struct aq_ring_s *aq_ring);255 256 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask);257 258 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask);259 260 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask);261 262 int (*hw_packet_filter_set)(struct aq_hw_s *self,263 unsigned int packet_filter);264 265 int (*hw_filter_l3l4_set)(struct aq_hw_s *self,266 struct aq_rx_filter_l3l4 *data);267 268 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self,269 struct aq_rx_filter_l3l4 *data);270 271 int (*hw_filter_l2_set)(struct aq_hw_s *self,272 struct aq_rx_filter_l2 *data);273 274 int (*hw_filter_l2_clear)(struct aq_hw_s *self,275 struct aq_rx_filter_l2 *data);276 277 int (*hw_filter_vlan_set)(struct aq_hw_s *self,278 struct aq_rx_filter_vlan *aq_vlans);279 280 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable);281 282 int (*hw_multicast_list_set)(struct aq_hw_s *self,283 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX]284 [ETH_ALEN],285 u32 count);286 287 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self);288 289 int (*hw_rss_set)(struct aq_hw_s *self,290 struct aq_rss_parameters *rss_params);291 292 int (*hw_rss_hash_set)(struct aq_hw_s *self,293 struct aq_rss_parameters *rss_params);294 295 int (*hw_tc_rate_limit_set)(struct aq_hw_s *self);296 297 int (*hw_get_regs)(struct aq_hw_s *self,298 const struct aq_hw_caps_s *aq_hw_caps,299 u32 *regs_buff);300 301 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self);302 303 u32 (*hw_get_fw_version)(struct aq_hw_s *self);304 305 int (*hw_set_offload)(struct aq_hw_s *self,306 struct aq_nic_cfg_s *aq_nic_cfg);307 308 int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self,309 struct aq_ring_s *aq_ring);310 311 int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self,312 struct aq_ring_s *ring);313 314 void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp);315 316 int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta);317 318 int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta);319 320 int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts);321 322 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time);323 324 int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start,325 u32 period);326 327 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index,328 u32 enable);329 330 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts);331 332 u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len,333 u64 *timestamp);334 335 int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len,336 u64 *timestamp);337 338 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc);339 340 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable);341 342 int (*hw_get_mac_temp)(struct aq_hw_s *self, u32 *temp);343};344 345struct aq_fw_ops {346 int (*init)(struct aq_hw_s *self);347 348 int (*deinit)(struct aq_hw_s *self);349 350 int (*reset)(struct aq_hw_s *self);351 352 int (*renegotiate)(struct aq_hw_s *self);353 354 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);355 356 int (*set_link_speed)(struct aq_hw_s *self, u32 speed);357 358 int (*set_state)(struct aq_hw_s *self,359 enum hal_atl_utils_fw_state_e state);360 361 int (*update_link_status)(struct aq_hw_s *self);362 363 int (*update_stats)(struct aq_hw_s *self);364 365 int (*get_mac_temp)(struct aq_hw_s *self, int *temp);366 367 int (*get_phy_temp)(struct aq_hw_s *self, int *temp);368 369 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode);370 371 int (*set_flow_control)(struct aq_hw_s *self);372 373 int (*led_control)(struct aq_hw_s *self, u32 mode);374 375 int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable);376 377 int (*set_power)(struct aq_hw_s *self, unsigned int power_state,378 const u8 *mac);379 380 int (*send_fw_request)(struct aq_hw_s *self,381 const struct hw_fw_request_iface *fw_req,382 size_t size);383 384 void (*enable_ptp)(struct aq_hw_s *self, int enable);385 386 void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj);387 388 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed);389 390 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate,391 u32 *supported_rates);392 393 int (*set_downshift)(struct aq_hw_s *self, u32 counter);394 395 int (*set_media_detect)(struct aq_hw_s *self, bool enable);396 397 u32 (*get_link_capabilities)(struct aq_hw_s *self);398 399 int (*send_macsec_req)(struct aq_hw_s *self,400 struct macsec_msg_fw_request *msg,401 struct macsec_msg_fw_response *resp);402};403 404#endif /* AQ_HW_H */405