258 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __BCMASP_INTF_DEFS_H3#define __BCMASP_INTF_DEFS_H4 5#define UMC_OFFSET(intf) \6 ((((intf)->port) * 0x800) + 0xc000)7#define UMC_CMD 0x0088#define UMC_CMD_TX_EN BIT(0)9#define UMC_CMD_RX_EN BIT(1)10#define UMC_CMD_SPEED_SHIFT 0x211#define UMC_CMD_SPEED_MASK 0x312#define UMC_CMD_SPEED_10 0x013#define UMC_CMD_SPEED_100 0x114#define UMC_CMD_SPEED_1000 0x215#define UMC_CMD_SPEED_2500 0x316#define UMC_CMD_PROMISC BIT(4)17#define UMC_CMD_PAD_EN BIT(5)18#define UMC_CMD_CRC_FWD BIT(6)19#define UMC_CMD_PAUSE_FWD BIT(7)20#define UMC_CMD_RX_PAUSE_IGNORE BIT(8)21#define UMC_CMD_TX_ADDR_INS BIT(9)22#define UMC_CMD_HD_EN BIT(10)23#define UMC_CMD_SW_RESET BIT(13)24#define UMC_CMD_LCL_LOOP_EN BIT(15)25#define UMC_CMD_AUTO_CONFIG BIT(22)26#define UMC_CMD_CNTL_FRM_EN BIT(23)27#define UMC_CMD_NO_LEN_CHK BIT(24)28#define UMC_CMD_RMT_LOOP_EN BIT(25)29#define UMC_CMD_PRBL_EN BIT(27)30#define UMC_CMD_TX_PAUSE_IGNORE BIT(28)31#define UMC_CMD_TX_RX_EN BIT(29)32#define UMC_CMD_RUNT_FILTER_DIS BIT(30)33#define UMC_MAC0 0x0c34#define UMC_MAC1 0x1035#define UMC_FRM_LEN 0x1436#define UMC_EEE_CTRL 0x6437#define EN_LPI_RX_PAUSE BIT(0)38#define EN_LPI_TX_PFC BIT(1)39#define EN_LPI_TX_PAUSE BIT(2)40#define EEE_EN BIT(3)41#define RX_FIFO_CHECK BIT(4)42#define EEE_TX_CLK_DIS BIT(5)43#define DIS_EEE_10M BIT(6)44#define LP_IDLE_PREDICTION_MODE BIT(7)45#define UMC_EEE_LPI_TIMER 0x6846#define UMC_PAUSE_CNTRL 0x33047#define UMC_TX_FLUSH 0x33448#define UMC_GR64 0x40049#define UMC_GR127 0x40450#define UMC_GR255 0x40851#define UMC_GR511 0x40c52#define UMC_GR1023 0x41053#define UMC_GR1518 0x41454#define UMC_GRMGV 0x41855#define UMC_GR2047 0x41c56#define UMC_GR4095 0x42057#define UMC_GR9216 0x42458#define UMC_GRPKT 0x42859#define UMC_GRBYT 0x42c60#define UMC_GRMCA 0x43061#define UMC_GRBCA 0x43462#define UMC_GRFCS 0x43863#define UMC_GRXCF 0x43c64#define UMC_GRXPF 0x44065#define UMC_GRXUO 0x44466#define UMC_GRALN 0x44867#define UMC_GRFLR 0x44c68#define UMC_GRCDE 0x45069#define UMC_GRFCR 0x45470#define UMC_GROVR 0x45871#define UMC_GRJBR 0x45c72#define UMC_GRMTUE 0x46073#define UMC_GRPOK 0x46474#define UMC_GRUC 0x46875#define UMC_GRPPP 0x46c76#define UMC_GRMCRC 0x47077#define UMC_TR64 0x48078#define UMC_TR127 0x48479#define UMC_TR255 0x48880#define UMC_TR511 0x48c81#define UMC_TR1023 0x49082#define UMC_TR1518 0x49483#define UMC_TRMGV 0x49884#define UMC_TR2047 0x49c85#define UMC_TR4095 0x4a086#define UMC_TR9216 0x4a487#define UMC_GTPKT 0x4a888#define UMC_GTMCA 0x4ac89#define UMC_GTBCA 0x4b090#define UMC_GTXPF 0x4b491#define UMC_GTXCF 0x4b892#define UMC_GTFCS 0x4bc93#define UMC_GTOVR 0x4c094#define UMC_GTDRF 0x4c495#define UMC_GTEDF 0x4c896#define UMC_GTSCL 0x4cc97#define UMC_GTMCL 0x4d098#define UMC_GTLCL 0x4d499#define UMC_GTXCL 0x4d8100#define UMC_GTFRG 0x4dc101#define UMC_GTNCL 0x4e0102#define UMC_GTJBR 0x4e4103#define UMC_GTBYT 0x4e8104#define UMC_GTPOK 0x4ec105#define UMC_GTUC 0x4f0106#define UMC_RRPKT 0x500107#define UMC_RRUND 0x504108#define UMC_RRFRG 0x508109#define UMC_RRBYT 0x50c110#define UMC_MIB_CNTRL 0x580111#define UMC_MIB_CNTRL_RX_CNT_RST BIT(0)112#define UMC_MIB_CNTRL_RUNT_CNT_RST BIT(1)113#define UMC_MIB_CNTRL_TX_CNT_RST BIT(2)114#define UMC_RX_MAX_PKT_SZ 0x608115#define UMC_MPD_CTRL 0x620116#define UMC_MPD_CTRL_MPD_EN BIT(0)117#define UMC_MPD_CTRL_PSW_EN BIT(27)118#define UMC_PSW_MS 0x624119#define UMC_PSW_LS 0x628120 121#define UMAC2FB_OFFSET_2_1 0x9f044122#define UMAC2FB_OFFSET 0x9f03c123#define UMAC2FB_CFG 0x0124#define UMAC2FB_CFG_OPUT_EN BIT(0)125#define UMAC2FB_CFG_VLAN_EN BIT(1)126#define UMAC2FB_CFG_SNAP_EN BIT(2)127#define UMAC2FB_CFG_BCM_TG_EN BIT(3)128#define UMAC2FB_CFG_IPUT_EN BIT(4)129#define UMAC2FB_CFG_CHID_SHIFT 8130#define UMAC2FB_CFG_OK_SEND_SHIFT 24131#define UMAC2FB_CFG_DEFAULT_EN \132 (UMAC2FB_CFG_OPUT_EN | UMAC2FB_CFG_VLAN_EN \133 | UMAC2FB_CFG_SNAP_EN | UMAC2FB_CFG_IPUT_EN)134 135#define RGMII_OFFSET(intf) \136 ((((intf)->port) * 0x100) + 0xd000)137#define RGMII_EPHY_CNTRL 0x00138#define RGMII_EPHY_CFG_IDDQ_BIAS BIT(0)139#define RGMII_EPHY_CFG_EXT_PWRDOWN BIT(1)140#define RGMII_EPHY_CFG_FORCE_DLL_EN BIT(2)141#define RGMII_EPHY_CFG_IDDQ_GLOBAL BIT(3)142#define RGMII_EPHY_CK25_DIS BIT(4)143#define RGMII_EPHY_RESET BIT(7)144#define RGMII_OOB_CNTRL 0x0c145#define RGMII_LINK BIT(4)146#define RGMII_OOB_DIS BIT(5)147#define RGMII_MODE_EN BIT(6)148#define RGMII_ID_MODE_DIS BIT(16)149 150#define RGMII_PORT_CNTRL 0x60151#define RGMII_PORT_MODE_EPHY 0152#define RGMII_PORT_MODE_GPHY 1153#define RGMII_PORT_MODE_EXT_EPHY 2154#define RGMII_PORT_MODE_EXT_GPHY 3155#define RGMII_PORT_MODE_EXT_RVMII 4156#define RGMII_PORT_MODE_MASK GENMASK(2, 0)157 158#define RGMII_SYS_LED_CNTRL 0x74159#define RGMII_SYS_LED_CNTRL_LINK_OVRD BIT(15)160 161#define TX_SPB_DMA_OFFSET(intf) \162 ((((intf)->channel) * 0x30) + 0x48180)163#define TX_SPB_DMA_READ 0x00164#define TX_SPB_DMA_BASE 0x08165#define TX_SPB_DMA_END 0x10166#define TX_SPB_DMA_VALID 0x18167#define TX_SPB_DMA_FIFO_CTRL 0x20168#define TX_SPB_DMA_FIFO_FLUSH BIT(0)169#define TX_SPB_DMA_FIFO_STATUS 0x24170 171#define TX_SPB_CTRL_OFFSET(intf) \172 ((((intf)->channel) * 0x68) + 0x49340)173#define TX_SPB_CTRL_ENABLE 0x0174#define TX_SPB_CTRL_ENABLE_EN BIT(0)175#define TX_SPB_CTRL_XF_CTRL2 0x20176#define TX_SPB_CTRL_XF_BID_SHIFT 16177 178#define TX_SPB_TOP_OFFSET(intf) \179 ((((intf)->channel) * 0x1c) + 0x4a0e0)180#define TX_SPB_TOP_BLKOUT 0x0181#define TX_SPB_TOP_SPRE_BW_CTRL 0x4182 183#define TX_EPKT_C_OFFSET(intf) \184 ((((intf)->channel) * 0x120) + 0x40900)185#define TX_EPKT_C_CFG_MISC 0x0186#define TX_EPKT_C_CFG_MISC_EN BIT(0)187#define TX_EPKT_C_CFG_MISC_PT BIT(1)188#define TX_EPKT_C_CFG_MISC_PS_SHIFT 14189#define TX_EPKT_C_CFG_MISC_FD_SHIFT 20190 191#define TX_PAUSE_CTRL_OFFSET(intf) \192 ((((intf)->channel * 0xc) + 0x49a20))193#define TX_PAUSE_MAP_VECTOR 0x8194 195#define RX_EDPKT_DMA_OFFSET(intf) \196 ((((intf)->channel) * 0x38) + 0x9ca00)197#define RX_EDPKT_DMA_WRITE 0x00198#define RX_EDPKT_DMA_READ 0x08199#define RX_EDPKT_DMA_BASE 0x10200#define RX_EDPKT_DMA_END 0x18201#define RX_EDPKT_DMA_VALID 0x20202#define RX_EDPKT_DMA_FULLNESS 0x28203#define RX_EDPKT_DMA_MIN_THRES 0x2c204#define RX_EDPKT_DMA_CH_XONOFF 0x30205 206#define RX_EDPKT_CFG_OFFSET(intf) \207 ((((intf)->channel) * 0x70) + 0x9c600)208#define RX_EDPKT_CFG_CFG0 0x0209#define RX_EDPKT_CFG_CFG0_DBUF_SHIFT 9210#define RX_EDPKT_CFG_CFG0_RBUF 0x0211#define RX_EDPKT_CFG_CFG0_RBUF_4K 0x1212#define RX_EDPKT_CFG_CFG0_BUF_4K 0x2213/* EFRM STUFF, 0 = no byte stuff, 1 = two byte stuff */214#define RX_EDPKT_CFG_CFG0_EFRM_STUF BIT(11)215#define RX_EDPKT_CFG_CFG0_BALN_SHIFT 12216#define RX_EDPKT_CFG_CFG0_NO_ALN 0217#define RX_EDPKT_CFG_CFG0_4_ALN 2218#define RX_EDPKT_CFG_CFG0_64_ALN 6219#define RX_EDPKT_RING_BUFFER_WRITE 0x38220#define RX_EDPKT_RING_BUFFER_READ 0x40221#define RX_EDPKT_RING_BUFFER_BASE 0x48222#define RX_EDPKT_RING_BUFFER_END 0x50223#define RX_EDPKT_RING_BUFFER_VALID 0x58224#define RX_EDPKT_CFG_ENABLE 0x6c225#define RX_EDPKT_CFG_ENABLE_EN BIT(0)226 227#define RX_SPB_DMA_OFFSET(intf) \228 ((((intf)->channel) * 0x30) + 0xa0000)229#define RX_SPB_DMA_READ 0x00230#define RX_SPB_DMA_BASE 0x08231#define RX_SPB_DMA_END 0x10232#define RX_SPB_DMA_VALID 0x18233#define RX_SPB_DMA_FIFO_CTRL 0x20234#define RX_SPB_DMA_FIFO_FLUSH BIT(0)235#define RX_SPB_DMA_FIFO_STATUS 0x24236 237#define RX_SPB_CTRL_OFFSET(intf) \238 ((((intf)->channel - 6) * 0x68) + 0xa1000)239#define RX_SPB_CTRL_ENABLE 0x00240#define RX_SPB_CTRL_ENABLE_EN BIT(0)241 242#define RX_PAUSE_CTRL_OFFSET(intf) \243 ((((intf)->channel - 6) * 0x4) + 0xa1138)244#define RX_PAUSE_MAP_VECTOR 0x00245 246#define RX_SPB_TOP_CTRL_OFFSET(intf) \247 ((((intf)->channel - 6) * 0x14) + 0xa2000)248#define RX_SPB_TOP_BLKOUT 0x00249 250#define NUM_4K_BUFFERS 32251#define RING_BUFFER_SIZE (PAGE_SIZE * NUM_4K_BUFFERS)252 253#define DESC_RING_COUNT (64 * NUM_4K_BUFFERS)254#define DESC_SIZE 16255#define DESC_RING_SIZE (DESC_RING_COUNT * DESC_SIZE)256 257#endif258