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1/* bnx2.h: QLogic bnx2 network driver.2 *3 * Copyright (c) 2004-2014 Broadcom Corporation4 * Copyright (c) 2014-2015 QLogic Corporation5 *6 * This program is free software; you can redistribute it and/or modify7 * it under the terms of the GNU General Public License as published by8 * the Free Software Foundation.9 *10 * Written by: Michael Chan  (mchan@broadcom.com)11 */12 13 14#ifndef BNX2_H15#define BNX2_H16 17/* Hardware data structures and register definitions automatically18 * generated from RTL code. Do not modify.19 */20 21/*22 *  tx_bd definition23 */24struct bnx2_tx_bd {25	u32 tx_bd_haddr_hi;26	u32 tx_bd_haddr_lo;27	u32 tx_bd_mss_nbytes;28		#define TX_BD_TCP6_OFF2_SHL		(14)29	u32 tx_bd_vlan_tag_flags;30		#define TX_BD_FLAGS_CONN_FAULT		(1<<0)31		#define TX_BD_FLAGS_TCP6_OFF0_MSK	(3<<1)32		#define TX_BD_FLAGS_TCP6_OFF0_SHL	(1)33		#define TX_BD_FLAGS_TCP_UDP_CKSUM	(1<<1)34		#define TX_BD_FLAGS_IP_CKSUM		(1<<2)35		#define TX_BD_FLAGS_VLAN_TAG		(1<<3)36		#define TX_BD_FLAGS_COAL_NOW		(1<<4)37		#define TX_BD_FLAGS_DONT_GEN_CRC	(1<<5)38		#define TX_BD_FLAGS_END			(1<<6)39		#define TX_BD_FLAGS_START		(1<<7)40		#define TX_BD_FLAGS_SW_OPTION_WORD	(0x1f<<8)41		#define TX_BD_FLAGS_TCP6_OFF4_SHL	(12)42		#define TX_BD_FLAGS_SW_FLAGS		(1<<13)43		#define TX_BD_FLAGS_SW_SNAP		(1<<14)44		#define TX_BD_FLAGS_SW_LSO		(1<<15)45 46};47 48 49/*50 *  rx_bd definition51 */52struct bnx2_rx_bd {53	u32 rx_bd_haddr_hi;54	u32 rx_bd_haddr_lo;55	u32 rx_bd_len;56	u32 rx_bd_flags;57		#define RX_BD_FLAGS_NOPUSH		(1<<0)58		#define RX_BD_FLAGS_DUMMY		(1<<1)59		#define RX_BD_FLAGS_END			(1<<2)60		#define RX_BD_FLAGS_START		(1<<3)61 62};63 64#define BNX2_RX_ALIGN			1665 66/*67 *  status_block definition68 */69struct status_block {70	u32 status_attn_bits;71		#define STATUS_ATTN_BITS_LINK_STATE		(1L<<0)72		#define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT	(1L<<1)73		#define STATUS_ATTN_BITS_TX_BD_READ_ABORT	(1L<<2)74		#define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT	(1L<<3)75		#define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT	(1L<<4)76		#define STATUS_ATTN_BITS_TX_DMA_ABORT		(1L<<5)77		#define STATUS_ATTN_BITS_TX_PATCHUP_ABORT	(1L<<6)78		#define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT	(1L<<7)79		#define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT	(1L<<8)80		#define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT	(1L<<9)81		#define STATUS_ATTN_BITS_RX_MBUF_ABORT		(1L<<10)82		#define STATUS_ATTN_BITS_RX_LOOKUP_ABORT	(1L<<11)83		#define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT	(1L<<12)84		#define STATUS_ATTN_BITS_RX_V2P_ABORT		(1L<<13)85		#define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT	(1L<<14)86		#define STATUS_ATTN_BITS_RX_DMA_ABORT		(1L<<15)87		#define STATUS_ATTN_BITS_COMPLETION_ABORT	(1L<<16)88		#define STATUS_ATTN_BITS_HOST_COALESCE_ABORT	(1L<<17)89		#define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT	(1L<<18)90		#define STATUS_ATTN_BITS_CONTEXT_ABORT		(1L<<19)91		#define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT	(1L<<20)92		#define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT	(1L<<21)93		#define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT	(1L<<22)94		#define STATUS_ATTN_BITS_MAC_ABORT		(1L<<23)95		#define STATUS_ATTN_BITS_TIMER_ABORT		(1L<<24)96		#define STATUS_ATTN_BITS_DMAE_ABORT		(1L<<25)97		#define STATUS_ATTN_BITS_FLSH_ABORT		(1L<<26)98		#define STATUS_ATTN_BITS_GRC_ABORT		(1L<<27)99		#define STATUS_ATTN_BITS_EPB_ERROR		(1L<<30)100		#define STATUS_ATTN_BITS_PARITY_ERROR		(1L<<31)101 102	u32 status_attn_bits_ack;103#if defined(__BIG_ENDIAN)104	u16 status_tx_quick_consumer_index0;105	u16 status_tx_quick_consumer_index1;106	u16 status_tx_quick_consumer_index2;107	u16 status_tx_quick_consumer_index3;108	u16 status_rx_quick_consumer_index0;109	u16 status_rx_quick_consumer_index1;110	u16 status_rx_quick_consumer_index2;111	u16 status_rx_quick_consumer_index3;112	u16 status_rx_quick_consumer_index4;113	u16 status_rx_quick_consumer_index5;114	u16 status_rx_quick_consumer_index6;115	u16 status_rx_quick_consumer_index7;116	u16 status_rx_quick_consumer_index8;117	u16 status_rx_quick_consumer_index9;118	u16 status_rx_quick_consumer_index10;119	u16 status_rx_quick_consumer_index11;120	u16 status_rx_quick_consumer_index12;121	u16 status_rx_quick_consumer_index13;122	u16 status_rx_quick_consumer_index14;123	u16 status_rx_quick_consumer_index15;124	u16 status_completion_producer_index;125	u16 status_cmd_consumer_index;126	u16 status_idx;127	u8 status_unused;128	u8 status_blk_num;129#elif defined(__LITTLE_ENDIAN)130	u16 status_tx_quick_consumer_index1;131	u16 status_tx_quick_consumer_index0;132	u16 status_tx_quick_consumer_index3;133	u16 status_tx_quick_consumer_index2;134	u16 status_rx_quick_consumer_index1;135	u16 status_rx_quick_consumer_index0;136	u16 status_rx_quick_consumer_index3;137	u16 status_rx_quick_consumer_index2;138	u16 status_rx_quick_consumer_index5;139	u16 status_rx_quick_consumer_index4;140	u16 status_rx_quick_consumer_index7;141	u16 status_rx_quick_consumer_index6;142	u16 status_rx_quick_consumer_index9;143	u16 status_rx_quick_consumer_index8;144	u16 status_rx_quick_consumer_index11;145	u16 status_rx_quick_consumer_index10;146	u16 status_rx_quick_consumer_index13;147	u16 status_rx_quick_consumer_index12;148	u16 status_rx_quick_consumer_index15;149	u16 status_rx_quick_consumer_index14;150	u16 status_cmd_consumer_index;151	u16 status_completion_producer_index;152	u8 status_blk_num;153	u8 status_unused;154	u16 status_idx;155#endif156};157 158/*159 *  status_block definition160 */161struct status_block_msix {162#if defined(__BIG_ENDIAN)163	u16 status_tx_quick_consumer_index;164	u16 status_rx_quick_consumer_index;165	u16 status_completion_producer_index;166	u16 status_cmd_consumer_index;167	u32 status_unused;168	u16 status_idx;169	u8 status_unused2;170	u8 status_blk_num;171#elif defined(__LITTLE_ENDIAN)172	u16 status_rx_quick_consumer_index;173	u16 status_tx_quick_consumer_index;174	u16 status_cmd_consumer_index;175	u16 status_completion_producer_index;176	u32 status_unused;177	u8 status_blk_num;178	u8 status_unused2;179	u16 status_idx;180#endif181};182 183#define BNX2_SBLK_MSIX_ALIGN_SIZE	128184 185 186/*187 *  statistics_block definition188 */189struct statistics_block {190	u32 stat_IfHCInOctets_hi;191	u32 stat_IfHCInOctets_lo;192	u32 stat_IfHCInBadOctets_hi;193	u32 stat_IfHCInBadOctets_lo;194	u32 stat_IfHCOutOctets_hi;195	u32 stat_IfHCOutOctets_lo;196	u32 stat_IfHCOutBadOctets_hi;197	u32 stat_IfHCOutBadOctets_lo;198	u32 stat_IfHCInUcastPkts_hi;199	u32 stat_IfHCInUcastPkts_lo;200	u32 stat_IfHCInMulticastPkts_hi;201	u32 stat_IfHCInMulticastPkts_lo;202	u32 stat_IfHCInBroadcastPkts_hi;203	u32 stat_IfHCInBroadcastPkts_lo;204	u32 stat_IfHCOutUcastPkts_hi;205	u32 stat_IfHCOutUcastPkts_lo;206	u32 stat_IfHCOutMulticastPkts_hi;207	u32 stat_IfHCOutMulticastPkts_lo;208	u32 stat_IfHCOutBroadcastPkts_hi;209	u32 stat_IfHCOutBroadcastPkts_lo;210	u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;211	u32 stat_Dot3StatsCarrierSenseErrors;212	u32 stat_Dot3StatsFCSErrors;213	u32 stat_Dot3StatsAlignmentErrors;214	u32 stat_Dot3StatsSingleCollisionFrames;215	u32 stat_Dot3StatsMultipleCollisionFrames;216	u32 stat_Dot3StatsDeferredTransmissions;217	u32 stat_Dot3StatsExcessiveCollisions;218	u32 stat_Dot3StatsLateCollisions;219	u32 stat_EtherStatsCollisions;220	u32 stat_EtherStatsFragments;221	u32 stat_EtherStatsJabbers;222	u32 stat_EtherStatsUndersizePkts;223	u32 stat_EtherStatsOverrsizePkts;224	u32 stat_EtherStatsPktsRx64Octets;225	u32 stat_EtherStatsPktsRx65Octetsto127Octets;226	u32 stat_EtherStatsPktsRx128Octetsto255Octets;227	u32 stat_EtherStatsPktsRx256Octetsto511Octets;228	u32 stat_EtherStatsPktsRx512Octetsto1023Octets;229	u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;230	u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;231	u32 stat_EtherStatsPktsTx64Octets;232	u32 stat_EtherStatsPktsTx65Octetsto127Octets;233	u32 stat_EtherStatsPktsTx128Octetsto255Octets;234	u32 stat_EtherStatsPktsTx256Octetsto511Octets;235	u32 stat_EtherStatsPktsTx512Octetsto1023Octets;236	u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;237	u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;238	u32 stat_XonPauseFramesReceived;239	u32 stat_XoffPauseFramesReceived;240	u32 stat_OutXonSent;241	u32 stat_OutXoffSent;242	u32 stat_FlowControlDone;243	u32 stat_MacControlFramesReceived;244	u32 stat_XoffStateEntered;245	u32 stat_IfInFramesL2FilterDiscards;246	u32 stat_IfInRuleCheckerDiscards;247	u32 stat_IfInFTQDiscards;248	u32 stat_IfInMBUFDiscards;249	u32 stat_IfInRuleCheckerP4Hit;250	u32 stat_CatchupInRuleCheckerDiscards;251	u32 stat_CatchupInFTQDiscards;252	u32 stat_CatchupInMBUFDiscards;253	u32 stat_CatchupInRuleCheckerP4Hit;254	u32 stat_GenStat00;255	u32 stat_GenStat01;256	u32 stat_GenStat02;257	u32 stat_GenStat03;258	u32 stat_GenStat04;259	u32 stat_GenStat05;260	u32 stat_GenStat06;261	u32 stat_GenStat07;262	u32 stat_GenStat08;263	u32 stat_GenStat09;264	u32 stat_GenStat10;265	u32 stat_GenStat11;266	u32 stat_GenStat12;267	u32 stat_GenStat13;268	u32 stat_GenStat14;269	u32 stat_GenStat15;270	u32 stat_FwRxDrop;271};272 273 274/*275 *  l2_fhdr definition276 */277struct l2_fhdr {278	u32 l2_fhdr_status;279		#define L2_FHDR_STATUS_RULE_CLASS	(0x7<<0)280		#define L2_FHDR_STATUS_RULE_P2		(1<<3)281		#define L2_FHDR_STATUS_RULE_P3		(1<<4)282		#define L2_FHDR_STATUS_RULE_P4		(1<<5)283		#define L2_FHDR_STATUS_L2_VLAN_TAG	(1<<6)284		#define L2_FHDR_STATUS_L2_LLC_SNAP	(1<<7)285		#define L2_FHDR_STATUS_RSS_HASH		(1<<8)286		#define L2_FHDR_STATUS_IP_DATAGRAM	(1<<13)287		#define L2_FHDR_STATUS_TCP_SEGMENT	(1<<14)288		#define L2_FHDR_STATUS_UDP_DATAGRAM	(1<<15)289 290		#define L2_FHDR_STATUS_SPLIT		(1<<16)291		#define L2_FHDR_ERRORS_BAD_CRC		(1<<17)292		#define L2_FHDR_ERRORS_PHY_DECODE	(1<<18)293		#define L2_FHDR_ERRORS_ALIGNMENT	(1<<19)294		#define L2_FHDR_ERRORS_TOO_SHORT	(1<<20)295		#define L2_FHDR_ERRORS_GIANT_FRAME	(1<<21)296		#define L2_FHDR_ERRORS_TCP_XSUM		(1<<28)297		#define L2_FHDR_ERRORS_UDP_XSUM		(1<<31)298 299		#define L2_FHDR_STATUS_USE_RXHASH	\300			(L2_FHDR_STATUS_TCP_SEGMENT | L2_FHDR_STATUS_RSS_HASH)301 302	u32 l2_fhdr_hash;303#if defined(__BIG_ENDIAN)304	u16 l2_fhdr_pkt_len;305	u16 l2_fhdr_vlan_tag;306	u16 l2_fhdr_ip_xsum;307	u16 l2_fhdr_tcp_udp_xsum;308#elif defined(__LITTLE_ENDIAN)309	u16 l2_fhdr_vlan_tag;310	u16 l2_fhdr_pkt_len;311	u16 l2_fhdr_tcp_udp_xsum;312	u16 l2_fhdr_ip_xsum;313#endif314};315 316#define BNX2_RX_OFFSET		(sizeof(struct l2_fhdr) + 2)317 318/*319 *  l2_context definition320 */321#define BNX2_L2CTX_TYPE					0x00000000322#define BNX2_L2CTX_TYPE_SIZE_L2				 ((0xc0/0x20)<<16)323#define BNX2_L2CTX_TYPE_TYPE				 (0xf<<28)324#define BNX2_L2CTX_TYPE_TYPE_EMPTY			 (0<<28)325#define BNX2_L2CTX_TYPE_TYPE_L2				 (1<<28)326 327#define BNX2_L2CTX_TX_HOST_BIDX				0x00000088328#define BNX2_L2CTX_EST_NBD				0x00000088329#define BNX2_L2CTX_CMD_TYPE				0x00000088330#define BNX2_L2CTX_CMD_TYPE_TYPE			 (0xf<<24)331#define BNX2_L2CTX_CMD_TYPE_TYPE_L2			 (0<<24)332#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP			 (1<<24)333 334#define BNX2_L2CTX_TX_HOST_BSEQ				0x00000090335#define BNX2_L2CTX_TSCH_BSEQ				0x00000094336#define BNX2_L2CTX_TBDR_BSEQ				0x00000098337#define BNX2_L2CTX_TBDR_BOFF				0x0000009c338#define BNX2_L2CTX_TBDR_BIDX				0x0000009c339#define BNX2_L2CTX_TBDR_BHADDR_HI			0x000000a0340#define BNX2_L2CTX_TBDR_BHADDR_LO			0x000000a4341#define BNX2_L2CTX_TXP_BOFF				0x000000a8342#define BNX2_L2CTX_TXP_BIDX				0x000000a8343#define BNX2_L2CTX_TXP_BSEQ				0x000000ac344 345#define BNX2_L2CTX_TYPE_XI				0x00000080346#define BNX2_L2CTX_CMD_TYPE_XI				0x00000240347#define BNX2_L2CTX_TBDR_BHADDR_HI_XI			0x00000258348#define BNX2_L2CTX_TBDR_BHADDR_LO_XI			0x0000025c349 350/*351 *  l2_bd_chain_context definition352 */353#define BNX2_L2CTX_BD_PRE_READ				0x00000000354#define BNX2_L2CTX_CTX_SIZE				0x00000000355#define BNX2_L2CTX_CTX_TYPE				0x00000000356#define BNX2_L2CTX_FLOW_CTRL_ENABLE			 0x000000ff357#define BNX2_L2CTX_CTX_TYPE_SIZE_L2			 ((0x20/20)<<16)358#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE		 (0xf<<28)359#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED	 (0<<28)360#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE	 (1<<28)361 362#define BNX2_L2CTX_HOST_BDIDX				0x00000004363#define BNX2_L2CTX_L5_STATUSB_NUM_SHIFT			 16364#define BNX2_L2CTX_L2_STATUSB_NUM_SHIFT			 24365#define BNX2_L2CTX_L5_STATUSB_NUM(sb_id)		\366	(((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L5_STATUSB_NUM_SHIFT) : 0)367#define BNX2_L2CTX_L2_STATUSB_NUM(sb_id)		\368	(((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT) : 0)369#define BNX2_L2CTX_HOST_BSEQ				0x00000008370#define BNX2_L2CTX_NX_BSEQ				0x0000000c371#define BNX2_L2CTX_NX_BDHADDR_HI			0x00000010372#define BNX2_L2CTX_NX_BDHADDR_LO			0x00000014373#define BNX2_L2CTX_NX_BDIDX				0x00000018374 375#define BNX2_L2CTX_HOST_PG_BDIDX			0x00000044376#define BNX2_L2CTX_PG_BUF_SIZE				0x00000048377#define BNX2_L2CTX_RBDC_KEY				0x0000004c378#define BNX2_L2CTX_RBDC_JUMBO_KEY			 0x3ffe379#define BNX2_L2CTX_NX_PG_BDHADDR_HI			0x00000050380#define BNX2_L2CTX_NX_PG_BDHADDR_LO			0x00000054381 382/*383 *  pci_config_l definition384 *  offset: 0000385 */386#define BNX2_PCICFG_MSI_CONTROL				0x00000058387#define BNX2_PCICFG_MSI_CONTROL_ENABLE			 (1L<<16)388 389#define BNX2_PCICFG_MISC_CONFIG				0x00000068390#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP	 (1L<<2)391#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP	 (1L<<3)392#define BNX2_PCICFG_MISC_CONFIG_RESERVED1		 (1L<<4)393#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA		 (1L<<5)394#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP	 (1L<<6)395#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA		 (1L<<7)396#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ		 (1L<<8)397#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY		 (1L<<9)398#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN	 (1L<<10)399#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN	 (1L<<11)400#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN	 (1L<<12)401#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV		 (0xffL<<16)402#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV		 (0xfL<<24)403#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID			 (0xfL<<28)404 405#define BNX2_PCICFG_MISC_STATUS				0x0000006c406#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE		 (1L<<0)407#define BNX2_PCICFG_MISC_STATUS_32BIT_DET		 (1L<<1)408#define BNX2_PCICFG_MISC_STATUS_M66EN			 (1L<<2)409#define BNX2_PCICFG_MISC_STATUS_PCIX_DET		 (1L<<3)410#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED		 (0x3L<<4)411#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66		 (0L<<4)412#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100		 (1L<<4)413#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133		 (2L<<4)414#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE	 (3L<<4)415#define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE	 (1L<<8)416 417#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS		0x00000070418#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)419#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)420#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)421#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)422#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)423#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)424#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)425#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)426#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)427#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)428#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)429#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)430#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)431#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)432#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)433#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)434#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)435#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER	 (1L<<11)436#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)437#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)438#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)439#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)440#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)441#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)442#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)443#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17	 (1L<<17)444#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18	 (1L<<18)445#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19	 (1L<<19)446#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED	 (0xfffL<<20)447 448#define BNX2_PCICFG_REG_WINDOW_ADDRESS			0x00000078449#define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL		 (0xfffffL<<2)450 451#define BNX2_PCICFG_REG_WINDOW				0x00000080452#define BNX2_PCICFG_INT_ACK_CMD				0x00000084453#define BNX2_PCICFG_INT_ACK_CMD_INDEX			 (0xffffL<<0)454#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID		 (1L<<16)455#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM	 (1L<<17)456#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT		 (1L<<18)457#define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM		 (0xfL<<24)458#define BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT		 24459 460#define BNX2_PCICFG_STATUS_BIT_SET_CMD			0x00000088461#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD		0x0000008c462#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR			0x00000090463#define BNX2_PCICFG_MAILBOX_QUEUE_DATA			0x00000094464 465#define BNX2_PCICFG_DEVICE_CONTROL			0x000000b4466#define BNX2_PCICFG_DEVICE_STATUS_NO_PEND		 ((1L<<5)<<16)467 468/*469 *  pci_reg definition470 *  offset: 0x400471 */472#define BNX2_PCI_GRC_WINDOW_ADDR			0x00000400473#define BNX2_PCI_GRC_WINDOW_ADDR_VALUE			 (0x1ffL<<13)474#define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN		 (1L<<31)475 476#define BNX2_PCI_GRC_WINDOW2_BASE		 	 0xc000477#define BNX2_PCI_GRC_WINDOW3_BASE		 	 0xe000478 479#define BNX2_PCI_CONFIG_1				0x00000404480#define BNX2_PCI_CONFIG_1_RESERVED0			 (0xffL<<0)481#define BNX2_PCI_CONFIG_1_READ_BOUNDARY			 (0x7L<<8)482#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF		 (0L<<8)483#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16		 (1L<<8)484#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32		 (2L<<8)485#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64		 (3L<<8)486#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128		 (4L<<8)487#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256		 (5L<<8)488#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512		 (6L<<8)489#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024		 (7L<<8)490#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY		 (0x7L<<11)491#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF		 (0L<<11)492#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16		 (1L<<11)493#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32		 (2L<<11)494#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64		 (3L<<11)495#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128		 (4L<<11)496#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256		 (5L<<11)497#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512		 (6L<<11)498#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024		 (7L<<11)499#define BNX2_PCI_CONFIG_1_RESERVED1			 (0x3ffffL<<14)500 501#define BNX2_PCI_CONFIG_2				0x00000408502#define BNX2_PCI_CONFIG_2_BAR1_SIZE			 (0xfL<<0)503#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED		 (0L<<0)504#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K			 (1L<<0)505#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K		 (2L<<0)506#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K		 (3L<<0)507#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K		 (4L<<0)508#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M			 (5L<<0)509#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M			 (6L<<0)510#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M			 (7L<<0)511#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M			 (8L<<0)512#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M			 (9L<<0)513#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M			 (10L<<0)514#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M			 (11L<<0)515#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M		 (12L<<0)516#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M		 (13L<<0)517#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M		 (14L<<0)518#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G			 (15L<<0)519#define BNX2_PCI_CONFIG_2_BAR1_64ENA			 (1L<<4)520#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY			 (1L<<5)521#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY		 (1L<<6)522#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE		 (1L<<7)523#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE			 (0xffL<<8)524#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED		 (0L<<8)525#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K		 (1L<<8)526#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K		 (2L<<8)527#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K		 (3L<<8)528#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K		 (4L<<8)529#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K		 (5L<<8)530#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K		 (6L<<8)531#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K		 (7L<<8)532#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K		 (8L<<8)533#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K		 (9L<<8)534#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K		 (10L<<8)535#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M		 (11L<<8)536#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M		 (12L<<8)537#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M		 (13L<<8)538#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M		 (14L<<8)539#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M		 (15L<<8)540#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT		 (0x1fL<<16)541#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT		 (0x3L<<21)542#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512		 (0L<<21)543#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K		 (1L<<21)544#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K		 (2L<<21)545#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K		 (3L<<21)546#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR		 (1L<<23)547#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT		 (1L<<24)548#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT		 (1L<<25)549#define BNX2_PCI_CONFIG_2_RESERVED0			 (0x3fL<<26)550#define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI		 (1L<<16)551#define BNX2_PCI_CONFIG_2_RESERVED0_XI			 (0x7fffL<<17)552 553#define BNX2_PCI_CONFIG_3				0x0000040c554#define BNX2_PCI_CONFIG_3_STICKY_BYTE			 (0xffL<<0)555#define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE		 (0xffL<<8)556#define BNX2_PCI_CONFIG_3_FORCE_PME			 (1L<<24)557#define BNX2_PCI_CONFIG_3_PME_STATUS			 (1L<<25)558#define BNX2_PCI_CONFIG_3_PME_ENABLE			 (1L<<26)559#define BNX2_PCI_CONFIG_3_PM_STATE			 (0x3L<<27)560#define BNX2_PCI_CONFIG_3_VAUX_PRESET			 (1L<<30)561#define BNX2_PCI_CONFIG_3_PCI_POWER			 (1L<<31)562 563#define BNX2_PCI_PM_DATA_A				0x00000410564#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG		 (0xffL<<0)565#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG		 (0xffL<<8)566#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG		 (0xffL<<16)567#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG		 (0xffL<<24)568 569#define BNX2_PCI_PM_DATA_B				0x00000414570#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG		 (0xffL<<0)571#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG		 (0xffL<<8)572#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG		 (0xffL<<16)573#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG		 (0xffL<<24)574 575#define BNX2_PCI_SWAP_DIAG0				0x00000418576#define BNX2_PCI_SWAP_DIAG1				0x0000041c577#define BNX2_PCI_EXP_ROM_ADDR				0x00000420578#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS			 (0x3fffffL<<2)579#define BNX2_PCI_EXP_ROM_ADDR_REQ			 (1L<<31)580 581#define BNX2_PCI_EXP_ROM_DATA				0x00000424582#define BNX2_PCI_VPD_INTF				0x00000428583#define BNX2_PCI_VPD_INTF_INTF_REQ			 (1L<<0)584 585#define BNX2_PCI_VPD_ADDR_FLAG				0x0000042c586#define BNX2_PCI_VPD_ADDR_FLAG_MSK			0x0000ffff587#define BNX2_PCI_VPD_ADDR_FLAG_SL			0L588#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS			 (0x1fffL<<2)589#define BNX2_PCI_VPD_ADDR_FLAG_WR			 (1L<<15)590 591#define BNX2_PCI_VPD_DATA				0x00000430592#define BNX2_PCI_ID_VAL1				0x00000434593#define BNX2_PCI_ID_VAL1_DEVICE_ID			 (0xffffL<<0)594#define BNX2_PCI_ID_VAL1_VENDOR_ID			 (0xffffL<<16)595 596#define BNX2_PCI_ID_VAL2				0x00000438597#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID		 (0xffffL<<0)598#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID			 (0xffffL<<16)599 600#define BNX2_PCI_ID_VAL3				0x0000043c601#define BNX2_PCI_ID_VAL3_CLASS_CODE			 (0xffffffL<<0)602#define BNX2_PCI_ID_VAL3_REVISION_ID			 (0xffL<<24)603 604#define BNX2_PCI_ID_VAL4				0x00000440605#define BNX2_PCI_ID_VAL4_CAP_ENA			 (0xfL<<0)606#define BNX2_PCI_ID_VAL4_CAP_ENA_0			 (0L<<0)607#define BNX2_PCI_ID_VAL4_CAP_ENA_1			 (1L<<0)608#define BNX2_PCI_ID_VAL4_CAP_ENA_2			 (2L<<0)609#define BNX2_PCI_ID_VAL4_CAP_ENA_3			 (3L<<0)610#define BNX2_PCI_ID_VAL4_CAP_ENA_4			 (4L<<0)611#define BNX2_PCI_ID_VAL4_CAP_ENA_5			 (5L<<0)612#define BNX2_PCI_ID_VAL4_CAP_ENA_6			 (6L<<0)613#define BNX2_PCI_ID_VAL4_CAP_ENA_7			 (7L<<0)614#define BNX2_PCI_ID_VAL4_CAP_ENA_8			 (8L<<0)615#define BNX2_PCI_ID_VAL4_CAP_ENA_9			 (9L<<0)616#define BNX2_PCI_ID_VAL4_CAP_ENA_10			 (10L<<0)617#define BNX2_PCI_ID_VAL4_CAP_ENA_11			 (11L<<0)618#define BNX2_PCI_ID_VAL4_CAP_ENA_12			 (12L<<0)619#define BNX2_PCI_ID_VAL4_CAP_ENA_13			 (13L<<0)620#define BNX2_PCI_ID_VAL4_CAP_ENA_14			 (14L<<0)621#define BNX2_PCI_ID_VAL4_CAP_ENA_15			 (15L<<0)622#define BNX2_PCI_ID_VAL4_RESERVED0			 (0x3L<<4)623#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG			 (0x3L<<6)624#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0			 (0L<<6)625#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1			 (1L<<6)626#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2			 (2L<<6)627#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3			 (3L<<6)628#define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP		 (1L<<8)629#define BNX2_PCI_ID_VAL4_MSI_LIMIT			 (0x7L<<9)630#define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP			 (0x7L<<12)631#define BNX2_PCI_ID_VAL4_MSI_ENABLE			 (1L<<15)632#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE		 (1L<<16)633#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE		 (1L<<17)634#define BNX2_PCI_ID_VAL4_RESERVED2			 (0x7L<<18)635#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21	 (0x3L<<21)636#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21		 (0x3L<<23)637#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0		 (1L<<25)638#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10		 (0x3L<<26)639#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0		 (1L<<28)640#define BNX2_PCI_ID_VAL4_RESERVED3			 (0x7L<<29)641#define BNX2_PCI_ID_VAL4_RESERVED3_XI			 (0xffffL<<16)642 643#define BNX2_PCI_ID_VAL5				0x00000444644#define BNX2_PCI_ID_VAL5_D1_SUPPORT			 (1L<<0)645#define BNX2_PCI_ID_VAL5_D2_SUPPORT			 (1L<<1)646#define BNX2_PCI_ID_VAL5_PME_IN_D0			 (1L<<2)647#define BNX2_PCI_ID_VAL5_PME_IN_D1			 (1L<<3)648#define BNX2_PCI_ID_VAL5_PME_IN_D2			 (1L<<4)649#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT			 (1L<<5)650#define BNX2_PCI_ID_VAL5_RESERVED0_TE			 (0x3ffffffL<<6)651#define BNX2_PCI_ID_VAL5_PM_VERSION_XI			 (0x7L<<6)652#define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI		 (1L<<9)653#define BNX2_PCI_ID_VAL5_RESERVED0_XI			 (0x3fffffL<<10)654 655#define BNX2_PCI_PCIX_EXTENDED_STATUS			0x00000448656#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP		 (1L<<8)657#define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST	 (1L<<9)658#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS	 (0xfL<<16)659#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX	 (0xffL<<24)660 661#define BNX2_PCI_ID_VAL6				0x0000044c662#define BNX2_PCI_ID_VAL6_MAX_LAT			 (0xffL<<0)663#define BNX2_PCI_ID_VAL6_MIN_GNT			 (0xffL<<8)664#define BNX2_PCI_ID_VAL6_BIST				 (0xffL<<16)665#define BNX2_PCI_ID_VAL6_RESERVED0			 (0xffL<<24)666 667#define BNX2_PCI_MSI_DATA				0x00000450668#define BNX2_PCI_MSI_DATA_MSI_DATA			 (0xffffL<<0)669 670#define BNX2_PCI_MSI_ADDR_H				0x00000454671#define BNX2_PCI_MSI_ADDR_L				0x00000458672#define BNX2_PCI_MSI_ADDR_L_VAL				 (0x3fffffffL<<2)673 674#define BNX2_PCI_CFG_ACCESS_CMD				0x0000045c675#define BNX2_PCI_CFG_ACCESS_CMD_ADR			 (0x3fL<<2)676#define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ			 (1L<<27)677#define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ			 (0xfL<<28)678 679#define BNX2_PCI_CFG_ACCESS_DATA			0x00000460680#define BNX2_PCI_MSI_MASK				0x00000464681#define BNX2_PCI_MSI_MASK_MSI_MASK			 (0xffffffffL<<0)682 683#define BNX2_PCI_MSI_PEND				0x00000468684#define BNX2_PCI_MSI_PEND_MSI_PEND			 (0xffffffffL<<0)685 686#define BNX2_PCI_PM_DATA_C				0x0000046c687#define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG		 (0xffL<<0)688#define BNX2_PCI_PM_DATA_C_RESERVED0			 (0xffffffL<<8)689 690#define BNX2_PCI_MSIX_CONTROL				0x000004c0691#define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ		 (0x7ffL<<0)692#define BNX2_PCI_MSIX_CONTROL_RESERVED0			 (0x1fffffL<<11)693 694#define BNX2_PCI_MSIX_TBL_OFF_BIR			0x000004c4695#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR		 (0x7L<<0)696#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF		 (0x1fffffffL<<3)697 698#define BNX2_PCI_MSIX_PBA_OFF_BIT			0x000004c8699#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR		 (0x7L<<0)700#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF		 (0x1fffffffL<<3)701 702#define BNX2_PCI_PCIE_CAPABILITY			0x000004d0703#define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM	 (0x1fL<<0)704#define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1	 (1L<<5)705 706#define BNX2_PCI_DEVICE_CAPABILITY			0x000004d4707#define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED	 (0x7L<<0)708#define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT	 (1L<<5)709#define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY	 (0x7L<<6)710#define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY	 (0x7L<<9)711#define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT	 (1L<<15)712 713#define BNX2_PCI_LINK_CAPABILITY			0x000004dc714#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED		 (0xfL<<0)715#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001	 (1L<<0)716#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010	 (1L<<0)717#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH		 (0x1fL<<4)718#define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT		 (1L<<9)719#define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT		 (0x3L<<10)720#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT		 (0x7L<<12)721#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101	 (5L<<12)722#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110	 (6L<<12)723#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT		 (0x7L<<15)724#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001	 (1L<<15)725#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010	 (2L<<15)726#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT	 (0x7L<<18)727#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101	 (5L<<18)728#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110	 (6L<<18)729#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT	 (0x7L<<21)730#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001	 (1L<<21)731#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010	 (2L<<21)732#define BNX2_PCI_LINK_CAPABILITY_PORT_NUM		 (0xffL<<24)733 734#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2		0x000004e4735#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP	 (0xfL<<0)736#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP	 (1L<<4)737#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED	 (0x7ffffffL<<5)738 739#define BNX2_PCI_PCIE_LINK_CAPABILITY_2			0x000004e8740#define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED	 (0xffffffffL<<0)741 742#define BNX2_PCI_GRC_WINDOW1_ADDR			0x00000610743#define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE			 (0x1ffL<<13)744 745#define BNX2_PCI_GRC_WINDOW2_ADDR			0x00000614746#define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE			 (0x1ffL<<13)747 748#define BNX2_PCI_GRC_WINDOW3_ADDR			0x00000618749#define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE			 (0x1ffL<<13)750 751#define BNX2_MSIX_TABLE_ADDR				 0x318000752#define BNX2_MSIX_PBA_ADDR				 0x31c000753 754/*755 *  misc_reg definition756 *  offset: 0x800757 */758#define BNX2_MISC_COMMAND				0x00000800759#define BNX2_MISC_COMMAND_ENABLE_ALL			 (1L<<0)760#define BNX2_MISC_COMMAND_DISABLE_ALL			 (1L<<1)761#define BNX2_MISC_COMMAND_SW_RESET			 (1L<<4)762#define BNX2_MISC_COMMAND_POR_RESET			 (1L<<5)763#define BNX2_MISC_COMMAND_HD_RESET			 (1L<<6)764#define BNX2_MISC_COMMAND_CMN_SW_RESET			 (1L<<7)765#define BNX2_MISC_COMMAND_PAR_ERROR			 (1L<<8)766#define BNX2_MISC_COMMAND_CS16_ERR			 (1L<<9)767#define BNX2_MISC_COMMAND_CS16_ERR_LOC			 (0xfL<<12)768#define BNX2_MISC_COMMAND_PAR_ERR_RAM			 (0x7fL<<16)769#define BNX2_MISC_COMMAND_POWERDOWN_EVENT		 (1L<<23)770#define BNX2_MISC_COMMAND_SW_SHUTDOWN			 (1L<<24)771#define BNX2_MISC_COMMAND_SHUTDOWN_EN			 (1L<<25)772#define BNX2_MISC_COMMAND_DINTEG_ATTN_EN		 (1L<<26)773#define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23		 (1L<<27)774#define BNX2_MISC_COMMAND_PCIE_DIS			 (1L<<28)775 776#define BNX2_MISC_CFG					0x00000804777#define BNX2_MISC_CFG_GRC_TMOUT				 (1L<<0)778#define BNX2_MISC_CFG_NVM_WR_EN				 (0x3L<<1)779#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT			 (0L<<1)780#define BNX2_MISC_CFG_NVM_WR_EN_PCI			 (1L<<1)781#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW			 (2L<<1)782#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2			 (3L<<1)783#define BNX2_MISC_CFG_BIST_EN				 (1L<<3)784#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC			 (1L<<4)785#define BNX2_MISC_CFG_RESERVED5_TE			 (1L<<5)786#define BNX2_MISC_CFG_RESERVED6_TE			 (1L<<6)787#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE			 (1L<<7)788#define BNX2_MISC_CFG_LEDMODE				 (0x7L<<8)789#define BNX2_MISC_CFG_LEDMODE_MAC			 (0L<<8)790#define BNX2_MISC_CFG_LEDMODE_PHY1_TE			 (1L<<8)791#define BNX2_MISC_CFG_LEDMODE_PHY2_TE			 (2L<<8)792#define BNX2_MISC_CFG_LEDMODE_PHY3_TE			 (3L<<8)793#define BNX2_MISC_CFG_LEDMODE_PHY4_TE			 (4L<<8)794#define BNX2_MISC_CFG_LEDMODE_PHY5_TE			 (5L<<8)795#define BNX2_MISC_CFG_LEDMODE_PHY6_TE			 (6L<<8)796#define BNX2_MISC_CFG_LEDMODE_PHY7_TE			 (7L<<8)797#define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE			 (1L<<11)798#define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE			 (1L<<12)799#define BNX2_MISC_CFG_LEDMODE_XI			 (0xfL<<8)800#define BNX2_MISC_CFG_LEDMODE_MAC_XI			 (0L<<8)801#define BNX2_MISC_CFG_LEDMODE_PHY1_XI			 (1L<<8)802#define BNX2_MISC_CFG_LEDMODE_PHY2_XI			 (2L<<8)803#define BNX2_MISC_CFG_LEDMODE_PHY3_XI			 (3L<<8)804#define BNX2_MISC_CFG_LEDMODE_MAC2_XI			 (4L<<8)805#define BNX2_MISC_CFG_LEDMODE_PHY4_XI			 (5L<<8)806#define BNX2_MISC_CFG_LEDMODE_PHY5_XI			 (6L<<8)807#define BNX2_MISC_CFG_LEDMODE_PHY6_XI			 (7L<<8)808#define BNX2_MISC_CFG_LEDMODE_MAC3_XI			 (8L<<8)809#define BNX2_MISC_CFG_LEDMODE_PHY7_XI			 (9L<<8)810#define BNX2_MISC_CFG_LEDMODE_PHY8_XI			 (10L<<8)811#define BNX2_MISC_CFG_LEDMODE_PHY9_XI			 (11L<<8)812#define BNX2_MISC_CFG_LEDMODE_MAC4_XI			 (12L<<8)813#define BNX2_MISC_CFG_LEDMODE_PHY10_XI			 (13L<<8)814#define BNX2_MISC_CFG_LEDMODE_PHY11_XI			 (14L<<8)815#define BNX2_MISC_CFG_LEDMODE_UNUSED_XI			 (15L<<8)816#define BNX2_MISC_CFG_PORT_SELECT_XI			 (1L<<13)817#define BNX2_MISC_CFG_PARITY_MODE_XI			 (1L<<14)818 819#define BNX2_MISC_ID					0x00000808820#define BNX2_MISC_ID_BOND_ID				 (0xfL<<0)821#define BNX2_MISC_ID_BOND_ID_X				 (0L<<0)822#define BNX2_MISC_ID_BOND_ID_C				 (3L<<0)823#define BNX2_MISC_ID_BOND_ID_S				 (12L<<0)824#define BNX2_MISC_ID_CHIP_METAL				 (0xffL<<4)825#define BNX2_MISC_ID_CHIP_REV				 (0xfL<<12)826#define BNX2_MISC_ID_CHIP_NUM				 (0xffffL<<16)827 828#define BNX2_MISC_ENABLE_STATUS_BITS			0x0000080c829#define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)830#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE	 (1L<<1)831#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)832#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)833#define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE	 (1L<<4)834#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE	 (1L<<5)835#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)836#define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)837#define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)838#define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE	 (1L<<9)839#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)840#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)841#define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE	 (1L<<12)842#define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE	 (1L<<13)843#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)844#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE	 (1L<<15)845#define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)846#define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE	 (1L<<17)847#define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE	 (1L<<18)848#define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE	 (1L<<19)849#define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)850#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE	 (1L<<21)851#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)852#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)853#define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)854#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE	 (1L<<25)855#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE	 (1L<<26)856#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE		 (1L<<27)857#define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE	 (1L<<28)858#define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE	 (0x7L<<29)859 860#define BNX2_MISC_ENABLE_SET_BITS			0x00000810861#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)862#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE	 (1L<<1)863#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)864#define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)865#define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE		 (1L<<4)866#define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE	 (1L<<5)867#define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)868#define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)869#define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)870#define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE		 (1L<<9)871#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)872#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)873#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE	 (1L<<12)874#define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE	 (1L<<13)875#define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)876#define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE		 (1L<<15)877#define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)878#define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE		 (1L<<17)879#define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE	 (1L<<18)880#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE	 (1L<<19)881#define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)882#define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE	 (1L<<21)883#define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)884#define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)885#define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)886#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE		 (1L<<25)887#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE	 (1L<<26)888#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE		 (1L<<27)889#define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE	 (1L<<28)890#define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE	 (0x7L<<29)891 892#define BNX2_MISC_ENABLE_CLR_BITS			0x00000814893#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)894#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE	 (1L<<1)895#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)896#define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)897#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE		 (1L<<4)898#define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE	 (1L<<5)899#define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)900#define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)901#define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)902#define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE		 (1L<<9)903#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)904#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)905#define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE	 (1L<<12)906#define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE	 (1L<<13)907#define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)908#define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE		 (1L<<15)909#define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)910#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE		 (1L<<17)911#define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE	 (1L<<18)912#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE	 (1L<<19)913#define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)914#define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE	 (1L<<21)915#define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)916#define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)917#define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)918#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE		 (1L<<25)919#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE	 (1L<<26)920#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE		 (1L<<27)921#define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE	 (1L<<28)922#define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE	 (0x7L<<29)923 924#define BNX2_MISC_CLOCK_CONTROL_BITS			0x00000818925#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)926#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)927#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)928#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)929#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)930#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)931#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)932#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)933#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)934#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)935#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)936#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)937#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)938#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)939#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)940#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)941#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)942#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI	 (0x7L<<8)943#define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER		 (1L<<11)944#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)945#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)946#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)947#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)948#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)949#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)950#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI	 (0xfL<<12)951#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)952#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE	 (1L<<17)953#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE	 (1L<<18)954#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE	 (1L<<19)955#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE	 (0xfffL<<20)956#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI	 (1L<<17)957#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI	 (0x3fL<<18)958#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI	 (0x7L<<24)959#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI	 (1L<<27)960#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI	 (0xfL<<28)961 962#define BNX2_MISC_SPIO					0x0000081c963#define BNX2_MISC_SPIO_VALUE				 (0xffL<<0)964#define BNX2_MISC_SPIO_SET				 (0xffL<<8)965#define BNX2_MISC_SPIO_CLR				 (0xffL<<16)966#define BNX2_MISC_SPIO_FLOAT				 (0xffL<<24)967 968#define BNX2_MISC_SPIO_INT				0x00000820969#define BNX2_MISC_SPIO_INT_INT_STATE_TE			 (0xfL<<0)970#define BNX2_MISC_SPIO_INT_OLD_VALUE_TE			 (0xfL<<8)971#define BNX2_MISC_SPIO_INT_OLD_SET_TE			 (0xfL<<16)972#define BNX2_MISC_SPIO_INT_OLD_CLR_TE			 (0xfL<<24)973#define BNX2_MISC_SPIO_INT_INT_STATE_XI			 (0xffL<<0)974#define BNX2_MISC_SPIO_INT_OLD_VALUE_XI			 (0xffL<<8)975#define BNX2_MISC_SPIO_INT_OLD_SET_XI			 (0xffL<<16)976#define BNX2_MISC_SPIO_INT_OLD_CLR_XI			 (0xffL<<24)977 978#define BNX2_MISC_CONFIG_LFSR				0x00000824979#define BNX2_MISC_CONFIG_LFSR_DIV			 (0xffffL<<0)980 981#define BNX2_MISC_LFSR_MASK_BITS			0x00000828982#define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)983#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE	 (1L<<1)984#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)985#define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)986#define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE		 (1L<<4)987#define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE	 (1L<<5)988#define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)989#define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)990#define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)991#define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE		 (1L<<9)992#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)993#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)994#define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE		 (1L<<12)995#define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE	 (1L<<13)996#define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)997#define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE		 (1L<<15)998#define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)999#define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE		 (1L<<17)1000#define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE	 (1L<<18)1001#define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE	 (1L<<19)1002#define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)1003#define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE		 (1L<<21)1004#define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)1005#define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)1006#define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)1007#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE		 (1L<<25)1008#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE	 (1L<<26)1009#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE		 (1L<<27)1010#define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE	 (1L<<28)1011#define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE	 (0x7L<<29)1012 1013#define BNX2_MISC_ARB_REQ0				0x0000082c1014#define BNX2_MISC_ARB_REQ1				0x000008301015#define BNX2_MISC_ARB_REQ2				0x000008341016#define BNX2_MISC_ARB_REQ3				0x000008381017#define BNX2_MISC_ARB_REQ4				0x0000083c1018#define BNX2_MISC_ARB_FREE0				0x000008401019#define BNX2_MISC_ARB_FREE1				0x000008441020#define BNX2_MISC_ARB_FREE2				0x000008481021#define BNX2_MISC_ARB_FREE3				0x0000084c1022#define BNX2_MISC_ARB_FREE4				0x000008501023#define BNX2_MISC_ARB_REQ_STATUS0			0x000008541024#define BNX2_MISC_ARB_REQ_STATUS1			0x000008581025#define BNX2_MISC_ARB_REQ_STATUS2			0x0000085c1026#define BNX2_MISC_ARB_REQ_STATUS3			0x000008601027#define BNX2_MISC_ARB_REQ_STATUS4			0x000008641028#define BNX2_MISC_ARB_GNT0				0x000008681029#define BNX2_MISC_ARB_GNT0_0				 (0x7L<<0)1030#define BNX2_MISC_ARB_GNT0_1				 (0x7L<<4)1031#define BNX2_MISC_ARB_GNT0_2				 (0x7L<<8)1032#define BNX2_MISC_ARB_GNT0_3				 (0x7L<<12)1033#define BNX2_MISC_ARB_GNT0_4				 (0x7L<<16)1034#define BNX2_MISC_ARB_GNT0_5				 (0x7L<<20)1035#define BNX2_MISC_ARB_GNT0_6				 (0x7L<<24)1036#define BNX2_MISC_ARB_GNT0_7				 (0x7L<<28)1037 1038#define BNX2_MISC_ARB_GNT1				0x0000086c1039#define BNX2_MISC_ARB_GNT1_8				 (0x7L<<0)1040#define BNX2_MISC_ARB_GNT1_9				 (0x7L<<4)1041#define BNX2_MISC_ARB_GNT1_10				 (0x7L<<8)1042#define BNX2_MISC_ARB_GNT1_11				 (0x7L<<12)1043#define BNX2_MISC_ARB_GNT1_12				 (0x7L<<16)1044#define BNX2_MISC_ARB_GNT1_13				 (0x7L<<20)1045#define BNX2_MISC_ARB_GNT1_14				 (0x7L<<24)1046#define BNX2_MISC_ARB_GNT1_15				 (0x7L<<28)1047 1048#define BNX2_MISC_ARB_GNT2				0x000008701049#define BNX2_MISC_ARB_GNT2_16				 (0x7L<<0)1050#define BNX2_MISC_ARB_GNT2_17				 (0x7L<<4)1051#define BNX2_MISC_ARB_GNT2_18				 (0x7L<<8)1052#define BNX2_MISC_ARB_GNT2_19				 (0x7L<<12)1053#define BNX2_MISC_ARB_GNT2_20				 (0x7L<<16)1054#define BNX2_MISC_ARB_GNT2_21				 (0x7L<<20)1055#define BNX2_MISC_ARB_GNT2_22				 (0x7L<<24)1056#define BNX2_MISC_ARB_GNT2_23				 (0x7L<<28)1057 1058#define BNX2_MISC_ARB_GNT3				0x000008741059#define BNX2_MISC_ARB_GNT3_24				 (0x7L<<0)1060#define BNX2_MISC_ARB_GNT3_25				 (0x7L<<4)1061#define BNX2_MISC_ARB_GNT3_26				 (0x7L<<8)1062#define BNX2_MISC_ARB_GNT3_27				 (0x7L<<12)1063#define BNX2_MISC_ARB_GNT3_28				 (0x7L<<16)1064#define BNX2_MISC_ARB_GNT3_29				 (0x7L<<20)1065#define BNX2_MISC_ARB_GNT3_30				 (0x7L<<24)1066#define BNX2_MISC_ARB_GNT3_31				 (0x7L<<28)1067 1068#define BNX2_MISC_RESERVED1				0x000008781069#define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE	 (0x3fL<<0)1070 1071#define BNX2_MISC_RESERVED2				0x0000087c1072#define BNX2_MISC_RESERVED2_PCIE_DIS			 (1L<<0)1073#define BNX2_MISC_RESERVED2_LINK_IN_L23			 (1L<<1)1074 1075#define BNX2_MISC_SM_ASF_CONTROL			0x000008801076#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST		 (1L<<0)1077#define BNX2_MISC_SM_ASF_CONTROL_TSC_EN			 (1L<<1)1078#define BNX2_MISC_SM_ASF_CONTROL_WG_TO			 (1L<<2)1079#define BNX2_MISC_SM_ASF_CONTROL_HB_TO			 (1L<<3)1080#define BNX2_MISC_SM_ASF_CONTROL_PA_TO			 (1L<<4)1081#define BNX2_MISC_SM_ASF_CONTROL_PL_TO			 (1L<<5)1082#define BNX2_MISC_SM_ASF_CONTROL_RT_TO			 (1L<<6)1083#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT		 (1L<<7)1084#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN		 (1L<<8)1085#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE		 (1L<<9)1086#define BNX2_MISC_SM_ASF_CONTROL_RES			 (0x3L<<10)1087#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN			 (1L<<12)1088#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN		 (1L<<13)1089#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT	 (1L<<14)1090#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD		 (1L<<15)1091#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1		 (0x7fL<<16)1092#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2		 (0x7fL<<23)1093#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0	 (1L<<30)1094#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN		 (1L<<31)1095 1096#define BNX2_MISC_SMB_IN				0x000008841097#define BNX2_MISC_SMB_IN_DAT_IN				 (0xffL<<0)1098#define BNX2_MISC_SMB_IN_RDY				 (1L<<8)1099#define BNX2_MISC_SMB_IN_DONE				 (1L<<9)1100#define BNX2_MISC_SMB_IN_FIRSTBYTE			 (1L<<10)1101#define BNX2_MISC_SMB_IN_STATUS				 (0x7L<<11)1102#define BNX2_MISC_SMB_IN_STATUS_OK			 (0x0L<<11)1103#define BNX2_MISC_SMB_IN_STATUS_PEC			 (0x1L<<11)1104#define BNX2_MISC_SMB_IN_STATUS_OFLOW			 (0x2L<<11)1105#define BNX2_MISC_SMB_IN_STATUS_STOP			 (0x3L<<11)1106#define BNX2_MISC_SMB_IN_STATUS_TIMEOUT			 (0x4L<<11)1107 1108#define BNX2_MISC_SMB_OUT				0x000008881109#define BNX2_MISC_SMB_OUT_DAT_OUT			 (0xffL<<0)1110#define BNX2_MISC_SMB_OUT_RDY				 (1L<<8)1111#define BNX2_MISC_SMB_OUT_START				 (1L<<9)1112#define BNX2_MISC_SMB_OUT_LAST				 (1L<<10)1113#define BNX2_MISC_SMB_OUT_ACC_TYPE			 (1L<<11)1114#define BNX2_MISC_SMB_OUT_ENB_PEC			 (1L<<12)1115#define BNX2_MISC_SMB_OUT_GET_RX_LEN			 (1L<<13)1116#define BNX2_MISC_SMB_OUT_SMB_READ_LEN			 (0x3fL<<14)1117#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS		 (0xfL<<20)1118#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK		 (0L<<20)1119#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK	 (1L<<20)1120#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW		 (2L<<20)1121#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP		 (3L<<20)1122#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT	 (4L<<20)1123#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST	 (5L<<20)1124#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK		 (6L<<20)1125#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK	 (9L<<20)1126#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST	 (0xdL<<20)1127#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE		 (1L<<24)1128#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN		 (1L<<25)1129#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN		 (1L<<26)1130#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN		 (1L<<27)1131#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN		 (1L<<28)1132 1133#define BNX2_MISC_SMB_WATCHDOG				0x0000088c1134#define BNX2_MISC_SMB_WATCHDOG_WATCHDOG			 (0xffffL<<0)1135 1136#define BNX2_MISC_SMB_HEARTBEAT				0x000008901137#define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT		 (0xffffL<<0)1138 1139#define BNX2_MISC_SMB_POLL_ASF				0x000008941140#define BNX2_MISC_SMB_POLL_ASF_POLL_ASF			 (0xffffL<<0)1141 1142#define BNX2_MISC_SMB_POLL_LEGACY			0x000008981143#define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY		 (0xffffL<<0)1144 1145#define BNX2_MISC_SMB_RETRAN				0x0000089c1146#define BNX2_MISC_SMB_RETRAN_RETRAN			 (0xffL<<0)1147 1148#define BNX2_MISC_SMB_TIMESTAMP				0x000008a01149#define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP		 (0xffffffffL<<0)1150 1151#define BNX2_MISC_PERR_ENA0				0x000008a41152#define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC		 (1L<<0)1153#define BNX2_MISC_PERR_ENA0_COM_MISC_REGF		 (1L<<1)1154#define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD		 (1L<<2)1155#define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC		 (1L<<3)1156#define BNX2_MISC_PERR_ENA0_CP_MISC_REGF		 (1L<<4)1157#define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD		 (1L<<5)1158#define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM		 (1L<<6)1159#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0		 (1L<<7)1160#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1		 (1L<<8)1161#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2		 (1L<<9)1162#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3		 (1L<<10)1163#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4		 (1L<<11)1164#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5		 (1L<<12)1165#define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL		 (1L<<13)1166#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0		 (1L<<14)1167#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1		 (1L<<15)1168#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2		 (1L<<16)1169#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3		 (1L<<17)1170#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4		 (1L<<18)1171#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0		 (1L<<19)1172#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1		 (1L<<20)1173#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2		 (1L<<21)1174#define BNX2_MISC_PERR_ENA0_HC_MISC_DMA			 (1L<<22)1175#define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF		 (1L<<23)1176#define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD		 (1L<<24)1177#define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX			 (1L<<25)1178#define BNX2_MISC_PERR_ENA0_RBDC_MISC			 (1L<<26)1179#define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB		 (1L<<27)1180#define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR		 (1L<<28)1181#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC		 (1L<<29)1182#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM		 (1L<<30)1183#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS		 (1L<<31)1184#define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI		 (1L<<0)1185#define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI		 (1L<<1)1186#define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI	 (1L<<2)1187#define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI	 (1L<<3)1188#define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI	 (1L<<4)1189#define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI	 (1L<<5)1190#define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI	 (1L<<6)1191#define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI		 (1L<<7)1192#define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI	 (1L<<8)1193#define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI		 (1L<<9)1194#define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI		 (1L<<10)1195#define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI	 (1L<<11)1196#define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI		 (1L<<12)1197#define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI	 (1L<<13)1198#define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI	 (1L<<14)1199#define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI		 (1L<<15)1200#define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI	 (1L<<16)1201#define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI		 (1L<<17)1202#define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI		 (1L<<18)1203#define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI	 (1L<<19)1204#define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI	 (1L<<20)1205#define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI	 (1L<<21)1206#define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI	 (1L<<22)1207#define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI	 (1L<<23)1208#define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI	 (1L<<24)1209#define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI	 (1L<<25)1210#define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI	 (1L<<26)1211#define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI		 (1L<<27)1212#define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI		 (1L<<28)1213#define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI		 (1L<<29)1214#define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI		 (1L<<30)1215#define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI		 (1L<<31)1216 1217#define BNX2_MISC_PERR_ENA1				0x000008a81218#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS		 (1L<<0)1219#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM		 (1L<<1)1220#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM		 (1L<<2)1221#define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC		 (1L<<3)1222#define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF		 (1L<<4)1223#define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD		 (1L<<5)1224#define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC		 (1L<<6)1225#define BNX2_MISC_PERR_ENA1_TBDC_MISC			 (1L<<7)1226#define BNX2_MISC_PERR_ENA1_TDMA_MISC			 (1L<<8)1227#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0		 (1L<<9)1228#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1		 (1L<<10)1229#define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF		 (1L<<11)1230#define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD		 (1L<<12)1231#define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB		 (1L<<13)1232#define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR		 (1L<<14)1233#define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC		 (1L<<15)1234#define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF		 (1L<<16)1235#define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD		 (1L<<17)1236#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX		 (1L<<18)1237#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX		 (1L<<19)1238#define BNX2_MISC_PERR_ENA1_UMP_MISC_RX			 (1L<<20)1239#define BNX2_MISC_PERR_ENA1_UMP_MISC_TX			 (1L<<21)1240#define BNX2_MISC_PERR_ENA1_RDMAQ_MISC			 (1L<<22)1241#define BNX2_MISC_PERR_ENA1_CSQ_MISC			 (1L<<23)1242#define BNX2_MISC_PERR_ENA1_CPQ_MISC			 (1L<<24)1243#define BNX2_MISC_PERR_ENA1_MCPQ_MISC			 (1L<<25)1244#define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC			 (1L<<26)1245#define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC			 (1L<<27)1246#define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC			 (1L<<28)1247#define BNX2_MISC_PERR_ENA1_RXPQ_MISC			 (1L<<29)1248#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC			 (1L<<30)1249#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC			 (1L<<31)1250#define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI		 (1L<<0)1251#define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI	 (1L<<2)1252#define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI		 (1L<<3)1253#define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI		 (1L<<4)1254#define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI	 (1L<<5)1255#define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI	 (1L<<6)1256#define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI		 (1L<<7)1257#define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI		 (1L<<8)1258#define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI		 (1L<<9)1259#define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI		 (1L<<10)1260#define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI		 (1L<<11)1261#define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI		 (1L<<12)1262#define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI		 (1L<<13)1263#define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI		 (1L<<14)1264#define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI		 (1L<<15)1265#define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI		 (1L<<16)1266#define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI		 (1L<<17)1267#define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI		 (1L<<18)1268#define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI		 (1L<<19)1269#define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI		 (1L<<20)1270#define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI		 (1L<<21)1271#define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI		 (1L<<22)1272#define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI		 (1L<<23)1273#define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI		 (1L<<24)1274#define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI		 (1L<<25)1275#define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI		 (1L<<26)1276#define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI	 (1L<<27)1277#define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI		 (1L<<28)1278#define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI		 (1L<<29)1279 1280#define BNX2_MISC_PERR_ENA2				0x000008ac1281#define BNX2_MISC_PERR_ENA2_COMQ_MISC			 (1L<<0)1282#define BNX2_MISC_PERR_ENA2_COMXQ_MISC			 (1L<<1)1283#define BNX2_MISC_PERR_ENA2_COMTQ_MISC			 (1L<<2)1284#define BNX2_MISC_PERR_ENA2_TSCHQ_MISC			 (1L<<3)1285#define BNX2_MISC_PERR_ENA2_TBDRQ_MISC			 (1L<<4)1286#define BNX2_MISC_PERR_ENA2_TXPQ_MISC			 (1L<<5)1287#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC			 (1L<<6)1288#define BNX2_MISC_PERR_ENA2_TPATQ_MISC			 (1L<<7)1289#define BNX2_MISC_PERR_ENA2_TASQ_MISC			 (1L<<8)1290#define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI		 (1L<<0)1291#define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI		 (1L<<1)1292#define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI		 (1L<<2)1293#define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI		 (1L<<3)1294#define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI	 (1L<<4)1295#define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI		 (1L<<5)1296#define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI	 (1L<<6)1297 1298#define BNX2_MISC_DEBUG_VECTOR_SEL			0x000008b01299#define BNX2_MISC_DEBUG_VECTOR_SEL_0			 (0xfffL<<0)1300#define BNX2_MISC_DEBUG_VECTOR_SEL_1			 (0xfffL<<12)1301#define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI			 (0xfffL<<15)1302 1303#define BNX2_MISC_VREG_CONTROL				0x000008b41304#define BNX2_MISC_VREG_CONTROL_1_2			 (0xfL<<0)1305#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI		 (0xfL<<0)1306#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI	 (0L<<0)1307#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI	 (1L<<0)1308#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI	 (2L<<0)1309#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI	 (3L<<0)1310#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI	 (4L<<0)1311#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI	 (5L<<0)1312#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI	 (6L<<0)1313#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI		 (7L<<0)1314#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI	 (8L<<0)1315#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI	 (9L<<0)1316#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI	 (10L<<0)1317#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI	 (11L<<0)1318#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI	 (12L<<0)1319#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI	 (13L<<0)1320#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI	 (14L<<0)1321#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI	 (15L<<0)1322#define BNX2_MISC_VREG_CONTROL_2_5			 (0xfL<<4)1323#define BNX2_MISC_VREG_CONTROL_2_5_PLUS14		 (0L<<4)1324#define BNX2_MISC_VREG_CONTROL_2_5_PLUS12		 (1L<<4)1325#define BNX2_MISC_VREG_CONTROL_2_5_PLUS10		 (2L<<4)1326#define BNX2_MISC_VREG_CONTROL_2_5_PLUS8		 (3L<<4)1327#define BNX2_MISC_VREG_CONTROL_2_5_PLUS6		 (4L<<4)1328#define BNX2_MISC_VREG_CONTROL_2_5_PLUS4		 (5L<<4)1329#define BNX2_MISC_VREG_CONTROL_2_5_PLUS2		 (6L<<4)1330#define BNX2_MISC_VREG_CONTROL_2_5_NOM			 (7L<<4)1331#define BNX2_MISC_VREG_CONTROL_2_5_MINUS2		 (8L<<4)1332#define BNX2_MISC_VREG_CONTROL_2_5_MINUS4		 (9L<<4)1333#define BNX2_MISC_VREG_CONTROL_2_5_MINUS6		 (10L<<4)1334#define BNX2_MISC_VREG_CONTROL_2_5_MINUS8		 (11L<<4)1335#define BNX2_MISC_VREG_CONTROL_2_5_MINUS10		 (12L<<4)1336#define BNX2_MISC_VREG_CONTROL_2_5_MINUS12		 (13L<<4)1337#define BNX2_MISC_VREG_CONTROL_2_5_MINUS14		 (14L<<4)1338#define BNX2_MISC_VREG_CONTROL_2_5_MINUS16		 (15L<<4)1339#define BNX2_MISC_VREG_CONTROL_1_0_MGMT			 (0xfL<<8)1340#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14		 (0L<<8)1341#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12		 (1L<<8)1342#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10		 (2L<<8)1343#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8		 (3L<<8)1344#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6		 (4L<<8)1345#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4		 (5L<<8)1346#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2		 (6L<<8)1347#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM		 (7L<<8)1348#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2		 (8L<<8)1349#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4		 (9L<<8)1350#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6		 (10L<<8)1351#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8		 (11L<<8)1352#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10		 (12L<<8)1353#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12		 (13L<<8)1354#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14		 (14L<<8)1355#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16		 (15L<<8)1356 1357#define BNX2_MISC_FINAL_CLK_CTL_VAL			0x000008b81358#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL	 (0x3ffffffL<<6)1359 1360#define BNX2_MISC_GP_HW_CTL0				0x000008bc1361#define BNX2_MISC_GP_HW_CTL0_TX_DRIVE			 (1L<<0)1362#define BNX2_MISC_GP_HW_CTL0_RMII_MODE			 (1L<<1)1363#define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL		 (1L<<2)1364#define BNX2_MISC_GP_HW_CTL0_RVMII_MODE			 (1L<<3)1365#define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE	 (1L<<4)1366#define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE	 (1L<<5)1367#define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE	 (1L<<6)1368#define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI		 (0x7L<<4)1369#define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY	 (1L<<7)1370#define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE	 (1L<<8)1371#define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE	 (1L<<9)1372#define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE		 (1L<<10)1373#define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI		 (0x7L<<8)1374#define BNX2_MISC_GP_HW_CTL0_UP1_DEF0			 (1L<<11)1375#define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF		 (1L<<12)1376#define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF		 (1L<<13)1377#define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF		 (1L<<14)1378#define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF	 (1L<<15)1379#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI		 (0xfL<<16)1380#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA		 (0L<<16)1381#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA		 (1L<<16)1382#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA		 (3L<<16)1383#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA		 (5L<<16)1384#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA		 (7L<<16)1385#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN		 (15L<<16)1386#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS		 (1L<<20)1387#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS		 (1L<<21)1388#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT		 (0x3L<<22)1389#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P		 (0L<<22)1390#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P		 (1L<<22)1391#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P		 (2L<<22)1392#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P		 (3L<<22)1393#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT		 (0x3L<<24)1394#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P		 (0L<<24)1395#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P		 (1L<<24)1396#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P		 (2L<<24)1397#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P		 (3L<<24)1398#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ		 (0x3L<<26)1399#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA	 (0L<<26)1400#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA	 (1L<<26)1401#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA	 (2L<<26)1402#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA	 (3L<<26)1403#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ		 (0x3L<<28)1404#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA	 (0L<<28)1405#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA	 (1L<<28)1406#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA	 (2L<<28)1407#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA	 (3L<<28)1408#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ		 (0x3L<<30)1409#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57	 (0L<<30)1410#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45	 (1L<<30)1411#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62	 (2L<<30)1412#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66	 (3L<<30)1413 1414#define BNX2_MISC_GP_HW_CTL1				0x000008c01415#define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE	 (1L<<0)1416#define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE	 (1L<<1)1417#define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE		 (1L<<2)1418#define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE		 (1L<<3)1419#define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI		 (0xffffL<<0)1420#define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI		 (0xffffL<<16)1421 1422#define BNX2_MISC_NEW_HW_CTL				0x000008c41423#define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS		 (1L<<0)1424#define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE		 (1L<<1)1425#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0		 (1L<<2)1426#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1		 (1L<<3)1427#define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED		 (0xfffL<<4)1428#define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT		 (0xffffL<<16)1429 1430#define BNX2_MISC_NEW_CORE_CTL				0x000008c81431#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS	 (1L<<0)1432#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ		 (1L<<1)1433#define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE		 (1L<<16)1434#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN		 (0x3fffL<<2)1435#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC		 (0xffffL<<16)1436 1437#define BNX2_MISC_ECO_HW_CTL				0x000008cc1438#define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN		 (1L<<0)1439#define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT		 (0x7fffL<<1)1440#define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD		 (0xffffL<<16)1441 1442#define BNX2_MISC_ECO_CORE_CTL				0x000008d01443#define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT		 (0xffffL<<0)1444#define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD		 (0xffffL<<16)1445 1446#define BNX2_MISC_PPIO					0x000008d41447#define BNX2_MISC_PPIO_VALUE				 (0xfL<<0)1448#define BNX2_MISC_PPIO_SET				 (0xfL<<8)1449#define BNX2_MISC_PPIO_CLR				 (0xfL<<16)1450#define BNX2_MISC_PPIO_FLOAT				 (0xfL<<24)1451 1452#define BNX2_MISC_PPIO_INT				0x000008d81453#define BNX2_MISC_PPIO_INT_INT_STATE			 (0xfL<<0)1454#define BNX2_MISC_PPIO_INT_OLD_VALUE			 (0xfL<<8)1455#define BNX2_MISC_PPIO_INT_OLD_SET			 (0xfL<<16)1456#define BNX2_MISC_PPIO_INT_OLD_CLR			 (0xfL<<24)1457 1458#define BNX2_MISC_RESET_NUMS				0x000008dc1459#define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS		 (0x7L<<0)1460#define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS		 (0x7L<<4)1461#define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS		 (0x7L<<8)1462#define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS		 (0x7L<<12)1463#define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS		 (0x7L<<16)1464 1465#define BNX2_MISC_CS16_ERR				0x000008e01466#define BNX2_MISC_CS16_ERR_ENA_PCI			 (1L<<0)1467#define BNX2_MISC_CS16_ERR_ENA_RDMA			 (1L<<1)1468#define BNX2_MISC_CS16_ERR_ENA_TDMA			 (1L<<2)1469#define BNX2_MISC_CS16_ERR_ENA_EMAC			 (1L<<3)1470#define BNX2_MISC_CS16_ERR_ENA_CTX			 (1L<<4)1471#define BNX2_MISC_CS16_ERR_ENA_TBDR			 (1L<<5)1472#define BNX2_MISC_CS16_ERR_ENA_RBDC			 (1L<<6)1473#define BNX2_MISC_CS16_ERR_ENA_COM			 (1L<<7)1474#define BNX2_MISC_CS16_ERR_ENA_CP			 (1L<<8)1475#define BNX2_MISC_CS16_ERR_STA_PCI			 (1L<<16)1476#define BNX2_MISC_CS16_ERR_STA_RDMA			 (1L<<17)1477#define BNX2_MISC_CS16_ERR_STA_TDMA			 (1L<<18)1478#define BNX2_MISC_CS16_ERR_STA_EMAC			 (1L<<19)1479#define BNX2_MISC_CS16_ERR_STA_CTX			 (1L<<20)1480#define BNX2_MISC_CS16_ERR_STA_TBDR			 (1L<<21)1481#define BNX2_MISC_CS16_ERR_STA_RBDC			 (1L<<22)1482#define BNX2_MISC_CS16_ERR_STA_COM			 (1L<<23)1483#define BNX2_MISC_CS16_ERR_STA_CP			 (1L<<24)1484 1485#define BNX2_MISC_SPIO_EVENT				0x000008e41486#define BNX2_MISC_SPIO_EVENT_ENABLE			 (0xffL<<0)1487 1488#define BNX2_MISC_PPIO_EVENT				0x000008e81489#define BNX2_MISC_PPIO_EVENT_ENABLE			 (0xfL<<0)1490 1491#define BNX2_MISC_DUAL_MEDIA_CTRL			0x000008ec1492#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID		 (0xffL<<0)1493#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X		 (0L<<0)1494#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C		 (3L<<0)1495#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S		 (12L<<0)1496#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP	 (0x7L<<8)1497#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN		 (1L<<11)1498#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET	 (1L<<12)1499#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET	 (1L<<13)1500#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET		 (1L<<14)1501#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET		 (1L<<15)1502#define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST		 (1L<<16)1503#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST		 (1L<<17)1504#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST		 (1L<<18)1505#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST		 (1L<<19)1506#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST		 (1L<<20)1507#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL		 (0x7L<<21)1508#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP		 (1L<<24)1509#define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE	 (1L<<25)1510#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ	 (0xfL<<26)1511#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ	 (1L<<26)1512#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ	 (2L<<26)1513#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ	 (4L<<26)1514#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ	 (8L<<26)1515 1516#define BNX2_MISC_OTP_CMD1				0x000008f01517#define BNX2_MISC_OTP_CMD1_FMODE			 (0x7L<<0)1518#define BNX2_MISC_OTP_CMD1_FMODE_IDLE			 (0L<<0)1519#define BNX2_MISC_OTP_CMD1_FMODE_WRITE			 (1L<<0)1520#define BNX2_MISC_OTP_CMD1_FMODE_INIT			 (2L<<0)1521#define BNX2_MISC_OTP_CMD1_FMODE_SET			 (3L<<0)1522#define BNX2_MISC_OTP_CMD1_FMODE_RST			 (4L<<0)1523#define BNX2_MISC_OTP_CMD1_FMODE_VERIFY			 (5L<<0)1524#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0		 (6L<<0)1525#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1		 (7L<<0)1526#define BNX2_MISC_OTP_CMD1_USEPINS			 (1L<<8)1527#define BNX2_MISC_OTP_CMD1_PROGSEL			 (1L<<9)1528#define BNX2_MISC_OTP_CMD1_PROGSTART			 (1L<<10)1529#define BNX2_MISC_OTP_CMD1_PCOUNT			 (0x7L<<16)1530#define BNX2_MISC_OTP_CMD1_PBYP				 (1L<<19)1531#define BNX2_MISC_OTP_CMD1_VSEL				 (0xfL<<20)1532#define BNX2_MISC_OTP_CMD1_TM				 (0x7L<<27)1533#define BNX2_MISC_OTP_CMD1_SADBYP			 (1L<<30)1534#define BNX2_MISC_OTP_CMD1_DEBUG			 (1L<<31)1535 1536#define BNX2_MISC_OTP_CMD2				0x000008f41537#define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR			 (0x3ffL<<0)1538#define BNX2_MISC_OTP_CMD2_DOSEL			 (0x7fL<<16)1539#define BNX2_MISC_OTP_CMD2_DOSEL_0			 (0L<<16)1540#define BNX2_MISC_OTP_CMD2_DOSEL_1			 (1L<<16)1541#define BNX2_MISC_OTP_CMD2_DOSEL_127			 (127L<<16)1542 1543#define BNX2_MISC_OTP_STATUS				0x000008f81544#define BNX2_MISC_OTP_STATUS_DATA			 (0xffL<<0)1545#define BNX2_MISC_OTP_STATUS_VALID			 (1L<<8)1546#define BNX2_MISC_OTP_STATUS_BUSY			 (1L<<9)1547#define BNX2_MISC_OTP_STATUS_BUSYSM			 (1L<<10)1548#define BNX2_MISC_OTP_STATUS_DONE			 (1L<<11)1549 1550#define BNX2_MISC_OTP_SHIFT1_CMD			0x000008fc1551#define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N		 (1L<<0)1552#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE		 (1L<<1)1553#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START		 (1L<<2)1554#define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA		 (1L<<3)1555#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT		 (0x1fL<<8)1556 1557#define BNX2_MISC_OTP_SHIFT1_DATA			0x000009001558#define BNX2_MISC_OTP_SHIFT2_CMD			0x000009041559#define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N		 (1L<<0)1560#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE		 (1L<<1)1561#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START		 (1L<<2)1562#define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA		 (1L<<3)1563#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT		 (0x1fL<<8)1564 1565#define BNX2_MISC_OTP_SHIFT2_DATA			0x000009081566#define BNX2_MISC_BIST_CS0				0x0000090c1567#define BNX2_MISC_BIST_CS0_MBIST_EN			 (1L<<0)1568#define BNX2_MISC_BIST_CS0_BIST_SETUP			 (0x3L<<1)1569#define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET		 (1L<<3)1570#define BNX2_MISC_BIST_CS0_MBIST_DONE			 (1L<<8)1571#define BNX2_MISC_BIST_CS0_MBIST_GO			 (1L<<9)1572#define BNX2_MISC_BIST_CS0_BIST_OVERRIDE		 (1L<<31)1573 1574#define BNX2_MISC_BIST_MEMSTATUS0			0x000009101575#define BNX2_MISC_BIST_CS1				0x000009141576#define BNX2_MISC_BIST_CS1_MBIST_EN			 (1L<<0)1577#define BNX2_MISC_BIST_CS1_BIST_SETUP			 (0x3L<<1)1578#define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET		 (1L<<3)1579#define BNX2_MISC_BIST_CS1_MBIST_DONE			 (1L<<8)1580#define BNX2_MISC_BIST_CS1_MBIST_GO			 (1L<<9)1581 1582#define BNX2_MISC_BIST_MEMSTATUS1			0x000009181583#define BNX2_MISC_BIST_CS2				0x0000091c1584#define BNX2_MISC_BIST_CS2_MBIST_EN			 (1L<<0)1585#define BNX2_MISC_BIST_CS2_BIST_SETUP			 (0x3L<<1)1586#define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET		 (1L<<3)1587#define BNX2_MISC_BIST_CS2_MBIST_DONE			 (1L<<8)1588#define BNX2_MISC_BIST_CS2_MBIST_GO			 (1L<<9)1589 1590#define BNX2_MISC_BIST_MEMSTATUS2			0x000009201591#define BNX2_MISC_BIST_CS3				0x000009241592#define BNX2_MISC_BIST_CS3_MBIST_EN			 (1L<<0)1593#define BNX2_MISC_BIST_CS3_BIST_SETUP			 (0x3L<<1)1594#define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET		 (1L<<3)1595#define BNX2_MISC_BIST_CS3_MBIST_DONE			 (1L<<8)1596#define BNX2_MISC_BIST_CS3_MBIST_GO			 (1L<<9)1597 1598#define BNX2_MISC_BIST_MEMSTATUS3			0x000009281599#define BNX2_MISC_BIST_CS4				0x0000092c1600#define BNX2_MISC_BIST_CS4_MBIST_EN			 (1L<<0)1601#define BNX2_MISC_BIST_CS4_BIST_SETUP			 (0x3L<<1)1602#define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET		 (1L<<3)1603#define BNX2_MISC_BIST_CS4_MBIST_DONE			 (1L<<8)1604#define BNX2_MISC_BIST_CS4_MBIST_GO			 (1L<<9)1605 1606#define BNX2_MISC_BIST_MEMSTATUS4			0x000009301607#define BNX2_MISC_BIST_CS5				0x000009341608#define BNX2_MISC_BIST_CS5_MBIST_EN			 (1L<<0)1609#define BNX2_MISC_BIST_CS5_BIST_SETUP			 (0x3L<<1)1610#define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET		 (1L<<3)1611#define BNX2_MISC_BIST_CS5_MBIST_DONE			 (1L<<8)1612#define BNX2_MISC_BIST_CS5_MBIST_GO			 (1L<<9)1613 1614#define BNX2_MISC_BIST_MEMSTATUS5			0x000009381615#define BNX2_MISC_MEM_TM0				0x0000093c1616#define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM		 (0xfL<<0)1617#define BNX2_MISC_MEM_TM0_MCP_SCPAD			 (0xfL<<8)1618#define BNX2_MISC_MEM_TM0_UMP_TM			 (0xffL<<16)1619#define BNX2_MISC_MEM_TM0_HB_MEM_TM			 (0xfL<<24)1620 1621#define BNX2_MISC_USPLL_CTRL				0x000009401622#define BNX2_MISC_USPLL_CTRL_PH_DET_DIS			 (1L<<0)1623#define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS		 (1L<<1)1624#define BNX2_MISC_USPLL_CTRL_LCPX			 (0x3fL<<2)1625#define BNX2_MISC_USPLL_CTRL_RX				 (0x3L<<8)1626#define BNX2_MISC_USPLL_CTRL_VC_EN			 (1L<<10)1627#define BNX2_MISC_USPLL_CTRL_VCO_MG			 (0x3L<<11)1628#define BNX2_MISC_USPLL_CTRL_KVCO_XF			 (0x7L<<13)1629#define BNX2_MISC_USPLL_CTRL_KVCO_XS			 (0x7L<<16)1630#define BNX2_MISC_USPLL_CTRL_TESTD_EN			 (1L<<19)1631#define BNX2_MISC_USPLL_CTRL_TESTD_SEL			 (0x7L<<20)1632#define BNX2_MISC_USPLL_CTRL_TESTA_EN			 (1L<<23)1633#define BNX2_MISC_USPLL_CTRL_TESTA_SEL			 (0x3L<<24)1634#define BNX2_MISC_USPLL_CTRL_ATTEN_FREF			 (1L<<26)1635#define BNX2_MISC_USPLL_CTRL_DIGITAL_RST		 (1L<<27)1636#define BNX2_MISC_USPLL_CTRL_ANALOG_RST			 (1L<<28)1637#define BNX2_MISC_USPLL_CTRL_LOCK			 (1L<<29)1638 1639#define BNX2_MISC_PERR_STATUS0				0x000009441640#define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR		 (1L<<0)1641#define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR		 (1L<<1)1642#define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR	 (1L<<2)1643#define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR	 (1L<<3)1644#define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR		 (1L<<4)1645#define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR		 (1L<<5)1646#define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR		 (1L<<6)1647#define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR		 (1L<<7)1648#define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR		 (1L<<8)1649#define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR		 (1L<<9)1650#define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR		 (1L<<10)1651#define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR		 (1L<<11)1652#define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR		 (1L<<12)1653#define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR		 (1L<<13)1654#define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR		 (1L<<14)1655#define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR		 (1L<<15)1656#define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR		 (1L<<16)1657#define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR		 (1L<<17)1658#define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR		 (1L<<18)1659#define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR	 (1L<<19)1660#define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR	 (1L<<20)1661#define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR		 (1L<<21)1662#define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR	 (1L<<22)1663#define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR		 (1L<<23)1664#define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR		 (1L<<24)1665#define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR	 (1L<<25)1666#define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR	 (1L<<26)1667#define BNX2_MISC_PERR_STATUS0_TPBUF_PERR		 (1L<<27)1668#define BNX2_MISC_PERR_STATUS0_THBUF_PERR		 (1L<<28)1669#define BNX2_MISC_PERR_STATUS0_TDMA_PERR		 (1L<<29)1670#define BNX2_MISC_PERR_STATUS0_TBDC_PERR		 (1L<<30)1671#define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR		 (1L<<31)1672 1673#define BNX2_MISC_PERR_STATUS1				0x000009481674#define BNX2_MISC_PERR_STATUS1_RBDC_PERR		 (1L<<0)1675#define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR		 (1L<<2)1676#define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR		 (1L<<3)1677#define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR		 (1L<<4)1678#define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR	 (1L<<5)1679#define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR	 (1L<<6)1680#define BNX2_MISC_PERR_STATUS1_TPATQ_PERR		 (1L<<7)1681#define BNX2_MISC_PERR_STATUS1_MCPQ_PERR		 (1L<<8)1682#define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR		 (1L<<9)1683#define BNX2_MISC_PERR_STATUS1_TXPQ_PERR		 (1L<<10)1684#define BNX2_MISC_PERR_STATUS1_COMTQ_PERR		 (1L<<11)1685#define BNX2_MISC_PERR_STATUS1_COMQ_PERR		 (1L<<12)1686#define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR		 (1L<<13)1687#define BNX2_MISC_PERR_STATUS1_RXPQ_PERR		 (1L<<14)1688#define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR		 (1L<<15)1689#define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR		 (1L<<16)1690#define BNX2_MISC_PERR_STATUS1_TASQ_PERR		 (1L<<17)1691#define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR		 (1L<<18)1692#define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR		 (1L<<19)1693#define BNX2_MISC_PERR_STATUS1_COMXQ_PERR		 (1L<<20)1694#define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR		 (1L<<21)1695#define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR		 (1L<<22)1696#define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR		 (1L<<23)1697#define BNX2_MISC_PERR_STATUS1_CPQ_PERR			 (1L<<24)1698#define BNX2_MISC_PERR_STATUS1_CSQ_PERR			 (1L<<25)1699#define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR		 (1L<<26)1700#define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR		 (1L<<27)1701#define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR		 (1L<<28)1702#define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR		 (1L<<29)1703 1704#define BNX2_MISC_PERR_STATUS2				0x0000094c1705#define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR		 (1L<<0)1706#define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR		 (1L<<1)1707#define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR		 (1L<<2)1708#define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR		 (1L<<3)1709#define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR		 (1L<<4)1710#define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR		 (1L<<5)1711#define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR		 (1L<<6)1712 1713#define BNX2_MISC_LCPLL_CTRL0				0x000009501714#define BNX2_MISC_LCPLL_CTRL0_OAC			 (0x7L<<0)1715#define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY		 (0L<<0)1716#define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO			 (1L<<0)1717#define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY		 (3L<<0)1718#define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY			 (7L<<0)1719#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL			 (0x7L<<3)1720#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360		 (0L<<3)1721#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480		 (1L<<3)1722#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600		 (3L<<3)1723#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720		 (7L<<3)1724#define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL			 (0x3L<<6)1725#define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE		 (0x7L<<8)1726#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL			 (0x3L<<11)1727#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0		 (0L<<11)1728#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1		 (1L<<11)1729#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2		 (2L<<11)1730#define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART		 (1L<<13)1731#define BNX2_MISC_LCPLL_CTRL0_RESERVED			 (1L<<14)1732#define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN		 (1L<<15)1733#define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN		 (1L<<16)1734#define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN		 (1L<<17)1735#define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN		 (1L<<18)1736#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN		 (1L<<19)1737#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE		 (1L<<20)1738#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS		 (1L<<21)1739#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN	 (1L<<22)1740#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE		 (1L<<23)1741#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN	 (1L<<24)1742#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS		 (1L<<25)1743#define BNX2_MISC_LCPLL_CTRL0_CAPRESTART		 (1L<<26)1744#define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN		 (1L<<27)1745 1746#define BNX2_MISC_LCPLL_CTRL1				0x000009541747#define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM		 (0x1fL<<0)1748#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN	 (1L<<5)1749#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN		 (1L<<6)1750#define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR		 (1L<<7)1751 1752#define BNX2_MISC_LCPLL_STATUS				0x000009581753#define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM		 (1L<<0)1754#define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM		 (1L<<1)1755#define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE		 (1L<<2)1756#define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS		 (1L<<3)1757#define BNX2_MISC_LCPLL_STATUS_PLLSTATE			 (0x7L<<4)1758#define BNX2_MISC_LCPLL_STATUS_CAPSTATE			 (0x7L<<7)1759#define BNX2_MISC_LCPLL_STATUS_CAPSELECT		 (0x1fL<<10)1760#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR		 (1L<<15)1761#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0	 (0L<<15)1762#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1	 (1L<<15)1763 1764#define BNX2_MISC_OSCFUNDS_CTRL				0x0000095c1765#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON		 (1L<<5)1766#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF		 (0L<<5)1767#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON		 (1L<<5)1768#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM		 (0x3L<<6)1769#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0		 (0L<<6)1770#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1		 (1L<<6)1771#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2		 (2L<<6)1772#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3		 (3L<<6)1773#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ		 (0x3L<<8)1774#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0		 (0L<<8)1775#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1		 (1L<<8)1776#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2		 (2L<<8)1777#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3		 (3L<<8)1778#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ		 (0x3L<<10)1779#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0		 (0L<<10)1780#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1		 (1L<<10)1781#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2		 (2L<<10)1782#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3		 (3L<<10)1783 1784 1785/*1786 *  nvm_reg definition1787 *  offset: 0x64001788 */1789#define BNX2_NVM_COMMAND				0x000064001790#define BNX2_NVM_COMMAND_RST				 (1L<<0)1791#define BNX2_NVM_COMMAND_DONE				 (1L<<3)1792#define BNX2_NVM_COMMAND_DOIT				 (1L<<4)1793#define BNX2_NVM_COMMAND_WR				 (1L<<5)1794#define BNX2_NVM_COMMAND_ERASE				 (1L<<6)1795#define BNX2_NVM_COMMAND_FIRST				 (1L<<7)1796#define BNX2_NVM_COMMAND_LAST				 (1L<<8)1797#define BNX2_NVM_COMMAND_WREN				 (1L<<16)1798#define BNX2_NVM_COMMAND_WRDI				 (1L<<17)1799#define BNX2_NVM_COMMAND_EWSR				 (1L<<18)1800#define BNX2_NVM_COMMAND_WRSR				 (1L<<19)1801#define BNX2_NVM_COMMAND_RD_ID				 (1L<<20)1802#define BNX2_NVM_COMMAND_RD_STATUS			 (1L<<21)1803#define BNX2_NVM_COMMAND_MODE_256			 (1L<<22)1804 1805#define BNX2_NVM_STATUS					0x000064041806#define BNX2_NVM_STATUS_PI_FSM_STATE			 (0xfL<<0)1807#define BNX2_NVM_STATUS_EE_FSM_STATE			 (0xfL<<4)1808#define BNX2_NVM_STATUS_EQ_FSM_STATE			 (0xfL<<8)1809#define BNX2_NVM_STATUS_SPI_FSM_STATE_XI		 (0x1fL<<0)1810#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI	 (0L<<0)1811#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI	 (1L<<0)1812#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI	 (2L<<0)1813#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI	 (3L<<0)1814#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI	 (4L<<0)1815#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI	 (5L<<0)1816#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI	 (6L<<0)1817#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI	 (7L<<0)1818#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI	 (8L<<0)1819#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI	 (9L<<0)1820#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI	 (10L<<0)1821#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI	 (11L<<0)1822#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI	 (12L<<0)1823#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI	 (13L<<0)1824#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI	 (14L<<0)1825#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI	 (15L<<0)1826#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI	 (16L<<0)1827#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI	 (17L<<0)1828#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI	 (18L<<0)1829#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI	 (19L<<0)1830 1831#define BNX2_NVM_WRITE					0x000064081832#define BNX2_NVM_WRITE_NVM_WRITE_VALUE			 (0xffffffffL<<0)1833#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG		 (0L<<0)1834#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK		 (1L<<0)1835#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA		 (2L<<0)1836#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK		 (4L<<0)1837#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B		 (8L<<0)1838#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO		 (16L<<0)1839#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI		 (32L<<0)1840#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI		 (1L<<0)1841#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI		 (2L<<0)1842#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI		 (4L<<0)1843#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI		 (8L<<0)1844 1845#define BNX2_NVM_ADDR					0x0000640c1846#define BNX2_NVM_ADDR_NVM_ADDR_VALUE			 (0xffffffL<<0)1847#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG		 (0L<<0)1848#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK		 (1L<<0)1849#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA		 (2L<<0)1850#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK		 (4L<<0)1851#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B		 (8L<<0)1852#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO			 (16L<<0)1853#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI			 (32L<<0)1854#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI		 (1L<<0)1855#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI		 (2L<<0)1856#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI		 (4L<<0)1857#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI		 (8L<<0)1858 1859#define BNX2_NVM_READ					0x000064101860#define BNX2_NVM_READ_NVM_READ_VALUE			 (0xffffffffL<<0)1861#define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG		 (0L<<0)1862#define BNX2_NVM_READ_NVM_READ_VALUE_EECLK		 (1L<<0)1863#define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA		 (2L<<0)1864#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK		 (4L<<0)1865#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B		 (8L<<0)1866#define BNX2_NVM_READ_NVM_READ_VALUE_SO			 (16L<<0)1867#define BNX2_NVM_READ_NVM_READ_VALUE_SI			 (32L<<0)1868#define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI		 (1L<<0)1869#define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI		 (2L<<0)1870#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI		 (4L<<0)1871#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI		 (8L<<0)1872 1873#define BNX2_NVM_CFG1					0x000064141874#define BNX2_NVM_CFG1_FLASH_MODE			 (1L<<0)1875#define BNX2_NVM_CFG1_BUFFER_MODE			 (1L<<1)1876#define BNX2_NVM_CFG1_PASS_MODE				 (1L<<2)1877#define BNX2_NVM_CFG1_BITBANG_MODE			 (1L<<3)1878#define BNX2_NVM_CFG1_STATUS_BIT			 (0x7L<<4)1879#define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY		 (0L<<4)1880#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY		 (7L<<4)1881#define BNX2_NVM_CFG1_SPI_CLK_DIV			 (0xfL<<7)1882#define BNX2_NVM_CFG1_SEE_CLK_DIV			 (0x7ffL<<11)1883#define BNX2_NVM_CFG1_STRAP_CONTROL_0			 (1L<<23)1884#define BNX2_NVM_CFG1_PROTECT_MODE			 (1L<<24)1885#define BNX2_NVM_CFG1_FLASH_SIZE			 (1L<<25)1886#define BNX2_NVM_CFG1_FW_USTRAP_1			 (1L<<26)1887#define BNX2_NVM_CFG1_FW_USTRAP_0			 (1L<<27)1888#define BNX2_NVM_CFG1_FW_USTRAP_2			 (1L<<28)1889#define BNX2_NVM_CFG1_FW_USTRAP_3			 (1L<<29)1890#define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN			 (1L<<30)1891#define BNX2_NVM_CFG1_COMPAT_BYPASSS			 (1L<<31)1892 1893#define BNX2_NVM_CFG2					0x000064181894#define BNX2_NVM_CFG2_ERASE_CMD				 (0xffL<<0)1895#define BNX2_NVM_CFG2_DUMMY				 (0xffL<<8)1896#define BNX2_NVM_CFG2_STATUS_CMD			 (0xffL<<16)1897#define BNX2_NVM_CFG2_READ_ID				 (0xffL<<24)1898 1899#define BNX2_NVM_CFG3					0x0000641c1900#define BNX2_NVM_CFG3_BUFFER_RD_CMD			 (0xffL<<0)1901#define BNX2_NVM_CFG3_WRITE_CMD				 (0xffL<<8)1902#define BNX2_NVM_CFG3_BUFFER_WRITE_CMD			 (0xffL<<16)1903#define BNX2_NVM_CFG3_READ_CMD				 (0xffL<<24)1904 1905#define BNX2_NVM_SW_ARB					0x000064201906#define BNX2_NVM_SW_ARB_ARB_REQ_SET0			 (1L<<0)1907#define BNX2_NVM_SW_ARB_ARB_REQ_SET1			 (1L<<1)1908#define BNX2_NVM_SW_ARB_ARB_REQ_SET2			 (1L<<2)1909#define BNX2_NVM_SW_ARB_ARB_REQ_SET3			 (1L<<3)1910#define BNX2_NVM_SW_ARB_ARB_REQ_CLR0			 (1L<<4)1911#define BNX2_NVM_SW_ARB_ARB_REQ_CLR1			 (1L<<5)1912#define BNX2_NVM_SW_ARB_ARB_REQ_CLR2			 (1L<<6)1913#define BNX2_NVM_SW_ARB_ARB_REQ_CLR3			 (1L<<7)1914#define BNX2_NVM_SW_ARB_ARB_ARB0			 (1L<<8)1915#define BNX2_NVM_SW_ARB_ARB_ARB1			 (1L<<9)1916#define BNX2_NVM_SW_ARB_ARB_ARB2			 (1L<<10)1917#define BNX2_NVM_SW_ARB_ARB_ARB3			 (1L<<11)1918#define BNX2_NVM_SW_ARB_REQ0				 (1L<<12)1919#define BNX2_NVM_SW_ARB_REQ1				 (1L<<13)1920#define BNX2_NVM_SW_ARB_REQ2				 (1L<<14)1921#define BNX2_NVM_SW_ARB_REQ3				 (1L<<15)1922 1923#define BNX2_NVM_ACCESS_ENABLE				0x000064241924#define BNX2_NVM_ACCESS_ENABLE_EN			 (1L<<0)1925#define BNX2_NVM_ACCESS_ENABLE_WR_EN			 (1L<<1)1926 1927#define BNX2_NVM_WRITE1					0x000064281928#define BNX2_NVM_WRITE1_WREN_CMD			 (0xffL<<0)1929#define BNX2_NVM_WRITE1_WRDI_CMD			 (0xffL<<8)1930#define BNX2_NVM_WRITE1_SR_DATA				 (0xffL<<16)1931 1932#define BNX2_NVM_CFG4					0x0000642c1933#define BNX2_NVM_CFG4_FLASH_SIZE			 (0x7L<<0)1934#define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT			 (0L<<0)1935#define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT			 (1L<<0)1936#define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT			 (2L<<0)1937#define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT			 (3L<<0)1938#define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT			 (4L<<0)1939#define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT			 (5L<<0)1940#define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT			 (6L<<0)1941#define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT		 (7L<<0)1942#define BNX2_NVM_CFG4_FLASH_VENDOR			 (1L<<3)1943#define BNX2_NVM_CFG4_FLASH_VENDOR_ST			 (0L<<3)1944#define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL		 (1L<<3)1945#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC		 (0x3L<<4)1946#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8	 (0L<<4)1947#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9	 (1L<<4)1948#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10	 (2L<<4)1949#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11	 (3L<<4)1950#define BNX2_NVM_CFG4_STATUS_BIT_POLARITY		 (1L<<6)1951#define BNX2_NVM_CFG4_RESERVED				 (0x1ffffffL<<7)1952 1953#define BNX2_NVM_RECONFIG				0x000064301954#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE		 (0xfL<<0)1955#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST		 (0L<<0)1956#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL	 (1L<<0)1957#define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE		 (0xfL<<4)1958#define BNX2_NVM_RECONFIG_RESERVED			 (0x7fffffL<<8)1959#define BNX2_NVM_RECONFIG_RECONFIG_DONE			 (1L<<31)1960 1961 1962 1963/*1964 *  dma_reg definition1965 *  offset: 0xc001966 */1967#define BNX2_DMA_COMMAND				0x00000c001968#define BNX2_DMA_COMMAND_ENABLE				 (1L<<0)1969 1970#define BNX2_DMA_STATUS					0x00000c041971#define BNX2_DMA_STATUS_PAR_ERROR_STATE			 (1L<<0)1972#define BNX2_DMA_STATUS_READ_TRANSFERS_STAT		 (1L<<16)1973#define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT	 (1L<<17)1974#define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT		 (1L<<18)1975#define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT	 (1L<<19)1976#define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT	 (1L<<20)1977#define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT		 (1L<<21)1978#define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<22)1979#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT	 (1L<<23)1980#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<24)1981#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT	 (1L<<25)1982#define BNX2_DMA_STATUS_GLOBAL_ERR_XI			 (1L<<0)1983#define BNX2_DMA_STATUS_BME_XI				 (1L<<4)1984 1985#define BNX2_DMA_CONFIG					0x00000c081986#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP			 (1L<<0)1987#define BNX2_DMA_CONFIG_DATA_WORD_SWAP			 (1L<<1)1988#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP			 (1L<<4)1989#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP			 (1L<<5)1990#define BNX2_DMA_CONFIG_ONE_DMA				 (1L<<6)1991#define BNX2_DMA_CONFIG_CNTL_TWO_DMA			 (1L<<7)1992#define BNX2_DMA_CONFIG_CNTL_FPGA_MODE			 (1L<<8)1993#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA		 (1L<<10)1994#define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY		 (1L<<11)1995#define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE		 (0xfL<<12)1996#define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE		 (0xfL<<16)1997#define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS		 (0x7L<<20)1998#define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP		 (1L<<23)1999#define BNX2_DMA_CONFIG_BIG_SIZE			 (0xfL<<24)2000#define BNX2_DMA_CONFIG_BIG_SIZE_NONE			 (0x0L<<24)2001#define BNX2_DMA_CONFIG_BIG_SIZE_64			 (0x1L<<24)2002#define BNX2_DMA_CONFIG_BIG_SIZE_128			 (0x2L<<24)2003#define BNX2_DMA_CONFIG_BIG_SIZE_256			 (0x4L<<24)2004#define BNX2_DMA_CONFIG_BIG_SIZE_512			 (0x8L<<24)2005#define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI		 (0x3L<<0)2006#define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI		 (0x3L<<4)2007#define BNX2_DMA_CONFIG_MAX_PL_XI			 (0x7L<<12)2008#define BNX2_DMA_CONFIG_MAX_PL_128B_XI			 (0L<<12)2009#define BNX2_DMA_CONFIG_MAX_PL_256B_XI			 (1L<<12)2010#define BNX2_DMA_CONFIG_MAX_PL_512B_XI			 (2L<<12)2011#define BNX2_DMA_CONFIG_MAX_PL_EN_XI			 (1L<<15)2012#define BNX2_DMA_CONFIG_MAX_RRS_XI			 (0x7L<<16)2013#define BNX2_DMA_CONFIG_MAX_RRS_128B_XI			 (0L<<16)2014#define BNX2_DMA_CONFIG_MAX_RRS_256B_XI			 (1L<<16)2015#define BNX2_DMA_CONFIG_MAX_RRS_512B_XI			 (2L<<16)2016#define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI		 (3L<<16)2017#define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI		 (4L<<16)2018#define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI		 (5L<<16)2019#define BNX2_DMA_CONFIG_MAX_RRS_EN_XI			 (1L<<19)2020#define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI			 (1L<<31)2021 2022#define BNX2_DMA_BLACKOUT				0x00000c0c2023#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT		 (0xffL<<0)2024#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT		 (0xffL<<8)2025#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT		 (0xffL<<16)2026 2027#define BNX2_DMA_READ_MASTER_SETTING_0			0x00000c102028#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP	 (1L<<0)2029#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER	 (1L<<1)2030#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY	 (1L<<2)2031#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS	 (0x7L<<4)2032#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN	 (1L<<7)2033#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP	 (1L<<8)2034#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER	 (1L<<9)2035#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY	 (1L<<10)2036#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS	 (0x7L<<12)2037#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN	 (1L<<15)2038#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP	 (1L<<16)2039#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER	 (1L<<17)2040#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY	 (1L<<18)2041#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS	 (0x7L<<20)2042#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN	 (1L<<23)2043#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP	 (1L<<24)2044#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER	 (1L<<25)2045#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY	 (1L<<26)2046#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS	 (0x7L<<28)2047#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN	 (1L<<31)2048 2049#define BNX2_DMA_READ_MASTER_SETTING_1			0x00000c142050#define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP	 (1L<<0)2051#define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER	 (1L<<1)2052#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY	 (1L<<2)2053#define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS	 (0x7L<<4)2054#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN	 (1L<<7)2055#define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP	 (1L<<8)2056#define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER	 (1L<<9)2057#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY	 (1L<<10)2058#define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS	 (0x7L<<12)2059#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN	 (1L<<15)2060 2061#define BNX2_DMA_WRITE_MASTER_SETTING_0			0x00000c182062#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP	 (1L<<0)2063#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER	 (1L<<1)2064#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY	 (1L<<2)2065#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD	 (1L<<3)2066#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS	 (0x7L<<4)2067#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN	 (1L<<7)2068#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP	 (1L<<8)2069#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER	 (1L<<9)2070#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY	 (1L<<10)2071#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD	 (1L<<11)2072#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS	 (0x7L<<12)2073#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN	 (1L<<15)2074#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP	 (1L<<24)2075#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER	 (1L<<25)2076#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY	 (1L<<26)2077#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD	 (1L<<27)2078#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS	 (0x7L<<28)2079#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN	 (1L<<31)2080 2081#define BNX2_DMA_WRITE_MASTER_SETTING_1			0x00000c1c2082#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP	 (1L<<0)2083#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER	 (1L<<1)2084#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY	 (1L<<2)2085#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD	 (1L<<3)2086#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS	 (0x7L<<4)2087#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN	 (1L<<7)2088#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP	 (1L<<8)2089#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER	 (1L<<9)2090#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY	 (1L<<10)2091#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD	 (1L<<11)2092#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS	 (0x7L<<12)2093#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN	 (1L<<15)2094 2095#define BNX2_DMA_ARBITER				0x00000c202096#define BNX2_DMA_ARBITER_NUM_READS			 (0x7L<<0)2097#define BNX2_DMA_ARBITER_WR_ARB_MODE			 (1L<<4)2098#define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT		 (0L<<4)2099#define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN		 (1L<<4)2100#define BNX2_DMA_ARBITER_RD_ARB_MODE			 (0x3L<<5)2101#define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT		 (0L<<5)2102#define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN		 (1L<<5)2103#define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN	 (2L<<5)2104#define BNX2_DMA_ARBITER_ALT_MODE_EN			 (1L<<8)2105#define BNX2_DMA_ARBITER_RR_MODE			 (1L<<9)2106#define BNX2_DMA_ARBITER_TIMER_MODE			 (1L<<10)2107#define BNX2_DMA_ARBITER_OUSTD_READ_REQ			 (0xfL<<12)2108 2109#define BNX2_DMA_ARB_TIMERS				0x00000c242110#define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME		 (0xffL<<0)2111#define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT		 (0xffL<<12)2112#define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT		 (0xfffL<<20)2113 2114#define BNX2_DMA_DEBUG_VECT_PEEK			0x00000c2c2115#define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)2116#define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)2117#define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)2118#define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)2119#define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)2120#define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)2121 2122#define BNX2_DMA_TAG_RAM_00				0x00000c302123#define BNX2_DMA_TAG_RAM_00_CHANNEL			 (0xfL<<0)2124#define BNX2_DMA_TAG_RAM_00_MASTER			 (0x7L<<4)2125#define BNX2_DMA_TAG_RAM_00_MASTER_CTX			 (0L<<4)2126#define BNX2_DMA_TAG_RAM_00_MASTER_RBDC			 (1L<<4)2127#define BNX2_DMA_TAG_RAM_00_MASTER_TBDC			 (2L<<4)2128#define BNX2_DMA_TAG_RAM_00_MASTER_COM			 (3L<<4)2129#define BNX2_DMA_TAG_RAM_00_MASTER_CP			 (4L<<4)2130#define BNX2_DMA_TAG_RAM_00_MASTER_TDMA			 (5L<<4)2131#define BNX2_DMA_TAG_RAM_00_SWAP			 (0x3L<<7)2132#define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG			 (0L<<7)2133#define BNX2_DMA_TAG_RAM_00_SWAP_DATA			 (1L<<7)2134#define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL		 (2L<<7)2135#define BNX2_DMA_TAG_RAM_00_FUNCTION			 (1L<<9)2136#define BNX2_DMA_TAG_RAM_00_VALID			 (1L<<10)2137 2138#define BNX2_DMA_TAG_RAM_01				0x00000c342139#define BNX2_DMA_TAG_RAM_01_CHANNEL			 (0xfL<<0)2140#define BNX2_DMA_TAG_RAM_01_MASTER			 (0x7L<<4)2141#define BNX2_DMA_TAG_RAM_01_MASTER_CTX			 (0L<<4)2142#define BNX2_DMA_TAG_RAM_01_MASTER_RBDC			 (1L<<4)2143#define BNX2_DMA_TAG_RAM_01_MASTER_TBDC			 (2L<<4)2144#define BNX2_DMA_TAG_RAM_01_MASTER_COM			 (3L<<4)2145#define BNX2_DMA_TAG_RAM_01_MASTER_CP			 (4L<<4)2146#define BNX2_DMA_TAG_RAM_01_MASTER_TDMA			 (5L<<4)2147#define BNX2_DMA_TAG_RAM_01_SWAP			 (0x3L<<7)2148#define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG			 (0L<<7)2149#define BNX2_DMA_TAG_RAM_01_SWAP_DATA			 (1L<<7)2150#define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL		 (2L<<7)2151#define BNX2_DMA_TAG_RAM_01_FUNCTION			 (1L<<9)2152#define BNX2_DMA_TAG_RAM_01_VALID			 (1L<<10)2153 2154#define BNX2_DMA_TAG_RAM_02				0x00000c382155#define BNX2_DMA_TAG_RAM_02_CHANNEL			 (0xfL<<0)2156#define BNX2_DMA_TAG_RAM_02_MASTER			 (0x7L<<4)2157#define BNX2_DMA_TAG_RAM_02_MASTER_CTX			 (0L<<4)2158#define BNX2_DMA_TAG_RAM_02_MASTER_RBDC			 (1L<<4)2159#define BNX2_DMA_TAG_RAM_02_MASTER_TBDC			 (2L<<4)2160#define BNX2_DMA_TAG_RAM_02_MASTER_COM			 (3L<<4)2161#define BNX2_DMA_TAG_RAM_02_MASTER_CP			 (4L<<4)2162#define BNX2_DMA_TAG_RAM_02_MASTER_TDMA			 (5L<<4)2163#define BNX2_DMA_TAG_RAM_02_SWAP			 (0x3L<<7)2164#define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG			 (0L<<7)2165#define BNX2_DMA_TAG_RAM_02_SWAP_DATA			 (1L<<7)2166#define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL		 (2L<<7)2167#define BNX2_DMA_TAG_RAM_02_FUNCTION			 (1L<<9)2168#define BNX2_DMA_TAG_RAM_02_VALID			 (1L<<10)2169 2170#define BNX2_DMA_TAG_RAM_03				0x00000c3c2171#define BNX2_DMA_TAG_RAM_03_CHANNEL			 (0xfL<<0)2172#define BNX2_DMA_TAG_RAM_03_MASTER			 (0x7L<<4)2173#define BNX2_DMA_TAG_RAM_03_MASTER_CTX			 (0L<<4)2174#define BNX2_DMA_TAG_RAM_03_MASTER_RBDC			 (1L<<4)2175#define BNX2_DMA_TAG_RAM_03_MASTER_TBDC			 (2L<<4)2176#define BNX2_DMA_TAG_RAM_03_MASTER_COM			 (3L<<4)2177#define BNX2_DMA_TAG_RAM_03_MASTER_CP			 (4L<<4)2178#define BNX2_DMA_TAG_RAM_03_MASTER_TDMA			 (5L<<4)2179#define BNX2_DMA_TAG_RAM_03_SWAP			 (0x3L<<7)2180#define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG			 (0L<<7)2181#define BNX2_DMA_TAG_RAM_03_SWAP_DATA			 (1L<<7)2182#define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL		 (2L<<7)2183#define BNX2_DMA_TAG_RAM_03_FUNCTION			 (1L<<9)2184#define BNX2_DMA_TAG_RAM_03_VALID			 (1L<<10)2185 2186#define BNX2_DMA_TAG_RAM_04				0x00000c402187#define BNX2_DMA_TAG_RAM_04_CHANNEL			 (0xfL<<0)2188#define BNX2_DMA_TAG_RAM_04_MASTER			 (0x7L<<4)2189#define BNX2_DMA_TAG_RAM_04_MASTER_CTX			 (0L<<4)2190#define BNX2_DMA_TAG_RAM_04_MASTER_RBDC			 (1L<<4)2191#define BNX2_DMA_TAG_RAM_04_MASTER_TBDC			 (2L<<4)2192#define BNX2_DMA_TAG_RAM_04_MASTER_COM			 (3L<<4)2193#define BNX2_DMA_TAG_RAM_04_MASTER_CP			 (4L<<4)2194#define BNX2_DMA_TAG_RAM_04_MASTER_TDMA			 (5L<<4)2195#define BNX2_DMA_TAG_RAM_04_SWAP			 (0x3L<<7)2196#define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG			 (0L<<7)2197#define BNX2_DMA_TAG_RAM_04_SWAP_DATA			 (1L<<7)2198#define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL		 (2L<<7)2199#define BNX2_DMA_TAG_RAM_04_FUNCTION			 (1L<<9)2200#define BNX2_DMA_TAG_RAM_04_VALID			 (1L<<10)2201 2202#define BNX2_DMA_TAG_RAM_05				0x00000c442203#define BNX2_DMA_TAG_RAM_05_CHANNEL			 (0xfL<<0)2204#define BNX2_DMA_TAG_RAM_05_MASTER			 (0x7L<<4)2205#define BNX2_DMA_TAG_RAM_05_MASTER_CTX			 (0L<<4)2206#define BNX2_DMA_TAG_RAM_05_MASTER_RBDC			 (1L<<4)2207#define BNX2_DMA_TAG_RAM_05_MASTER_TBDC			 (2L<<4)2208#define BNX2_DMA_TAG_RAM_05_MASTER_COM			 (3L<<4)2209#define BNX2_DMA_TAG_RAM_05_MASTER_CP			 (4L<<4)2210#define BNX2_DMA_TAG_RAM_05_MASTER_TDMA			 (5L<<4)2211#define BNX2_DMA_TAG_RAM_05_SWAP			 (0x3L<<7)2212#define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG			 (0L<<7)2213#define BNX2_DMA_TAG_RAM_05_SWAP_DATA			 (1L<<7)2214#define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL		 (2L<<7)2215#define BNX2_DMA_TAG_RAM_05_FUNCTION			 (1L<<9)2216#define BNX2_DMA_TAG_RAM_05_VALID			 (1L<<10)2217 2218#define BNX2_DMA_TAG_RAM_06				0x00000c482219#define BNX2_DMA_TAG_RAM_06_CHANNEL			 (0xfL<<0)2220#define BNX2_DMA_TAG_RAM_06_MASTER			 (0x7L<<4)2221#define BNX2_DMA_TAG_RAM_06_MASTER_CTX			 (0L<<4)2222#define BNX2_DMA_TAG_RAM_06_MASTER_RBDC			 (1L<<4)2223#define BNX2_DMA_TAG_RAM_06_MASTER_TBDC			 (2L<<4)2224#define BNX2_DMA_TAG_RAM_06_MASTER_COM			 (3L<<4)2225#define BNX2_DMA_TAG_RAM_06_MASTER_CP			 (4L<<4)2226#define BNX2_DMA_TAG_RAM_06_MASTER_TDMA			 (5L<<4)2227#define BNX2_DMA_TAG_RAM_06_SWAP			 (0x3L<<7)2228#define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG			 (0L<<7)2229#define BNX2_DMA_TAG_RAM_06_SWAP_DATA			 (1L<<7)2230#define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL		 (2L<<7)2231#define BNX2_DMA_TAG_RAM_06_FUNCTION			 (1L<<9)2232#define BNX2_DMA_TAG_RAM_06_VALID			 (1L<<10)2233 2234#define BNX2_DMA_TAG_RAM_07				0x00000c4c2235#define BNX2_DMA_TAG_RAM_07_CHANNEL			 (0xfL<<0)2236#define BNX2_DMA_TAG_RAM_07_MASTER			 (0x7L<<4)2237#define BNX2_DMA_TAG_RAM_07_MASTER_CTX			 (0L<<4)2238#define BNX2_DMA_TAG_RAM_07_MASTER_RBDC			 (1L<<4)2239#define BNX2_DMA_TAG_RAM_07_MASTER_TBDC			 (2L<<4)2240#define BNX2_DMA_TAG_RAM_07_MASTER_COM			 (3L<<4)2241#define BNX2_DMA_TAG_RAM_07_MASTER_CP			 (4L<<4)2242#define BNX2_DMA_TAG_RAM_07_MASTER_TDMA			 (5L<<4)2243#define BNX2_DMA_TAG_RAM_07_SWAP			 (0x3L<<7)2244#define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG			 (0L<<7)2245#define BNX2_DMA_TAG_RAM_07_SWAP_DATA			 (1L<<7)2246#define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL		 (2L<<7)2247#define BNX2_DMA_TAG_RAM_07_FUNCTION			 (1L<<9)2248#define BNX2_DMA_TAG_RAM_07_VALID			 (1L<<10)2249 2250#define BNX2_DMA_TAG_RAM_08				0x00000c502251#define BNX2_DMA_TAG_RAM_08_CHANNEL			 (0xfL<<0)2252#define BNX2_DMA_TAG_RAM_08_MASTER			 (0x7L<<4)2253#define BNX2_DMA_TAG_RAM_08_MASTER_CTX			 (0L<<4)2254#define BNX2_DMA_TAG_RAM_08_MASTER_RBDC			 (1L<<4)2255#define BNX2_DMA_TAG_RAM_08_MASTER_TBDC			 (2L<<4)2256#define BNX2_DMA_TAG_RAM_08_MASTER_COM			 (3L<<4)2257#define BNX2_DMA_TAG_RAM_08_MASTER_CP			 (4L<<4)2258#define BNX2_DMA_TAG_RAM_08_MASTER_TDMA			 (5L<<4)2259#define BNX2_DMA_TAG_RAM_08_SWAP			 (0x3L<<7)2260#define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG			 (0L<<7)2261#define BNX2_DMA_TAG_RAM_08_SWAP_DATA			 (1L<<7)2262#define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL		 (2L<<7)2263#define BNX2_DMA_TAG_RAM_08_FUNCTION			 (1L<<9)2264#define BNX2_DMA_TAG_RAM_08_VALID			 (1L<<10)2265 2266#define BNX2_DMA_TAG_RAM_09				0x00000c542267#define BNX2_DMA_TAG_RAM_09_CHANNEL			 (0xfL<<0)2268#define BNX2_DMA_TAG_RAM_09_MASTER			 (0x7L<<4)2269#define BNX2_DMA_TAG_RAM_09_MASTER_CTX			 (0L<<4)2270#define BNX2_DMA_TAG_RAM_09_MASTER_RBDC			 (1L<<4)2271#define BNX2_DMA_TAG_RAM_09_MASTER_TBDC			 (2L<<4)2272#define BNX2_DMA_TAG_RAM_09_MASTER_COM			 (3L<<4)2273#define BNX2_DMA_TAG_RAM_09_MASTER_CP			 (4L<<4)2274#define BNX2_DMA_TAG_RAM_09_MASTER_TDMA			 (5L<<4)2275#define BNX2_DMA_TAG_RAM_09_SWAP			 (0x3L<<7)2276#define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG			 (0L<<7)2277#define BNX2_DMA_TAG_RAM_09_SWAP_DATA			 (1L<<7)2278#define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL		 (2L<<7)2279#define BNX2_DMA_TAG_RAM_09_FUNCTION			 (1L<<9)2280#define BNX2_DMA_TAG_RAM_09_VALID			 (1L<<10)2281 2282#define BNX2_DMA_TAG_RAM_10				0x00000c582283#define BNX2_DMA_TAG_RAM_10_CHANNEL			 (0xfL<<0)2284#define BNX2_DMA_TAG_RAM_10_MASTER			 (0x7L<<4)2285#define BNX2_DMA_TAG_RAM_10_MASTER_CTX			 (0L<<4)2286#define BNX2_DMA_TAG_RAM_10_MASTER_RBDC			 (1L<<4)2287#define BNX2_DMA_TAG_RAM_10_MASTER_TBDC			 (2L<<4)2288#define BNX2_DMA_TAG_RAM_10_MASTER_COM			 (3L<<4)2289#define BNX2_DMA_TAG_RAM_10_MASTER_CP			 (4L<<4)2290#define BNX2_DMA_TAG_RAM_10_MASTER_TDMA			 (5L<<4)2291#define BNX2_DMA_TAG_RAM_10_SWAP			 (0x3L<<7)2292#define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG			 (0L<<7)2293#define BNX2_DMA_TAG_RAM_10_SWAP_DATA			 (1L<<7)2294#define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL		 (2L<<7)2295#define BNX2_DMA_TAG_RAM_10_FUNCTION			 (1L<<9)2296#define BNX2_DMA_TAG_RAM_10_VALID			 (1L<<10)2297 2298#define BNX2_DMA_TAG_RAM_11				0x00000c5c2299#define BNX2_DMA_TAG_RAM_11_CHANNEL			 (0xfL<<0)2300#define BNX2_DMA_TAG_RAM_11_MASTER			 (0x7L<<4)2301#define BNX2_DMA_TAG_RAM_11_MASTER_CTX			 (0L<<4)2302#define BNX2_DMA_TAG_RAM_11_MASTER_RBDC			 (1L<<4)2303#define BNX2_DMA_TAG_RAM_11_MASTER_TBDC			 (2L<<4)2304#define BNX2_DMA_TAG_RAM_11_MASTER_COM			 (3L<<4)2305#define BNX2_DMA_TAG_RAM_11_MASTER_CP			 (4L<<4)2306#define BNX2_DMA_TAG_RAM_11_MASTER_TDMA			 (5L<<4)2307#define BNX2_DMA_TAG_RAM_11_SWAP			 (0x3L<<7)2308#define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG			 (0L<<7)2309#define BNX2_DMA_TAG_RAM_11_SWAP_DATA			 (1L<<7)2310#define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL		 (2L<<7)2311#define BNX2_DMA_TAG_RAM_11_FUNCTION			 (1L<<9)2312#define BNX2_DMA_TAG_RAM_11_VALID			 (1L<<10)2313 2314#define BNX2_DMA_RCHAN_STAT_22				0x00000c602315#define BNX2_DMA_RCHAN_STAT_30				0x00000c642316#define BNX2_DMA_RCHAN_STAT_31				0x00000c682317#define BNX2_DMA_RCHAN_STAT_32				0x00000c6c2318#define BNX2_DMA_RCHAN_STAT_40				0x00000c702319#define BNX2_DMA_RCHAN_STAT_41				0x00000c742320#define BNX2_DMA_RCHAN_STAT_42				0x00000c782321#define BNX2_DMA_RCHAN_STAT_50				0x00000c7c2322#define BNX2_DMA_RCHAN_STAT_51				0x00000c802323#define BNX2_DMA_RCHAN_STAT_52				0x00000c842324#define BNX2_DMA_RCHAN_STAT_60				0x00000c882325#define BNX2_DMA_RCHAN_STAT_61				0x00000c8c2326#define BNX2_DMA_RCHAN_STAT_62				0x00000c902327#define BNX2_DMA_RCHAN_STAT_70				0x00000c942328#define BNX2_DMA_RCHAN_STAT_71				0x00000c982329#define BNX2_DMA_RCHAN_STAT_72				0x00000c9c2330#define BNX2_DMA_WCHAN_STAT_00				0x00000ca02331#define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)2332 2333#define BNX2_DMA_WCHAN_STAT_01				0x00000ca42334#define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)2335 2336#define BNX2_DMA_WCHAN_STAT_02				0x00000ca82337#define BNX2_DMA_WCHAN_STAT_02_LENGTH			 (0xffffL<<0)2338#define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP		 (1L<<16)2339#define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP		 (1L<<17)2340#define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL		 (1L<<18)2341 2342#define BNX2_DMA_WCHAN_STAT_10				0x00000cac2343#define BNX2_DMA_WCHAN_STAT_11				0x00000cb02344#define BNX2_DMA_WCHAN_STAT_12				0x00000cb42345#define BNX2_DMA_WCHAN_STAT_20				0x00000cb82346#define BNX2_DMA_WCHAN_STAT_21				0x00000cbc2347#define BNX2_DMA_WCHAN_STAT_22				0x00000cc02348#define BNX2_DMA_WCHAN_STAT_30				0x00000cc42349#define BNX2_DMA_WCHAN_STAT_31				0x00000cc82350#define BNX2_DMA_WCHAN_STAT_32				0x00000ccc2351#define BNX2_DMA_WCHAN_STAT_40				0x00000cd02352#define BNX2_DMA_WCHAN_STAT_41				0x00000cd42353#define BNX2_DMA_WCHAN_STAT_42				0x00000cd82354#define BNX2_DMA_WCHAN_STAT_50				0x00000cdc2355#define BNX2_DMA_WCHAN_STAT_51				0x00000ce02356#define BNX2_DMA_WCHAN_STAT_52				0x00000ce42357#define BNX2_DMA_WCHAN_STAT_60				0x00000ce82358#define BNX2_DMA_WCHAN_STAT_61				0x00000cec2359#define BNX2_DMA_WCHAN_STAT_62				0x00000cf02360#define BNX2_DMA_WCHAN_STAT_70				0x00000cf42361#define BNX2_DMA_WCHAN_STAT_71				0x00000cf82362#define BNX2_DMA_WCHAN_STAT_72				0x00000cfc2363#define BNX2_DMA_ARB_STAT_00				0x00000d002364#define BNX2_DMA_ARB_STAT_00_MASTER			 (0xffffL<<0)2365#define BNX2_DMA_ARB_STAT_00_MASTER_ENC			 (0xffL<<16)2366#define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR		 (0xffL<<24)2367 2368#define BNX2_DMA_ARB_STAT_01				0x00000d042369#define BNX2_DMA_ARB_STAT_01_LPR_RPTR			 (0xfL<<0)2370#define BNX2_DMA_ARB_STAT_01_LPR_WPTR			 (0xfL<<4)2371#define BNX2_DMA_ARB_STAT_01_LPB_RPTR			 (0xfL<<8)2372#define BNX2_DMA_ARB_STAT_01_LPB_WPTR			 (0xfL<<12)2373#define BNX2_DMA_ARB_STAT_01_HPR_RPTR			 (0xfL<<16)2374#define BNX2_DMA_ARB_STAT_01_HPR_WPTR			 (0xfL<<20)2375#define BNX2_DMA_ARB_STAT_01_HPB_RPTR			 (0xfL<<24)2376#define BNX2_DMA_ARB_STAT_01_HPB_WPTR			 (0xfL<<28)2377 2378#define BNX2_DMA_FUSE_CTRL0_CMD				0x00000f002379#define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE		 (1L<<0)2380#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE		 (1L<<1)2381#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT			 (1L<<2)2382#define BNX2_DMA_FUSE_CTRL0_CMD_LOAD			 (1L<<3)2383#define BNX2_DMA_FUSE_CTRL0_CMD_SEL			 (0xfL<<8)2384 2385#define BNX2_DMA_FUSE_CTRL0_DATA			0x00000f042386#define BNX2_DMA_FUSE_CTRL1_CMD				0x00000f082387#define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE		 (1L<<0)2388#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE		 (1L<<1)2389#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT			 (1L<<2)2390#define BNX2_DMA_FUSE_CTRL1_CMD_LOAD			 (1L<<3)2391#define BNX2_DMA_FUSE_CTRL1_CMD_SEL			 (0xfL<<8)2392 2393#define BNX2_DMA_FUSE_CTRL1_DATA			0x00000f0c2394#define BNX2_DMA_FUSE_CTRL2_CMD				0x00000f102395#define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE		 (1L<<0)2396#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE		 (1L<<1)2397#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT			 (1L<<2)2398#define BNX2_DMA_FUSE_CTRL2_CMD_LOAD			 (1L<<3)2399#define BNX2_DMA_FUSE_CTRL2_CMD_SEL			 (0xfL<<8)2400 2401#define BNX2_DMA_FUSE_CTRL2_DATA			0x00000f142402 2403 2404/*2405 *  context_reg definition2406 *  offset: 0x10002407 */2408#define BNX2_CTX_COMMAND				0x000010002409#define BNX2_CTX_COMMAND_ENABLED			 (1L<<0)2410#define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT		 (1L<<1)2411#define BNX2_CTX_COMMAND_DISABLE_PLRU			 (1L<<2)2412#define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ		 (1L<<3)2413#define BNX2_CTX_COMMAND_FLUSH_AHEAD			 (0x1fL<<8)2414#define BNX2_CTX_COMMAND_MEM_INIT			 (1L<<13)2415#define BNX2_CTX_COMMAND_PAGE_SIZE			 (0xfL<<16)2416#define BNX2_CTX_COMMAND_PAGE_SIZE_256			 (0L<<16)2417#define BNX2_CTX_COMMAND_PAGE_SIZE_512			 (1L<<16)2418#define BNX2_CTX_COMMAND_PAGE_SIZE_1K			 (2L<<16)2419#define BNX2_CTX_COMMAND_PAGE_SIZE_2K			 (3L<<16)2420#define BNX2_CTX_COMMAND_PAGE_SIZE_4K			 (4L<<16)2421#define BNX2_CTX_COMMAND_PAGE_SIZE_8K			 (5L<<16)2422#define BNX2_CTX_COMMAND_PAGE_SIZE_16K			 (6L<<16)2423#define BNX2_CTX_COMMAND_PAGE_SIZE_32K			 (7L<<16)2424#define BNX2_CTX_COMMAND_PAGE_SIZE_64K			 (8L<<16)2425#define BNX2_CTX_COMMAND_PAGE_SIZE_128K			 (9L<<16)2426#define BNX2_CTX_COMMAND_PAGE_SIZE_256K			 (10L<<16)2427#define BNX2_CTX_COMMAND_PAGE_SIZE_512K			 (11L<<16)2428#define BNX2_CTX_COMMAND_PAGE_SIZE_1M			 (12L<<16)2429 2430#define BNX2_CTX_STATUS					0x000010042431#define BNX2_CTX_STATUS_LOCK_WAIT			 (1L<<0)2432#define BNX2_CTX_STATUS_READ_STAT			 (1L<<16)2433#define BNX2_CTX_STATUS_WRITE_STAT			 (1L<<17)2434#define BNX2_CTX_STATUS_ACC_STALL_STAT			 (1L<<18)2435#define BNX2_CTX_STATUS_LOCK_STALL_STAT			 (1L<<19)2436#define BNX2_CTX_STATUS_EXT_READ_STAT			 (1L<<20)2437#define BNX2_CTX_STATUS_EXT_WRITE_STAT			 (1L<<21)2438#define BNX2_CTX_STATUS_MISS_STAT			 (1L<<22)2439#define BNX2_CTX_STATUS_HIT_STAT			 (1L<<23)2440#define BNX2_CTX_STATUS_DEAD_LOCK			 (1L<<24)2441#define BNX2_CTX_STATUS_USAGE_CNT_ERR			 (1L<<25)2442#define BNX2_CTX_STATUS_INVALID_PAGE			 (1L<<26)2443 2444#define BNX2_CTX_VIRT_ADDR				0x000010082445#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR			 (0x7fffL<<6)2446 2447#define BNX2_CTX_PAGE_TBL				0x0000100c2448#define BNX2_CTX_PAGE_TBL_PAGE_TBL			 (0x3fffL<<6)2449 2450#define BNX2_CTX_DATA_ADR				0x000010102451#define BNX2_CTX_DATA_ADR_DATA_ADR			 (0x7ffffL<<2)2452 2453#define BNX2_CTX_DATA					0x000010142454#define BNX2_CTX_LOCK					0x000010182455#define BNX2_CTX_LOCK_TYPE				 (0x7L<<0)2456#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID		 (0x0L<<0)2457#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL		 (0x1L<<0)2458#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX			 (0x2L<<0)2459#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER		 (0x4L<<0)2460#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE		 (0x7L<<0)2461#define BNX2_CTX_LOCK_TYPE_VOID_XI			 (0L<<0)2462#define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI			 (1L<<0)2463#define BNX2_CTX_LOCK_TYPE_TX_XI			 (2L<<0)2464#define BNX2_CTX_LOCK_TYPE_TIMER_XI			 (4L<<0)2465#define BNX2_CTX_LOCK_TYPE_COMPLETE_XI			 (7L<<0)2466#define BNX2_CTX_LOCK_CID_VALUE				 (0x3fffL<<7)2467#define BNX2_CTX_LOCK_GRANTED				 (1L<<26)2468#define BNX2_CTX_LOCK_MODE				 (0x7L<<27)2469#define BNX2_CTX_LOCK_MODE_UNLOCK			 (0x0L<<27)2470#define BNX2_CTX_LOCK_MODE_IMMEDIATE			 (0x1L<<27)2471#define BNX2_CTX_LOCK_MODE_SURE				 (0x2L<<27)2472#define BNX2_CTX_LOCK_STATUS				 (1L<<30)2473#define BNX2_CTX_LOCK_REQ				 (1L<<31)2474 2475#define BNX2_CTX_CTX_CTRL				0x0000101c2476#define BNX2_CTX_CTX_CTRL_CTX_ADDR			 (0x7ffffL<<2)2477#define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT			 (0x3L<<21)2478#define BNX2_CTX_CTX_CTRL_NO_RAM_ACC			 (1L<<23)2479#define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE			 (0x3L<<24)2480#define BNX2_CTX_CTX_CTRL_ATTR				 (1L<<26)2481#define BNX2_CTX_CTX_CTRL_WRITE_REQ			 (1L<<30)2482#define BNX2_CTX_CTX_CTRL_READ_REQ			 (1L<<31)2483 2484#define BNX2_CTX_CTX_DATA				0x000010202485#define BNX2_CTX_ACCESS_STATUS				0x000010402486#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED		 (0xfL<<0)2487#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM		 (0x3L<<10)2488#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM		 (0x3L<<12)2489#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM	 (0x3L<<14)2490#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST	 (0x7ffL<<17)2491#define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI	 (0x1fL<<0)2492#define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI	 (0x1fL<<5)2493#define BNX2_CTX_ACCESS_STATUS_REQUEST_XI		 (0x3fffffL<<10)2494 2495#define BNX2_CTX_DBG_LOCK_STATUS			0x000010442496#define BNX2_CTX_DBG_LOCK_STATUS_SM			 (0x3ffL<<0)2497#define BNX2_CTX_DBG_LOCK_STATUS_MATCH			 (0x3ffL<<22)2498 2499#define BNX2_CTX_CACHE_CTRL_STATUS			0x000010482500#define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW	 (1L<<0)2501#define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP	 (1L<<1)2502#define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START		 (1L<<6)2503#define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT	 (0x3fL<<7)2504#define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED	 (0x3fL<<13)2505#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE	 (1L<<19)2506#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE	 (1L<<20)2507#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE	 (1L<<21)2508#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE	 (1L<<22)2509#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE	 (1L<<23)2510#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE	 (1L<<24)2511#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE	 (1L<<25)2512#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE	 (1L<<26)2513#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE	 (1L<<27)2514#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE	 (1L<<28)2515#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE	 (1L<<29)2516 2517#define BNX2_CTX_CACHE_CTRL_SM_STATUS			0x0000104c2518#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC		 (0x7L<<0)2519#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC		 (0x7L<<3)2520#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC		 (0x7L<<6)2521#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC		 (0x7L<<9)2522#define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR	 (0x7fffL<<16)2523 2524#define BNX2_CTX_CACHE_STATUS				0x000010502525#define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES		 (0x3ffL<<0)2526#define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES		 (0x3ffL<<16)2527 2528#define BNX2_CTX_DMA_STATUS				0x000010542529#define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS		 (0x3L<<0)2530#define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS		 (0x3L<<2)2531#define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS		 (0x3L<<4)2532#define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS		 (0x3L<<6)2533#define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS		 (0x3L<<8)2534#define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS		 (0x3L<<10)2535#define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS		 (0x3L<<12)2536#define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS		 (0x3L<<14)2537#define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS		 (0x3L<<16)2538#define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS		 (0x3L<<18)2539#define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS		 (0x3L<<20)2540 2541#define BNX2_CTX_REP_STATUS				0x000010582542#define BNX2_CTX_REP_STATUS_ERROR_ENTRY			 (0x3ffL<<0)2543#define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID		 (0x1fL<<10)2544#define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR		 (1L<<16)2545#define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR		 (1L<<17)2546#define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR		 (1L<<18)2547 2548#define BNX2_CTX_CKSUM_ERROR_STATUS			0x0000105c2549#define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED		 (0xffffL<<0)2550#define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED		 (0xffffL<<16)2551 2552#define BNX2_CTX_CHNL_LOCK_STATUS_0			0x000010802553#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID			 (0x3fffL<<0)2554#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE		 (0x3L<<14)2555#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE		 (1L<<16)2556#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI		 (1L<<14)2557#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI		 (0x7L<<15)2558 2559#define BNX2_CTX_CHNL_LOCK_STATUS_1			0x000010842560#define BNX2_CTX_CHNL_LOCK_STATUS_2			0x000010882561#define BNX2_CTX_CHNL_LOCK_STATUS_3			0x0000108c2562#define BNX2_CTX_CHNL_LOCK_STATUS_4			0x000010902563#define BNX2_CTX_CHNL_LOCK_STATUS_5			0x000010942564#define BNX2_CTX_CHNL_LOCK_STATUS_6			0x000010982565#define BNX2_CTX_CHNL_LOCK_STATUS_7			0x0000109c2566#define BNX2_CTX_CHNL_LOCK_STATUS_8			0x000010a02567#define BNX2_CTX_CHNL_LOCK_STATUS_9			0x000010a42568 2569#define BNX2_CTX_CACHE_DATA				0x000010c42570#define BNX2_CTX_HOST_PAGE_TBL_CTRL			0x000010c82571#define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR	 (0x1ffL<<0)2572#define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ		 (1L<<30)2573#define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ		 (1L<<31)2574 2575#define BNX2_CTX_HOST_PAGE_TBL_DATA0			0x000010cc2576#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID		 (1L<<0)2577#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE		 (0xffffffL<<8)2578 2579#define BNX2_CTX_HOST_PAGE_TBL_DATA1			0x000010d02580#define BNX2_CTX_CAM_CTRL				0x000010d42581#define BNX2_CTX_CAM_CTRL_CAM_ADDR			 (0x3ffL<<0)2582#define BNX2_CTX_CAM_CTRL_RESET				 (1L<<27)2583#define BNX2_CTX_CAM_CTRL_INVALIDATE			 (1L<<28)2584#define BNX2_CTX_CAM_CTRL_SEARCH			 (1L<<29)2585#define BNX2_CTX_CAM_CTRL_WRITE_REQ			 (1L<<30)2586#define BNX2_CTX_CAM_CTRL_READ_REQ			 (1L<<31)2587 2588 2589/*2590 *  emac_reg definition2591 *  offset: 0x14002592 */2593#define BNX2_EMAC_MODE					0x000014002594#define BNX2_EMAC_MODE_RESET				 (1L<<0)2595#define BNX2_EMAC_MODE_HALF_DUPLEX			 (1L<<1)2596#define BNX2_EMAC_MODE_PORT				 (0x3L<<2)2597#define BNX2_EMAC_MODE_PORT_NONE			 (0L<<2)2598#define BNX2_EMAC_MODE_PORT_MII				 (1L<<2)2599#define BNX2_EMAC_MODE_PORT_GMII			 (2L<<2)2600#define BNX2_EMAC_MODE_PORT_MII_10M			 (3L<<2)2601#define BNX2_EMAC_MODE_MAC_LOOP				 (1L<<4)2602#define BNX2_EMAC_MODE_25G_MODE				 (1L<<5)2603#define BNX2_EMAC_MODE_TAGGED_MAC_CTL			 (1L<<7)2604#define BNX2_EMAC_MODE_TX_BURST				 (1L<<8)2605#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA		 (1L<<9)2606#define BNX2_EMAC_MODE_EXT_LINK_POL			 (1L<<10)2607#define BNX2_EMAC_MODE_FORCE_LINK			 (1L<<11)2608#define BNX2_EMAC_MODE_SERDES_MODE			 (1L<<12)2609#define BNX2_EMAC_MODE_BOND_OVRD			 (1L<<13)2610#define BNX2_EMAC_MODE_MPKT				 (1L<<18)2611#define BNX2_EMAC_MODE_MPKT_RCVD			 (1L<<19)2612#define BNX2_EMAC_MODE_ACPI_RCVD			 (1L<<20)2613 2614#define BNX2_EMAC_STATUS				0x000014042615#define BNX2_EMAC_STATUS_LINK				 (1L<<11)2616#define BNX2_EMAC_STATUS_LINK_CHANGE			 (1L<<12)2617#define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE	 (1L<<13)2618#define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE		 (1L<<14)2619#define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE		 (1L<<16)2620#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0		 (1L<<17)2621#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE	 (1L<<18)2622#define BNX2_EMAC_STATUS_MI_COMPLETE			 (1L<<22)2623#define BNX2_EMAC_STATUS_MI_INT				 (1L<<23)2624#define BNX2_EMAC_STATUS_AP_ERROR			 (1L<<24)2625#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE		 (1L<<31)2626 2627#define BNX2_EMAC_ATTENTION_ENA				0x000014082628#define BNX2_EMAC_ATTENTION_ENA_LINK			 (1L<<11)2629#define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE		 (1L<<14)2630#define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE		 (1L<<16)2631#define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE	 (1L<<18)2632#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE		 (1L<<22)2633#define BNX2_EMAC_ATTENTION_ENA_MI_INT			 (1L<<23)2634#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR		 (1L<<24)2635 2636#define BNX2_EMAC_LED					0x0000140c2637#define BNX2_EMAC_LED_OVERRIDE				 (1L<<0)2638#define BNX2_EMAC_LED_1000MB_OVERRIDE			 (1L<<1)2639#define BNX2_EMAC_LED_100MB_OVERRIDE			 (1L<<2)2640#define BNX2_EMAC_LED_10MB_OVERRIDE			 (1L<<3)2641#define BNX2_EMAC_LED_TRAFFIC_OVERRIDE			 (1L<<4)2642#define BNX2_EMAC_LED_BLNK_TRAFFIC			 (1L<<5)2643#define BNX2_EMAC_LED_TRAFFIC				 (1L<<6)2644#define BNX2_EMAC_LED_1000MB				 (1L<<7)2645#define BNX2_EMAC_LED_100MB				 (1L<<8)2646#define BNX2_EMAC_LED_10MB				 (1L<<9)2647#define BNX2_EMAC_LED_TRAFFIC_STAT			 (1L<<10)2648#define BNX2_EMAC_LED_2500MB				 (1L<<11)2649#define BNX2_EMAC_LED_2500MB_OVERRIDE			 (1L<<12)2650#define BNX2_EMAC_LED_ACTIVITY_SEL			 (0x3L<<17)2651#define BNX2_EMAC_LED_ACTIVITY_SEL_0			 (0L<<17)2652#define BNX2_EMAC_LED_ACTIVITY_SEL_1			 (1L<<17)2653#define BNX2_EMAC_LED_ACTIVITY_SEL_2			 (2L<<17)2654#define BNX2_EMAC_LED_ACTIVITY_SEL_3			 (3L<<17)2655#define BNX2_EMAC_LED_BLNK_RATE				 (0xfffL<<19)2656#define BNX2_EMAC_LED_BLNK_RATE_ENA			 (1L<<31)2657 2658#define BNX2_EMAC_MAC_MATCH0				0x000014102659#define BNX2_EMAC_MAC_MATCH1				0x000014142660#define BNX2_EMAC_MAC_MATCH2				0x000014182661#define BNX2_EMAC_MAC_MATCH3				0x0000141c2662#define BNX2_EMAC_MAC_MATCH4				0x000014202663#define BNX2_EMAC_MAC_MATCH5				0x000014242664#define BNX2_EMAC_MAC_MATCH6				0x000014282665#define BNX2_EMAC_MAC_MATCH7				0x0000142c2666#define BNX2_EMAC_MAC_MATCH8				0x000014302667#define BNX2_EMAC_MAC_MATCH9				0x000014342668#define BNX2_EMAC_MAC_MATCH10				0x000014382669#define BNX2_EMAC_MAC_MATCH11				0x0000143c2670#define BNX2_EMAC_MAC_MATCH12				0x000014402671#define BNX2_EMAC_MAC_MATCH13				0x000014442672#define BNX2_EMAC_MAC_MATCH14				0x000014482673#define BNX2_EMAC_MAC_MATCH15				0x0000144c2674#define BNX2_EMAC_MAC_MATCH16				0x000014502675#define BNX2_EMAC_MAC_MATCH17				0x000014542676#define BNX2_EMAC_MAC_MATCH18				0x000014582677#define BNX2_EMAC_MAC_MATCH19				0x0000145c2678#define BNX2_EMAC_MAC_MATCH20				0x000014602679#define BNX2_EMAC_MAC_MATCH21				0x000014642680#define BNX2_EMAC_MAC_MATCH22				0x000014682681#define BNX2_EMAC_MAC_MATCH23				0x0000146c2682#define BNX2_EMAC_MAC_MATCH24				0x000014702683#define BNX2_EMAC_MAC_MATCH25				0x000014742684#define BNX2_EMAC_MAC_MATCH26				0x000014782685#define BNX2_EMAC_MAC_MATCH27				0x0000147c2686#define BNX2_EMAC_MAC_MATCH28				0x000014802687#define BNX2_EMAC_MAC_MATCH29				0x000014842688#define BNX2_EMAC_MAC_MATCH30				0x000014882689#define BNX2_EMAC_MAC_MATCH31				0x0000148c2690#define BNX2_EMAC_BACKOFF_SEED				0x000014982691#define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED	 (0x3ffL<<0)2692 2693#define BNX2_EMAC_RX_MTU_SIZE				0x0000149c2694#define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE			 (0xffffL<<0)2695#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA			 (1L<<31)2696 2697#define BNX2_EMAC_SERDES_CNTL				0x000014a42698#define BNX2_EMAC_SERDES_CNTL_RXR			 (0x7L<<0)2699#define BNX2_EMAC_SERDES_CNTL_RXG			 (0x3L<<3)2700#define BNX2_EMAC_SERDES_CNTL_RXCKSEL			 (1L<<6)2701#define BNX2_EMAC_SERDES_CNTL_TXBIAS			 (0x7L<<7)2702#define BNX2_EMAC_SERDES_CNTL_BGMAX			 (1L<<10)2703#define BNX2_EMAC_SERDES_CNTL_BGMIN			 (1L<<11)2704#define BNX2_EMAC_SERDES_CNTL_TXMODE			 (1L<<12)2705#define BNX2_EMAC_SERDES_CNTL_TXEDGE			 (1L<<13)2706#define BNX2_EMAC_SERDES_CNTL_SERDES_MODE		 (1L<<14)2707#define BNX2_EMAC_SERDES_CNTL_PLLTEST			 (1L<<15)2708#define BNX2_EMAC_SERDES_CNTL_CDET_EN			 (1L<<16)2709#define BNX2_EMAC_SERDES_CNTL_TBI_LBK			 (1L<<17)2710#define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK		 (1L<<18)2711#define BNX2_EMAC_SERDES_CNTL_REV_PHASE			 (1L<<19)2712#define BNX2_EMAC_SERDES_CNTL_REGCTL12			 (0x3L<<20)2713#define BNX2_EMAC_SERDES_CNTL_REGCTL25			 (0x3L<<22)2714 2715#define BNX2_EMAC_SERDES_STATUS				0x000014a82716#define BNX2_EMAC_SERDES_STATUS_RX_STAT			 (0xffL<<0)2717#define BNX2_EMAC_SERDES_STATUS_COMMA_DET		 (1L<<8)2718 2719#define BNX2_EMAC_MDIO_COMM				0x000014ac2720#define BNX2_EMAC_MDIO_COMM_DATA			 (0xffffL<<0)2721#define BNX2_EMAC_MDIO_COMM_REG_ADDR			 (0x1fL<<16)2722#define BNX2_EMAC_MDIO_COMM_PHY_ADDR			 (0x1fL<<21)2723#define BNX2_EMAC_MDIO_COMM_COMMAND			 (0x3L<<26)2724#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0		 (0L<<26)2725#define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS		 (0L<<26)2726#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE		 (1L<<26)2727#define BNX2_EMAC_MDIO_COMM_COMMAND_READ		 (2L<<26)2728#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI		 (1L<<26)2729#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI		 (1L<<26)2730#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI		 (2L<<26)2731#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI	 (2L<<26)2732#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3		 (3L<<26)2733#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45		 (3L<<26)2734#define BNX2_EMAC_MDIO_COMM_FAIL			 (1L<<28)2735#define BNX2_EMAC_MDIO_COMM_START_BUSY			 (1L<<29)2736#define BNX2_EMAC_MDIO_COMM_DISEXT			 (1L<<30)2737 2738#define BNX2_EMAC_MDIO_STATUS				0x000014b02739#define BNX2_EMAC_MDIO_STATUS_LINK			 (1L<<0)2740#define BNX2_EMAC_MDIO_STATUS_10MB			 (1L<<1)2741 2742#define BNX2_EMAC_MDIO_MODE				0x000014b42743#define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE		 (1L<<1)2744#define BNX2_EMAC_MDIO_MODE_AUTO_POLL			 (1L<<4)2745#define BNX2_EMAC_MDIO_MODE_BIT_BANG			 (1L<<8)2746#define BNX2_EMAC_MDIO_MODE_MDIO			 (1L<<9)2747#define BNX2_EMAC_MDIO_MODE_MDIO_OE			 (1L<<10)2748#define BNX2_EMAC_MDIO_MODE_MDC				 (1L<<11)2749#define BNX2_EMAC_MDIO_MODE_MDINT			 (1L<<12)2750#define BNX2_EMAC_MDIO_MODE_EXT_MDINT			 (1L<<13)2751#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT			 (0x1fL<<16)2752#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI		 (0x3fL<<16)2753#define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI		 (1L<<31)2754 2755#define BNX2_EMAC_MDIO_AUTO_STATUS			0x000014b82756#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR		 (1L<<0)2757 2758#define BNX2_EMAC_TX_MODE				0x000014bc2759#define BNX2_EMAC_TX_MODE_RESET				 (1L<<0)2760#define BNX2_EMAC_TX_MODE_CS16_TEST			 (1L<<2)2761#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN			 (1L<<3)2762#define BNX2_EMAC_TX_MODE_FLOW_EN			 (1L<<4)2763#define BNX2_EMAC_TX_MODE_BIG_BACKOFF			 (1L<<5)2764#define BNX2_EMAC_TX_MODE_LONG_PAUSE			 (1L<<6)2765#define BNX2_EMAC_TX_MODE_LINK_AWARE			 (1L<<7)2766 2767#define BNX2_EMAC_TX_STATUS				0x000014c02768#define BNX2_EMAC_TX_STATUS_XOFFED			 (1L<<0)2769#define BNX2_EMAC_TX_STATUS_XOFF_SENT			 (1L<<1)2770#define BNX2_EMAC_TX_STATUS_XON_SENT			 (1L<<2)2771#define BNX2_EMAC_TX_STATUS_LINK_UP			 (1L<<3)2772#define BNX2_EMAC_TX_STATUS_UNDERRUN			 (1L<<4)2773#define BNX2_EMAC_TX_STATUS_CS16_ERROR			 (1L<<5)2774 2775#define BNX2_EMAC_TX_LENGTHS				0x000014c42776#define BNX2_EMAC_TX_LENGTHS_SLOT			 (0xffL<<0)2777#define BNX2_EMAC_TX_LENGTHS_IPG			 (0xfL<<8)2778#define BNX2_EMAC_TX_LENGTHS_IPG_CRS			 (0x3L<<12)2779 2780#define BNX2_EMAC_RX_MODE				0x000014c82781#define BNX2_EMAC_RX_MODE_RESET				 (1L<<0)2782#define BNX2_EMAC_RX_MODE_FLOW_EN			 (1L<<2)2783#define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL		 (1L<<3)2784#define BNX2_EMAC_RX_MODE_KEEP_PAUSE			 (1L<<4)2785#define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE		 (1L<<5)2786#define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS			 (1L<<6)2787#define BNX2_EMAC_RX_MODE_LLC_CHK			 (1L<<7)2788#define BNX2_EMAC_RX_MODE_PROMISCUOUS			 (1L<<8)2789#define BNX2_EMAC_RX_MODE_NO_CRC_CHK			 (1L<<9)2790#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG			 (1L<<10)2791#define BNX2_EMAC_RX_MODE_FILT_BROADCAST		 (1L<<11)2792#define BNX2_EMAC_RX_MODE_SORT_MODE			 (1L<<12)2793 2794#define BNX2_EMAC_RX_STATUS				0x000014cc2795#define BNX2_EMAC_RX_STATUS_FFED			 (1L<<0)2796#define BNX2_EMAC_RX_STATUS_FF_RECEIVED			 (1L<<1)2797#define BNX2_EMAC_RX_STATUS_N_RECEIVED			 (1L<<2)2798 2799#define BNX2_EMAC_MULTICAST_HASH0			0x000014d02800#define BNX2_EMAC_MULTICAST_HASH1			0x000014d42801#define BNX2_EMAC_MULTICAST_HASH2			0x000014d82802#define BNX2_EMAC_MULTICAST_HASH3			0x000014dc2803#define BNX2_EMAC_MULTICAST_HASH4			0x000014e02804#define BNX2_EMAC_MULTICAST_HASH5			0x000014e42805#define BNX2_EMAC_MULTICAST_HASH6			0x000014e82806#define BNX2_EMAC_MULTICAST_HASH7			0x000014ec2807#define BNX2_EMAC_CKSUM_ERROR_STATUS			0x000014f02808#define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED		 (0xffffL<<0)2809#define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED		 (0xffffL<<16)2810 2811#define BNX2_EMAC_RX_STAT_IFHCINOCTETS			0x000015002812#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS		0x000015042813#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS		0x000015082814#define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS		0x0000150c2815#define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS		0x000015102816#define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS		0x000015142817#define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS		0x000015182818#define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS	0x0000151c2819#define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS	0x000015202820#define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED	0x000015242821#define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED	0x000015282822#define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED	0x0000152c2823#define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED		0x000015302824#define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG	0x000015342825#define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS		0x000015382826#define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS	0x0000153c2827#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS	0x000015402828#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x000015442829#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x000015482830#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x0000154c2831#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x000015502832#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x000015542833#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS	0x000015582834#define BNX2_EMAC_RXMAC_DEBUG0				0x0000155c2835#define BNX2_EMAC_RXMAC_DEBUG1				0x000015602836#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT	 (1L<<0)2837#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE		 (1L<<1)2838#define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC			 (1L<<2)2839#define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR			 (1L<<3)2840#define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR		 (1L<<4)2841#define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA		 (1L<<5)2842#define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START		 (1L<<6)2843#define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT		 (0xffffL<<7)2844#define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME		 (0xffL<<23)2845 2846#define BNX2_EMAC_RXMAC_DEBUG2				0x000015642847#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE			 (0x7L<<0)2848#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE		 (0x0L<<0)2849#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD		 (0x1L<<0)2850#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA		 (0x2L<<0)2851#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP		 (0x3L<<0)2852#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT		 (0x4L<<0)2853#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP		 (0x5L<<0)2854#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP		 (0x6L<<0)2855#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC		 (0x7L<<0)2856#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE		 (0xfL<<3)2857#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE		 (0x0L<<3)2858#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0		 (0x1L<<3)2859#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1		 (0x2L<<3)2860#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2		 (0x3L<<3)2861#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3		 (0x4L<<3)2862#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT		 (0x5L<<3)2863#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT		 (0x6L<<3)2864#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS		 (0x7L<<3)2865#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST		 (0x8L<<3)2866#define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN			 (0xffL<<7)2867#define BNX2_EMAC_RXMAC_DEBUG2_FALSEC			 (1L<<15)2868#define BNX2_EMAC_RXMAC_DEBUG2_TAGGED			 (1L<<16)2869#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE		 (1L<<18)2870#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE		 (0L<<18)2871#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED	 (1L<<18)2872#define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER		 (0xfL<<19)2873#define BNX2_EMAC_RXMAC_DEBUG2_QUANTA			 (0x1fL<<23)2874 2875#define BNX2_EMAC_RXMAC_DEBUG3				0x000015682876#define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR		 (0xffffL<<0)2877#define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR		 (0xffffL<<16)2878 2879#define BNX2_EMAC_RXMAC_DEBUG4				0x0000156c2880#define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD		 (0xffffL<<0)2881#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE		 (0x3fL<<16)2882#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE		 (0x0L<<16)2883#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2		 (0x1L<<16)2884#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3		 (0x2L<<16)2885#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI		 (0x3L<<16)2886#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3		 (0x5L<<16)2887#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1		 (0x6L<<16)2888#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2		 (0x7L<<16)2889#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2		 (0x7L<<16)2890#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3		 (0x8L<<16)2891#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2		 (0x9L<<16)2892#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3		 (0xaL<<16)2893#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1	 (0xeL<<16)2894#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2	 (0xfL<<16)2895#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK	 (0x10L<<16)2896#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC		 (0x11L<<16)2897#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2		 (0x12L<<16)2898#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3		 (0x13L<<16)2899#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1		 (0x14L<<16)2900#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2		 (0x15L<<16)2901#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3		 (0x16L<<16)2902#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE		 (0x17L<<16)2903#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC		 (0x18L<<16)2904#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE		 (0x19L<<16)2905#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD		 (0x1aL<<16)2906#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC		 (0x1bL<<16)2907#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH		 (0x1cL<<16)2908#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF		 (0x1dL<<16)2909#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON		 (0x1eL<<16)2910#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED	 (0x1fL<<16)2911#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED	 (0x20L<<16)2912#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE		 (0x21L<<16)2913#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL		 (0x22L<<16)2914#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1		 (0x23L<<16)2915#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2		 (0x24L<<16)2916#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3		 (0x25L<<16)2917#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE		 (0x26L<<16)2918#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE	 (0x27L<<16)2919#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL		 (0x28L<<16)2920#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE		 (0x29L<<16)2921#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP		 (0x2aL<<16)2922#define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT			 (1L<<22)2923#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED		 (1L<<23)2924#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER		 (1L<<24)2925#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA		 (1L<<25)2926#define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND		 (1L<<26)2927#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE			 (1L<<27)2928#define BNX2_EMAC_RXMAC_DEBUG4_START			 (1L<<28)2929 2930#define BNX2_EMAC_RXMAC_DEBUG5				0x000015702931#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM			 (0x7L<<0)2932#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE		 (0L<<0)2933#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF	 (1L<<0)2934#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT	 (2L<<0)2935#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC	 (3L<<0)2936#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE	 (4L<<0)2937#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL	 (5L<<0)2938#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT	 (6L<<0)2939#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1		 (0x7L<<4)2940#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW		 (0x0L<<4)2941#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT		 (0x1L<<4)2942#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF		 (0x2L<<4)2943#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF		 (0x3L<<4)2944#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF		 (0x4L<<4)2945#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF		 (0x6L<<4)2946#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF		 (0x7L<<4)2947#define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED		 (1L<<7)2948#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0		 (0x7L<<8)2949#define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL	 (1L<<11)2950#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE		 (1L<<12)2951#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA		 (1L<<13)2952#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT		 (1L<<14)2953#define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT			 (1L<<15)2954#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE		 (0x3L<<16)2955#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT		 (1L<<19)2956#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN			 (0xfffL<<20)2957 2958#define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS		0x000015742959#define BNX2_EMAC_RX_STAT_AC0				0x000015802960#define BNX2_EMAC_RX_STAT_AC1				0x000015842961#define BNX2_EMAC_RX_STAT_AC2				0x000015882962#define BNX2_EMAC_RX_STAT_AC3				0x0000158c2963#define BNX2_EMAC_RX_STAT_AC4				0x000015902964#define BNX2_EMAC_RX_STAT_AC5				0x000015942965#define BNX2_EMAC_RX_STAT_AC6				0x000015982966#define BNX2_EMAC_RX_STAT_AC7				0x0000159c2967#define BNX2_EMAC_RX_STAT_AC8				0x000015a02968#define BNX2_EMAC_RX_STAT_AC9				0x000015a42969#define BNX2_EMAC_RX_STAT_AC10				0x000015a82970#define BNX2_EMAC_RX_STAT_AC11				0x000015ac2971#define BNX2_EMAC_RX_STAT_AC12				0x000015b02972#define BNX2_EMAC_RX_STAT_AC13				0x000015b42973#define BNX2_EMAC_RX_STAT_AC14				0x000015b82974#define BNX2_EMAC_RX_STAT_AC15				0x000015bc2975#define BNX2_EMAC_RX_STAT_AC16				0x000015c02976#define BNX2_EMAC_RX_STAT_AC17				0x000015c42977#define BNX2_EMAC_RX_STAT_AC18				0x000015c82978#define BNX2_EMAC_RX_STAT_AC19				0x000015cc2979#define BNX2_EMAC_RX_STAT_AC20				0x000015d02980#define BNX2_EMAC_RX_STAT_AC21				0x000015d42981#define BNX2_EMAC_RX_STAT_AC22				0x000015d82982#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC		0x000015dc2983#define BNX2_EMAC_RX_STAT_AC_28				0x000015f42984#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS			0x000016002985#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS		0x000016042986#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS		0x000016082987#define BNX2_EMAC_TX_STAT_OUTXONSENT			0x0000160c2988#define BNX2_EMAC_TX_STAT_OUTXOFFSENT			0x000016102989#define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE		0x000016142990#define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES	0x000016182991#define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES	0x0000161c2992#define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS	0x000016202993#define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS	0x000016242994#define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS	0x000016282995#define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS		0x0000162c2996#define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS		0x000016302997#define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS		0x000016342998#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS	0x000016382999#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x0000163c3000#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x000016403001#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x000016443002#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x000016483003#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x0000164c3004#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS	0x000016503005#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS	0x000016543006#define BNX2_EMAC_TXMAC_DEBUG0				0x000016583007#define BNX2_EMAC_TXMAC_DEBUG1				0x0000165c3008#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE		 (0xfL<<0)3009#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE		 (0x0L<<0)3010#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0		 (0x1L<<0)3011#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0		 (0x4L<<0)3012#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1		 (0x5L<<0)3013#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2		 (0x6L<<0)3014#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3		 (0x7L<<0)3015#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0		 (0x8L<<0)3016#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1		 (0x9L<<0)3017#define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE		 (1L<<4)3018#define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC			 (1L<<5)3019#define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER		 (0xfL<<6)3020#define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE		 (1L<<10)3021#define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION		 (1L<<11)3022#define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER		 (1L<<12)3023#define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED			 (1L<<13)3024#define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE			 (1L<<14)3025#define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME			 (0xfL<<15)3026#define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME		 (0xffL<<19)3027 3028#define BNX2_EMAC_TXMAC_DEBUG2				0x000016603029#define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF			 (0x3ffL<<0)3030#define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT		 (0xffffL<<10)3031#define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT		 (0x1fL<<26)3032#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT			 (1L<<31)3033 3034#define BNX2_EMAC_TXMAC_DEBUG3				0x000016643035#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE			 (0xfL<<0)3036#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE		 (0x0L<<0)3037#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1		 (0x1L<<0)3038#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2		 (0x2L<<0)3039#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD		 (0x3L<<0)3040#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA		 (0x4L<<0)3041#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1		 (0x5L<<0)3042#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2		 (0x6L<<0)3043#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT		 (0x7L<<0)3044#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB		 (0x8L<<0)3045#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG		 (0x9L<<0)3046#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM		 (0xaL<<0)3047#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM		 (0xbL<<0)3048#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM		 (0xcL<<0)3049#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT		 (0xdL<<0)3050#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF		 (0xeL<<0)3051#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE		 (0x7L<<4)3052#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE		 (0x0L<<4)3053#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT		 (0x1L<<4)3054#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI		 (0x2L<<4)3055#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC		 (0x3L<<4)3056#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2		 (0x4L<<4)3057#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3		 (0x5L<<4)3058#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC		 (0x6L<<4)3059#define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE			 (1L<<7)3060#define BNX2_EMAC_TXMAC_DEBUG3_XOFF			 (1L<<8)3061#define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER		 (0xfL<<9)3062#define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER		 (0x1fL<<13)3063 3064#define BNX2_EMAC_TXMAC_DEBUG4				0x000016683065#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER		 (0xffffL<<0)3066#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE		 (0xfL<<16)3067#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE		 (0x0L<<16)3068#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1		 (0x2L<<16)3069#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2		 (0x3L<<16)3070#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3		 (0x4L<<16)3071#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2		 (0x5L<<16)3072#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3		 (0x6L<<16)3073#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1		 (0x7L<<16)3074#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1		 (0x8L<<16)3075#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2		 (0x9L<<16)3076#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME		 (0xaL<<16)3077#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE		 (0xcL<<16)3078#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT		 (0xdL<<16)3079#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD		 (0xeL<<16)3080#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID		 (1L<<20)3081#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC		 (1L<<21)3082#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED		 (1L<<22)3083#define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER		 (1L<<23)3084#define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND		 (1L<<24)3085#define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING		 (1L<<25)3086#define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC			 (1L<<26)3087#define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING		 (1L<<27)3088#define BNX2_EMAC_TXMAC_DEBUG4_COL_IN			 (1L<<28)3089#define BNX2_EMAC_TXMAC_DEBUG4_BURSTING			 (1L<<29)3090#define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE			 (1L<<30)3091#define BNX2_EMAC_TXMAC_DEBUG4_GO			 (1L<<31)3092 3093#define BNX2_EMAC_TX_STAT_AC0				0x000016803094#define BNX2_EMAC_TX_STAT_AC1				0x000016843095#define BNX2_EMAC_TX_STAT_AC2				0x000016883096#define BNX2_EMAC_TX_STAT_AC3				0x0000168c3097#define BNX2_EMAC_TX_STAT_AC4				0x000016903098#define BNX2_EMAC_TX_STAT_AC5				0x000016943099#define BNX2_EMAC_TX_STAT_AC6				0x000016983100#define BNX2_EMAC_TX_STAT_AC7				0x0000169c3101#define BNX2_EMAC_TX_STAT_AC8				0x000016a03102#define BNX2_EMAC_TX_STAT_AC9				0x000016a43103#define BNX2_EMAC_TX_STAT_AC10				0x000016a83104#define BNX2_EMAC_TX_STAT_AC11				0x000016ac3105#define BNX2_EMAC_TX_STAT_AC12				0x000016b03106#define BNX2_EMAC_TX_STAT_AC13				0x000016b43107#define BNX2_EMAC_TX_STAT_AC14				0x000016b83108#define BNX2_EMAC_TX_STAT_AC15				0x000016bc3109#define BNX2_EMAC_TX_STAT_AC16				0x000016c03110#define BNX2_EMAC_TX_STAT_AC17				0x000016c43111#define BNX2_EMAC_TX_STAT_AC18				0x000016c83112#define BNX2_EMAC_TX_STAT_AC19				0x000016cc3113#define BNX2_EMAC_TX_STAT_AC20				0x000016d03114#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC		0x000016d83115#define BNX2_EMAC_TX_RATE_LIMIT_CTRL			0x000016fc3116#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC	 (0x7fL<<0)3117#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM	 (0x7fL<<16)3118#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN	 (1L<<31)3119 3120 3121/*3122 *  rpm_reg definition3123 *  offset: 0x18003124 */3125#define BNX2_RPM_COMMAND				0x000018003126#define BNX2_RPM_COMMAND_ENABLED			 (1L<<0)3127#define BNX2_RPM_COMMAND_OVERRUN_ABORT			 (1L<<4)3128 3129#define BNX2_RPM_STATUS					0x000018043130#define BNX2_RPM_STATUS_MBUF_WAIT			 (1L<<0)3131#define BNX2_RPM_STATUS_FREE_WAIT			 (1L<<1)3132 3133#define BNX2_RPM_CONFIG					0x000018083134#define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM		 (1L<<0)3135#define BNX2_RPM_CONFIG_ACPI_ENA			 (1L<<1)3136#define BNX2_RPM_CONFIG_ACPI_KEEP			 (1L<<2)3137#define BNX2_RPM_CONFIG_MP_KEEP				 (1L<<3)3138#define BNX2_RPM_CONFIG_SORT_VECT_VAL			 (0xfL<<4)3139#define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT		 (1L<<30)3140#define BNX2_RPM_CONFIG_IGNORE_VLAN			 (1L<<31)3141 3142#define BNX2_RPM_MGMT_PKT_CTRL				0x0000180c3143#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT		 (0xfL<<0)3144#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE		 (0xfL<<4)3145#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN		 (1L<<30)3146#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN			 (1L<<31)3147 3148#define BNX2_RPM_VLAN_MATCH0				0x000018103149#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE	 (0xfffL<<0)3150 3151#define BNX2_RPM_VLAN_MATCH1				0x000018143152#define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE	 (0xfffL<<0)3153 3154#define BNX2_RPM_VLAN_MATCH2				0x000018183155#define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE	 (0xfffL<<0)3156 3157#define BNX2_RPM_VLAN_MATCH3				0x0000181c3158#define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE	 (0xfffL<<0)3159 3160#define BNX2_RPM_SORT_USER0				0x000018203161#define BNX2_RPM_SORT_USER0_PM_EN			 (0xffffL<<0)3162#define BNX2_RPM_SORT_USER0_BC_EN			 (1L<<16)3163#define BNX2_RPM_SORT_USER0_MC_EN			 (1L<<17)3164#define BNX2_RPM_SORT_USER0_MC_HSH_EN			 (1L<<18)3165#define BNX2_RPM_SORT_USER0_PROM_EN			 (1L<<19)3166#define BNX2_RPM_SORT_USER0_VLAN_EN			 (0xfL<<20)3167#define BNX2_RPM_SORT_USER0_PROM_VLAN			 (1L<<24)3168#define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH		 (1L<<25)3169#define BNX2_RPM_SORT_USER0_ENA				 (1L<<31)3170 3171#define BNX2_RPM_SORT_USER1				0x000018243172#define BNX2_RPM_SORT_USER1_PM_EN			 (0xffffL<<0)3173#define BNX2_RPM_SORT_USER1_BC_EN			 (1L<<16)3174#define BNX2_RPM_SORT_USER1_MC_EN			 (1L<<17)3175#define BNX2_RPM_SORT_USER1_MC_HSH_EN			 (1L<<18)3176#define BNX2_RPM_SORT_USER1_PROM_EN			 (1L<<19)3177#define BNX2_RPM_SORT_USER1_VLAN_EN			 (0xfL<<20)3178#define BNX2_RPM_SORT_USER1_PROM_VLAN			 (1L<<24)3179#define BNX2_RPM_SORT_USER1_ENA				 (1L<<31)3180 3181#define BNX2_RPM_SORT_USER2				0x000018283182#define BNX2_RPM_SORT_USER2_PM_EN			 (0xffffL<<0)3183#define BNX2_RPM_SORT_USER2_BC_EN			 (1L<<16)3184#define BNX2_RPM_SORT_USER2_MC_EN			 (1L<<17)3185#define BNX2_RPM_SORT_USER2_MC_HSH_EN			 (1L<<18)3186#define BNX2_RPM_SORT_USER2_PROM_EN			 (1L<<19)3187#define BNX2_RPM_SORT_USER2_VLAN_EN			 (0xfL<<20)3188#define BNX2_RPM_SORT_USER2_PROM_VLAN			 (1L<<24)3189#define BNX2_RPM_SORT_USER2_ENA				 (1L<<31)3190 3191#define BNX2_RPM_SORT_USER3				0x0000182c3192#define BNX2_RPM_SORT_USER3_PM_EN			 (0xffffL<<0)3193#define BNX2_RPM_SORT_USER3_BC_EN			 (1L<<16)3194#define BNX2_RPM_SORT_USER3_MC_EN			 (1L<<17)3195#define BNX2_RPM_SORT_USER3_MC_HSH_EN			 (1L<<18)3196#define BNX2_RPM_SORT_USER3_PROM_EN			 (1L<<19)3197#define BNX2_RPM_SORT_USER3_VLAN_EN			 (0xfL<<20)3198#define BNX2_RPM_SORT_USER3_PROM_VLAN			 (1L<<24)3199#define BNX2_RPM_SORT_USER3_ENA				 (1L<<31)3200 3201#define BNX2_RPM_STAT_L2_FILTER_DISCARDS		0x000018403202#define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS		0x000018443203#define BNX2_RPM_STAT_IFINFTQDISCARDS			0x000018483204#define BNX2_RPM_STAT_IFINMBUFDISCARD			0x0000184c3205#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT		0x000018503206#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0		0x000018543207#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN	 (0xffL<<0)3208#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER	 (0xffL<<16)3209#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE	 (1L<<30)3210#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN	 (1L<<31)3211 3212#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1		0x000018583213#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN	 (0xffL<<0)3214#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER	 (0xffL<<16)3215#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE	 (1L<<30)3216#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN	 (1L<<31)3217 3218#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2		0x0000185c3219#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN	 (0xffL<<0)3220#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER	 (0xffL<<16)3221#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE	 (1L<<30)3222#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN	 (1L<<31)3223 3224#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3		0x000018603225#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN	 (0xffL<<0)3226#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER	 (0xffL<<16)3227#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE	 (1L<<30)3228#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN	 (1L<<31)3229 3230#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4		0x000018643231#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN	 (0xffL<<0)3232#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER	 (0xffL<<16)3233#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE	 (1L<<30)3234#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN	 (1L<<31)3235 3236#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5		0x000018683237#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN	 (0xffL<<0)3238#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER	 (0xffL<<16)3239#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE	 (1L<<30)3240#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN	 (1L<<31)3241 3242#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6		0x0000186c3243#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN	 (0xffL<<0)3244#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER	 (0xffL<<16)3245#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE	 (1L<<30)3246#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN	 (1L<<31)3247 3248#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7		0x000018703249#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN	 (0xffL<<0)3250#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER	 (0xffL<<16)3251#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE	 (1L<<30)3252#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN	 (1L<<31)3253 3254#define BNX2_RPM_STAT_AC0				0x000018803255#define BNX2_RPM_STAT_AC1				0x000018843256#define BNX2_RPM_STAT_AC2				0x000018883257#define BNX2_RPM_STAT_AC3				0x0000188c3258#define BNX2_RPM_STAT_AC4				0x000018903259#define BNX2_RPM_RC_CNTL_16				0x000018e03260#define BNX2_RPM_RC_CNTL_16_OFFSET			 (0xffL<<0)3261#define BNX2_RPM_RC_CNTL_16_CLASS			 (0x7L<<8)3262#define BNX2_RPM_RC_CNTL_16_PRIORITY			 (1L<<11)3263#define BNX2_RPM_RC_CNTL_16_P4				 (1L<<12)3264#define BNX2_RPM_RC_CNTL_16_HDR_TYPE			 (0x7L<<13)3265#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START		 (0L<<13)3266#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP			 (1L<<13)3267#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP		 (2L<<13)3268#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP		 (3L<<13)3269#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA		 (4L<<13)3270#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP		 (5L<<13)3271#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6		 (6L<<13)3272#define BNX2_RPM_RC_CNTL_16_COMP			 (0x3L<<16)3273#define BNX2_RPM_RC_CNTL_16_COMP_EQUAL			 (0L<<16)3274#define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL			 (1L<<16)3275#define BNX2_RPM_RC_CNTL_16_COMP_GREATER		 (2L<<16)3276#define BNX2_RPM_RC_CNTL_16_COMP_LESS			 (3L<<16)3277#define BNX2_RPM_RC_CNTL_16_MAP				 (1L<<18)3278#define BNX2_RPM_RC_CNTL_16_SBIT			 (1L<<19)3279#define BNX2_RPM_RC_CNTL_16_CMDSEL			 (0x1fL<<20)3280#define BNX2_RPM_RC_CNTL_16_DISCARD			 (1L<<25)3281#define BNX2_RPM_RC_CNTL_16_MASK			 (1L<<26)3282#define BNX2_RPM_RC_CNTL_16_P1				 (1L<<27)3283#define BNX2_RPM_RC_CNTL_16_P2				 (1L<<28)3284#define BNX2_RPM_RC_CNTL_16_P3				 (1L<<29)3285#define BNX2_RPM_RC_CNTL_16_NBIT			 (1L<<30)3286 3287#define BNX2_RPM_RC_VALUE_MASK_16			0x000018e43288#define BNX2_RPM_RC_VALUE_MASK_16_VALUE			 (0xffffL<<0)3289#define BNX2_RPM_RC_VALUE_MASK_16_MASK			 (0xffffL<<16)3290 3291#define BNX2_RPM_RC_CNTL_17				0x000018e83292#define BNX2_RPM_RC_CNTL_17_OFFSET			 (0xffL<<0)3293#define BNX2_RPM_RC_CNTL_17_CLASS			 (0x7L<<8)3294#define BNX2_RPM_RC_CNTL_17_PRIORITY			 (1L<<11)3295#define BNX2_RPM_RC_CNTL_17_P4				 (1L<<12)3296#define BNX2_RPM_RC_CNTL_17_HDR_TYPE			 (0x7L<<13)3297#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START		 (0L<<13)3298#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP			 (1L<<13)3299#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP		 (2L<<13)3300#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP		 (3L<<13)3301#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA		 (4L<<13)3302#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP		 (5L<<13)3303#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6		 (6L<<13)3304#define BNX2_RPM_RC_CNTL_17_COMP			 (0x3L<<16)3305#define BNX2_RPM_RC_CNTL_17_COMP_EQUAL			 (0L<<16)3306#define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL			 (1L<<16)3307#define BNX2_RPM_RC_CNTL_17_COMP_GREATER		 (2L<<16)3308#define BNX2_RPM_RC_CNTL_17_COMP_LESS			 (3L<<16)3309#define BNX2_RPM_RC_CNTL_17_MAP				 (1L<<18)3310#define BNX2_RPM_RC_CNTL_17_SBIT			 (1L<<19)3311#define BNX2_RPM_RC_CNTL_17_CMDSEL			 (0x1fL<<20)3312#define BNX2_RPM_RC_CNTL_17_DISCARD			 (1L<<25)3313#define BNX2_RPM_RC_CNTL_17_MASK			 (1L<<26)3314#define BNX2_RPM_RC_CNTL_17_P1				 (1L<<27)3315#define BNX2_RPM_RC_CNTL_17_P2				 (1L<<28)3316#define BNX2_RPM_RC_CNTL_17_P3				 (1L<<29)3317#define BNX2_RPM_RC_CNTL_17_NBIT			 (1L<<30)3318 3319#define BNX2_RPM_RC_VALUE_MASK_17			0x000018ec3320#define BNX2_RPM_RC_VALUE_MASK_17_VALUE			 (0xffffL<<0)3321#define BNX2_RPM_RC_VALUE_MASK_17_MASK			 (0xffffL<<16)3322 3323#define BNX2_RPM_RC_CNTL_18				0x000018f03324#define BNX2_RPM_RC_CNTL_18_OFFSET			 (0xffL<<0)3325#define BNX2_RPM_RC_CNTL_18_CLASS			 (0x7L<<8)3326#define BNX2_RPM_RC_CNTL_18_PRIORITY			 (1L<<11)3327#define BNX2_RPM_RC_CNTL_18_P4				 (1L<<12)3328#define BNX2_RPM_RC_CNTL_18_HDR_TYPE			 (0x7L<<13)3329#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START		 (0L<<13)3330#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP			 (1L<<13)3331#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP		 (2L<<13)3332#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP		 (3L<<13)3333#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA		 (4L<<13)3334#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP		 (5L<<13)3335#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6		 (6L<<13)3336#define BNX2_RPM_RC_CNTL_18_COMP			 (0x3L<<16)3337#define BNX2_RPM_RC_CNTL_18_COMP_EQUAL			 (0L<<16)3338#define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL			 (1L<<16)3339#define BNX2_RPM_RC_CNTL_18_COMP_GREATER		 (2L<<16)3340#define BNX2_RPM_RC_CNTL_18_COMP_LESS			 (3L<<16)3341#define BNX2_RPM_RC_CNTL_18_MAP				 (1L<<18)3342#define BNX2_RPM_RC_CNTL_18_SBIT			 (1L<<19)3343#define BNX2_RPM_RC_CNTL_18_CMDSEL			 (0x1fL<<20)3344#define BNX2_RPM_RC_CNTL_18_DISCARD			 (1L<<25)3345#define BNX2_RPM_RC_CNTL_18_MASK			 (1L<<26)3346#define BNX2_RPM_RC_CNTL_18_P1				 (1L<<27)3347#define BNX2_RPM_RC_CNTL_18_P2				 (1L<<28)3348#define BNX2_RPM_RC_CNTL_18_P3				 (1L<<29)3349#define BNX2_RPM_RC_CNTL_18_NBIT			 (1L<<30)3350 3351#define BNX2_RPM_RC_VALUE_MASK_18			0x000018f43352#define BNX2_RPM_RC_VALUE_MASK_18_VALUE			 (0xffffL<<0)3353#define BNX2_RPM_RC_VALUE_MASK_18_MASK			 (0xffffL<<16)3354 3355#define BNX2_RPM_RC_CNTL_19				0x000018f83356#define BNX2_RPM_RC_CNTL_19_OFFSET			 (0xffL<<0)3357#define BNX2_RPM_RC_CNTL_19_CLASS			 (0x7L<<8)3358#define BNX2_RPM_RC_CNTL_19_PRIORITY			 (1L<<11)3359#define BNX2_RPM_RC_CNTL_19_P4				 (1L<<12)3360#define BNX2_RPM_RC_CNTL_19_HDR_TYPE			 (0x7L<<13)3361#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START		 (0L<<13)3362#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP			 (1L<<13)3363#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP		 (2L<<13)3364#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP		 (3L<<13)3365#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA		 (4L<<13)3366#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP		 (5L<<13)3367#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6		 (6L<<13)3368#define BNX2_RPM_RC_CNTL_19_COMP			 (0x3L<<16)3369#define BNX2_RPM_RC_CNTL_19_COMP_EQUAL			 (0L<<16)3370#define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL			 (1L<<16)3371#define BNX2_RPM_RC_CNTL_19_COMP_GREATER		 (2L<<16)3372#define BNX2_RPM_RC_CNTL_19_COMP_LESS			 (3L<<16)3373#define BNX2_RPM_RC_CNTL_19_MAP				 (1L<<18)3374#define BNX2_RPM_RC_CNTL_19_SBIT			 (1L<<19)3375#define BNX2_RPM_RC_CNTL_19_CMDSEL			 (0x1fL<<20)3376#define BNX2_RPM_RC_CNTL_19_DISCARD			 (1L<<25)3377#define BNX2_RPM_RC_CNTL_19_MASK			 (1L<<26)3378#define BNX2_RPM_RC_CNTL_19_P1				 (1L<<27)3379#define BNX2_RPM_RC_CNTL_19_P2				 (1L<<28)3380#define BNX2_RPM_RC_CNTL_19_P3				 (1L<<29)3381#define BNX2_RPM_RC_CNTL_19_NBIT			 (1L<<30)3382 3383#define BNX2_RPM_RC_VALUE_MASK_19			0x000018fc3384#define BNX2_RPM_RC_VALUE_MASK_19_VALUE			 (0xffffL<<0)3385#define BNX2_RPM_RC_VALUE_MASK_19_MASK			 (0xffffL<<16)3386 3387#define BNX2_RPM_RC_CNTL_0				0x000019003388#define BNX2_RPM_RC_CNTL_0_OFFSET			 (0xffL<<0)3389#define BNX2_RPM_RC_CNTL_0_CLASS			 (0x7L<<8)3390#define BNX2_RPM_RC_CNTL_0_PRIORITY			 (1L<<11)3391#define BNX2_RPM_RC_CNTL_0_P4				 (1L<<12)3392#define BNX2_RPM_RC_CNTL_0_HDR_TYPE			 (0x7L<<13)3393#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START		 (0L<<13)3394#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP			 (1L<<13)3395#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP			 (2L<<13)3396#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP			 (3L<<13)3397#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA		 (4L<<13)3398#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP		 (5L<<13)3399#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6		 (6L<<13)3400#define BNX2_RPM_RC_CNTL_0_COMP				 (0x3L<<16)3401#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL			 (0L<<16)3402#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL			 (1L<<16)3403#define BNX2_RPM_RC_CNTL_0_COMP_GREATER			 (2L<<16)3404#define BNX2_RPM_RC_CNTL_0_COMP_LESS			 (3L<<16)3405#define BNX2_RPM_RC_CNTL_0_MAP_XI			 (1L<<18)3406#define BNX2_RPM_RC_CNTL_0_SBIT				 (1L<<19)3407#define BNX2_RPM_RC_CNTL_0_CMDSEL			 (0xfL<<20)3408#define BNX2_RPM_RC_CNTL_0_MAP				 (1L<<24)3409#define BNX2_RPM_RC_CNTL_0_CMDSEL_XI			 (0x1fL<<20)3410#define BNX2_RPM_RC_CNTL_0_DISCARD			 (1L<<25)3411#define BNX2_RPM_RC_CNTL_0_MASK				 (1L<<26)3412#define BNX2_RPM_RC_CNTL_0_P1				 (1L<<27)3413#define BNX2_RPM_RC_CNTL_0_P2				 (1L<<28)3414#define BNX2_RPM_RC_CNTL_0_P3				 (1L<<29)3415#define BNX2_RPM_RC_CNTL_0_NBIT				 (1L<<30)3416 3417#define BNX2_RPM_RC_VALUE_MASK_0			0x000019043418#define BNX2_RPM_RC_VALUE_MASK_0_VALUE			 (0xffffL<<0)3419#define BNX2_RPM_RC_VALUE_MASK_0_MASK			 (0xffffL<<16)3420 3421#define BNX2_RPM_RC_CNTL_1				0x000019083422#define BNX2_RPM_RC_CNTL_1_A				 (0x3ffffL<<0)3423#define BNX2_RPM_RC_CNTL_1_B				 (0xfffL<<19)3424#define BNX2_RPM_RC_CNTL_1_OFFSET_XI			 (0xffL<<0)3425#define BNX2_RPM_RC_CNTL_1_CLASS_XI			 (0x7L<<8)3426#define BNX2_RPM_RC_CNTL_1_PRIORITY_XI			 (1L<<11)3427#define BNX2_RPM_RC_CNTL_1_P4_XI			 (1L<<12)3428#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI			 (0x7L<<13)3429#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI		 (0L<<13)3430#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI		 (1L<<13)3431#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI		 (2L<<13)3432#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI		 (3L<<13)3433#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI		 (4L<<13)3434#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3435#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI		 (6L<<13)3436#define BNX2_RPM_RC_CNTL_1_COMP_XI			 (0x3L<<16)3437#define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI		 (0L<<16)3438#define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI		 (1L<<16)3439#define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI		 (2L<<16)3440#define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI			 (3L<<16)3441#define BNX2_RPM_RC_CNTL_1_MAP_XI			 (1L<<18)3442#define BNX2_RPM_RC_CNTL_1_SBIT_XI			 (1L<<19)3443#define BNX2_RPM_RC_CNTL_1_CMDSEL_XI			 (0x1fL<<20)3444#define BNX2_RPM_RC_CNTL_1_DISCARD_XI			 (1L<<25)3445#define BNX2_RPM_RC_CNTL_1_MASK_XI			 (1L<<26)3446#define BNX2_RPM_RC_CNTL_1_P1_XI			 (1L<<27)3447#define BNX2_RPM_RC_CNTL_1_P2_XI			 (1L<<28)3448#define BNX2_RPM_RC_CNTL_1_P3_XI			 (1L<<29)3449#define BNX2_RPM_RC_CNTL_1_NBIT_XI			 (1L<<30)3450 3451#define BNX2_RPM_RC_VALUE_MASK_1			0x0000190c3452#define BNX2_RPM_RC_VALUE_MASK_1_VALUE			 (0xffffL<<0)3453#define BNX2_RPM_RC_VALUE_MASK_1_MASK			 (0xffffL<<16)3454 3455#define BNX2_RPM_RC_CNTL_2				0x000019103456#define BNX2_RPM_RC_CNTL_2_A				 (0x3ffffL<<0)3457#define BNX2_RPM_RC_CNTL_2_B				 (0xfffL<<19)3458#define BNX2_RPM_RC_CNTL_2_OFFSET_XI			 (0xffL<<0)3459#define BNX2_RPM_RC_CNTL_2_CLASS_XI			 (0x7L<<8)3460#define BNX2_RPM_RC_CNTL_2_PRIORITY_XI			 (1L<<11)3461#define BNX2_RPM_RC_CNTL_2_P4_XI			 (1L<<12)3462#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI			 (0x7L<<13)3463#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI		 (0L<<13)3464#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI		 (1L<<13)3465#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI		 (2L<<13)3466#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI		 (3L<<13)3467#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI		 (4L<<13)3468#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3469#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI		 (6L<<13)3470#define BNX2_RPM_RC_CNTL_2_COMP_XI			 (0x3L<<16)3471#define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI		 (0L<<16)3472#define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI		 (1L<<16)3473#define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI		 (2L<<16)3474#define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI			 (3L<<16)3475#define BNX2_RPM_RC_CNTL_2_MAP_XI			 (1L<<18)3476#define BNX2_RPM_RC_CNTL_2_SBIT_XI			 (1L<<19)3477#define BNX2_RPM_RC_CNTL_2_CMDSEL_XI			 (0x1fL<<20)3478#define BNX2_RPM_RC_CNTL_2_DISCARD_XI			 (1L<<25)3479#define BNX2_RPM_RC_CNTL_2_MASK_XI			 (1L<<26)3480#define BNX2_RPM_RC_CNTL_2_P1_XI			 (1L<<27)3481#define BNX2_RPM_RC_CNTL_2_P2_XI			 (1L<<28)3482#define BNX2_RPM_RC_CNTL_2_P3_XI			 (1L<<29)3483#define BNX2_RPM_RC_CNTL_2_NBIT_XI			 (1L<<30)3484 3485#define BNX2_RPM_RC_VALUE_MASK_2			0x000019143486#define BNX2_RPM_RC_VALUE_MASK_2_VALUE			 (0xffffL<<0)3487#define BNX2_RPM_RC_VALUE_MASK_2_MASK			 (0xffffL<<16)3488 3489#define BNX2_RPM_RC_CNTL_3				0x000019183490#define BNX2_RPM_RC_CNTL_3_A				 (0x3ffffL<<0)3491#define BNX2_RPM_RC_CNTL_3_B				 (0xfffL<<19)3492#define BNX2_RPM_RC_CNTL_3_OFFSET_XI			 (0xffL<<0)3493#define BNX2_RPM_RC_CNTL_3_CLASS_XI			 (0x7L<<8)3494#define BNX2_RPM_RC_CNTL_3_PRIORITY_XI			 (1L<<11)3495#define BNX2_RPM_RC_CNTL_3_P4_XI			 (1L<<12)3496#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI			 (0x7L<<13)3497#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI		 (0L<<13)3498#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI		 (1L<<13)3499#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI		 (2L<<13)3500#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI		 (3L<<13)3501#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI		 (4L<<13)3502#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3503#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI		 (6L<<13)3504#define BNX2_RPM_RC_CNTL_3_COMP_XI			 (0x3L<<16)3505#define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI		 (0L<<16)3506#define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI		 (1L<<16)3507#define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI		 (2L<<16)3508#define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI			 (3L<<16)3509#define BNX2_RPM_RC_CNTL_3_MAP_XI			 (1L<<18)3510#define BNX2_RPM_RC_CNTL_3_SBIT_XI			 (1L<<19)3511#define BNX2_RPM_RC_CNTL_3_CMDSEL_XI			 (0x1fL<<20)3512#define BNX2_RPM_RC_CNTL_3_DISCARD_XI			 (1L<<25)3513#define BNX2_RPM_RC_CNTL_3_MASK_XI			 (1L<<26)3514#define BNX2_RPM_RC_CNTL_3_P1_XI			 (1L<<27)3515#define BNX2_RPM_RC_CNTL_3_P2_XI			 (1L<<28)3516#define BNX2_RPM_RC_CNTL_3_P3_XI			 (1L<<29)3517#define BNX2_RPM_RC_CNTL_3_NBIT_XI			 (1L<<30)3518 3519#define BNX2_RPM_RC_VALUE_MASK_3			0x0000191c3520#define BNX2_RPM_RC_VALUE_MASK_3_VALUE			 (0xffffL<<0)3521#define BNX2_RPM_RC_VALUE_MASK_3_MASK			 (0xffffL<<16)3522 3523#define BNX2_RPM_RC_CNTL_4				0x000019203524#define BNX2_RPM_RC_CNTL_4_A				 (0x3ffffL<<0)3525#define BNX2_RPM_RC_CNTL_4_B				 (0xfffL<<19)3526#define BNX2_RPM_RC_CNTL_4_OFFSET_XI			 (0xffL<<0)3527#define BNX2_RPM_RC_CNTL_4_CLASS_XI			 (0x7L<<8)3528#define BNX2_RPM_RC_CNTL_4_PRIORITY_XI			 (1L<<11)3529#define BNX2_RPM_RC_CNTL_4_P4_XI			 (1L<<12)3530#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI			 (0x7L<<13)3531#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI		 (0L<<13)3532#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI		 (1L<<13)3533#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI		 (2L<<13)3534#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI		 (3L<<13)3535#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI		 (4L<<13)3536#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3537#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI		 (6L<<13)3538#define BNX2_RPM_RC_CNTL_4_COMP_XI			 (0x3L<<16)3539#define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI		 (0L<<16)3540#define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI		 (1L<<16)3541#define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI		 (2L<<16)3542#define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI			 (3L<<16)3543#define BNX2_RPM_RC_CNTL_4_MAP_XI			 (1L<<18)3544#define BNX2_RPM_RC_CNTL_4_SBIT_XI			 (1L<<19)3545#define BNX2_RPM_RC_CNTL_4_CMDSEL_XI			 (0x1fL<<20)3546#define BNX2_RPM_RC_CNTL_4_DISCARD_XI			 (1L<<25)3547#define BNX2_RPM_RC_CNTL_4_MASK_XI			 (1L<<26)3548#define BNX2_RPM_RC_CNTL_4_P1_XI			 (1L<<27)3549#define BNX2_RPM_RC_CNTL_4_P2_XI			 (1L<<28)3550#define BNX2_RPM_RC_CNTL_4_P3_XI			 (1L<<29)3551#define BNX2_RPM_RC_CNTL_4_NBIT_XI			 (1L<<30)3552 3553#define BNX2_RPM_RC_VALUE_MASK_4			0x000019243554#define BNX2_RPM_RC_VALUE_MASK_4_VALUE			 (0xffffL<<0)3555#define BNX2_RPM_RC_VALUE_MASK_4_MASK			 (0xffffL<<16)3556 3557#define BNX2_RPM_RC_CNTL_5				0x000019283558#define BNX2_RPM_RC_CNTL_5_A				 (0x3ffffL<<0)3559#define BNX2_RPM_RC_CNTL_5_B				 (0xfffL<<19)3560#define BNX2_RPM_RC_CNTL_5_OFFSET_XI			 (0xffL<<0)3561#define BNX2_RPM_RC_CNTL_5_CLASS_XI			 (0x7L<<8)3562#define BNX2_RPM_RC_CNTL_5_PRIORITY_XI			 (1L<<11)3563#define BNX2_RPM_RC_CNTL_5_P4_XI			 (1L<<12)3564#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI			 (0x7L<<13)3565#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI		 (0L<<13)3566#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI		 (1L<<13)3567#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI		 (2L<<13)3568#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI		 (3L<<13)3569#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI		 (4L<<13)3570#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3571#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI		 (6L<<13)3572#define BNX2_RPM_RC_CNTL_5_COMP_XI			 (0x3L<<16)3573#define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI		 (0L<<16)3574#define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI		 (1L<<16)3575#define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI		 (2L<<16)3576#define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI			 (3L<<16)3577#define BNX2_RPM_RC_CNTL_5_MAP_XI			 (1L<<18)3578#define BNX2_RPM_RC_CNTL_5_SBIT_XI			 (1L<<19)3579#define BNX2_RPM_RC_CNTL_5_CMDSEL_XI			 (0x1fL<<20)3580#define BNX2_RPM_RC_CNTL_5_DISCARD_XI			 (1L<<25)3581#define BNX2_RPM_RC_CNTL_5_MASK_XI			 (1L<<26)3582#define BNX2_RPM_RC_CNTL_5_P1_XI			 (1L<<27)3583#define BNX2_RPM_RC_CNTL_5_P2_XI			 (1L<<28)3584#define BNX2_RPM_RC_CNTL_5_P3_XI			 (1L<<29)3585#define BNX2_RPM_RC_CNTL_5_NBIT_XI			 (1L<<30)3586 3587#define BNX2_RPM_RC_VALUE_MASK_5			0x0000192c3588#define BNX2_RPM_RC_VALUE_MASK_5_VALUE			 (0xffffL<<0)3589#define BNX2_RPM_RC_VALUE_MASK_5_MASK			 (0xffffL<<16)3590 3591#define BNX2_RPM_RC_CNTL_6				0x000019303592#define BNX2_RPM_RC_CNTL_6_A				 (0x3ffffL<<0)3593#define BNX2_RPM_RC_CNTL_6_B				 (0xfffL<<19)3594#define BNX2_RPM_RC_CNTL_6_OFFSET_XI			 (0xffL<<0)3595#define BNX2_RPM_RC_CNTL_6_CLASS_XI			 (0x7L<<8)3596#define BNX2_RPM_RC_CNTL_6_PRIORITY_XI			 (1L<<11)3597#define BNX2_RPM_RC_CNTL_6_P4_XI			 (1L<<12)3598#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI			 (0x7L<<13)3599#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI		 (0L<<13)3600#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI		 (1L<<13)3601#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI		 (2L<<13)3602#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI		 (3L<<13)3603#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI		 (4L<<13)3604#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3605#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI		 (6L<<13)3606#define BNX2_RPM_RC_CNTL_6_COMP_XI			 (0x3L<<16)3607#define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI		 (0L<<16)3608#define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI		 (1L<<16)3609#define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI		 (2L<<16)3610#define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI			 (3L<<16)3611#define BNX2_RPM_RC_CNTL_6_MAP_XI			 (1L<<18)3612#define BNX2_RPM_RC_CNTL_6_SBIT_XI			 (1L<<19)3613#define BNX2_RPM_RC_CNTL_6_CMDSEL_XI			 (0x1fL<<20)3614#define BNX2_RPM_RC_CNTL_6_DISCARD_XI			 (1L<<25)3615#define BNX2_RPM_RC_CNTL_6_MASK_XI			 (1L<<26)3616#define BNX2_RPM_RC_CNTL_6_P1_XI			 (1L<<27)3617#define BNX2_RPM_RC_CNTL_6_P2_XI			 (1L<<28)3618#define BNX2_RPM_RC_CNTL_6_P3_XI			 (1L<<29)3619#define BNX2_RPM_RC_CNTL_6_NBIT_XI			 (1L<<30)3620 3621#define BNX2_RPM_RC_VALUE_MASK_6			0x000019343622#define BNX2_RPM_RC_VALUE_MASK_6_VALUE			 (0xffffL<<0)3623#define BNX2_RPM_RC_VALUE_MASK_6_MASK			 (0xffffL<<16)3624 3625#define BNX2_RPM_RC_CNTL_7				0x000019383626#define BNX2_RPM_RC_CNTL_7_A				 (0x3ffffL<<0)3627#define BNX2_RPM_RC_CNTL_7_B				 (0xfffL<<19)3628#define BNX2_RPM_RC_CNTL_7_OFFSET_XI			 (0xffL<<0)3629#define BNX2_RPM_RC_CNTL_7_CLASS_XI			 (0x7L<<8)3630#define BNX2_RPM_RC_CNTL_7_PRIORITY_XI			 (1L<<11)3631#define BNX2_RPM_RC_CNTL_7_P4_XI			 (1L<<12)3632#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI			 (0x7L<<13)3633#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI		 (0L<<13)3634#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI		 (1L<<13)3635#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI		 (2L<<13)3636#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI		 (3L<<13)3637#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI		 (4L<<13)3638#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3639#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI		 (6L<<13)3640#define BNX2_RPM_RC_CNTL_7_COMP_XI			 (0x3L<<16)3641#define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI		 (0L<<16)3642#define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI		 (1L<<16)3643#define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI		 (2L<<16)3644#define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI			 (3L<<16)3645#define BNX2_RPM_RC_CNTL_7_MAP_XI			 (1L<<18)3646#define BNX2_RPM_RC_CNTL_7_SBIT_XI			 (1L<<19)3647#define BNX2_RPM_RC_CNTL_7_CMDSEL_XI			 (0x1fL<<20)3648#define BNX2_RPM_RC_CNTL_7_DISCARD_XI			 (1L<<25)3649#define BNX2_RPM_RC_CNTL_7_MASK_XI			 (1L<<26)3650#define BNX2_RPM_RC_CNTL_7_P1_XI			 (1L<<27)3651#define BNX2_RPM_RC_CNTL_7_P2_XI			 (1L<<28)3652#define BNX2_RPM_RC_CNTL_7_P3_XI			 (1L<<29)3653#define BNX2_RPM_RC_CNTL_7_NBIT_XI			 (1L<<30)3654 3655#define BNX2_RPM_RC_VALUE_MASK_7			0x0000193c3656#define BNX2_RPM_RC_VALUE_MASK_7_VALUE			 (0xffffL<<0)3657#define BNX2_RPM_RC_VALUE_MASK_7_MASK			 (0xffffL<<16)3658 3659#define BNX2_RPM_RC_CNTL_8				0x000019403660#define BNX2_RPM_RC_CNTL_8_A				 (0x3ffffL<<0)3661#define BNX2_RPM_RC_CNTL_8_B				 (0xfffL<<19)3662#define BNX2_RPM_RC_CNTL_8_OFFSET_XI			 (0xffL<<0)3663#define BNX2_RPM_RC_CNTL_8_CLASS_XI			 (0x7L<<8)3664#define BNX2_RPM_RC_CNTL_8_PRIORITY_XI			 (1L<<11)3665#define BNX2_RPM_RC_CNTL_8_P4_XI			 (1L<<12)3666#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI			 (0x7L<<13)3667#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI		 (0L<<13)3668#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI		 (1L<<13)3669#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI		 (2L<<13)3670#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI		 (3L<<13)3671#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI		 (4L<<13)3672#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3673#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI		 (6L<<13)3674#define BNX2_RPM_RC_CNTL_8_COMP_XI			 (0x3L<<16)3675#define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI		 (0L<<16)3676#define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI		 (1L<<16)3677#define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI		 (2L<<16)3678#define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI			 (3L<<16)3679#define BNX2_RPM_RC_CNTL_8_MAP_XI			 (1L<<18)3680#define BNX2_RPM_RC_CNTL_8_SBIT_XI			 (1L<<19)3681#define BNX2_RPM_RC_CNTL_8_CMDSEL_XI			 (0x1fL<<20)3682#define BNX2_RPM_RC_CNTL_8_DISCARD_XI			 (1L<<25)3683#define BNX2_RPM_RC_CNTL_8_MASK_XI			 (1L<<26)3684#define BNX2_RPM_RC_CNTL_8_P1_XI			 (1L<<27)3685#define BNX2_RPM_RC_CNTL_8_P2_XI			 (1L<<28)3686#define BNX2_RPM_RC_CNTL_8_P3_XI			 (1L<<29)3687#define BNX2_RPM_RC_CNTL_8_NBIT_XI			 (1L<<30)3688 3689#define BNX2_RPM_RC_VALUE_MASK_8			0x000019443690#define BNX2_RPM_RC_VALUE_MASK_8_VALUE			 (0xffffL<<0)3691#define BNX2_RPM_RC_VALUE_MASK_8_MASK			 (0xffffL<<16)3692 3693#define BNX2_RPM_RC_CNTL_9				0x000019483694#define BNX2_RPM_RC_CNTL_9_A				 (0x3ffffL<<0)3695#define BNX2_RPM_RC_CNTL_9_B				 (0xfffL<<19)3696#define BNX2_RPM_RC_CNTL_9_OFFSET_XI			 (0xffL<<0)3697#define BNX2_RPM_RC_CNTL_9_CLASS_XI			 (0x7L<<8)3698#define BNX2_RPM_RC_CNTL_9_PRIORITY_XI			 (1L<<11)3699#define BNX2_RPM_RC_CNTL_9_P4_XI			 (1L<<12)3700#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI			 (0x7L<<13)3701#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI		 (0L<<13)3702#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI		 (1L<<13)3703#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI		 (2L<<13)3704#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI		 (3L<<13)3705#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI		 (4L<<13)3706#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3707#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI		 (6L<<13)3708#define BNX2_RPM_RC_CNTL_9_COMP_XI			 (0x3L<<16)3709#define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI		 (0L<<16)3710#define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI		 (1L<<16)3711#define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI		 (2L<<16)3712#define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI			 (3L<<16)3713#define BNX2_RPM_RC_CNTL_9_MAP_XI			 (1L<<18)3714#define BNX2_RPM_RC_CNTL_9_SBIT_XI			 (1L<<19)3715#define BNX2_RPM_RC_CNTL_9_CMDSEL_XI			 (0x1fL<<20)3716#define BNX2_RPM_RC_CNTL_9_DISCARD_XI			 (1L<<25)3717#define BNX2_RPM_RC_CNTL_9_MASK_XI			 (1L<<26)3718#define BNX2_RPM_RC_CNTL_9_P1_XI			 (1L<<27)3719#define BNX2_RPM_RC_CNTL_9_P2_XI			 (1L<<28)3720#define BNX2_RPM_RC_CNTL_9_P3_XI			 (1L<<29)3721#define BNX2_RPM_RC_CNTL_9_NBIT_XI			 (1L<<30)3722 3723#define BNX2_RPM_RC_VALUE_MASK_9			0x0000194c3724#define BNX2_RPM_RC_VALUE_MASK_9_VALUE			 (0xffffL<<0)3725#define BNX2_RPM_RC_VALUE_MASK_9_MASK			 (0xffffL<<16)3726 3727#define BNX2_RPM_RC_CNTL_10				0x000019503728#define BNX2_RPM_RC_CNTL_10_A				 (0x3ffffL<<0)3729#define BNX2_RPM_RC_CNTL_10_B				 (0xfffL<<19)3730#define BNX2_RPM_RC_CNTL_10_OFFSET_XI			 (0xffL<<0)3731#define BNX2_RPM_RC_CNTL_10_CLASS_XI			 (0x7L<<8)3732#define BNX2_RPM_RC_CNTL_10_PRIORITY_XI			 (1L<<11)3733#define BNX2_RPM_RC_CNTL_10_P4_XI			 (1L<<12)3734#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI			 (0x7L<<13)3735#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI		 (0L<<13)3736#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI		 (1L<<13)3737#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI		 (2L<<13)3738#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI		 (3L<<13)3739#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI		 (4L<<13)3740#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3741#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI		 (6L<<13)3742#define BNX2_RPM_RC_CNTL_10_COMP_XI			 (0x3L<<16)3743#define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI		 (0L<<16)3744#define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI		 (1L<<16)3745#define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI		 (2L<<16)3746#define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI		 (3L<<16)3747#define BNX2_RPM_RC_CNTL_10_MAP_XI			 (1L<<18)3748#define BNX2_RPM_RC_CNTL_10_SBIT_XI			 (1L<<19)3749#define BNX2_RPM_RC_CNTL_10_CMDSEL_XI			 (0x1fL<<20)3750#define BNX2_RPM_RC_CNTL_10_DISCARD_XI			 (1L<<25)3751#define BNX2_RPM_RC_CNTL_10_MASK_XI			 (1L<<26)3752#define BNX2_RPM_RC_CNTL_10_P1_XI			 (1L<<27)3753#define BNX2_RPM_RC_CNTL_10_P2_XI			 (1L<<28)3754#define BNX2_RPM_RC_CNTL_10_P3_XI			 (1L<<29)3755#define BNX2_RPM_RC_CNTL_10_NBIT_XI			 (1L<<30)3756 3757#define BNX2_RPM_RC_VALUE_MASK_10			0x000019543758#define BNX2_RPM_RC_VALUE_MASK_10_VALUE			 (0xffffL<<0)3759#define BNX2_RPM_RC_VALUE_MASK_10_MASK			 (0xffffL<<16)3760 3761#define BNX2_RPM_RC_CNTL_11				0x000019583762#define BNX2_RPM_RC_CNTL_11_A				 (0x3ffffL<<0)3763#define BNX2_RPM_RC_CNTL_11_B				 (0xfffL<<19)3764#define BNX2_RPM_RC_CNTL_11_OFFSET_XI			 (0xffL<<0)3765#define BNX2_RPM_RC_CNTL_11_CLASS_XI			 (0x7L<<8)3766#define BNX2_RPM_RC_CNTL_11_PRIORITY_XI			 (1L<<11)3767#define BNX2_RPM_RC_CNTL_11_P4_XI			 (1L<<12)3768#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI			 (0x7L<<13)3769#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI		 (0L<<13)3770#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI		 (1L<<13)3771#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI		 (2L<<13)3772#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI		 (3L<<13)3773#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI		 (4L<<13)3774#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3775#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI		 (6L<<13)3776#define BNX2_RPM_RC_CNTL_11_COMP_XI			 (0x3L<<16)3777#define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI		 (0L<<16)3778#define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI		 (1L<<16)3779#define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI		 (2L<<16)3780#define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI		 (3L<<16)3781#define BNX2_RPM_RC_CNTL_11_MAP_XI			 (1L<<18)3782#define BNX2_RPM_RC_CNTL_11_SBIT_XI			 (1L<<19)3783#define BNX2_RPM_RC_CNTL_11_CMDSEL_XI			 (0x1fL<<20)3784#define BNX2_RPM_RC_CNTL_11_DISCARD_XI			 (1L<<25)3785#define BNX2_RPM_RC_CNTL_11_MASK_XI			 (1L<<26)3786#define BNX2_RPM_RC_CNTL_11_P1_XI			 (1L<<27)3787#define BNX2_RPM_RC_CNTL_11_P2_XI			 (1L<<28)3788#define BNX2_RPM_RC_CNTL_11_P3_XI			 (1L<<29)3789#define BNX2_RPM_RC_CNTL_11_NBIT_XI			 (1L<<30)3790 3791#define BNX2_RPM_RC_VALUE_MASK_11			0x0000195c3792#define BNX2_RPM_RC_VALUE_MASK_11_VALUE			 (0xffffL<<0)3793#define BNX2_RPM_RC_VALUE_MASK_11_MASK			 (0xffffL<<16)3794 3795#define BNX2_RPM_RC_CNTL_12				0x000019603796#define BNX2_RPM_RC_CNTL_12_A				 (0x3ffffL<<0)3797#define BNX2_RPM_RC_CNTL_12_B				 (0xfffL<<19)3798#define BNX2_RPM_RC_CNTL_12_OFFSET_XI			 (0xffL<<0)3799#define BNX2_RPM_RC_CNTL_12_CLASS_XI			 (0x7L<<8)3800#define BNX2_RPM_RC_CNTL_12_PRIORITY_XI			 (1L<<11)3801#define BNX2_RPM_RC_CNTL_12_P4_XI			 (1L<<12)3802#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI			 (0x7L<<13)3803#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI		 (0L<<13)3804#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI		 (1L<<13)3805#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI		 (2L<<13)3806#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI		 (3L<<13)3807#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI		 (4L<<13)3808#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3809#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI		 (6L<<13)3810#define BNX2_RPM_RC_CNTL_12_COMP_XI			 (0x3L<<16)3811#define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI		 (0L<<16)3812#define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI		 (1L<<16)3813#define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI		 (2L<<16)3814#define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI		 (3L<<16)3815#define BNX2_RPM_RC_CNTL_12_MAP_XI			 (1L<<18)3816#define BNX2_RPM_RC_CNTL_12_SBIT_XI			 (1L<<19)3817#define BNX2_RPM_RC_CNTL_12_CMDSEL_XI			 (0x1fL<<20)3818#define BNX2_RPM_RC_CNTL_12_DISCARD_XI			 (1L<<25)3819#define BNX2_RPM_RC_CNTL_12_MASK_XI			 (1L<<26)3820#define BNX2_RPM_RC_CNTL_12_P1_XI			 (1L<<27)3821#define BNX2_RPM_RC_CNTL_12_P2_XI			 (1L<<28)3822#define BNX2_RPM_RC_CNTL_12_P3_XI			 (1L<<29)3823#define BNX2_RPM_RC_CNTL_12_NBIT_XI			 (1L<<30)3824 3825#define BNX2_RPM_RC_VALUE_MASK_12			0x000019643826#define BNX2_RPM_RC_VALUE_MASK_12_VALUE			 (0xffffL<<0)3827#define BNX2_RPM_RC_VALUE_MASK_12_MASK			 (0xffffL<<16)3828 3829#define BNX2_RPM_RC_CNTL_13				0x000019683830#define BNX2_RPM_RC_CNTL_13_A				 (0x3ffffL<<0)3831#define BNX2_RPM_RC_CNTL_13_B				 (0xfffL<<19)3832#define BNX2_RPM_RC_CNTL_13_OFFSET_XI			 (0xffL<<0)3833#define BNX2_RPM_RC_CNTL_13_CLASS_XI			 (0x7L<<8)3834#define BNX2_RPM_RC_CNTL_13_PRIORITY_XI			 (1L<<11)3835#define BNX2_RPM_RC_CNTL_13_P4_XI			 (1L<<12)3836#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI			 (0x7L<<13)3837#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI		 (0L<<13)3838#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI		 (1L<<13)3839#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI		 (2L<<13)3840#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI		 (3L<<13)3841#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI		 (4L<<13)3842#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3843#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI		 (6L<<13)3844#define BNX2_RPM_RC_CNTL_13_COMP_XI			 (0x3L<<16)3845#define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI		 (0L<<16)3846#define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI		 (1L<<16)3847#define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI		 (2L<<16)3848#define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI		 (3L<<16)3849#define BNX2_RPM_RC_CNTL_13_MAP_XI			 (1L<<18)3850#define BNX2_RPM_RC_CNTL_13_SBIT_XI			 (1L<<19)3851#define BNX2_RPM_RC_CNTL_13_CMDSEL_XI			 (0x1fL<<20)3852#define BNX2_RPM_RC_CNTL_13_DISCARD_XI			 (1L<<25)3853#define BNX2_RPM_RC_CNTL_13_MASK_XI			 (1L<<26)3854#define BNX2_RPM_RC_CNTL_13_P1_XI			 (1L<<27)3855#define BNX2_RPM_RC_CNTL_13_P2_XI			 (1L<<28)3856#define BNX2_RPM_RC_CNTL_13_P3_XI			 (1L<<29)3857#define BNX2_RPM_RC_CNTL_13_NBIT_XI			 (1L<<30)3858 3859#define BNX2_RPM_RC_VALUE_MASK_13			0x0000196c3860#define BNX2_RPM_RC_VALUE_MASK_13_VALUE			 (0xffffL<<0)3861#define BNX2_RPM_RC_VALUE_MASK_13_MASK			 (0xffffL<<16)3862 3863#define BNX2_RPM_RC_CNTL_14				0x000019703864#define BNX2_RPM_RC_CNTL_14_A				 (0x3ffffL<<0)3865#define BNX2_RPM_RC_CNTL_14_B				 (0xfffL<<19)3866#define BNX2_RPM_RC_CNTL_14_OFFSET_XI			 (0xffL<<0)3867#define BNX2_RPM_RC_CNTL_14_CLASS_XI			 (0x7L<<8)3868#define BNX2_RPM_RC_CNTL_14_PRIORITY_XI			 (1L<<11)3869#define BNX2_RPM_RC_CNTL_14_P4_XI			 (1L<<12)3870#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI			 (0x7L<<13)3871#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI		 (0L<<13)3872#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI		 (1L<<13)3873#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI		 (2L<<13)3874#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI		 (3L<<13)3875#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI		 (4L<<13)3876#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3877#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI		 (6L<<13)3878#define BNX2_RPM_RC_CNTL_14_COMP_XI			 (0x3L<<16)3879#define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI		 (0L<<16)3880#define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI		 (1L<<16)3881#define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI		 (2L<<16)3882#define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI		 (3L<<16)3883#define BNX2_RPM_RC_CNTL_14_MAP_XI			 (1L<<18)3884#define BNX2_RPM_RC_CNTL_14_SBIT_XI			 (1L<<19)3885#define BNX2_RPM_RC_CNTL_14_CMDSEL_XI			 (0x1fL<<20)3886#define BNX2_RPM_RC_CNTL_14_DISCARD_XI			 (1L<<25)3887#define BNX2_RPM_RC_CNTL_14_MASK_XI			 (1L<<26)3888#define BNX2_RPM_RC_CNTL_14_P1_XI			 (1L<<27)3889#define BNX2_RPM_RC_CNTL_14_P2_XI			 (1L<<28)3890#define BNX2_RPM_RC_CNTL_14_P3_XI			 (1L<<29)3891#define BNX2_RPM_RC_CNTL_14_NBIT_XI			 (1L<<30)3892 3893#define BNX2_RPM_RC_VALUE_MASK_14			0x000019743894#define BNX2_RPM_RC_VALUE_MASK_14_VALUE			 (0xffffL<<0)3895#define BNX2_RPM_RC_VALUE_MASK_14_MASK			 (0xffffL<<16)3896 3897#define BNX2_RPM_RC_CNTL_15				0x000019783898#define BNX2_RPM_RC_CNTL_15_A				 (0x3ffffL<<0)3899#define BNX2_RPM_RC_CNTL_15_B				 (0xfffL<<19)3900#define BNX2_RPM_RC_CNTL_15_OFFSET_XI			 (0xffL<<0)3901#define BNX2_RPM_RC_CNTL_15_CLASS_XI			 (0x7L<<8)3902#define BNX2_RPM_RC_CNTL_15_PRIORITY_XI			 (1L<<11)3903#define BNX2_RPM_RC_CNTL_15_P4_XI			 (1L<<12)3904#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI			 (0x7L<<13)3905#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI		 (0L<<13)3906#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI		 (1L<<13)3907#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI		 (2L<<13)3908#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI		 (3L<<13)3909#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI		 (4L<<13)3910#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI		 (5L<<13)3911#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI		 (6L<<13)3912#define BNX2_RPM_RC_CNTL_15_COMP_XI			 (0x3L<<16)3913#define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI		 (0L<<16)3914#define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI		 (1L<<16)3915#define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI		 (2L<<16)3916#define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI		 (3L<<16)3917#define BNX2_RPM_RC_CNTL_15_MAP_XI			 (1L<<18)3918#define BNX2_RPM_RC_CNTL_15_SBIT_XI			 (1L<<19)3919#define BNX2_RPM_RC_CNTL_15_CMDSEL_XI			 (0x1fL<<20)3920#define BNX2_RPM_RC_CNTL_15_DISCARD_XI			 (1L<<25)3921#define BNX2_RPM_RC_CNTL_15_MASK_XI			 (1L<<26)3922#define BNX2_RPM_RC_CNTL_15_P1_XI			 (1L<<27)3923#define BNX2_RPM_RC_CNTL_15_P2_XI			 (1L<<28)3924#define BNX2_RPM_RC_CNTL_15_P3_XI			 (1L<<29)3925#define BNX2_RPM_RC_CNTL_15_NBIT_XI			 (1L<<30)3926 3927#define BNX2_RPM_RC_VALUE_MASK_15			0x0000197c3928#define BNX2_RPM_RC_VALUE_MASK_15_VALUE			 (0xffffL<<0)3929#define BNX2_RPM_RC_VALUE_MASK_15_MASK			 (0xffffL<<16)3930 3931#define BNX2_RPM_RC_CONFIG				0x000019803932#define BNX2_RPM_RC_CONFIG_RULE_ENABLE			 (0xffffL<<0)3933#define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI		 (0xfffffL<<0)3934#define BNX2_RPM_RC_CONFIG_DEF_CLASS			 (0x7L<<24)3935#define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE		 (1L<<31)3936 3937#define BNX2_RPM_DEBUG0					0x000019843938#define BNX2_RPM_DEBUG0_FM_BCNT				 (0xffffL<<0)3939#define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD			 (1L<<16)3940#define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD			 (1L<<17)3941#define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD			 (1L<<18)3942#define BNX2_RPM_DEBUG0_T_IP_OFST_VLD			 (1L<<19)3943#define BNX2_RPM_DEBUG0_IP_MORE_FRGMT			 (1L<<20)3944#define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR		 (1L<<21)3945#define BNX2_RPM_DEBUG0_LLC_SNAP			 (1L<<22)3946#define BNX2_RPM_DEBUG0_FM_STARTED			 (1L<<23)3947#define BNX2_RPM_DEBUG0_DONE				 (1L<<24)3948#define BNX2_RPM_DEBUG0_WAIT_4_DONE			 (1L<<25)3949#define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM			 (1L<<26)3950#define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM		 (1L<<27)3951#define BNX2_RPM_DEBUG0_IGNORE_VLAN			 (1L<<28)3952#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE			 (1L<<31)3953 3954#define BNX2_RPM_DEBUG1					0x000019883955#define BNX2_RPM_DEBUG1_FSM_CUR_ST			 (0xffffL<<0)3956#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE			 (0L<<0)3957#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL		 (1L<<0)3958#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC	 (2L<<0)3959#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP		 (4L<<0)3960#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP		 (8L<<0)3961#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START		 (16L<<0)3962#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP			 (32L<<0)3963#define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP			 (64L<<0)3964#define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP			 (128L<<0)3965#define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH			 (256L<<0)3966#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP			 (512L<<0)3967#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD		 (1024L<<0)3968#define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA			 (2048L<<0)3969#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY		 (0x2000L<<0)3970#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT		 (0x4000L<<0)3971#define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT		 (0x8000L<<0)3972#define BNX2_RPM_DEBUG1_HDR_BCNT			 (0x7ffL<<16)3973#define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D			 (1L<<28)3974#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2			 (1L<<29)3975#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1			 (1L<<30)3976#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD			 (1L<<31)3977 3978#define BNX2_RPM_DEBUG2					0x0000198c3979#define BNX2_RPM_DEBUG2_CMD_HIT_VEC			 (0xffffL<<0)3980#define BNX2_RPM_DEBUG2_IP_BCNT				 (0xffL<<16)3981#define BNX2_RPM_DEBUG2_THIS_CMD_M4			 (1L<<24)3982#define BNX2_RPM_DEBUG2_THIS_CMD_M3			 (1L<<25)3983#define BNX2_RPM_DEBUG2_THIS_CMD_M2			 (1L<<26)3984#define BNX2_RPM_DEBUG2_THIS_CMD_M1			 (1L<<27)3985#define BNX2_RPM_DEBUG2_IPIPE_EMPTY			 (1L<<28)3986#define BNX2_RPM_DEBUG2_FM_DISCARD			 (1L<<29)3987#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2		 (1L<<30)3988#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1		 (1L<<31)3989 3990#define BNX2_RPM_DEBUG3					0x000019903991#define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR			 (0x1ffL<<0)3992#define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT		 (1L<<9)3993#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT		 (1L<<10)3994#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT		 (1L<<11)3995#define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ		 (1L<<12)3996#define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ		 (1L<<13)3997#define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL		 (1L<<14)3998#define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP		 (1L<<15)3999#define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT		 (0xfL<<16)4000#define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL		 (1L<<21)4001#define BNX2_RPM_DEBUG3_DROP_NXT_VLD			 (1L<<22)4002#define BNX2_RPM_DEBUG3_DROP_NXT			 (1L<<23)4003#define BNX2_RPM_DEBUG3_FTQ_FSM				 (0x3L<<24)4004#define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE			 (0x0L<<24)4005#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK		 (0x1L<<24)4006#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE		 (0x2L<<24)4007#define BNX2_RPM_DEBUG3_MBWRITE_FSM			 (0x3L<<26)4008#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF		 (0x0L<<26)4009#define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF		 (0x1L<<26)4010#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA		 (0x2L<<26)4011#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA		 (0x3L<<26)4012#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF		 (0x4L<<26)4013#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK		 (0x5L<<26)4014#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD	 (0x6L<<26)4015#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE		 (0x7L<<26)4016#define BNX2_RPM_DEBUG3_MBFREE_FSM			 (1L<<29)4017#define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE			 (0L<<29)4018#define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK		 (1L<<29)4019#define BNX2_RPM_DEBUG3_MBALLOC_FSM			 (1L<<30)4020#define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF		 (0x0L<<30)4021#define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF		 (0x1L<<30)4022#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR			 (1L<<31)4023 4024#define BNX2_RPM_DEBUG4					0x000019944025#define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER		 (0x1ffffffL<<0)4026#define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE			 (0x7L<<25)4027#define BNX2_RPM_DEBUG4_MBWRITE_FSM			 (0x7L<<28)4028#define BNX2_RPM_DEBUG4_DFIFO_EMPTY			 (1L<<31)4029 4030#define BNX2_RPM_DEBUG5					0x000019984031#define BNX2_RPM_DEBUG5_RDROP_WPTR			 (0x1fL<<0)4032#define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR			 (0x1fL<<5)4033#define BNX2_RPM_DEBUG5_RDROP_MC_RPTR			 (0x1fL<<10)4034#define BNX2_RPM_DEBUG5_RDROP_RC_RPTR			 (0x1fL<<15)4035#define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY		 (1L<<20)4036#define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY			 (1L<<21)4037#define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR	 (1L<<22)4038#define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT		 (1L<<23)4039#define BNX2_RPM_DEBUG5_HOLDREG_DISCARD			 (1L<<24)4040#define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL		 (1L<<25)4041#define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY		 (1L<<26)4042#define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY		 (1L<<27)4043#define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY		 (1L<<28)4044#define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY		 (1L<<29)4045#define BNX2_RPM_DEBUG5_HOLDREG_FULL_T			 (1L<<30)4046#define BNX2_RPM_DEBUG5_HOLDREG_RD			 (1L<<31)4047 4048#define BNX2_RPM_DEBUG6					0x0000199c4049#define BNX2_RPM_DEBUG6_ACPI_VEC			 (0xffffL<<0)4050#define BNX2_RPM_DEBUG6_VEC				 (0xffffL<<16)4051 4052#define BNX2_RPM_DEBUG7					0x000019a04053#define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC		 (0xffffffffL<<0)4054 4055#define BNX2_RPM_DEBUG8					0x000019a44056#define BNX2_RPM_DEBUG8_PS_ACPI_FSM			 (0xfL<<0)4057#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE		 (0L<<0)4058#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR		 (1L<<0)4059#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR		 (2L<<0)4060#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR		 (3L<<0)4061#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF	 (4L<<0)4062#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA		 (5L<<0)4063#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR		 (6L<<0)4064#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR		 (7L<<0)4065#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR		 (8L<<0)4066#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR		 (9L<<0)4067#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF		 (10L<<0)4068#define BNX2_RPM_DEBUG8_COMPARE_AT_W0			 (1L<<4)4069#define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA		 (1L<<5)4070#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT		 (1L<<6)4071#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3		 (1L<<7)4072#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2		 (1L<<8)4073#define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES		 (1L<<9)4074#define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES		 (1L<<10)4075#define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES		 (1L<<11)4076#define BNX2_RPM_DEBUG8_EOF_DET				 (1L<<12)4077#define BNX2_RPM_DEBUG8_SOF_DET				 (1L<<13)4078#define BNX2_RPM_DEBUG8_WAIT_4_SOF			 (1L<<14)4079#define BNX2_RPM_DEBUG8_ALL_DONE			 (1L<<15)4080#define BNX2_RPM_DEBUG8_THBUF_ADDR			 (0x7fL<<16)4081#define BNX2_RPM_DEBUG8_BYTE_CTR			 (0xffL<<24)4082 4083#define BNX2_RPM_DEBUG9					0x000019a84084#define BNX2_RPM_DEBUG9_OUTFIFO_COUNT			 (0x7L<<0)4085#define BNX2_RPM_DEBUG9_RDE_ACPI_RDY			 (1L<<3)4086#define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT			 (0x7L<<4)4087#define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED	 (1L<<28)4088#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED		 (1L<<29)4089#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT			 (1L<<30)4090#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN			 (1L<<31)4091#define BNX2_RPM_DEBUG9_BEMEM_R_XI			 (0x1fL<<0)4092#define BNX2_RPM_DEBUG9_EO_XI				 (1L<<5)4093#define BNX2_RPM_DEBUG9_AEOF_DE_XI			 (1L<<6)4094#define BNX2_RPM_DEBUG9_SO_XI				 (1L<<7)4095#define BNX2_RPM_DEBUG9_WD64_CT_XI			 (0x1fL<<8)4096#define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI			 (0x7L<<13)4097#define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI		 (0xfL<<16)4098#define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI		 (0x3ffL<<20)4099#define BNX2_RPM_DEBUG9_DATA_IN_VL_XI			 (1L<<30)4100#define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI		 (1L<<31)4101 4102#define BNX2_RPM_ACPI_DBG_BUF_W00			0x000019c04103#define BNX2_RPM_ACPI_DBG_BUF_W01			0x000019c44104#define BNX2_RPM_ACPI_DBG_BUF_W02			0x000019c84105#define BNX2_RPM_ACPI_DBG_BUF_W03			0x000019cc4106#define BNX2_RPM_ACPI_DBG_BUF_W10			0x000019d04107#define BNX2_RPM_ACPI_DBG_BUF_W11			0x000019d44108#define BNX2_RPM_ACPI_DBG_BUF_W12			0x000019d84109#define BNX2_RPM_ACPI_DBG_BUF_W13			0x000019dc4110#define BNX2_RPM_ACPI_DBG_BUF_W20			0x000019e04111#define BNX2_RPM_ACPI_DBG_BUF_W21			0x000019e44112#define BNX2_RPM_ACPI_DBG_BUF_W22			0x000019e84113#define BNX2_RPM_ACPI_DBG_BUF_W23			0x000019ec4114#define BNX2_RPM_ACPI_DBG_BUF_W30			0x000019f04115#define BNX2_RPM_ACPI_DBG_BUF_W31			0x000019f44116#define BNX2_RPM_ACPI_DBG_BUF_W32			0x000019f84117#define BNX2_RPM_ACPI_DBG_BUF_W33			0x000019fc4118#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL			0x00001a004119#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS	 (0xffffL<<0)4120#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD		 (1L<<28)4121#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE		 (1L<<29)4122#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT		 (1L<<30)4123#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR		 (1L<<31)4124 4125#define BNX2_RPM_ACPI_PATTERN_CTRL			0x00001a044126#define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID		 (0xfL<<0)4127#define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR		 (1L<<30)4128#define BNX2_RPM_ACPI_PATTERN_CTRL_WR			 (1L<<31)4129 4130#define BNX2_RPM_ACPI_DATA				0x00001a084131#define BNX2_RPM_ACPI_DATA_PATTERN_BE			 (0xffffffffL<<0)4132 4133#define BNX2_RPM_ACPI_PATTERN_LEN0			0x00001a0c4134#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3		 (0xffL<<0)4135#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2		 (0xffL<<8)4136#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1		 (0xffL<<16)4137#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0		 (0xffL<<24)4138 4139#define BNX2_RPM_ACPI_PATTERN_LEN1			0x00001a104140#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7		 (0xffL<<0)4141#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6		 (0xffL<<8)4142#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5		 (0xffL<<16)4143#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4		 (0xffL<<24)4144 4145#define BNX2_RPM_ACPI_PATTERN_CRC0			0x00001a184146#define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0		 (0xffffffffL<<0)4147 4148#define BNX2_RPM_ACPI_PATTERN_CRC1			0x00001a1c4149#define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1		 (0xffffffffL<<0)4150 4151#define BNX2_RPM_ACPI_PATTERN_CRC2			0x00001a204152#define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2		 (0xffffffffL<<0)4153 4154#define BNX2_RPM_ACPI_PATTERN_CRC3			0x00001a244155#define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3		 (0xffffffffL<<0)4156 4157#define BNX2_RPM_ACPI_PATTERN_CRC4			0x00001a284158#define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4		 (0xffffffffL<<0)4159 4160#define BNX2_RPM_ACPI_PATTERN_CRC5			0x00001a2c4161#define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5		 (0xffffffffL<<0)4162 4163#define BNX2_RPM_ACPI_PATTERN_CRC6			0x00001a304164#define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6		 (0xffffffffL<<0)4165 4166#define BNX2_RPM_ACPI_PATTERN_CRC7			0x00001a344167#define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7		 (0xffffffffL<<0)4168 4169 4170/*4171 *  rlup_reg definition4172 *  offset: 0x20004173 */4174#define BNX2_RLUP_RSS_CONFIG				0x0000201c4175#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI		 (0x3L<<0)4176#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI	 (0L<<0)4177#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI	 (1L<<0)4178#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI	 (2L<<0)4179#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI	 (3L<<0)4180#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI		 (0x3L<<2)4181#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI	 (0L<<2)4182#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI	 (1L<<2)4183#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI	 (2L<<2)4184#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI	 (3L<<2)4185 4186#define BNX2_RLUP_RSS_COMMAND				0x000020484187#define BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR	 (0xfUL<<0)4188#define BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK		 (0xffUL<<4)4189#define BNX2_RLUP_RSS_COMMAND_WRITE			 (1UL<<12)4190#define BNX2_RLUP_RSS_COMMAND_READ			 (1UL<<13)4191#define BNX2_RLUP_RSS_COMMAND_HASH_MASK			 (0x7UL<<14)4192 4193#define BNX2_RLUP_RSS_DATA				0x0000204c4194 4195 4196/*4197 *  rbuf_reg definition4198 *  offset: 0x2000004199 */4200#define BNX2_RBUF_COMMAND				0x002000004201#define BNX2_RBUF_COMMAND_ENABLED			 (1L<<0)4202#define BNX2_RBUF_COMMAND_FREE_INIT			 (1L<<1)4203#define BNX2_RBUF_COMMAND_RAM_INIT			 (1L<<2)4204#define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL		 (1L<<3)4205#define BNX2_RBUF_COMMAND_OVER_FREE			 (1L<<4)4206#define BNX2_RBUF_COMMAND_ALLOC_REQ			 (1L<<5)4207#define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE		 (1L<<6)4208#define BNX2_RBUF_COMMAND_CU_ISOLATE_XI			 (1L<<5)4209#define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI		 (1L<<6)4210#define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI	 (1L<<7)4211 4212#define BNX2_RBUF_STATUS1				0x002000044213#define BNX2_RBUF_STATUS1_FREE_COUNT			 (0x3ffL<<0)4214 4215#define BNX2_RBUF_STATUS2				0x002000084216#define BNX2_RBUF_STATUS2_FREE_TAIL			 (0x1ffL<<0)4217#define BNX2_RBUF_STATUS2_FREE_HEAD			 (0x1ffL<<16)4218 4219#define BNX2_RBUF_CONFIG				0x0020000c4220#define BNX2_RBUF_CONFIG_XOFF_TRIP			 (0x3ffL<<0)4221#define BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu)		 \4222	((((mtu) - 1500) * 31 / 1000) + 54)4223#define BNX2_RBUF_CONFIG_XON_TRIP			 (0x3ffL<<16)4224#define BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu)		 \4225	((((mtu) - 1500) * 39 / 1000) + 66)4226#define BNX2_RBUF_CONFIG_VAL(mtu)			 \4227	(BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) |		 \4228	(BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) << 16))4229 4230#define BNX2_RBUF_FW_BUF_ALLOC				0x002000104231#define BNX2_RBUF_FW_BUF_ALLOC_VALUE			 (0x1ffL<<7)4232#define BNX2_RBUF_FW_BUF_ALLOC_TYPE			 (1L<<16)4233#define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ		 (1L<<31)4234 4235#define BNX2_RBUF_FW_BUF_FREE				0x002000144236#define BNX2_RBUF_FW_BUF_FREE_COUNT			 (0x7fL<<0)4237#define BNX2_RBUF_FW_BUF_FREE_TAIL			 (0x1ffL<<7)4238#define BNX2_RBUF_FW_BUF_FREE_HEAD			 (0x1ffL<<16)4239#define BNX2_RBUF_FW_BUF_FREE_TYPE			 (1L<<25)4240#define BNX2_RBUF_FW_BUF_FREE_FREE_REQ			 (1L<<31)4241 4242#define BNX2_RBUF_FW_BUF_SEL				0x002000184243#define BNX2_RBUF_FW_BUF_SEL_COUNT			 (0x7fL<<0)4244#define BNX2_RBUF_FW_BUF_SEL_TAIL			 (0x1ffL<<7)4245#define BNX2_RBUF_FW_BUF_SEL_HEAD			 (0x1ffL<<16)4246#define BNX2_RBUF_FW_BUF_SEL_SEL_REQ			 (1L<<31)4247 4248#define BNX2_RBUF_CONFIG2				0x0020001c4249#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP			 (0x3ffL<<0)4250#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu)	 \4251	((((mtu) - 1500) * 4 / 1000) + 5)4252#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP			 (0x3ffL<<16)4253#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu)	 \4254	((((mtu) - 1500) * 2 / 100) + 30)4255#define BNX2_RBUF_CONFIG2_VAL(mtu)			 \4256	(BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) |	 \4257	(BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) << 16))4258 4259#define BNX2_RBUF_CONFIG3				0x002000204260#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP			 (0x3ffL<<0)4261#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu)		 \4262	((((mtu) - 1500) * 12 / 1000) + 18)4263#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP			 (0x3ffL<<16)4264#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu)		 \4265	((((mtu) - 1500) * 2 / 100) + 30)4266#define BNX2_RBUF_CONFIG3_VAL(mtu)			 \4267	(BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) |	 \4268	(BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) << 16))4269 4270#define BNX2_RBUF_PKT_DATA				0x002080004271#define BNX2_RBUF_CLIST_DATA				0x002100004272#define BNX2_RBUF_BUF_DATA				0x002200004273 4274 4275/*4276 *  rv2p_reg definition4277 *  offset: 0x28004278 */4279#define BNX2_RV2P_COMMAND				0x000028004280#define BNX2_RV2P_COMMAND_ENABLED			 (1L<<0)4281#define BNX2_RV2P_COMMAND_PROC1_INTRPT			 (1L<<1)4282#define BNX2_RV2P_COMMAND_PROC2_INTRPT			 (1L<<2)4283#define BNX2_RV2P_COMMAND_ABORT0			 (1L<<4)4284#define BNX2_RV2P_COMMAND_ABORT1			 (1L<<5)4285#define BNX2_RV2P_COMMAND_ABORT2			 (1L<<6)4286#define BNX2_RV2P_COMMAND_ABORT3			 (1L<<7)4287#define BNX2_RV2P_COMMAND_ABORT4			 (1L<<8)4288#define BNX2_RV2P_COMMAND_ABORT5			 (1L<<9)4289#define BNX2_RV2P_COMMAND_PROC1_RESET			 (1L<<16)4290#define BNX2_RV2P_COMMAND_PROC2_RESET			 (1L<<17)4291#define BNX2_RV2P_COMMAND_CTXIF_RESET			 (1L<<18)4292 4293#define BNX2_RV2P_STATUS				0x000028044294#define BNX2_RV2P_STATUS_ALWAYS_0			 (1L<<0)4295#define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT		 (1L<<8)4296#define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT		 (1L<<9)4297#define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT		 (1L<<10)4298#define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT		 (1L<<11)4299#define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT		 (1L<<12)4300#define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT		 (1L<<13)4301 4302#define BNX2_RV2P_CONFIG				0x000028084303#define BNX2_RV2P_CONFIG_STALL_PROC1			 (1L<<0)4304#define BNX2_RV2P_CONFIG_STALL_PROC2			 (1L<<1)4305#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0		 (1L<<8)4306#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1		 (1L<<9)4307#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2		 (1L<<10)4308#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3		 (1L<<11)4309#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4		 (1L<<12)4310#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5		 (1L<<13)4311#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0		 (1L<<16)4312#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1		 (1L<<17)4313#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2		 (1L<<18)4314#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3		 (1L<<19)4315#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4		 (1L<<20)4316#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5		 (1L<<21)4317#define BNX2_RV2P_CONFIG_PAGE_SIZE			 (0xfL<<24)4318#define BNX2_RV2P_CONFIG_PAGE_SIZE_256			 (0L<<24)4319#define BNX2_RV2P_CONFIG_PAGE_SIZE_512			 (1L<<24)4320#define BNX2_RV2P_CONFIG_PAGE_SIZE_1K			 (2L<<24)4321#define BNX2_RV2P_CONFIG_PAGE_SIZE_2K			 (3L<<24)4322#define BNX2_RV2P_CONFIG_PAGE_SIZE_4K			 (4L<<24)4323#define BNX2_RV2P_CONFIG_PAGE_SIZE_8K			 (5L<<24)4324#define BNX2_RV2P_CONFIG_PAGE_SIZE_16K			 (6L<<24)4325#define BNX2_RV2P_CONFIG_PAGE_SIZE_32K			 (7L<<24)4326#define BNX2_RV2P_CONFIG_PAGE_SIZE_64K			 (8L<<24)4327#define BNX2_RV2P_CONFIG_PAGE_SIZE_128K			 (9L<<24)4328#define BNX2_RV2P_CONFIG_PAGE_SIZE_256K			 (10L<<24)4329#define BNX2_RV2P_CONFIG_PAGE_SIZE_512K			 (11L<<24)4330#define BNX2_RV2P_CONFIG_PAGE_SIZE_1M			 (12L<<24)4331 4332#define BNX2_RV2P_GEN_BFR_ADDR_0			0x000028104333#define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE			 (0xffffL<<16)4334 4335#define BNX2_RV2P_GEN_BFR_ADDR_1			0x000028144336#define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE			 (0xffffL<<16)4337 4338#define BNX2_RV2P_GEN_BFR_ADDR_2			0x000028184339#define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE			 (0xffffL<<16)4340 4341#define BNX2_RV2P_GEN_BFR_ADDR_3			0x0000281c4342#define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE			 (0xffffL<<16)4343 4344#define BNX2_RV2P_INSTR_HIGH				0x000028304345#define BNX2_RV2P_INSTR_HIGH_HIGH			 (0x1fL<<0)4346 4347#define BNX2_RV2P_INSTR_LOW				0x000028344348#define BNX2_RV2P_INSTR_LOW_LOW				 (0xffffffffL<<0)4349 4350#define BNX2_RV2P_PROC1_ADDR_CMD			0x000028384351#define BNX2_RV2P_PROC1_ADDR_CMD_ADD			 (0x3ffL<<0)4352#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR			 (1L<<31)4353 4354#define BNX2_RV2P_PROC2_ADDR_CMD			0x0000283c4355#define BNX2_RV2P_PROC2_ADDR_CMD_ADD			 (0x3ffL<<0)4356#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR			 (1L<<31)4357 4358#define BNX2_RV2P_PROC1_GRC_DEBUG			0x000028404359#define BNX2_RV2P_PROC2_GRC_DEBUG			0x000028444360#define BNX2_RV2P_GRC_PROC_DEBUG			0x000028484361#define BNX2_RV2P_DEBUG_VECT_PEEK			0x0000284c4362#define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)4363#define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)4364#define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)4365#define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)4366#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)4367#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)4368 4369#define BNX2_RV2P_MPFE_PFE_CTL				0x00002afc4370#define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT		 (1L<<0)4371#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE			 (0xfL<<4)4372#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0		 (0L<<4)4373#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1		 (1L<<4)4374#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2		 (2L<<4)4375#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3		 (3L<<4)4376#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4		 (4L<<4)4377#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5		 (5L<<4)4378#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6		 (6L<<4)4379#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7		 (7L<<4)4380#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8		 (8L<<4)4381#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9		 (9L<<4)4382#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10		 (10L<<4)4383#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11		 (11L<<4)4384#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12		 (12L<<4)4385#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13		 (13L<<4)4386#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14		 (14L<<4)4387#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15		 (15L<<4)4388#define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT		 (0xfL<<12)4389#define BNX2_RV2P_MPFE_PFE_CTL_OFFSET			 (0x1ffL<<16)4390 4391#define BNX2_RV2P_RV2PPQ				0x00002b404392#define BNX2_RV2P_PFTQ_CMD				0x00002b784393#define BNX2_RV2P_PFTQ_CMD_OFFSET			 (0x3ffL<<0)4394#define BNX2_RV2P_PFTQ_CMD_WR_TOP			 (1L<<10)4395#define BNX2_RV2P_PFTQ_CMD_WR_TOP_0			 (0L<<10)4396#define BNX2_RV2P_PFTQ_CMD_WR_TOP_1			 (1L<<10)4397#define BNX2_RV2P_PFTQ_CMD_SFT_RESET			 (1L<<25)4398#define BNX2_RV2P_PFTQ_CMD_RD_DATA			 (1L<<26)4399#define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN			 (1L<<27)4400#define BNX2_RV2P_PFTQ_CMD_ADD_DATA			 (1L<<28)4401#define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR		 (1L<<29)4402#define BNX2_RV2P_PFTQ_CMD_POP				 (1L<<30)4403#define BNX2_RV2P_PFTQ_CMD_BUSY				 (1L<<31)4404 4405#define BNX2_RV2P_PFTQ_CTL				0x00002b7c4406#define BNX2_RV2P_PFTQ_CTL_INTERVENE			 (1L<<0)4407#define BNX2_RV2P_PFTQ_CTL_OVERFLOW			 (1L<<1)4408#define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE		 (1L<<2)4409#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)4410#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)4411 4412#define BNX2_RV2P_RV2PTQ				0x00002b804413#define BNX2_RV2P_TFTQ_CMD				0x00002bb84414#define BNX2_RV2P_TFTQ_CMD_OFFSET			 (0x3ffL<<0)4415#define BNX2_RV2P_TFTQ_CMD_WR_TOP			 (1L<<10)4416#define BNX2_RV2P_TFTQ_CMD_WR_TOP_0			 (0L<<10)4417#define BNX2_RV2P_TFTQ_CMD_WR_TOP_1			 (1L<<10)4418#define BNX2_RV2P_TFTQ_CMD_SFT_RESET			 (1L<<25)4419#define BNX2_RV2P_TFTQ_CMD_RD_DATA			 (1L<<26)4420#define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN			 (1L<<27)4421#define BNX2_RV2P_TFTQ_CMD_ADD_DATA			 (1L<<28)4422#define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR		 (1L<<29)4423#define BNX2_RV2P_TFTQ_CMD_POP				 (1L<<30)4424#define BNX2_RV2P_TFTQ_CMD_BUSY				 (1L<<31)4425 4426#define BNX2_RV2P_TFTQ_CTL				0x00002bbc4427#define BNX2_RV2P_TFTQ_CTL_INTERVENE			 (1L<<0)4428#define BNX2_RV2P_TFTQ_CTL_OVERFLOW			 (1L<<1)4429#define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE		 (1L<<2)4430#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)4431#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)4432 4433#define BNX2_RV2P_RV2PMQ				0x00002bc04434#define BNX2_RV2P_MFTQ_CMD				0x00002bf84435#define BNX2_RV2P_MFTQ_CMD_OFFSET			 (0x3ffL<<0)4436#define BNX2_RV2P_MFTQ_CMD_WR_TOP			 (1L<<10)4437#define BNX2_RV2P_MFTQ_CMD_WR_TOP_0			 (0L<<10)4438#define BNX2_RV2P_MFTQ_CMD_WR_TOP_1			 (1L<<10)4439#define BNX2_RV2P_MFTQ_CMD_SFT_RESET			 (1L<<25)4440#define BNX2_RV2P_MFTQ_CMD_RD_DATA			 (1L<<26)4441#define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN			 (1L<<27)4442#define BNX2_RV2P_MFTQ_CMD_ADD_DATA			 (1L<<28)4443#define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR		 (1L<<29)4444#define BNX2_RV2P_MFTQ_CMD_POP				 (1L<<30)4445#define BNX2_RV2P_MFTQ_CMD_BUSY				 (1L<<31)4446 4447#define BNX2_RV2P_MFTQ_CTL				0x00002bfc4448#define BNX2_RV2P_MFTQ_CTL_INTERVENE			 (1L<<0)4449#define BNX2_RV2P_MFTQ_CTL_OVERFLOW			 (1L<<1)4450#define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE		 (1L<<2)4451#define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)4452#define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)4453 4454 4455 4456/*4457 *  mq_reg definition4458 *  offset: 0x3c004459 */4460#define BNX2_MQ_COMMAND					0x00003c004461#define BNX2_MQ_COMMAND_ENABLED				 (1L<<0)4462#define BNX2_MQ_COMMAND_INIT				 (1L<<1)4463#define BNX2_MQ_COMMAND_OVERFLOW			 (1L<<4)4464#define BNX2_MQ_COMMAND_WR_ERROR			 (1L<<5)4465#define BNX2_MQ_COMMAND_RD_ERROR			 (1L<<6)4466#define BNX2_MQ_COMMAND_IDB_CFG_ERROR			 (1L<<7)4467#define BNX2_MQ_COMMAND_IDB_OVERFLOW			 (1L<<10)4468#define BNX2_MQ_COMMAND_NO_BIN_ERROR			 (1L<<11)4469#define BNX2_MQ_COMMAND_NO_MAP_ERROR			 (1L<<12)4470 4471#define BNX2_MQ_STATUS					0x00003c044472#define BNX2_MQ_STATUS_CTX_ACCESS_STAT			 (1L<<16)4473#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT		 (1L<<17)4474#define BNX2_MQ_STATUS_PCI_STALL_STAT			 (1L<<18)4475#define BNX2_MQ_STATUS_IDB_OFLOW_STAT			 (1L<<19)4476 4477#define BNX2_MQ_CONFIG					0x00003c084478#define BNX2_MQ_CONFIG_TX_HIGH_PRI			 (1L<<0)4479#define BNX2_MQ_CONFIG_HALT_DIS				 (1L<<1)4480#define BNX2_MQ_CONFIG_BIN_MQ_MODE			 (1L<<2)4481#define BNX2_MQ_CONFIG_DIS_IDB_DROP			 (1L<<3)4482#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE			 (0x7L<<4)4483#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256		 (0L<<4)4484#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512		 (1L<<4)4485#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K		 (2L<<4)4486#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K		 (3L<<4)4487#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K		 (4L<<4)4488#define BNX2_MQ_CONFIG_MAX_DEPTH			 (0x7fL<<8)4489#define BNX2_MQ_CONFIG_CUR_DEPTH			 (0x7fL<<20)4490 4491#define BNX2_MQ_ENQUEUE1				0x00003c0c4492#define BNX2_MQ_ENQUEUE1_OFFSET				 (0x3fL<<2)4493#define BNX2_MQ_ENQUEUE1_CID				 (0x3fffL<<8)4494#define BNX2_MQ_ENQUEUE1_BYTE_MASK			 (0xfL<<24)4495#define BNX2_MQ_ENQUEUE1_KNL_MODE			 (1L<<28)4496 4497#define BNX2_MQ_ENQUEUE2				0x00003c104498#define BNX2_MQ_BAD_WR_ADDR				0x00003c144499#define BNX2_MQ_BAD_RD_ADDR				0x00003c184500#define BNX2_MQ_KNL_BYP_WIND_START			0x00003c1c4501#define BNX2_MQ_KNL_BYP_WIND_START_VALUE		 (0xfffffL<<12)4502 4503#define BNX2_MQ_KNL_WIND_END				0x00003c204504#define BNX2_MQ_KNL_WIND_END_VALUE			 (0xffffffL<<8)4505 4506#define BNX2_MQ_KNL_WRITE_MASK1				0x00003c244507#define BNX2_MQ_KNL_TX_MASK1				0x00003c284508#define BNX2_MQ_KNL_CMD_MASK1				0x00003c2c4509#define BNX2_MQ_KNL_COND_ENQUEUE_MASK1			0x00003c304510#define BNX2_MQ_KNL_RX_V2P_MASK1			0x00003c344511#define BNX2_MQ_KNL_WRITE_MASK2				0x00003c384512#define BNX2_MQ_KNL_TX_MASK2				0x00003c3c4513#define BNX2_MQ_KNL_CMD_MASK2				0x00003c404514#define BNX2_MQ_KNL_COND_ENQUEUE_MASK2			0x00003c444515#define BNX2_MQ_KNL_RX_V2P_MASK2			0x00003c484516#define BNX2_MQ_KNL_BYP_WRITE_MASK1			0x00003c4c4517#define BNX2_MQ_KNL_BYP_TX_MASK1			0x00003c504518#define BNX2_MQ_KNL_BYP_CMD_MASK1			0x00003c544519#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1		0x00003c584520#define BNX2_MQ_KNL_BYP_RX_V2P_MASK1			0x00003c5c4521#define BNX2_MQ_KNL_BYP_WRITE_MASK2			0x00003c604522#define BNX2_MQ_KNL_BYP_TX_MASK2			0x00003c644523#define BNX2_MQ_KNL_BYP_CMD_MASK2			0x00003c684524#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2		0x00003c6c4525#define BNX2_MQ_KNL_BYP_RX_V2P_MASK2			0x00003c704526#define BNX2_MQ_MEM_WR_ADDR				0x00003c744527#define BNX2_MQ_MEM_WR_ADDR_VALUE			 (0x3fL<<0)4528 4529#define BNX2_MQ_MEM_WR_DATA0				0x00003c784530#define BNX2_MQ_MEM_WR_DATA0_VALUE			 (0xffffffffL<<0)4531 4532#define BNX2_MQ_MEM_WR_DATA1				0x00003c7c4533#define BNX2_MQ_MEM_WR_DATA1_VALUE			 (0xffffffffL<<0)4534 4535#define BNX2_MQ_MEM_WR_DATA2				0x00003c804536#define BNX2_MQ_MEM_WR_DATA2_VALUE			 (0x3fffffffL<<0)4537#define BNX2_MQ_MEM_WR_DATA2_VALUE_XI			 (0x7fffffffL<<0)4538 4539#define BNX2_MQ_MEM_RD_ADDR				0x00003c844540#define BNX2_MQ_MEM_RD_ADDR_VALUE			 (0x3fL<<0)4541 4542#define BNX2_MQ_MEM_RD_DATA0				0x00003c884543#define BNX2_MQ_MEM_RD_DATA0_VALUE			 (0xffffffffL<<0)4544 4545#define BNX2_MQ_MEM_RD_DATA1				0x00003c8c4546#define BNX2_MQ_MEM_RD_DATA1_VALUE			 (0xffffffffL<<0)4547 4548#define BNX2_MQ_MEM_RD_DATA2				0x00003c904549#define BNX2_MQ_MEM_RD_DATA2_VALUE			 (0x3fffffffL<<0)4550#define BNX2_MQ_MEM_RD_DATA2_VALUE_XI			 (0x7fffffffL<<0)4551 4552#define BNX2_MQ_MAP_L2_3				0x00003d2c4553#define BNX2_MQ_MAP_L2_3_MQ_OFFSET			 (0xffL<<0)4554#define BNX2_MQ_MAP_L2_3_SZ				 (0x3L<<8)4555#define BNX2_MQ_MAP_L2_3_CTX_OFFSET			 (0x2ffL<<10)4556#define BNX2_MQ_MAP_L2_3_BIN_OFFSET			 (0x7L<<23)4557#define BNX2_MQ_MAP_L2_3_ARM				 (0x3L<<26)4558#define BNX2_MQ_MAP_L2_3_ENA				 (0x1L<<31)4559#define BNX2_MQ_MAP_L2_3_DEFAULT			 0x820046464560 4561#define BNX2_MQ_MAP_L2_5				0x00003d344562#define BNX2_MQ_MAP_L2_5_ARM				 (0x3L<<26)4563 4564/*4565 *  tsch_reg definition4566 *  offset: 0x4c004567 */4568#define BNX2_TSCH_TSS_CFG				0x00004c1c4569#define BNX2_TSCH_TSS_CFG_TSS_START_CID			 (0x7ffL<<8)4570#define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON		 (0xfL<<24)4571 4572 4573 4574/*4575 *  tbdr_reg definition4576 *  offset: 0x50004577 */4578#define BNX2_TBDR_COMMAND				0x000050004579#define BNX2_TBDR_COMMAND_ENABLE			 (1L<<0)4580#define BNX2_TBDR_COMMAND_SOFT_RST			 (1L<<1)4581#define BNX2_TBDR_COMMAND_MSTR_ABORT			 (1L<<4)4582 4583#define BNX2_TBDR_STATUS				0x000050044584#define BNX2_TBDR_STATUS_DMA_WAIT			 (1L<<0)4585#define BNX2_TBDR_STATUS_FTQ_WAIT			 (1L<<1)4586#define BNX2_TBDR_STATUS_FIFO_OVERFLOW			 (1L<<2)4587#define BNX2_TBDR_STATUS_FIFO_UNDERFLOW			 (1L<<3)4588#define BNX2_TBDR_STATUS_SEARCHMISS_ERROR		 (1L<<4)4589#define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT			 (1L<<5)4590#define BNX2_TBDR_STATUS_BURST_CNT			 (1L<<6)4591 4592#define BNX2_TBDR_CONFIG				0x000050084593#define BNX2_TBDR_CONFIG_MAX_BDS			 (0xffL<<0)4594#define BNX2_TBDR_CONFIG_SWAP_MODE			 (1L<<8)4595#define BNX2_TBDR_CONFIG_PRIORITY			 (1L<<9)4596#define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS		 (1L<<10)4597#define BNX2_TBDR_CONFIG_PAGE_SIZE			 (0xfL<<24)4598#define BNX2_TBDR_CONFIG_PAGE_SIZE_256			 (0L<<24)4599#define BNX2_TBDR_CONFIG_PAGE_SIZE_512			 (1L<<24)4600#define BNX2_TBDR_CONFIG_PAGE_SIZE_1K			 (2L<<24)4601#define BNX2_TBDR_CONFIG_PAGE_SIZE_2K			 (3L<<24)4602#define BNX2_TBDR_CONFIG_PAGE_SIZE_4K			 (4L<<24)4603#define BNX2_TBDR_CONFIG_PAGE_SIZE_8K			 (5L<<24)4604#define BNX2_TBDR_CONFIG_PAGE_SIZE_16K			 (6L<<24)4605#define BNX2_TBDR_CONFIG_PAGE_SIZE_32K			 (7L<<24)4606#define BNX2_TBDR_CONFIG_PAGE_SIZE_64K			 (8L<<24)4607#define BNX2_TBDR_CONFIG_PAGE_SIZE_128K			 (9L<<24)4608#define BNX2_TBDR_CONFIG_PAGE_SIZE_256K			 (10L<<24)4609#define BNX2_TBDR_CONFIG_PAGE_SIZE_512K			 (11L<<24)4610#define BNX2_TBDR_CONFIG_PAGE_SIZE_1M			 (12L<<24)4611 4612#define BNX2_TBDR_DEBUG_VECT_PEEK			0x0000500c4613#define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)4614#define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)4615#define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)4616#define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)4617#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)4618#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)4619 4620#define BNX2_TBDR_CKSUM_ERROR_STATUS			0x000050104621#define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED		 (0xffffL<<0)4622#define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED		 (0xffffL<<16)4623 4624#define BNX2_TBDR_TBDRQ					0x000053c04625#define BNX2_TBDR_FTQ_CMD				0x000053f84626#define BNX2_TBDR_FTQ_CMD_OFFSET			 (0x3ffL<<0)4627#define BNX2_TBDR_FTQ_CMD_WR_TOP			 (1L<<10)4628#define BNX2_TBDR_FTQ_CMD_WR_TOP_0			 (0L<<10)4629#define BNX2_TBDR_FTQ_CMD_WR_TOP_1			 (1L<<10)4630#define BNX2_TBDR_FTQ_CMD_SFT_RESET			 (1L<<25)4631#define BNX2_TBDR_FTQ_CMD_RD_DATA			 (1L<<26)4632#define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN			 (1L<<27)4633#define BNX2_TBDR_FTQ_CMD_ADD_DATA			 (1L<<28)4634#define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR			 (1L<<29)4635#define BNX2_TBDR_FTQ_CMD_POP				 (1L<<30)4636#define BNX2_TBDR_FTQ_CMD_BUSY				 (1L<<31)4637 4638#define BNX2_TBDR_FTQ_CTL				0x000053fc4639#define BNX2_TBDR_FTQ_CTL_INTERVENE			 (1L<<0)4640#define BNX2_TBDR_FTQ_CTL_OVERFLOW			 (1L<<1)4641#define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)4642#define BNX2_TBDR_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)4643#define BNX2_TBDR_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)4644 4645 4646/*4647 *  tbdc definition4648 *  offset: 0x54004649 */4650#define BNX2_TBDC_COMMAND                               0x54004651#define BNX2_TBDC_COMMAND_CMD_ENABLED                    (1UL<<0)4652#define BNX2_TBDC_COMMAND_CMD_FLUSH                      (1UL<<1)4653#define BNX2_TBDC_COMMAND_CMD_SOFT_RST                   (1UL<<2)4654#define BNX2_TBDC_COMMAND_CMD_REG_ARB                    (1UL<<3)4655#define BNX2_TBDC_COMMAND_WRCHK_RANGE_ERROR              (1UL<<4)4656#define BNX2_TBDC_COMMAND_WRCHK_ALL_ONES_ERROR           (1UL<<5)4657#define BNX2_TBDC_COMMAND_WRCHK_ALL_ZEROS_ERROR          (1UL<<6)4658#define BNX2_TBDC_COMMAND_WRCHK_ANY_ONES_ERROR           (1UL<<7)4659#define BNX2_TBDC_COMMAND_WRCHK_ANY_ZEROS_ERROR          (1UL<<8)4660 4661#define BNX2_TBDC_STATUS				0x54044662#define BNX2_TBDC_STATUS_FREE_CNT                        (0x3fUL<<0)4663 4664#define BNX2_TBDC_BD_ADDR                               0x54244665 4666#define BNX2_TBDC_BIDX                                  0x542c4667#define BNX2_TBDC_BDIDX_BDIDX                            (0xffffUL<<0)4668#define BNX2_TBDC_BDIDX_CMD                              (0xffUL<<24)4669 4670#define BNX2_TBDC_CID                                   0x54304671 4672#define BNX2_TBDC_CAM_OPCODE                            0x54344673#define BNX2_TBDC_CAM_OPCODE_OPCODE                      (0x7UL<<0)4674#define BNX2_TBDC_CAM_OPCODE_OPCODE_SEARCH               (0UL<<0)4675#define BNX2_TBDC_CAM_OPCODE_OPCODE_CACHE_WRITE          (1UL<<0)4676#define BNX2_TBDC_CAM_OPCODE_OPCODE_INVALIDATE           (2UL<<0)4677#define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_WRITE            (4UL<<0)4678#define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ             (5UL<<0)4679#define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_WRITE            (6UL<<0)4680#define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_READ             (7UL<<0)4681#define BNX2_TBDC_CAM_OPCODE_SMASK_BDIDX                 (1UL<<4)4682#define BNX2_TBDC_CAM_OPCODE_SMASK_CID                   (1UL<<5)4683#define BNX2_TBDC_CAM_OPCODE_SMASK_CMD                   (1UL<<6)4684#define BNX2_TBDC_CAM_OPCODE_WMT_FAILED                  (1UL<<7)4685#define BNX2_TBDC_CAM_OPCODE_CAM_VALIDS                  (0xffUL<<8)4686 4687 4688/*4689 *  tdma_reg definition4690 *  offset: 0x5c004691 */4692#define BNX2_TDMA_COMMAND				0x00005c004693#define BNX2_TDMA_COMMAND_ENABLED			 (1L<<0)4694#define BNX2_TDMA_COMMAND_MASTER_ABORT			 (1L<<4)4695#define BNX2_TDMA_COMMAND_CS16_ERR			 (1L<<5)4696#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT		 (1L<<7)4697#define BNX2_TDMA_COMMAND_MASK_CS1			 (1L<<20)4698#define BNX2_TDMA_COMMAND_MASK_CS2			 (1L<<21)4699#define BNX2_TDMA_COMMAND_MASK_CS3			 (1L<<22)4700#define BNX2_TDMA_COMMAND_MASK_CS4			 (1L<<23)4701#define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR		 (1L<<24)4702#define BNX2_TDMA_COMMAND_OFIFO_CLR			 (1L<<30)4703#define BNX2_TDMA_COMMAND_IFIFO_CLR			 (1L<<31)4704 4705#define BNX2_TDMA_STATUS				0x00005c044706#define BNX2_TDMA_STATUS_DMA_WAIT			 (1L<<0)4707#define BNX2_TDMA_STATUS_PAYLOAD_WAIT			 (1L<<1)4708#define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT			 (1L<<2)4709#define BNX2_TDMA_STATUS_LOCK_WAIT			 (1L<<3)4710#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT			 (1L<<16)4711#define BNX2_TDMA_STATUS_BURST_CNT			 (1L<<17)4712#define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH		 (0x3fL<<20)4713#define BNX2_TDMA_STATUS_OFIFO_OVERFLOW			 (1L<<30)4714#define BNX2_TDMA_STATUS_IFIFO_OVERFLOW			 (1L<<31)4715 4716#define BNX2_TDMA_CONFIG				0x00005c084717#define BNX2_TDMA_CONFIG_ONE_DMA			 (1L<<0)4718#define BNX2_TDMA_CONFIG_ONE_RECORD			 (1L<<1)4719#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN			 (0x3L<<2)4720#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0			 (0L<<2)4721#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1			 (1L<<2)4722#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2			 (2L<<2)4723#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3			 (3L<<2)4724#define BNX2_TDMA_CONFIG_LIMIT_SZ			 (0xfL<<4)4725#define BNX2_TDMA_CONFIG_LIMIT_SZ_64			 (0L<<4)4726#define BNX2_TDMA_CONFIG_LIMIT_SZ_128			 (0x4L<<4)4727#define BNX2_TDMA_CONFIG_LIMIT_SZ_256			 (0x6L<<4)4728#define BNX2_TDMA_CONFIG_LIMIT_SZ_512			 (0x8L<<4)4729#define BNX2_TDMA_CONFIG_LINE_SZ			 (0xfL<<8)4730#define BNX2_TDMA_CONFIG_LINE_SZ_64			 (0L<<8)4731#define BNX2_TDMA_CONFIG_LINE_SZ_128			 (4L<<8)4732#define BNX2_TDMA_CONFIG_LINE_SZ_256			 (6L<<8)4733#define BNX2_TDMA_CONFIG_LINE_SZ_512			 (8L<<8)4734#define BNX2_TDMA_CONFIG_ALIGN_ENA			 (1L<<15)4735#define BNX2_TDMA_CONFIG_CHK_L2_BD			 (1L<<16)4736#define BNX2_TDMA_CONFIG_CMPL_ENTRY			 (1L<<17)4737#define BNX2_TDMA_CONFIG_OFIFO_CMP			 (1L<<19)4738#define BNX2_TDMA_CONFIG_OFIFO_CMP_3			 (0L<<19)4739#define BNX2_TDMA_CONFIG_OFIFO_CMP_2			 (1L<<19)4740#define BNX2_TDMA_CONFIG_FIFO_CMP			 (0xfL<<20)4741#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI			 (0x7L<<20)4742#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI		 (0L<<20)4743#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI		 (1L<<20)4744#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI		 (2L<<20)4745#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI		 (3L<<20)4746#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI		 (4L<<20)4747#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI		 (5L<<20)4748#define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI			 (1L<<23)4749#define BNX2_TDMA_CONFIG_BYTES_OST_XI			 (0x7L<<24)4750#define BNX2_TDMA_CONFIG_BYTES_OST_512_XI		 (0L<<24)4751#define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI		 (1L<<24)4752#define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI		 (2L<<24)4753#define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI		 (3L<<24)4754#define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI		 (4L<<24)4755#define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI		 (5L<<24)4756#define BNX2_TDMA_CONFIG_HC_BYPASS_XI			 (1L<<27)4757#define BNX2_TDMA_CONFIG_LCL_MRRS_XI			 (0x7L<<28)4758#define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI		 (0L<<28)4759#define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI		 (1L<<28)4760#define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI		 (2L<<28)4761#define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI		 (3L<<28)4762#define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI		 (4L<<28)4763#define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI		 (5L<<28)4764#define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI			 (1L<<31)4765 4766#define BNX2_TDMA_PAYLOAD_PROD				0x00005c0c4767#define BNX2_TDMA_PAYLOAD_PROD_VALUE			 (0x1fffL<<3)4768 4769#define BNX2_TDMA_DBG_WATCHDOG				0x00005c104770#define BNX2_TDMA_DBG_TRIGGER				0x00005c144771#define BNX2_TDMA_DMAD_FSM				0x00005c804772#define BNX2_TDMA_DMAD_FSM_BD_INVLD			 (1L<<0)4773#define BNX2_TDMA_DMAD_FSM_PUSH				 (0xfL<<4)4774#define BNX2_TDMA_DMAD_FSM_ARB_TBDC			 (0x3L<<8)4775#define BNX2_TDMA_DMAD_FSM_ARB_CTX			 (1L<<12)4776#define BNX2_TDMA_DMAD_FSM_DR_INTF			 (1L<<16)4777#define BNX2_TDMA_DMAD_FSM_DMAD				 (0x7L<<20)4778#define BNX2_TDMA_DMAD_FSM_BD				 (0xfL<<24)4779 4780#define BNX2_TDMA_DMAD_STATUS				0x00005c844781#define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY		 (0x3L<<0)4782#define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY		 (0x3L<<4)4783#define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY		 (0x3L<<8)4784#define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM			 (0xfL<<12)4785 4786#define BNX2_TDMA_DR_INTF_FSM				0x00005c884787#define BNX2_TDMA_DR_INTF_FSM_L2_COMP			 (0x3L<<0)4788#define BNX2_TDMA_DR_INTF_FSM_TPATQ			 (0x7L<<4)4789#define BNX2_TDMA_DR_INTF_FSM_TPBUF			 (0x3L<<8)4790#define BNX2_TDMA_DR_INTF_FSM_DR_BUF			 (0x7L<<12)4791#define BNX2_TDMA_DR_INTF_FSM_DMAD			 (0x7L<<16)4792 4793#define BNX2_TDMA_DR_INTF_STATUS			0x00005c8c4794#define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE		 (0x7L<<0)4795#define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL		 (0x3L<<4)4796#define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR		 (0x7L<<8)4797#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR		 (0xfL<<12)4798#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT		 (0x7L<<16)4799 4800#define BNX2_TDMA_PUSH_FSM				0x00005c904801#define BNX2_TDMA_BD_IF_DEBUG				0x00005c944802#define BNX2_TDMA_DMAD_IF_DEBUG				0x00005c984803#define BNX2_TDMA_CTX_IF_DEBUG				0x00005c9c4804#define BNX2_TDMA_TPBUF_IF_DEBUG			0x00005ca04805#define BNX2_TDMA_DR_IF_DEBUG				0x00005ca44806#define BNX2_TDMA_TPATQ_IF_DEBUG			0x00005ca84807#define BNX2_TDMA_TDMA_ILOCK_CKSUM			0x00005cac4808#define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED		 (0xffffL<<0)4809#define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED		 (0xffffL<<16)4810 4811#define BNX2_TDMA_TDMA_PCIE_CKSUM			0x00005cb04812#define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED		 (0xffffL<<0)4813#define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED		 (0xffffL<<16)4814 4815#define BNX2_TDMA_TDMAQ					0x00005fc04816#define BNX2_TDMA_FTQ_CMD				0x00005ff84817#define BNX2_TDMA_FTQ_CMD_OFFSET			 (0x3ffL<<0)4818#define BNX2_TDMA_FTQ_CMD_WR_TOP			 (1L<<10)4819#define BNX2_TDMA_FTQ_CMD_WR_TOP_0			 (0L<<10)4820#define BNX2_TDMA_FTQ_CMD_WR_TOP_1			 (1L<<10)4821#define BNX2_TDMA_FTQ_CMD_SFT_RESET			 (1L<<25)4822#define BNX2_TDMA_FTQ_CMD_RD_DATA			 (1L<<26)4823#define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN			 (1L<<27)4824#define BNX2_TDMA_FTQ_CMD_ADD_DATA			 (1L<<28)4825#define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR			 (1L<<29)4826#define BNX2_TDMA_FTQ_CMD_POP				 (1L<<30)4827#define BNX2_TDMA_FTQ_CMD_BUSY				 (1L<<31)4828 4829#define BNX2_TDMA_FTQ_CTL				0x00005ffc4830#define BNX2_TDMA_FTQ_CTL_INTERVENE			 (1L<<0)4831#define BNX2_TDMA_FTQ_CTL_OVERFLOW			 (1L<<1)4832#define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)4833#define BNX2_TDMA_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)4834#define BNX2_TDMA_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)4835 4836 4837 4838/*4839 *  hc_reg definition4840 *  offset: 0x68004841 */4842#define BNX2_HC_COMMAND					0x000068004843#define BNX2_HC_COMMAND_ENABLE				 (1L<<0)4844#define BNX2_HC_COMMAND_SKIP_ABORT			 (1L<<4)4845#define BNX2_HC_COMMAND_COAL_NOW			 (1L<<16)4846#define BNX2_HC_COMMAND_COAL_NOW_WO_INT			 (1L<<17)4847#define BNX2_HC_COMMAND_STATS_NOW			 (1L<<18)4848#define BNX2_HC_COMMAND_FORCE_INT			 (0x3L<<19)4849#define BNX2_HC_COMMAND_FORCE_INT_NULL			 (0L<<19)4850#define BNX2_HC_COMMAND_FORCE_INT_HIGH			 (1L<<19)4851#define BNX2_HC_COMMAND_FORCE_INT_LOW			 (2L<<19)4852#define BNX2_HC_COMMAND_FORCE_INT_FREE			 (3L<<19)4853#define BNX2_HC_COMMAND_CLR_STAT_NOW			 (1L<<21)4854#define BNX2_HC_COMMAND_MAIN_PWR_INT			 (1L<<22)4855#define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT		 (1L<<27)4856 4857#define BNX2_HC_STATUS					0x000068044858#define BNX2_HC_STATUS_MASTER_ABORT			 (1L<<0)4859#define BNX2_HC_STATUS_PARITY_ERROR_STATE		 (1L<<1)4860#define BNX2_HC_STATUS_PCI_CLK_CNT_STAT			 (1L<<16)4861#define BNX2_HC_STATUS_CORE_CLK_CNT_STAT		 (1L<<17)4862#define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT		 (1L<<18)4863#define BNX2_HC_STATUS_NUM_INT_GEN_STAT			 (1L<<19)4864#define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT		 (1L<<20)4865#define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT	 (1L<<23)4866#define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT	 (1L<<24)4867#define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT	 (1L<<25)4868 4869#define BNX2_HC_CONFIG					0x000068084870#define BNX2_HC_CONFIG_COLLECT_STATS			 (1L<<0)4871#define BNX2_HC_CONFIG_RX_TMR_MODE			 (1L<<1)4872#define BNX2_HC_CONFIG_TX_TMR_MODE			 (1L<<2)4873#define BNX2_HC_CONFIG_COM_TMR_MODE			 (1L<<3)4874#define BNX2_HC_CONFIG_CMD_TMR_MODE			 (1L<<4)4875#define BNX2_HC_CONFIG_STATISTIC_PRIORITY		 (1L<<5)4876#define BNX2_HC_CONFIG_STATUS_PRIORITY			 (1L<<6)4877#define BNX2_HC_CONFIG_STAT_MEM_ADDR			 (0xffL<<8)4878#define BNX2_HC_CONFIG_PER_MODE				 (1L<<16)4879#define BNX2_HC_CONFIG_ONE_SHOT				 (1L<<17)4880#define BNX2_HC_CONFIG_USE_INT_PARAM			 (1L<<18)4881#define BNX2_HC_CONFIG_SET_MASK_AT_RD			 (1L<<19)4882#define BNX2_HC_CONFIG_PER_COLLECT_LIMIT		 (0xfL<<20)4883#define BNX2_HC_CONFIG_SB_ADDR_INC			 (0x7L<<24)4884#define BNX2_HC_CONFIG_SB_ADDR_INC_64B			 (0L<<24)4885#define BNX2_HC_CONFIG_SB_ADDR_INC_128B			 (1L<<24)4886#define BNX2_HC_CONFIG_SB_ADDR_INC_256B			 (2L<<24)4887#define BNX2_HC_CONFIG_SB_ADDR_INC_512B			 (3L<<24)4888#define BNX2_HC_CONFIG_SB_ADDR_INC_1024B		 (4L<<24)4889#define BNX2_HC_CONFIG_SB_ADDR_INC_2048B		 (5L<<24)4890#define BNX2_HC_CONFIG_SB_ADDR_INC_4096B		 (6L<<24)4891#define BNX2_HC_CONFIG_SB_ADDR_INC_8192B		 (7L<<24)4892#define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR		 (1L<<29)4893#define BNX2_HC_CONFIG_UNMASK_ALL			 (1L<<30)4894#define BNX2_HC_CONFIG_TX_SEL				 (1L<<31)4895 4896#define BNX2_HC_ATTN_BITS_ENABLE			0x0000680c4897#define BNX2_HC_STATUS_ADDR_L				0x000068104898#define BNX2_HC_STATUS_ADDR_H				0x000068144899#define BNX2_HC_STATISTICS_ADDR_L			0x000068184900#define BNX2_HC_STATISTICS_ADDR_H			0x0000681c4901#define BNX2_HC_TX_QUICK_CONS_TRIP			0x000068204902#define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE		 (0xffL<<0)4903#define BNX2_HC_TX_QUICK_CONS_TRIP_INT			 (0xffL<<16)4904 4905#define BNX2_HC_COMP_PROD_TRIP				0x000068244906#define BNX2_HC_COMP_PROD_TRIP_VALUE			 (0xffL<<0)4907#define BNX2_HC_COMP_PROD_TRIP_INT			 (0xffL<<16)4908 4909#define BNX2_HC_RX_QUICK_CONS_TRIP			0x000068284910#define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE		 (0xffL<<0)4911#define BNX2_HC_RX_QUICK_CONS_TRIP_INT			 (0xffL<<16)4912 4913#define BNX2_HC_RX_TICKS				0x0000682c4914#define BNX2_HC_RX_TICKS_VALUE				 (0x3ffL<<0)4915#define BNX2_HC_RX_TICKS_INT				 (0x3ffL<<16)4916 4917#define BNX2_HC_TX_TICKS				0x000068304918#define BNX2_HC_TX_TICKS_VALUE				 (0x3ffL<<0)4919#define BNX2_HC_TX_TICKS_INT				 (0x3ffL<<16)4920 4921#define BNX2_HC_COM_TICKS				0x000068344922#define BNX2_HC_COM_TICKS_VALUE				 (0x3ffL<<0)4923#define BNX2_HC_COM_TICKS_INT				 (0x3ffL<<16)4924 4925#define BNX2_HC_CMD_TICKS				0x000068384926#define BNX2_HC_CMD_TICKS_VALUE				 (0x3ffL<<0)4927#define BNX2_HC_CMD_TICKS_INT				 (0x3ffL<<16)4928 4929#define BNX2_HC_PERIODIC_TICKS				0x0000683c4930#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS	 (0xffffL<<0)4931#define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)4932 4933#define BNX2_HC_STAT_COLLECT_TICKS			0x000068404934#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS	 (0xffL<<4)4935 4936#define BNX2_HC_STATS_TICKS				0x000068444937#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS		 (0xffffL<<8)4938 4939#define BNX2_HC_STATS_INTERRUPT_STATUS			0x000068484940#define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS	 (0x1ffL<<0)4941#define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS	 (0x1ffL<<16)4942 4943#define BNX2_HC_STAT_MEM_DATA				0x0000684c4944#define BNX2_HC_STAT_GEN_SEL_0				0x000068504945#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0		 (0x7fL<<0)4946#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0	 (0L<<0)4947#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1	 (1L<<0)4948#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2	 (2L<<0)4949#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3	 (3L<<0)4950#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4	 (4L<<0)4951#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5	 (5L<<0)4952#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6	 (6L<<0)4953#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7	 (7L<<0)4954#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8	 (8L<<0)4955#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9	 (9L<<0)4956#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10	 (10L<<0)4957#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11	 (11L<<0)4958#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0	 (12L<<0)4959#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1	 (13L<<0)4960#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2	 (14L<<0)4961#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3	 (15L<<0)4962#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4	 (16L<<0)4963#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5	 (17L<<0)4964#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6	 (18L<<0)4965#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7	 (19L<<0)4966#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0	 (20L<<0)4967#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1	 (21L<<0)4968#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2	 (22L<<0)4969#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3	 (23L<<0)4970#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4	 (24L<<0)4971#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5	 (25L<<0)4972#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6	 (26L<<0)4973#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7	 (27L<<0)4974#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8	 (28L<<0)4975#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9	 (29L<<0)4976#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10	 (30L<<0)4977#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11	 (31L<<0)4978#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0	 (32L<<0)4979#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1	 (33L<<0)4980#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2	 (34L<<0)4981#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3	 (35L<<0)4982#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0	 (36L<<0)4983#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1	 (37L<<0)4984#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2	 (38L<<0)4985#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3	 (39L<<0)4986#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4	 (40L<<0)4987#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5	 (41L<<0)4988#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6	 (42L<<0)4989#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7	 (43L<<0)4990#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0	 (44L<<0)4991#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1	 (45L<<0)4992#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2	 (46L<<0)4993#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3	 (47L<<0)4994#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4	 (48L<<0)4995#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5	 (49L<<0)4996#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6	 (50L<<0)4997#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7	 (51L<<0)4998#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT	 (52L<<0)4999#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT	 (53L<<0)5000#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS	 (54L<<0)5001#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN	 (55L<<0)5002#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR	 (56L<<0)5003#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK	 (59L<<0)5004#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK	 (60L<<0)5005#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK	 (61L<<0)5006#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT	 (62L<<0)5007#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT	 (63L<<0)5008#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT	 (64L<<0)5009#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT	 (65L<<0)5010#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT	 (66L<<0)5011#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT	 (67L<<0)5012#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT	 (68L<<0)5013#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT	 (69L<<0)5014#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT	 (70L<<0)5015#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT	 (71L<<0)5016#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT	 (72L<<0)5017#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT	 (73L<<0)5018#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT	 (74L<<0)5019#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT	 (75L<<0)5020#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT	 (76L<<0)5021#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT	 (77L<<0)5022#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT	 (78L<<0)5023#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT	 (79L<<0)5024#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT	 (80L<<0)5025#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT	 (81L<<0)5026#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT	 (82L<<0)5027#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT	 (83L<<0)5028#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT	 (84L<<0)5029#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT	 (85L<<0)5030#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT	 (86L<<0)5031#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT	 (87L<<0)5032#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT	 (88L<<0)5033#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT	 (89L<<0)5034#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT	 (90L<<0)5035#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT	 (91L<<0)5036#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT	 (92L<<0)5037#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT	 (93L<<0)5038#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT	 (94L<<0)5039#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64	 (95L<<0)5040#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64	 (96L<<0)5041#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS	 (97L<<0)5042#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS	 (98L<<0)5043#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT	 (99L<<0)5044#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT	 (100L<<0)5045#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT	 (101L<<0)5046#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT	 (102L<<0)5047#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT	 (103L<<0)5048#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT	 (104L<<0)5049#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT	 (105L<<0)5050#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT	 (106L<<0)5051#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT	 (107L<<0)5052#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT	 (108L<<0)5053#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT	 (109L<<0)5054#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT	 (110L<<0)5055#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT	 (111L<<0)5056#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT	 (112L<<0)5057#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT	 (113L<<0)5058#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT	 (114L<<0)5059#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0	 (115L<<0)5060#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1	 (116L<<0)5061#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2	 (117L<<0)5062#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3	 (118L<<0)5063#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4	 (119L<<0)5064#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5	 (120L<<0)5065#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS	 (121L<<0)5066#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS	 (122L<<0)5067#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT	 (127L<<0)5068#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1		 (0x7fL<<8)5069#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2		 (0x7fL<<16)5070#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3		 (0x7fL<<24)5071#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI		 (0xffL<<0)5072#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI	 (52L<<0)5073#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI	 (57L<<0)5074#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI	 (58L<<0)5075#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI	 (85L<<0)5076#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI	 (86L<<0)5077#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI	 (87L<<0)5078#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI	 (88L<<0)5079#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI	 (89L<<0)5080#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI	 (90L<<0)5081#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI	 (91L<<0)5082#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI	 (92L<<0)5083#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI	 (93L<<0)5084#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI	 (94L<<0)5085#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI	 (123L<<0)5086#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI	 (124L<<0)5087#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI	 (125L<<0)5088#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI	 (126L<<0)5089#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI	 (128L<<0)5090#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI	 (129L<<0)5091#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI	 (130L<<0)5092#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI	 (131L<<0)5093#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI	 (132L<<0)5094#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI	 (133L<<0)5095#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI	 (134L<<0)5096#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI	 (135L<<0)5097#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI	 (136L<<0)5098#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI	 (137L<<0)5099#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI	 (138L<<0)5100#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI	 (139L<<0)5101#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI	 (140L<<0)5102#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI	 (141L<<0)5103#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI	 (142L<<0)5104#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI	 (143L<<0)5105#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI	 (144L<<0)5106#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI	 (145L<<0)5107#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI	 (146L<<0)5108#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI	 (147L<<0)5109#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI	 (148L<<0)5110#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI	 (149L<<0)5111#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI	 (150L<<0)5112#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI	 (151L<<0)5113#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI	 (152L<<0)5114#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI	 (153L<<0)5115#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI	 (154L<<0)5116#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI	 (155L<<0)5117#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI	 (156L<<0)5118#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI	 (157L<<0)5119#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI	 (158L<<0)5120#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI	 (159L<<0)5121#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI	 (160L<<0)5122#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI	 (161L<<0)5123#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI	 (162L<<0)5124#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI	 (163L<<0)5125#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI	 (164L<<0)5126#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI	 (165L<<0)5127#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI	 (166L<<0)5128#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI	 (167L<<0)5129#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI	 (168L<<0)5130#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI	 (169L<<0)5131#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI	 (170L<<0)5132#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI	 (171L<<0)5133#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI	 (172L<<0)5134#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI	 (173L<<0)5135#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI	 (174L<<0)5136#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI	 (175L<<0)5137#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI	 (176L<<0)5138#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI	 (177L<<0)5139#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI	 (178L<<0)5140#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI		 (0xffL<<8)5141#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI		 (0xffL<<16)5142#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI		 (0xffL<<24)5143 5144#define BNX2_HC_STAT_GEN_SEL_1				0x000068545145#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4		 (0x7fL<<0)5146#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5		 (0x7fL<<8)5147#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6		 (0x7fL<<16)5148#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7		 (0x7fL<<24)5149#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI		 (0xffL<<0)5150#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI		 (0xffL<<8)5151#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI		 (0xffL<<16)5152#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI		 (0xffL<<24)5153 5154#define BNX2_HC_STAT_GEN_SEL_2				0x000068585155#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8		 (0x7fL<<0)5156#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9		 (0x7fL<<8)5157#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10		 (0x7fL<<16)5158#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11		 (0x7fL<<24)5159#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI		 (0xffL<<0)5160#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI		 (0xffL<<8)5161#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI		 (0xffL<<16)5162#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI		 (0xffL<<24)5163 5164#define BNX2_HC_STAT_GEN_SEL_3				0x0000685c5165#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12		 (0x7fL<<0)5166#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13		 (0x7fL<<8)5167#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14		 (0x7fL<<16)5168#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15		 (0x7fL<<24)5169#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI		 (0xffL<<0)5170#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI		 (0xffL<<8)5171#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI		 (0xffL<<16)5172#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI		 (0xffL<<24)5173 5174#define BNX2_HC_STAT_GEN_STAT0				0x000068885175#define BNX2_HC_STAT_GEN_STAT1				0x0000688c5176#define BNX2_HC_STAT_GEN_STAT2				0x000068905177#define BNX2_HC_STAT_GEN_STAT3				0x000068945178#define BNX2_HC_STAT_GEN_STAT4				0x000068985179#define BNX2_HC_STAT_GEN_STAT5				0x0000689c5180#define BNX2_HC_STAT_GEN_STAT6				0x000068a05181#define BNX2_HC_STAT_GEN_STAT7				0x000068a45182#define BNX2_HC_STAT_GEN_STAT8				0x000068a85183#define BNX2_HC_STAT_GEN_STAT9				0x000068ac5184#define BNX2_HC_STAT_GEN_STAT10				0x000068b05185#define BNX2_HC_STAT_GEN_STAT11				0x000068b45186#define BNX2_HC_STAT_GEN_STAT12				0x000068b85187#define BNX2_HC_STAT_GEN_STAT13				0x000068bc5188#define BNX2_HC_STAT_GEN_STAT14				0x000068c05189#define BNX2_HC_STAT_GEN_STAT15				0x000068c45190#define BNX2_HC_STAT_GEN_STAT_AC0			0x000068c85191#define BNX2_HC_STAT_GEN_STAT_AC1			0x000068cc5192#define BNX2_HC_STAT_GEN_STAT_AC2			0x000068d05193#define BNX2_HC_STAT_GEN_STAT_AC3			0x000068d45194#define BNX2_HC_STAT_GEN_STAT_AC4			0x000068d85195#define BNX2_HC_STAT_GEN_STAT_AC5			0x000068dc5196#define BNX2_HC_STAT_GEN_STAT_AC6			0x000068e05197#define BNX2_HC_STAT_GEN_STAT_AC7			0x000068e45198#define BNX2_HC_STAT_GEN_STAT_AC8			0x000068e85199#define BNX2_HC_STAT_GEN_STAT_AC9			0x000068ec5200#define BNX2_HC_STAT_GEN_STAT_AC10			0x000068f05201#define BNX2_HC_STAT_GEN_STAT_AC11			0x000068f45202#define BNX2_HC_STAT_GEN_STAT_AC12			0x000068f85203#define BNX2_HC_STAT_GEN_STAT_AC13			0x000068fc5204#define BNX2_HC_STAT_GEN_STAT_AC14			0x000069005205#define BNX2_HC_STAT_GEN_STAT_AC15			0x000069045206#define BNX2_HC_STAT_GEN_STAT_AC			0x000068c85207#define BNX2_HC_VIS					0x000069085208#define BNX2_HC_VIS_STAT_BUILD_STATE			 (0xfL<<0)5209#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE		 (0L<<0)5210#define BNX2_HC_VIS_STAT_BUILD_STATE_START		 (1L<<0)5211#define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST		 (2L<<0)5212#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64		 (3L<<0)5213#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32		 (4L<<0)5214#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE	 (5L<<0)5215#define BNX2_HC_VIS_STAT_BUILD_STATE_DMA		 (6L<<0)5216#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL	 (7L<<0)5217#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW		 (8L<<0)5218#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH		 (9L<<0)5219#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA		 (10L<<0)5220#define BNX2_HC_VIS_DMA_STAT_STATE			 (0xfL<<8)5221#define BNX2_HC_VIS_DMA_STAT_STATE_IDLE			 (0L<<8)5222#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM		 (1L<<8)5223#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA		 (2L<<8)5224#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP		 (3L<<8)5225#define BNX2_HC_VIS_DMA_STAT_STATE_COMP			 (4L<<8)5226#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM	 (5L<<8)5227#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA	 (6L<<8)5228#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1		 (7L<<8)5229#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2		 (8L<<8)5230#define BNX2_HC_VIS_DMA_STAT_STATE_WAIT			 (9L<<8)5231#define BNX2_HC_VIS_DMA_STAT_STATE_ABORT		 (15L<<8)5232#define BNX2_HC_VIS_DMA_MSI_STATE			 (0x7L<<12)5233#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE		 (0x3L<<15)5234#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE		 (0L<<15)5235#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT	 (1L<<15)5236#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START	 (2L<<15)5237 5238#define BNX2_HC_VIS_1					0x0000690c5239#define BNX2_HC_VIS_1_HW_INTACK_STATE			 (1L<<4)5240#define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE		 (0L<<4)5241#define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT		 (1L<<4)5242#define BNX2_HC_VIS_1_SW_INTACK_STATE			 (1L<<5)5243#define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE		 (0L<<5)5244#define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT		 (1L<<5)5245#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE		 (1L<<6)5246#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE	 (0L<<6)5247#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT	 (1L<<6)5248#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE		 (1L<<7)5249#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE		 (0L<<7)5250#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT		 (1L<<7)5251#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE			 (0xfL<<17)5252#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE		 (0L<<17)5253#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA		 (1L<<17)5254#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE		 (2L<<17)5255#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN		 (3L<<17)5256#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT		 (4L<<17)5257#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE	 (5L<<17)5258#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN	 (6L<<17)5259#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT		 (7L<<17)5260#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE			 (0x3L<<21)5261#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL		 (0L<<21)5262#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR		 (1L<<21)5263#define BNX2_HC_VIS_1_INT_GEN_STATE			 (1L<<23)5264#define BNX2_HC_VIS_1_INT_GEN_STATE_DLE			 (0L<<23)5265#define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT		 (1L<<23)5266#define BNX2_HC_VIS_1_STAT_CHAN_ID			 (0x7L<<24)5267#define BNX2_HC_VIS_1_INT_B				 (1L<<27)5268 5269#define BNX2_HC_DEBUG_VECT_PEEK				0x000069105270#define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE			 (0x7ffL<<0)5271#define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)5272#define BNX2_HC_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)5273#define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE			 (0x7ffL<<16)5274#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)5275#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)5276 5277#define BNX2_HC_COALESCE_NOW				0x000069145278#define BNX2_HC_COALESCE_NOW_COAL_NOW			 (0x1ffL<<1)5279#define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT		 (0x1ffL<<11)5280#define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT		 (0x1ffL<<21)5281 5282#define BNX2_HC_MSIX_BIT_VECTOR				0x000069185283#define BNX2_HC_MSIX_BIT_VECTOR_VAL			 (0x1ffL<<0)5284 5285#define BNX2_HC_SB_CONFIG_1				0x00006a005286#define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE			 (1L<<1)5287#define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE			 (1L<<2)5288#define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE		 (1L<<3)5289#define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE		 (1L<<4)5290#define BNX2_HC_SB_CONFIG_1_PER_MODE			 (1L<<16)5291#define BNX2_HC_SB_CONFIG_1_ONE_SHOT			 (1L<<17)5292#define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM		 (1L<<18)5293#define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT		 (0xfL<<20)5294 5295#define BNX2_HC_TX_QUICK_CONS_TRIP_1			0x00006a045296#define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE		 (0xffL<<0)5297#define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT		 (0xffL<<16)5298 5299#define BNX2_HC_COMP_PROD_TRIP_1			0x00006a085300#define BNX2_HC_COMP_PROD_TRIP_1_VALUE			 (0xffL<<0)5301#define BNX2_HC_COMP_PROD_TRIP_1_INT			 (0xffL<<16)5302 5303#define BNX2_HC_RX_QUICK_CONS_TRIP_1			0x00006a0c5304#define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE		 (0xffL<<0)5305#define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT		 (0xffL<<16)5306 5307#define BNX2_HC_RX_TICKS_1				0x00006a105308#define BNX2_HC_RX_TICKS_1_VALUE			 (0x3ffL<<0)5309#define BNX2_HC_RX_TICKS_1_INT				 (0x3ffL<<16)5310 5311#define BNX2_HC_TX_TICKS_1				0x00006a145312#define BNX2_HC_TX_TICKS_1_VALUE			 (0x3ffL<<0)5313#define BNX2_HC_TX_TICKS_1_INT				 (0x3ffL<<16)5314 5315#define BNX2_HC_COM_TICKS_1				0x00006a185316#define BNX2_HC_COM_TICKS_1_VALUE			 (0x3ffL<<0)5317#define BNX2_HC_COM_TICKS_1_INT				 (0x3ffL<<16)5318 5319#define BNX2_HC_CMD_TICKS_1				0x00006a1c5320#define BNX2_HC_CMD_TICKS_1_VALUE			 (0x3ffL<<0)5321#define BNX2_HC_CMD_TICKS_1_INT				 (0x3ffL<<16)5322 5323#define BNX2_HC_PERIODIC_TICKS_1			0x00006a205324#define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS	 (0xffffL<<0)5325#define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5326 5327#define BNX2_HC_SB_CONFIG_2				0x00006a245328#define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE			 (1L<<1)5329#define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE			 (1L<<2)5330#define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE		 (1L<<3)5331#define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE		 (1L<<4)5332#define BNX2_HC_SB_CONFIG_2_PER_MODE			 (1L<<16)5333#define BNX2_HC_SB_CONFIG_2_ONE_SHOT			 (1L<<17)5334#define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM		 (1L<<18)5335#define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT		 (0xfL<<20)5336 5337#define BNX2_HC_TX_QUICK_CONS_TRIP_2			0x00006a285338#define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE		 (0xffL<<0)5339#define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT		 (0xffL<<16)5340 5341#define BNX2_HC_COMP_PROD_TRIP_2			0x00006a2c5342#define BNX2_HC_COMP_PROD_TRIP_2_VALUE			 (0xffL<<0)5343#define BNX2_HC_COMP_PROD_TRIP_2_INT			 (0xffL<<16)5344 5345#define BNX2_HC_RX_QUICK_CONS_TRIP_2			0x00006a305346#define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE		 (0xffL<<0)5347#define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT		 (0xffL<<16)5348 5349#define BNX2_HC_RX_TICKS_2				0x00006a345350#define BNX2_HC_RX_TICKS_2_VALUE			 (0x3ffL<<0)5351#define BNX2_HC_RX_TICKS_2_INT				 (0x3ffL<<16)5352 5353#define BNX2_HC_TX_TICKS_2				0x00006a385354#define BNX2_HC_TX_TICKS_2_VALUE			 (0x3ffL<<0)5355#define BNX2_HC_TX_TICKS_2_INT				 (0x3ffL<<16)5356 5357#define BNX2_HC_COM_TICKS_2				0x00006a3c5358#define BNX2_HC_COM_TICKS_2_VALUE			 (0x3ffL<<0)5359#define BNX2_HC_COM_TICKS_2_INT				 (0x3ffL<<16)5360 5361#define BNX2_HC_CMD_TICKS_2				0x00006a405362#define BNX2_HC_CMD_TICKS_2_VALUE			 (0x3ffL<<0)5363#define BNX2_HC_CMD_TICKS_2_INT				 (0x3ffL<<16)5364 5365#define BNX2_HC_PERIODIC_TICKS_2			0x00006a445366#define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS	 (0xffffL<<0)5367#define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5368 5369#define BNX2_HC_SB_CONFIG_3				0x00006a485370#define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE			 (1L<<1)5371#define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE			 (1L<<2)5372#define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE		 (1L<<3)5373#define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE		 (1L<<4)5374#define BNX2_HC_SB_CONFIG_3_PER_MODE			 (1L<<16)5375#define BNX2_HC_SB_CONFIG_3_ONE_SHOT			 (1L<<17)5376#define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM		 (1L<<18)5377#define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT		 (0xfL<<20)5378 5379#define BNX2_HC_TX_QUICK_CONS_TRIP_3			0x00006a4c5380#define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE		 (0xffL<<0)5381#define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT		 (0xffL<<16)5382 5383#define BNX2_HC_COMP_PROD_TRIP_3			0x00006a505384#define BNX2_HC_COMP_PROD_TRIP_3_VALUE			 (0xffL<<0)5385#define BNX2_HC_COMP_PROD_TRIP_3_INT			 (0xffL<<16)5386 5387#define BNX2_HC_RX_QUICK_CONS_TRIP_3			0x00006a545388#define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE		 (0xffL<<0)5389#define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT		 (0xffL<<16)5390 5391#define BNX2_HC_RX_TICKS_3				0x00006a585392#define BNX2_HC_RX_TICKS_3_VALUE			 (0x3ffL<<0)5393#define BNX2_HC_RX_TICKS_3_INT				 (0x3ffL<<16)5394 5395#define BNX2_HC_TX_TICKS_3				0x00006a5c5396#define BNX2_HC_TX_TICKS_3_VALUE			 (0x3ffL<<0)5397#define BNX2_HC_TX_TICKS_3_INT				 (0x3ffL<<16)5398 5399#define BNX2_HC_COM_TICKS_3				0x00006a605400#define BNX2_HC_COM_TICKS_3_VALUE			 (0x3ffL<<0)5401#define BNX2_HC_COM_TICKS_3_INT				 (0x3ffL<<16)5402 5403#define BNX2_HC_CMD_TICKS_3				0x00006a645404#define BNX2_HC_CMD_TICKS_3_VALUE			 (0x3ffL<<0)5405#define BNX2_HC_CMD_TICKS_3_INT				 (0x3ffL<<16)5406 5407#define BNX2_HC_PERIODIC_TICKS_3			0x00006a685408#define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS	 (0xffffL<<0)5409#define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5410 5411#define BNX2_HC_SB_CONFIG_4				0x00006a6c5412#define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE			 (1L<<1)5413#define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE			 (1L<<2)5414#define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE		 (1L<<3)5415#define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE		 (1L<<4)5416#define BNX2_HC_SB_CONFIG_4_PER_MODE			 (1L<<16)5417#define BNX2_HC_SB_CONFIG_4_ONE_SHOT			 (1L<<17)5418#define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM		 (1L<<18)5419#define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT		 (0xfL<<20)5420 5421#define BNX2_HC_TX_QUICK_CONS_TRIP_4			0x00006a705422#define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE		 (0xffL<<0)5423#define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT		 (0xffL<<16)5424 5425#define BNX2_HC_COMP_PROD_TRIP_4			0x00006a745426#define BNX2_HC_COMP_PROD_TRIP_4_VALUE			 (0xffL<<0)5427#define BNX2_HC_COMP_PROD_TRIP_4_INT			 (0xffL<<16)5428 5429#define BNX2_HC_RX_QUICK_CONS_TRIP_4			0x00006a785430#define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE		 (0xffL<<0)5431#define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT		 (0xffL<<16)5432 5433#define BNX2_HC_RX_TICKS_4				0x00006a7c5434#define BNX2_HC_RX_TICKS_4_VALUE			 (0x3ffL<<0)5435#define BNX2_HC_RX_TICKS_4_INT				 (0x3ffL<<16)5436 5437#define BNX2_HC_TX_TICKS_4				0x00006a805438#define BNX2_HC_TX_TICKS_4_VALUE			 (0x3ffL<<0)5439#define BNX2_HC_TX_TICKS_4_INT				 (0x3ffL<<16)5440 5441#define BNX2_HC_COM_TICKS_4				0x00006a845442#define BNX2_HC_COM_TICKS_4_VALUE			 (0x3ffL<<0)5443#define BNX2_HC_COM_TICKS_4_INT				 (0x3ffL<<16)5444 5445#define BNX2_HC_CMD_TICKS_4				0x00006a885446#define BNX2_HC_CMD_TICKS_4_VALUE			 (0x3ffL<<0)5447#define BNX2_HC_CMD_TICKS_4_INT				 (0x3ffL<<16)5448 5449#define BNX2_HC_PERIODIC_TICKS_4			0x00006a8c5450#define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS	 (0xffffL<<0)5451#define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5452 5453#define BNX2_HC_SB_CONFIG_5				0x00006a905454#define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE			 (1L<<1)5455#define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE			 (1L<<2)5456#define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE		 (1L<<3)5457#define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE		 (1L<<4)5458#define BNX2_HC_SB_CONFIG_5_PER_MODE			 (1L<<16)5459#define BNX2_HC_SB_CONFIG_5_ONE_SHOT			 (1L<<17)5460#define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM		 (1L<<18)5461#define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT		 (0xfL<<20)5462 5463#define BNX2_HC_TX_QUICK_CONS_TRIP_5			0x00006a945464#define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE		 (0xffL<<0)5465#define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT		 (0xffL<<16)5466 5467#define BNX2_HC_COMP_PROD_TRIP_5			0x00006a985468#define BNX2_HC_COMP_PROD_TRIP_5_VALUE			 (0xffL<<0)5469#define BNX2_HC_COMP_PROD_TRIP_5_INT			 (0xffL<<16)5470 5471#define BNX2_HC_RX_QUICK_CONS_TRIP_5			0x00006a9c5472#define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE		 (0xffL<<0)5473#define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT		 (0xffL<<16)5474 5475#define BNX2_HC_RX_TICKS_5				0x00006aa05476#define BNX2_HC_RX_TICKS_5_VALUE			 (0x3ffL<<0)5477#define BNX2_HC_RX_TICKS_5_INT				 (0x3ffL<<16)5478 5479#define BNX2_HC_TX_TICKS_5				0x00006aa45480#define BNX2_HC_TX_TICKS_5_VALUE			 (0x3ffL<<0)5481#define BNX2_HC_TX_TICKS_5_INT				 (0x3ffL<<16)5482 5483#define BNX2_HC_COM_TICKS_5				0x00006aa85484#define BNX2_HC_COM_TICKS_5_VALUE			 (0x3ffL<<0)5485#define BNX2_HC_COM_TICKS_5_INT				 (0x3ffL<<16)5486 5487#define BNX2_HC_CMD_TICKS_5				0x00006aac5488#define BNX2_HC_CMD_TICKS_5_VALUE			 (0x3ffL<<0)5489#define BNX2_HC_CMD_TICKS_5_INT				 (0x3ffL<<16)5490 5491#define BNX2_HC_PERIODIC_TICKS_5			0x00006ab05492#define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS	 (0xffffL<<0)5493#define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5494 5495#define BNX2_HC_SB_CONFIG_6				0x00006ab45496#define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE			 (1L<<1)5497#define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE			 (1L<<2)5498#define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE		 (1L<<3)5499#define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE		 (1L<<4)5500#define BNX2_HC_SB_CONFIG_6_PER_MODE			 (1L<<16)5501#define BNX2_HC_SB_CONFIG_6_ONE_SHOT			 (1L<<17)5502#define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM		 (1L<<18)5503#define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT		 (0xfL<<20)5504 5505#define BNX2_HC_TX_QUICK_CONS_TRIP_6			0x00006ab85506#define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE		 (0xffL<<0)5507#define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT		 (0xffL<<16)5508 5509#define BNX2_HC_COMP_PROD_TRIP_6			0x00006abc5510#define BNX2_HC_COMP_PROD_TRIP_6_VALUE			 (0xffL<<0)5511#define BNX2_HC_COMP_PROD_TRIP_6_INT			 (0xffL<<16)5512 5513#define BNX2_HC_RX_QUICK_CONS_TRIP_6			0x00006ac05514#define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE		 (0xffL<<0)5515#define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT		 (0xffL<<16)5516 5517#define BNX2_HC_RX_TICKS_6				0x00006ac45518#define BNX2_HC_RX_TICKS_6_VALUE			 (0x3ffL<<0)5519#define BNX2_HC_RX_TICKS_6_INT				 (0x3ffL<<16)5520 5521#define BNX2_HC_TX_TICKS_6				0x00006ac85522#define BNX2_HC_TX_TICKS_6_VALUE			 (0x3ffL<<0)5523#define BNX2_HC_TX_TICKS_6_INT				 (0x3ffL<<16)5524 5525#define BNX2_HC_COM_TICKS_6				0x00006acc5526#define BNX2_HC_COM_TICKS_6_VALUE			 (0x3ffL<<0)5527#define BNX2_HC_COM_TICKS_6_INT				 (0x3ffL<<16)5528 5529#define BNX2_HC_CMD_TICKS_6				0x00006ad05530#define BNX2_HC_CMD_TICKS_6_VALUE			 (0x3ffL<<0)5531#define BNX2_HC_CMD_TICKS_6_INT				 (0x3ffL<<16)5532 5533#define BNX2_HC_PERIODIC_TICKS_6			0x00006ad45534#define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS	 (0xffffL<<0)5535#define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5536 5537#define BNX2_HC_SB_CONFIG_7				0x00006ad85538#define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE			 (1L<<1)5539#define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE			 (1L<<2)5540#define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE		 (1L<<3)5541#define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE		 (1L<<4)5542#define BNX2_HC_SB_CONFIG_7_PER_MODE			 (1L<<16)5543#define BNX2_HC_SB_CONFIG_7_ONE_SHOT			 (1L<<17)5544#define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM		 (1L<<18)5545#define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT		 (0xfL<<20)5546 5547#define BNX2_HC_TX_QUICK_CONS_TRIP_7			0x00006adc5548#define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE		 (0xffL<<0)5549#define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT		 (0xffL<<16)5550 5551#define BNX2_HC_COMP_PROD_TRIP_7			0x00006ae05552#define BNX2_HC_COMP_PROD_TRIP_7_VALUE			 (0xffL<<0)5553#define BNX2_HC_COMP_PROD_TRIP_7_INT			 (0xffL<<16)5554 5555#define BNX2_HC_RX_QUICK_CONS_TRIP_7			0x00006ae45556#define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE		 (0xffL<<0)5557#define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT		 (0xffL<<16)5558 5559#define BNX2_HC_RX_TICKS_7				0x00006ae85560#define BNX2_HC_RX_TICKS_7_VALUE			 (0x3ffL<<0)5561#define BNX2_HC_RX_TICKS_7_INT				 (0x3ffL<<16)5562 5563#define BNX2_HC_TX_TICKS_7				0x00006aec5564#define BNX2_HC_TX_TICKS_7_VALUE			 (0x3ffL<<0)5565#define BNX2_HC_TX_TICKS_7_INT				 (0x3ffL<<16)5566 5567#define BNX2_HC_COM_TICKS_7				0x00006af05568#define BNX2_HC_COM_TICKS_7_VALUE			 (0x3ffL<<0)5569#define BNX2_HC_COM_TICKS_7_INT				 (0x3ffL<<16)5570 5571#define BNX2_HC_CMD_TICKS_7				0x00006af45572#define BNX2_HC_CMD_TICKS_7_VALUE			 (0x3ffL<<0)5573#define BNX2_HC_CMD_TICKS_7_INT				 (0x3ffL<<16)5574 5575#define BNX2_HC_PERIODIC_TICKS_7			0x00006af85576#define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS	 (0xffffL<<0)5577#define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5578 5579#define BNX2_HC_SB_CONFIG_8				0x00006afc5580#define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE			 (1L<<1)5581#define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE			 (1L<<2)5582#define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE		 (1L<<3)5583#define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE		 (1L<<4)5584#define BNX2_HC_SB_CONFIG_8_PER_MODE			 (1L<<16)5585#define BNX2_HC_SB_CONFIG_8_ONE_SHOT			 (1L<<17)5586#define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM		 (1L<<18)5587#define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT		 (0xfL<<20)5588 5589#define BNX2_HC_TX_QUICK_CONS_TRIP_8			0x00006b005590#define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE		 (0xffL<<0)5591#define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT		 (0xffL<<16)5592 5593#define BNX2_HC_COMP_PROD_TRIP_8			0x00006b045594#define BNX2_HC_COMP_PROD_TRIP_8_VALUE			 (0xffL<<0)5595#define BNX2_HC_COMP_PROD_TRIP_8_INT			 (0xffL<<16)5596 5597#define BNX2_HC_RX_QUICK_CONS_TRIP_8			0x00006b085598#define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE		 (0xffL<<0)5599#define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT		 (0xffL<<16)5600 5601#define BNX2_HC_RX_TICKS_8				0x00006b0c5602#define BNX2_HC_RX_TICKS_8_VALUE			 (0x3ffL<<0)5603#define BNX2_HC_RX_TICKS_8_INT				 (0x3ffL<<16)5604 5605#define BNX2_HC_TX_TICKS_8				0x00006b105606#define BNX2_HC_TX_TICKS_8_VALUE			 (0x3ffL<<0)5607#define BNX2_HC_TX_TICKS_8_INT				 (0x3ffL<<16)5608 5609#define BNX2_HC_COM_TICKS_8				0x00006b145610#define BNX2_HC_COM_TICKS_8_VALUE			 (0x3ffL<<0)5611#define BNX2_HC_COM_TICKS_8_INT				 (0x3ffL<<16)5612 5613#define BNX2_HC_CMD_TICKS_8				0x00006b185614#define BNX2_HC_CMD_TICKS_8_VALUE			 (0x3ffL<<0)5615#define BNX2_HC_CMD_TICKS_8_INT				 (0x3ffL<<16)5616 5617#define BNX2_HC_PERIODIC_TICKS_8			0x00006b1c5618#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS	 (0xffffL<<0)5619#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)5620 5621#define BNX2_HC_SB_CONFIG_SIZE	(BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1)5622#define BNX2_HC_COMP_PROD_TRIP_OFF	(BNX2_HC_COMP_PROD_TRIP_1 -	\5623					 BNX2_HC_SB_CONFIG_1)5624#define BNX2_HC_COM_TICKS_OFF	(BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1)5625#define BNX2_HC_CMD_TICKS_OFF	(BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1)5626#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF	(BNX2_HC_TX_QUICK_CONS_TRIP_1 -	\5627					 BNX2_HC_SB_CONFIG_1)5628#define BNX2_HC_TX_TICKS_OFF	(BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)5629#define BNX2_HC_RX_QUICK_CONS_TRIP_OFF	(BNX2_HC_RX_QUICK_CONS_TRIP_1 - \5630					 BNX2_HC_SB_CONFIG_1)5631#define BNX2_HC_RX_TICKS_OFF	(BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1)5632 5633 5634/*5635 *  txp_reg definition5636 *  offset: 0x400005637 */5638#define BNX2_TXP_CPU_MODE				0x000450005639#define BNX2_TXP_CPU_MODE_LOCAL_RST			 (1L<<0)5640#define BNX2_TXP_CPU_MODE_STEP_ENA			 (1L<<1)5641#define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)5642#define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)5643#define BNX2_TXP_CPU_MODE_MSG_BIT1			 (1L<<6)5644#define BNX2_TXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)5645#define BNX2_TXP_CPU_MODE_SOFT_HALT			 (1L<<10)5646#define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)5647#define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)5648#define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)5649#define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)5650 5651#define BNX2_TXP_CPU_STATE				0x000450045652#define BNX2_TXP_CPU_STATE_BREAKPOINT			 (1L<<0)5653#define BNX2_TXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)5654#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)5655#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)5656#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)5657#define BNX2_TXP_CPU_STATE_BAD_PC_HALTED		 (1L<<6)5658#define BNX2_TXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)5659#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)5660#define BNX2_TXP_CPU_STATE_SOFT_HALTED			 (1L<<10)5661#define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)5662#define BNX2_TXP_CPU_STATE_INTERRUPT			 (1L<<12)5663#define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)5664#define BNX2_TXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)5665#define BNX2_TXP_CPU_STATE_BLOCKED_READ			 (1L<<31)5666 5667#define BNX2_TXP_CPU_EVENT_MASK				0x000450085668#define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)5669#define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)5670#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)5671#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)5672#define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)5673#define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)5674#define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)5675#define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)5676#define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)5677#define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)5678#define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)5679 5680#define BNX2_TXP_CPU_PROGRAM_COUNTER			0x0004501c5681#define BNX2_TXP_CPU_INSTRUCTION			0x000450205682#define BNX2_TXP_CPU_DATA_ACCESS			0x000450245683#define BNX2_TXP_CPU_INTERRUPT_ENABLE			0x000450285684#define BNX2_TXP_CPU_INTERRUPT_VECTOR			0x0004502c5685#define BNX2_TXP_CPU_INTERRUPT_SAVED_PC			0x000450305686#define BNX2_TXP_CPU_HW_BREAKPOINT			0x000450345687#define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)5688#define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)5689 5690#define BNX2_TXP_CPU_DEBUG_VECT_PEEK			0x000450385691#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)5692#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)5693#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)5694#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)5695#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)5696#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)5697 5698#define BNX2_TXP_CPU_LAST_BRANCH_ADDR			0x000450485699#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)5700#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)5701#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)5702#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)5703 5704#define BNX2_TXP_CPU_REG_FILE				0x000452005705#define BNX2_TXP_TXPQ					0x000453c05706#define BNX2_TXP_FTQ_CMD				0x000453f85707#define BNX2_TXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)5708#define BNX2_TXP_FTQ_CMD_WR_TOP				 (1L<<10)5709#define BNX2_TXP_FTQ_CMD_WR_TOP_0			 (0L<<10)5710#define BNX2_TXP_FTQ_CMD_WR_TOP_1			 (1L<<10)5711#define BNX2_TXP_FTQ_CMD_SFT_RESET			 (1L<<25)5712#define BNX2_TXP_FTQ_CMD_RD_DATA			 (1L<<26)5713#define BNX2_TXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)5714#define BNX2_TXP_FTQ_CMD_ADD_DATA			 (1L<<28)5715#define BNX2_TXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)5716#define BNX2_TXP_FTQ_CMD_POP				 (1L<<30)5717#define BNX2_TXP_FTQ_CMD_BUSY				 (1L<<31)5718 5719#define BNX2_TXP_FTQ_CTL				0x000453fc5720#define BNX2_TXP_FTQ_CTL_INTERVENE			 (1L<<0)5721#define BNX2_TXP_FTQ_CTL_OVERFLOW			 (1L<<1)5722#define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)5723#define BNX2_TXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)5724#define BNX2_TXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)5725 5726#define BNX2_TXP_SCRATCH				0x000600005727 5728 5729/*5730 *  tpat_reg definition5731 *  offset: 0x800005732 */5733#define BNX2_TPAT_CPU_MODE				0x000850005734#define BNX2_TPAT_CPU_MODE_LOCAL_RST			 (1L<<0)5735#define BNX2_TPAT_CPU_MODE_STEP_ENA			 (1L<<1)5736#define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)5737#define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)5738#define BNX2_TPAT_CPU_MODE_MSG_BIT1			 (1L<<6)5739#define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA		 (1L<<7)5740#define BNX2_TPAT_CPU_MODE_SOFT_HALT			 (1L<<10)5741#define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)5742#define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)5743#define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)5744#define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)5745 5746#define BNX2_TPAT_CPU_STATE				0x000850045747#define BNX2_TPAT_CPU_STATE_BREAKPOINT			 (1L<<0)5748#define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED		 (1L<<2)5749#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)5750#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)5751#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)5752#define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED		 (1L<<6)5753#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED		 (1L<<7)5754#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)5755#define BNX2_TPAT_CPU_STATE_SOFT_HALTED			 (1L<<10)5756#define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)5757#define BNX2_TPAT_CPU_STATE_INTERRUPT			 (1L<<12)5758#define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)5759#define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL		 (1L<<15)5760#define BNX2_TPAT_CPU_STATE_BLOCKED_READ		 (1L<<31)5761 5762#define BNX2_TPAT_CPU_EVENT_MASK			0x000850085763#define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK	 (1L<<0)5764#define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)5765#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)5766#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)5767#define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)5768#define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)5769#define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)5770#define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)5771#define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)5772#define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)5773#define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)5774 5775#define BNX2_TPAT_CPU_PROGRAM_COUNTER			0x0008501c5776#define BNX2_TPAT_CPU_INSTRUCTION			0x000850205777#define BNX2_TPAT_CPU_DATA_ACCESS			0x000850245778#define BNX2_TPAT_CPU_INTERRUPT_ENABLE			0x000850285779#define BNX2_TPAT_CPU_INTERRUPT_VECTOR			0x0008502c5780#define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC		0x000850305781#define BNX2_TPAT_CPU_HW_BREAKPOINT			0x000850345782#define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)5783#define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)5784 5785#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK			0x000850385786#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)5787#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)5788#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)5789#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)5790#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)5791#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)5792 5793#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR			0x000850485794#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)5795#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)5796#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)5797#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)5798 5799#define BNX2_TPAT_CPU_REG_FILE				0x000852005800#define BNX2_TPAT_TPATQ					0x000853c05801#define BNX2_TPAT_FTQ_CMD				0x000853f85802#define BNX2_TPAT_FTQ_CMD_OFFSET			 (0x3ffL<<0)5803#define BNX2_TPAT_FTQ_CMD_WR_TOP			 (1L<<10)5804#define BNX2_TPAT_FTQ_CMD_WR_TOP_0			 (0L<<10)5805#define BNX2_TPAT_FTQ_CMD_WR_TOP_1			 (1L<<10)5806#define BNX2_TPAT_FTQ_CMD_SFT_RESET			 (1L<<25)5807#define BNX2_TPAT_FTQ_CMD_RD_DATA			 (1L<<26)5808#define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN			 (1L<<27)5809#define BNX2_TPAT_FTQ_CMD_ADD_DATA			 (1L<<28)5810#define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR			 (1L<<29)5811#define BNX2_TPAT_FTQ_CMD_POP				 (1L<<30)5812#define BNX2_TPAT_FTQ_CMD_BUSY				 (1L<<31)5813 5814#define BNX2_TPAT_FTQ_CTL				0x000853fc5815#define BNX2_TPAT_FTQ_CTL_INTERVENE			 (1L<<0)5816#define BNX2_TPAT_FTQ_CTL_OVERFLOW			 (1L<<1)5817#define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)5818#define BNX2_TPAT_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)5819#define BNX2_TPAT_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)5820 5821#define BNX2_TPAT_SCRATCH				0x000a00005822 5823 5824/*5825 *  rxp_reg definition5826 *  offset: 0xc00005827 */5828#define BNX2_RXP_CPU_MODE				0x000c50005829#define BNX2_RXP_CPU_MODE_LOCAL_RST			 (1L<<0)5830#define BNX2_RXP_CPU_MODE_STEP_ENA			 (1L<<1)5831#define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)5832#define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)5833#define BNX2_RXP_CPU_MODE_MSG_BIT1			 (1L<<6)5834#define BNX2_RXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)5835#define BNX2_RXP_CPU_MODE_SOFT_HALT			 (1L<<10)5836#define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)5837#define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)5838#define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)5839#define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)5840 5841#define BNX2_RXP_CPU_STATE				0x000c50045842#define BNX2_RXP_CPU_STATE_BREAKPOINT			 (1L<<0)5843#define BNX2_RXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)5844#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)5845#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)5846#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)5847#define BNX2_RXP_CPU_STATE_BAD_PC_HALTED		 (1L<<6)5848#define BNX2_RXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)5849#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)5850#define BNX2_RXP_CPU_STATE_SOFT_HALTED			 (1L<<10)5851#define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)5852#define BNX2_RXP_CPU_STATE_INTERRUPT			 (1L<<12)5853#define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)5854#define BNX2_RXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)5855#define BNX2_RXP_CPU_STATE_BLOCKED_READ			 (1L<<31)5856 5857#define BNX2_RXP_CPU_EVENT_MASK				0x000c50085858#define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)5859#define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)5860#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)5861#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)5862#define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)5863#define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)5864#define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)5865#define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)5866#define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)5867#define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)5868#define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)5869 5870#define BNX2_RXP_CPU_PROGRAM_COUNTER			0x000c501c5871#define BNX2_RXP_CPU_INSTRUCTION			0x000c50205872#define BNX2_RXP_CPU_DATA_ACCESS			0x000c50245873#define BNX2_RXP_CPU_INTERRUPT_ENABLE			0x000c50285874#define BNX2_RXP_CPU_INTERRUPT_VECTOR			0x000c502c5875#define BNX2_RXP_CPU_INTERRUPT_SAVED_PC			0x000c50305876#define BNX2_RXP_CPU_HW_BREAKPOINT			0x000c50345877#define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)5878#define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)5879 5880#define BNX2_RXP_CPU_DEBUG_VECT_PEEK			0x000c50385881#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)5882#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)5883#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)5884#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)5885#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)5886#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)5887 5888#define BNX2_RXP_CPU_LAST_BRANCH_ADDR			0x000c50485889#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)5890#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)5891#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)5892#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)5893 5894#define BNX2_RXP_CPU_REG_FILE				0x000c52005895#define BNX2_RXP_PFE_PFE_CTL				0x000c537c5896#define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT		 (1L<<0)5897#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE			 (0xfL<<4)5898#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0			 (0L<<4)5899#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1			 (1L<<4)5900#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2			 (2L<<4)5901#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3			 (3L<<4)5902#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4			 (4L<<4)5903#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5			 (5L<<4)5904#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6			 (6L<<4)5905#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7			 (7L<<4)5906#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8			 (8L<<4)5907#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9			 (9L<<4)5908#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10		 (10L<<4)5909#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11		 (11L<<4)5910#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12		 (12L<<4)5911#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13		 (13L<<4)5912#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14		 (14L<<4)5913#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15		 (15L<<4)5914#define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT			 (0xfL<<12)5915#define BNX2_RXP_PFE_PFE_CTL_OFFSET			 (0x1ffL<<16)5916 5917#define BNX2_RXP_RXPCQ					0x000c53805918#define BNX2_RXP_CFTQ_CMD				0x000c53b85919#define BNX2_RXP_CFTQ_CMD_OFFSET			 (0x3ffL<<0)5920#define BNX2_RXP_CFTQ_CMD_WR_TOP			 (1L<<10)5921#define BNX2_RXP_CFTQ_CMD_WR_TOP_0			 (0L<<10)5922#define BNX2_RXP_CFTQ_CMD_WR_TOP_1			 (1L<<10)5923#define BNX2_RXP_CFTQ_CMD_SFT_RESET			 (1L<<25)5924#define BNX2_RXP_CFTQ_CMD_RD_DATA			 (1L<<26)5925#define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN			 (1L<<27)5926#define BNX2_RXP_CFTQ_CMD_ADD_DATA			 (1L<<28)5927#define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR			 (1L<<29)5928#define BNX2_RXP_CFTQ_CMD_POP				 (1L<<30)5929#define BNX2_RXP_CFTQ_CMD_BUSY				 (1L<<31)5930 5931#define BNX2_RXP_CFTQ_CTL				0x000c53bc5932#define BNX2_RXP_CFTQ_CTL_INTERVENE			 (1L<<0)5933#define BNX2_RXP_CFTQ_CTL_OVERFLOW			 (1L<<1)5934#define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE		 (1L<<2)5935#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)5936#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)5937 5938#define BNX2_RXP_RXPQ					0x000c53c05939#define BNX2_RXP_FTQ_CMD				0x000c53f85940#define BNX2_RXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)5941#define BNX2_RXP_FTQ_CMD_WR_TOP				 (1L<<10)5942#define BNX2_RXP_FTQ_CMD_WR_TOP_0			 (0L<<10)5943#define BNX2_RXP_FTQ_CMD_WR_TOP_1			 (1L<<10)5944#define BNX2_RXP_FTQ_CMD_SFT_RESET			 (1L<<25)5945#define BNX2_RXP_FTQ_CMD_RD_DATA			 (1L<<26)5946#define BNX2_RXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)5947#define BNX2_RXP_FTQ_CMD_ADD_DATA			 (1L<<28)5948#define BNX2_RXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)5949#define BNX2_RXP_FTQ_CMD_POP				 (1L<<30)5950#define BNX2_RXP_FTQ_CMD_BUSY				 (1L<<31)5951 5952#define BNX2_RXP_FTQ_CTL				0x000c53fc5953#define BNX2_RXP_FTQ_CTL_INTERVENE			 (1L<<0)5954#define BNX2_RXP_FTQ_CTL_OVERFLOW			 (1L<<1)5955#define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)5956#define BNX2_RXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)5957#define BNX2_RXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)5958 5959#define BNX2_RXP_SCRATCH				0x000e00005960#define BNX2_RXP_SCRATCH_RXP_FLOOD			 0x000e00245961#define BNX2_RXP_SCRATCH_RSS_TBL_SZ			 0x000e00385962#define BNX2_RXP_SCRATCH_RSS_TBL			 0x000e003c5963#define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES		 1285964 5965 5966/*5967 *  com_reg definition5968 *  offset: 0x1000005969 */5970#define BNX2_COM_CKSUM_ERROR_STATUS			0x001000005971#define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED		 (0xffffL<<0)5972#define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED		 (0xffffL<<16)5973 5974#define BNX2_COM_CPU_MODE				0x001050005975#define BNX2_COM_CPU_MODE_LOCAL_RST			 (1L<<0)5976#define BNX2_COM_CPU_MODE_STEP_ENA			 (1L<<1)5977#define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)5978#define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)5979#define BNX2_COM_CPU_MODE_MSG_BIT1			 (1L<<6)5980#define BNX2_COM_CPU_MODE_INTERRUPT_ENA			 (1L<<7)5981#define BNX2_COM_CPU_MODE_SOFT_HALT			 (1L<<10)5982#define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)5983#define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)5984#define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)5985#define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)5986 5987#define BNX2_COM_CPU_STATE				0x001050045988#define BNX2_COM_CPU_STATE_BREAKPOINT			 (1L<<0)5989#define BNX2_COM_CPU_STATE_BAD_INST_HALTED		 (1L<<2)5990#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)5991#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)5992#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)5993#define BNX2_COM_CPU_STATE_BAD_PC_HALTED		 (1L<<6)5994#define BNX2_COM_CPU_STATE_ALIGN_HALTED			 (1L<<7)5995#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)5996#define BNX2_COM_CPU_STATE_SOFT_HALTED			 (1L<<10)5997#define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)5998#define BNX2_COM_CPU_STATE_INTERRUPT			 (1L<<12)5999#define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)6000#define BNX2_COM_CPU_STATE_INST_FETCH_STALL		 (1L<<15)6001#define BNX2_COM_CPU_STATE_BLOCKED_READ			 (1L<<31)6002 6003#define BNX2_COM_CPU_EVENT_MASK				0x001050086004#define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)6005#define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)6006#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)6007#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)6008#define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)6009#define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)6010#define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)6011#define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)6012#define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)6013#define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)6014#define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)6015 6016#define BNX2_COM_CPU_PROGRAM_COUNTER			0x0010501c6017#define BNX2_COM_CPU_INSTRUCTION			0x001050206018#define BNX2_COM_CPU_DATA_ACCESS			0x001050246019#define BNX2_COM_CPU_INTERRUPT_ENABLE			0x001050286020#define BNX2_COM_CPU_INTERRUPT_VECTOR			0x0010502c6021#define BNX2_COM_CPU_INTERRUPT_SAVED_PC			0x001050306022#define BNX2_COM_CPU_HW_BREAKPOINT			0x001050346023#define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)6024#define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)6025 6026#define BNX2_COM_CPU_DEBUG_VECT_PEEK			0x001050386027#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)6028#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)6029#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)6030#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)6031#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)6032#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)6033 6034#define BNX2_COM_CPU_LAST_BRANCH_ADDR			0x001050486035#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)6036#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)6037#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)6038#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)6039 6040#define BNX2_COM_CPU_REG_FILE				0x001052006041#define BNX2_COM_COMTQ_PFE_PFE_CTL			0x001052bc6042#define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT	 (1L<<0)6043#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE		 (0xfL<<4)6044#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0		 (0L<<4)6045#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1		 (1L<<4)6046#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2		 (2L<<4)6047#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3		 (3L<<4)6048#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4		 (4L<<4)6049#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5		 (5L<<4)6050#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6		 (6L<<4)6051#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7		 (7L<<4)6052#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8		 (8L<<4)6053#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9		 (9L<<4)6054#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10		 (10L<<4)6055#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11		 (11L<<4)6056#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12		 (12L<<4)6057#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13		 (13L<<4)6058#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14		 (14L<<4)6059#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15		 (15L<<4)6060#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT		 (0xfL<<12)6061#define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET		 (0x1ffL<<16)6062 6063#define BNX2_COM_COMXQ					0x001053406064#define BNX2_COM_COMXQ_FTQ_CMD				0x001053786065#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)6066#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP			 (1L<<10)6067#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0			 (0L<<10)6068#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1			 (1L<<10)6069#define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET		 (1L<<25)6070#define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA			 (1L<<26)6071#define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)6072#define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA			 (1L<<28)6073#define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)6074#define BNX2_COM_COMXQ_FTQ_CMD_POP			 (1L<<30)6075#define BNX2_COM_COMXQ_FTQ_CMD_BUSY			 (1L<<31)6076 6077#define BNX2_COM_COMXQ_FTQ_CTL				0x0010537c6078#define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE		 (1L<<0)6079#define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW			 (1L<<1)6080#define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)6081#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)6082#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)6083 6084#define BNX2_COM_COMTQ					0x001053806085#define BNX2_COM_COMTQ_FTQ_CMD				0x001053b86086#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)6087#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP			 (1L<<10)6088#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0			 (0L<<10)6089#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1			 (1L<<10)6090#define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET		 (1L<<25)6091#define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA			 (1L<<26)6092#define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)6093#define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA			 (1L<<28)6094#define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)6095#define BNX2_COM_COMTQ_FTQ_CMD_POP			 (1L<<30)6096#define BNX2_COM_COMTQ_FTQ_CMD_BUSY			 (1L<<31)6097 6098#define BNX2_COM_COMTQ_FTQ_CTL				0x001053bc6099#define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE		 (1L<<0)6100#define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW			 (1L<<1)6101#define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)6102#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)6103#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)6104 6105#define BNX2_COM_COMQ					0x001053c06106#define BNX2_COM_COMQ_FTQ_CMD				0x001053f86107#define BNX2_COM_COMQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)6108#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP			 (1L<<10)6109#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0			 (0L<<10)6110#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1			 (1L<<10)6111#define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET			 (1L<<25)6112#define BNX2_COM_COMQ_FTQ_CMD_RD_DATA			 (1L<<26)6113#define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)6114#define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA			 (1L<<28)6115#define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)6116#define BNX2_COM_COMQ_FTQ_CMD_POP			 (1L<<30)6117#define BNX2_COM_COMQ_FTQ_CMD_BUSY			 (1L<<31)6118 6119#define BNX2_COM_COMQ_FTQ_CTL				0x001053fc6120#define BNX2_COM_COMQ_FTQ_CTL_INTERVENE			 (1L<<0)6121#define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW			 (1L<<1)6122#define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)6123#define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)6124#define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)6125 6126#define BNX2_COM_SCRATCH				0x001200006127 6128#define BNX2_FW_RX_LOW_LATENCY				 0x001200586129#define BNX2_FW_RX_DROP_COUNT				 0x001200846130 6131 6132/*6133 *  cp_reg definition6134 *  offset: 0x1800006135 */6136#define BNX2_CP_CKSUM_ERROR_STATUS			0x001800006137#define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED		 (0xffffL<<0)6138#define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED		 (0xffffL<<16)6139 6140#define BNX2_CP_CPU_MODE				0x001850006141#define BNX2_CP_CPU_MODE_LOCAL_RST			 (1L<<0)6142#define BNX2_CP_CPU_MODE_STEP_ENA			 (1L<<1)6143#define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)6144#define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)6145#define BNX2_CP_CPU_MODE_MSG_BIT1			 (1L<<6)6146#define BNX2_CP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)6147#define BNX2_CP_CPU_MODE_SOFT_HALT			 (1L<<10)6148#define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)6149#define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)6150#define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)6151#define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)6152 6153#define BNX2_CP_CPU_STATE				0x001850046154#define BNX2_CP_CPU_STATE_BREAKPOINT			 (1L<<0)6155#define BNX2_CP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)6156#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)6157#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)6158#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)6159#define BNX2_CP_CPU_STATE_BAD_PC_HALTED			 (1L<<6)6160#define BNX2_CP_CPU_STATE_ALIGN_HALTED			 (1L<<7)6161#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)6162#define BNX2_CP_CPU_STATE_SOFT_HALTED			 (1L<<10)6163#define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)6164#define BNX2_CP_CPU_STATE_INTERRUPT			 (1L<<12)6165#define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)6166#define BNX2_CP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)6167#define BNX2_CP_CPU_STATE_BLOCKED_READ			 (1L<<31)6168 6169#define BNX2_CP_CPU_EVENT_MASK				0x001850086170#define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)6171#define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)6172#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)6173#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)6174#define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)6175#define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)6176#define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)6177#define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)6178#define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)6179#define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)6180#define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)6181 6182#define BNX2_CP_CPU_PROGRAM_COUNTER			0x0018501c6183#define BNX2_CP_CPU_INSTRUCTION				0x001850206184#define BNX2_CP_CPU_DATA_ACCESS				0x001850246185#define BNX2_CP_CPU_INTERRUPT_ENABLE			0x001850286186#define BNX2_CP_CPU_INTERRUPT_VECTOR			0x0018502c6187#define BNX2_CP_CPU_INTERRUPT_SAVED_PC			0x001850306188#define BNX2_CP_CPU_HW_BREAKPOINT			0x001850346189#define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)6190#define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)6191 6192#define BNX2_CP_CPU_DEBUG_VECT_PEEK			0x001850386193#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)6194#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)6195#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)6196#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)6197#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)6198#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)6199 6200#define BNX2_CP_CPU_LAST_BRANCH_ADDR			0x001850486201#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)6202#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)6203#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)6204#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)6205 6206#define BNX2_CP_CPU_REG_FILE				0x001852006207#define BNX2_CP_CPQ_PFE_PFE_CTL				0x001853bc6208#define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT		 (1L<<0)6209#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE		 (0xfL<<4)6210#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0		 (0L<<4)6211#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1		 (1L<<4)6212#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2		 (2L<<4)6213#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3		 (3L<<4)6214#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4		 (4L<<4)6215#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5		 (5L<<4)6216#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6		 (6L<<4)6217#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7		 (7L<<4)6218#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8		 (8L<<4)6219#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9		 (9L<<4)6220#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10		 (10L<<4)6221#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11		 (11L<<4)6222#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12		 (12L<<4)6223#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13		 (13L<<4)6224#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14		 (14L<<4)6225#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15		 (15L<<4)6226#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT		 (0xfL<<12)6227#define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET			 (0x1ffL<<16)6228 6229#define BNX2_CP_CPQ					0x001853c06230#define BNX2_CP_CPQ_FTQ_CMD				0x001853f86231#define BNX2_CP_CPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)6232#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP			 (1L<<10)6233#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)6234#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)6235#define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET			 (1L<<25)6236#define BNX2_CP_CPQ_FTQ_CMD_RD_DATA			 (1L<<26)6237#define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)6238#define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA			 (1L<<28)6239#define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)6240#define BNX2_CP_CPQ_FTQ_CMD_POP				 (1L<<30)6241#define BNX2_CP_CPQ_FTQ_CMD_BUSY			 (1L<<31)6242 6243#define BNX2_CP_CPQ_FTQ_CTL				0x001853fc6244#define BNX2_CP_CPQ_FTQ_CTL_INTERVENE			 (1L<<0)6245#define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW			 (1L<<1)6246#define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)6247#define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)6248#define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)6249 6250#define BNX2_CP_SCRATCH					0x001a00006251 6252#define BNX2_FW_MAX_ISCSI_CONN				 0x001a00806253 6254 6255/*6256 *  mcp_reg definition6257 *  offset: 0x1400006258 */6259#define BNX2_MCP_MCP_CONTROL				0x001400806260#define BNX2_MCP_MCP_CONTROL_SMBUS_SEL			 (1L<<30)6261#define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE		 (1L<<31)6262 6263#define BNX2_MCP_MCP_ATTENTION_STATUS			0x001400846264#define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL	 (1L<<29)6265#define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT	 (1L<<30)6266#define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT		 (1L<<31)6267 6268#define BNX2_MCP_MCP_HEARTBEAT_CONTROL			0x001400886269#define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE	 (1L<<31)6270 6271#define BNX2_MCP_MCP_HEARTBEAT_STATUS			0x0014008c6272#define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD	 (0x7ffL<<0)6273#define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID		 (1L<<31)6274 6275#define BNX2_MCP_MCP_HEARTBEAT				0x001400906276#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT	 (0x3fffffffL<<0)6277#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC	 (1L<<30)6278#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET	 (1L<<31)6279 6280#define BNX2_MCP_WATCHDOG_RESET				0x001400946281#define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET		 (1L<<31)6282 6283#define BNX2_MCP_WATCHDOG_CONTROL			0x001400986284#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT	 (0xfffffffL<<0)6285#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN		 (1L<<29)6286#define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE	 (1L<<30)6287#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE	 (1L<<31)6288 6289#define BNX2_MCP_ACCESS_LOCK				0x0014009c6290#define BNX2_MCP_ACCESS_LOCK_LOCK			 (1L<<31)6291 6292#define BNX2_MCP_TOE_ID					0x001400a06293#define BNX2_MCP_TOE_ID_FUNCTION_ID			 (1L<<31)6294 6295#define BNX2_MCP_MAILBOX_CFG				0x001400a46296#define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET		 (0x3fffL<<0)6297#define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE		 (0xfffL<<20)6298 6299#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC			0x001400a86300#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET	 (0x3fffL<<0)6301#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE	 (0xfffL<<20)6302 6303#define BNX2_MCP_MCP_DOORBELL				0x001400ac6304#define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL		 (1L<<31)6305 6306#define BNX2_MCP_DRIVER_DOORBELL			0x001400b06307#define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL	 (1L<<31)6308 6309#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC		0x001400b46310#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL	 (1L<<31)6311 6312#define BNX2_MCP_CPU_MODE				0x001450006313#define BNX2_MCP_CPU_MODE_LOCAL_RST			 (1L<<0)6314#define BNX2_MCP_CPU_MODE_STEP_ENA			 (1L<<1)6315#define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)6316#define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)6317#define BNX2_MCP_CPU_MODE_MSG_BIT1			 (1L<<6)6318#define BNX2_MCP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)6319#define BNX2_MCP_CPU_MODE_SOFT_HALT			 (1L<<10)6320#define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)6321#define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)6322#define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)6323#define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)6324 6325#define BNX2_MCP_CPU_STATE				0x001450046326#define BNX2_MCP_CPU_STATE_BREAKPOINT			 (1L<<0)6327#define BNX2_MCP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)6328#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)6329#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)6330#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)6331#define BNX2_MCP_CPU_STATE_BAD_PC_HALTED		 (1L<<6)6332#define BNX2_MCP_CPU_STATE_ALIGN_HALTED			 (1L<<7)6333#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)6334#define BNX2_MCP_CPU_STATE_SOFT_HALTED			 (1L<<10)6335#define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)6336#define BNX2_MCP_CPU_STATE_INTERRUPT			 (1L<<12)6337#define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)6338#define BNX2_MCP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)6339#define BNX2_MCP_CPU_STATE_BLOCKED_READ			 (1L<<31)6340 6341#define BNX2_MCP_CPU_EVENT_MASK				0x001450086342#define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)6343#define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)6344#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)6345#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)6346#define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)6347#define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)6348#define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)6349#define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)6350#define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)6351#define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)6352#define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)6353 6354#define BNX2_MCP_CPU_PROGRAM_COUNTER			0x0014501c6355#define BNX2_MCP_CPU_INSTRUCTION			0x001450206356#define BNX2_MCP_CPU_DATA_ACCESS			0x001450246357#define BNX2_MCP_CPU_INTERRUPT_ENABLE			0x001450286358#define BNX2_MCP_CPU_INTERRUPT_VECTOR			0x0014502c6359#define BNX2_MCP_CPU_INTERRUPT_SAVED_PC			0x001450306360#define BNX2_MCP_CPU_HW_BREAKPOINT			0x001450346361#define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)6362#define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)6363 6364#define BNX2_MCP_CPU_DEBUG_VECT_PEEK			0x001450386365#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)6366#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)6367#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)6368#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)6369#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)6370#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)6371 6372#define BNX2_MCP_CPU_LAST_BRANCH_ADDR			0x001450486373#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)6374#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)6375#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)6376#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)6377 6378#define BNX2_MCP_CPU_REG_FILE				0x001452006379#define BNX2_MCP_MCPQ					0x001453c06380#define BNX2_MCP_MCPQ_FTQ_CMD				0x001453f86381#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)6382#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP			 (1L<<10)6383#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)6384#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)6385#define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET			 (1L<<25)6386#define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA			 (1L<<26)6387#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)6388#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA			 (1L<<28)6389#define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)6390#define BNX2_MCP_MCPQ_FTQ_CMD_POP			 (1L<<30)6391#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY			 (1L<<31)6392 6393#define BNX2_MCP_MCPQ_FTQ_CTL				0x001453fc6394#define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE			 (1L<<0)6395#define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW			 (1L<<1)6396#define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)6397#define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)6398#define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)6399 6400#define BNX2_MCP_ROM					0x001500006401#define BNX2_MCP_SCRATCH				0x001600006402#define BNX2_MCP_STATE_P1				 0x0016f9c86403#define BNX2_MCP_STATE_P0				 0x0016fdc86404#define BNX2_MCP_STATE_P1_5708				 0x001699c86405#define BNX2_MCP_STATE_P0_5708				 0x00169dc86406 6407#define BNX2_SHM_HDR_SIGNATURE				BNX2_MCP_SCRATCH6408#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK			 0xffff00006409#define BNX2_SHM_HDR_SIGNATURE_SIG			 0x535300006410#define BNX2_SHM_HDR_SIGNATURE_VER_MASK			 0x000000ff6411#define BNX2_SHM_HDR_SIGNATURE_VER_ONE			 0x000000016412 6413#define BNX2_SHM_HDR_ADDR_0				BNX2_MCP_SCRATCH + 46414#define BNX2_SHM_HDR_ADDR_1				BNX2_MCP_SCRATCH + 86415 6416 6417#define NUM_MC_HASH_REGISTERS   86418 6419 6420/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0.  */6421#define PHY_BCM5706_PHY_ID                          0x002061606422 6423#define PHY_ID(id)                                  ((id) & 0xfffffff0)6424#define PHY_REV_ID(id)                              ((id) & 0xf)6425 6426/* 5708 Serdes PHY registers */6427 6428#define BCM5708S_BMCR_FORCE_2500		0x206429 6430#define BCM5708S_UP1				0xb6431 6432#define BCM5708S_UP1_2G5			0x16433 6434#define BCM5708S_BLK_ADDR			0x1f6435 6436#define BCM5708S_BLK_ADDR_DIG			0x00006437#define BCM5708S_BLK_ADDR_DIG3			0x00026438#define BCM5708S_BLK_ADDR_TX_MISC		0x00056439 6440/* Digital Block */6441#define BCM5708S_1000X_CTL1			0x106442 6443#define BCM5708S_1000X_CTL1_FIBER_MODE		0x00016444#define BCM5708S_1000X_CTL1_AUTODET_EN		0x00106445 6446#define BCM5708S_1000X_CTL2			0x116447 6448#define BCM5708S_1000X_CTL2_PLLEL_DET_EN	0x00016449 6450#define BCM5708S_1000X_STAT1			0x146451 6452#define BCM5708S_1000X_STAT1_SGMII		0x00016453#define BCM5708S_1000X_STAT1_LINK		0x00026454#define BCM5708S_1000X_STAT1_FD			0x00046455#define BCM5708S_1000X_STAT1_SPEED_MASK		0x00186456#define BCM5708S_1000X_STAT1_SPEED_10		0x00006457#define BCM5708S_1000X_STAT1_SPEED_100		0x00086458#define BCM5708S_1000X_STAT1_SPEED_1G		0x00106459#define BCM5708S_1000X_STAT1_SPEED_2G5		0x00186460#define BCM5708S_1000X_STAT1_TX_PAUSE		0x00206461#define BCM5708S_1000X_STAT1_RX_PAUSE		0x00406462 6463/* Digital3 Block */6464#define BCM5708S_DIG_3_0			0x106465 6466#define BCM5708S_DIG_3_0_USE_IEEE		0x00016467 6468/* Tx/Misc Block */6469#define BCM5708S_TX_ACTL1			0x156470 6471#define BCM5708S_TX_ACTL1_DRIVER_VCM		0x306472 6473#define BCM5708S_TX_ACTL3			0x176474 6475#define MII_BNX2_EXT_STATUS			0x116476#define EXT_STATUS_MDIX				 (1 << 13)6477 6478#define MII_BNX2_AUX_CTL			0x186479#define AUX_CTL_MISC_CTL			 0x70076480#define AUX_CTL_MISC_CTL_WIRESPEED		  (1 << 4)6481#define AUX_CTL_MISC_CTL_AUTOMDIX		  (1 << 9)6482#define AUX_CTL_MISC_CTL_WR			  (1 << 15)6483 6484#define MII_BNX2_DSP_RW_PORT			0x156485#define MII_BNX2_DSP_ADDRESS			0x176486#define MII_BNX2_DSP_EXPAND_REG			 0x0f006487#define MII_EXPAND_REG1				  (MII_BNX2_DSP_EXPAND_REG | 1)6488#define MII_EXPAND_REG1_RUDI_C			   0x206489#define MII_EXPAND_SERDES_CTL			  (MII_BNX2_DSP_EXPAND_REG | 3)6490 6491#define MII_BNX2_MISC_SHADOW			0x1c6492#define MISC_SHDW_AN_DBG			 0x68006493#define MISC_SHDW_AN_DBG_NOSYNC			  0x00026494#define MISC_SHDW_AN_DBG_RUDI_INVALID		  0x01006495#define MISC_SHDW_MODE_CTL			 0x7c006496#define MISC_SHDW_MODE_CTL_SIG_DET		  0x00106497 6498#define MII_BNX2_BLK_ADDR			0x1f6499#define MII_BNX2_BLK_ADDR_IEEE0			 0x00006500#define MII_BNX2_BLK_ADDR_GP_STATUS		 0x81206501#define MII_BNX2_GP_TOP_AN_STATUS1		  0x1b6502#define MII_BNX2_GP_TOP_AN_SPEED_MSK		   0x3f006503#define MII_BNX2_GP_TOP_AN_SPEED_10		   0x00006504#define MII_BNX2_GP_TOP_AN_SPEED_100		   0x01006505#define MII_BNX2_GP_TOP_AN_SPEED_1G		   0x02006506#define MII_BNX2_GP_TOP_AN_SPEED_2_5G		   0x03006507#define MII_BNX2_GP_TOP_AN_SPEED_1GKV		   0x0d006508#define MII_BNX2_GP_TOP_AN_FD			   0x86509#define MII_BNX2_BLK_ADDR_SERDES_DIG		 0x83006510#define MII_BNX2_SERDES_DIG_1000XCTL1		  0x106511#define MII_BNX2_SD_1000XCTL1_FIBER		   0x016512#define MII_BNX2_SD_1000XCTL1_AUTODET		   0x106513#define MII_BNX2_SERDES_DIG_MISC1		  0x186514#define MII_BNX2_SD_MISC1_FORCE_MSK		   0xf6515#define MII_BNX2_SD_MISC1_FORCE_2_5G		   0x06516#define MII_BNX2_SD_MISC1_FORCE			   0x106517#define MII_BNX2_BLK_ADDR_OVER1G		 0x83206518#define MII_BNX2_OVER1G_UP1			  0x196519#define MII_BNX2_BLK_ADDR_BAM_NXTPG		 0x83506520#define MII_BNX2_BAM_NXTPG_CTL			  0x106521#define MII_BNX2_NXTPG_CTL_BAM			   0x16522#define MII_BNX2_NXTPG_CTL_T2			   0x26523#define MII_BNX2_BLK_ADDR_CL73_USERB0		 0x83706524#define MII_BNX2_CL73_BAM_CTL1			  0x126525#define MII_BNX2_CL73_BAM_EN			   0x80006526#define MII_BNX2_CL73_BAM_STA_MGR_EN		   0x40006527#define MII_BNX2_CL73_BAM_NP_AFT_BP_EN		   0x20006528#define MII_BNX2_BLK_ADDR_AER			 0xffd06529#define MII_BNX2_AER_AER			  0x1e6530#define MII_BNX2_AER_AER_AN_MMD			   0x38006531#define MII_BNX2_BLK_ADDR_COMBO_IEEEB0		 0xffe06532 6533#define MIN_ETHERNET_PACKET_SIZE	(ETH_ZLEN - ETH_HLEN)6534#define MAX_ETHERNET_PACKET_SIZE	ETH_DATA_LEN6535#define MAX_ETHERNET_JUMBO_PACKET_SIZE	90006536 6537#define BNX2_RX_COPY_THRESH		1286538 6539#define BNX2_MISC_ENABLE_DEFAULT	0x17ffffff6540 6541#define BNX2_START_UNICAST_ADDRESS_INDEX	46542#define BNX2_END_UNICAST_ADDRESS_INDEX		76543#define BNX2_MAX_UNICAST_ADDRESSES     	(BNX2_END_UNICAST_ADDRESS_INDEX - \6544					 BNX2_START_UNICAST_ADDRESS_INDEX + 1)6545 6546#define DMA_READ_CHANS	56547#define DMA_WRITE_CHANS	36548 6549/* Use CPU native page size up to 16K for the ring sizes.  */6550#if (PAGE_SHIFT > 14)6551#define BNX2_PAGE_BITS	146552#else6553#define BNX2_PAGE_BITS	PAGE_SHIFT6554#endif6555#define BNX2_PAGE_SIZE	(1 << BNX2_PAGE_BITS)6556 6557#define BNX2_TX_DESC_CNT  (BNX2_PAGE_SIZE / sizeof(struct bnx2_tx_bd))6558#define BNX2_MAX_TX_DESC_CNT (BNX2_TX_DESC_CNT - 1)6559 6560#define BNX2_MAX_RX_RINGS	86561#define BNX2_MAX_RX_PG_RINGS	326562#define BNX2_RX_DESC_CNT  (BNX2_PAGE_SIZE / sizeof(struct bnx2_rx_bd))6563#define BNX2_MAX_RX_DESC_CNT (BNX2_RX_DESC_CNT - 1)6564#define BNX2_MAX_TOTAL_RX_DESC_CNT (BNX2_MAX_RX_DESC_CNT * BNX2_MAX_RX_RINGS)6565#define BNX2_MAX_TOTAL_RX_PG_DESC_CNT	\6566	(BNX2_MAX_RX_DESC_CNT * BNX2_MAX_RX_PG_RINGS)6567 6568#define BNX2_NEXT_TX_BD(x) (((x) & (BNX2_MAX_TX_DESC_CNT - 1)) ==	\6569		(BNX2_MAX_TX_DESC_CNT - 1)) ?				\6570	(x) + 2 : (x) + 16571 6572#define BNX2_TX_RING_IDX(x) ((x) & BNX2_MAX_TX_DESC_CNT)6573 6574#define BNX2_NEXT_RX_BD(x) (((x) & (BNX2_MAX_RX_DESC_CNT - 1)) ==	\6575		(BNX2_MAX_RX_DESC_CNT - 1)) ?				\6576	(x) + 2 : (x) + 16577 6578#define BNX2_RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)6579#define BNX2_RX_PG_RING_IDX(x) ((x) & bp->rx_max_pg_ring_idx)6580 6581#define BNX2_RX_RING(x) (((x) & ~BNX2_MAX_RX_DESC_CNT) >> (BNX2_PAGE_BITS - 4))6582#define BNX2_RX_IDX(x) ((x) & BNX2_MAX_RX_DESC_CNT)6583 6584/* Context size. */6585#define CTX_SHIFT                   76586#define CTX_SIZE                    (1 << CTX_SHIFT)6587#define CTX_MASK                    (CTX_SIZE - 1)6588#define GET_CID_ADDR(_cid)          ((_cid) << CTX_SHIFT)6589#define GET_CID(_cid_addr)          ((_cid_addr) >> CTX_SHIFT)6590 6591#define PHY_CTX_SHIFT               66592#define PHY_CTX_SIZE                (1 << PHY_CTX_SHIFT)6593#define PHY_CTX_MASK                (PHY_CTX_SIZE - 1)6594#define GET_PCID_ADDR(_pcid)        ((_pcid) << PHY_CTX_SHIFT)6595#define GET_PCID(_pcid_addr)        ((_pcid_addr) >> PHY_CTX_SHIFT)6596 6597#define MB_KERNEL_CTX_SHIFT         86598#define MB_KERNEL_CTX_SIZE          (1 << MB_KERNEL_CTX_SHIFT)6599#define MB_KERNEL_CTX_MASK          (MB_KERNEL_CTX_SIZE - 1)6600#define MB_GET_CID_ADDR(_cid)       (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))6601 6602#define MAX_CID_CNT                 0x40006603#define MAX_CID_ADDR                (GET_CID_ADDR(MAX_CID_CNT))6604#define INVALID_CID_ADDR            0xffffffff6605 6606#define TX_CID		166607#define TX_TSS_CID	326608#define RX_CID		06609#define RX_RSS_CID	46610#define RX_MAX_RSS_RINGS	76611#define RX_MAX_RINGS		(RX_MAX_RSS_RINGS + 1)6612#define TX_MAX_TSS_RINGS	76613#define TX_MAX_RINGS		(TX_MAX_TSS_RINGS + 1)6614 6615#define MB_TX_CID_ADDR	MB_GET_CID_ADDR(TX_CID)6616#define MB_RX_CID_ADDR	MB_GET_CID_ADDR(RX_CID)6617 6618/*6619 * This driver uses new build_skb() API :6620 * RX ring buffer contains pointer to kmalloc() data only,6621 * skb are built only after Hardware filled the frame.6622 */6623struct bnx2_sw_bd {6624	u8			*data;6625	DEFINE_DMA_UNMAP_ADDR(mapping);6626};6627 6628/* Its faster to compute this from data than storing it in sw_bd6629 * (less cache misses)6630 */6631static inline struct l2_fhdr *get_l2_fhdr(u8 *data)6632{6633	return (struct l2_fhdr *)(PTR_ALIGN(data, BNX2_RX_ALIGN) + NET_SKB_PAD);6634}6635 6636 6637struct bnx2_sw_pg {6638	struct page		*page;6639	DEFINE_DMA_UNMAP_ADDR(mapping);6640};6641 6642struct bnx2_sw_tx_bd {6643	struct sk_buff		*skb;6644	DEFINE_DMA_UNMAP_ADDR(mapping);6645	unsigned short		is_gso;6646	unsigned short		nr_frags;6647};6648 6649#define SW_RXBD_RING_SIZE (sizeof(struct bnx2_sw_bd) * BNX2_RX_DESC_CNT)6650#define SW_RXPG_RING_SIZE (sizeof(struct bnx2_sw_pg) * BNX2_RX_DESC_CNT)6651#define RXBD_RING_SIZE (sizeof(struct bnx2_rx_bd) * BNX2_RX_DESC_CNT)6652#define SW_TXBD_RING_SIZE (sizeof(struct bnx2_sw_tx_bd) * BNX2_TX_DESC_CNT)6653#define TXBD_RING_SIZE (sizeof(struct bnx2_tx_bd) * BNX2_TX_DESC_CNT)6654 6655/* Buffered flash (Atmel: AT45DB011B) specific information */6656#define SEEPROM_PAGE_BITS			26657#define SEEPROM_PHY_PAGE_SIZE			(1 << SEEPROM_PAGE_BITS)6658#define SEEPROM_BYTE_ADDR_MASK			(SEEPROM_PHY_PAGE_SIZE-1)6659#define SEEPROM_PAGE_SIZE			46660#define SEEPROM_TOTAL_SIZE			655366661 6662#define BUFFERED_FLASH_PAGE_BITS		96663#define BUFFERED_FLASH_PHY_PAGE_SIZE		(1 << BUFFERED_FLASH_PAGE_BITS)6664#define BUFFERED_FLASH_BYTE_ADDR_MASK		(BUFFERED_FLASH_PHY_PAGE_SIZE-1)6665#define BUFFERED_FLASH_PAGE_SIZE		2646666#define BUFFERED_FLASH_TOTAL_SIZE		0x210006667 6668#define SAIFUN_FLASH_PAGE_BITS			86669#define SAIFUN_FLASH_PHY_PAGE_SIZE		(1 << SAIFUN_FLASH_PAGE_BITS)6670#define SAIFUN_FLASH_BYTE_ADDR_MASK		(SAIFUN_FLASH_PHY_PAGE_SIZE-1)6671#define SAIFUN_FLASH_PAGE_SIZE			2566672#define SAIFUN_FLASH_BASE_TOTAL_SIZE		655366673 6674#define ST_MICRO_FLASH_PAGE_BITS		86675#define ST_MICRO_FLASH_PHY_PAGE_SIZE		(1 << ST_MICRO_FLASH_PAGE_BITS)6676#define ST_MICRO_FLASH_BYTE_ADDR_MASK		(ST_MICRO_FLASH_PHY_PAGE_SIZE-1)6677#define ST_MICRO_FLASH_PAGE_SIZE		2566678#define ST_MICRO_FLASH_BASE_TOTAL_SIZE		655366679 6680#define BCM5709_FLASH_PAGE_BITS			86681#define BCM5709_FLASH_PHY_PAGE_SIZE		(1 << BCM5709_FLASH_PAGE_BITS)6682#define BCM5709_FLASH_BYTE_ADDR_MASK		(BCM5709_FLASH_PHY_PAGE_SIZE-1)6683#define BCM5709_FLASH_PAGE_SIZE			2566684 6685#define NVRAM_TIMEOUT_COUNT			300006686 6687 6688#define FLASH_STRAP_MASK			(BNX2_NVM_CFG1_FLASH_MODE   | \6689						 BNX2_NVM_CFG1_BUFFER_MODE  | \6690						 BNX2_NVM_CFG1_PROTECT_MODE | \6691						 BNX2_NVM_CFG1_FLASH_SIZE)6692 6693#define FLASH_BACKUP_STRAP_MASK			(0xf << 26)6694 6695struct flash_spec {6696	u32 strapping;6697	u32 config1;6698	u32 config2;6699	u32 config3;6700	u32 write1;6701	u32 flags;6702#define BNX2_NV_BUFFERED	0x000000016703#define BNX2_NV_TRANSLATE	0x000000026704#define BNX2_NV_WREN		0x000000046705	u32 page_bits;6706	u32 page_size;6707	u32 addr_mask;6708	u32 total_size;6709	u8  *name;6710};6711 6712#define BNX2_MAX_MSIX_HW_VEC	96713#define BNX2_MAX_MSIX_VEC	96714#ifdef BCM_CNIC6715#define BNX2_MIN_MSIX_VEC	26716#else6717#define BNX2_MIN_MSIX_VEC	16718#endif6719 6720 6721struct bnx2_irq {6722	irq_handler_t	handler;6723	unsigned int	vector;6724	u8		requested;6725	char		name[IFNAMSIZ + 2];6726};6727 6728struct bnx2_tx_ring_info {6729	u32			tx_prod_bseq;6730	u16			tx_prod;6731	u32			tx_bidx_addr;6732	u32			tx_bseq_addr;6733 6734	struct bnx2_tx_bd	*tx_desc_ring;6735	struct bnx2_sw_tx_bd	*tx_buf_ring;6736 6737	u16			tx_cons;6738	u16			hw_tx_cons;6739 6740	dma_addr_t		tx_desc_mapping;6741};6742 6743struct bnx2_rx_ring_info {6744	u32			rx_prod_bseq;6745	u16			rx_prod;6746	u16			rx_cons;6747 6748	u32			rx_bidx_addr;6749	u32			rx_bseq_addr;6750	u32			rx_pg_bidx_addr;6751 6752	u16			rx_pg_prod;6753	u16			rx_pg_cons;6754 6755	struct bnx2_sw_bd	*rx_buf_ring;6756	struct bnx2_rx_bd	*rx_desc_ring[BNX2_MAX_RX_RINGS];6757	struct bnx2_sw_pg	*rx_pg_ring;6758	struct bnx2_rx_bd	*rx_pg_desc_ring[BNX2_MAX_RX_PG_RINGS];6759 6760	dma_addr_t		rx_desc_mapping[BNX2_MAX_RX_RINGS];6761	dma_addr_t		rx_pg_desc_mapping[BNX2_MAX_RX_PG_RINGS];6762};6763 6764struct bnx2_napi {6765	struct napi_struct	napi		____cacheline_aligned;6766	struct bnx2		*bp;6767	union {6768		struct status_block		*msi;6769		struct status_block_msix	*msix;6770	} status_blk;6771	u16			*hw_tx_cons_ptr;6772	u16			*hw_rx_cons_ptr;6773	u32 			last_status_idx;6774	u32			int_num;6775 6776#ifdef BCM_CNIC6777	u32			cnic_tag;6778	int			cnic_present;6779#endif6780 6781	struct bnx2_rx_ring_info	rx_ring;6782	struct bnx2_tx_ring_info	tx_ring;6783};6784 6785struct bnx2 {6786	/* Fields used in the tx and intr/napi performance paths are grouped */6787	/* together in the beginning of the structure. */6788	void __iomem		*regview;6789 6790	struct net_device	*dev;6791	struct pci_dev		*pdev;6792 6793	atomic_t		intr_sem;6794 6795	u32			flags;6796#define BNX2_FLAG_PCIX			0x000000016797#define BNX2_FLAG_PCI_32BIT		0x000000026798#define BNX2_FLAG_MSIX_CAP		0x000000046799#define BNX2_FLAG_NO_WOL		0x000000086800#define BNX2_FLAG_USING_MSI		0x000000206801#define BNX2_FLAG_ASF_ENABLE		0x000000406802#define BNX2_FLAG_MSI_CAP		0x000000806803#define BNX2_FLAG_ONE_SHOT_MSI		0x000001006804#define BNX2_FLAG_PCIE			0x000002006805#define BNX2_FLAG_USING_MSIX		0x000004006806#define BNX2_FLAG_USING_MSI_OR_MSIX	(BNX2_FLAG_USING_MSI | \6807					 BNX2_FLAG_USING_MSIX)6808#define BNX2_FLAG_JUMBO_BROKEN		0x000008006809#define BNX2_FLAG_CAN_KEEP_VLAN		0x000010006810#define BNX2_FLAG_BROKEN_STATS		0x000020006811 6812	struct bnx2_napi	bnx2_napi[BNX2_MAX_MSIX_VEC];6813 6814	u32			rx_buf_use_size;	/* useable size */6815	u32			rx_buf_size;		/* with alignment */6816	u32			rx_copy_thresh;6817	u32			rx_jumbo_thresh;6818	u32			rx_max_ring_idx;6819	u32			rx_max_pg_ring_idx;6820 6821	/* TX constants */6822	int		tx_ring_size;6823	u32		tx_wake_thresh;6824 6825#ifdef BCM_CNIC6826	struct cnic_ops	__rcu	*cnic_ops;6827	void			*cnic_data;6828#endif6829 6830	/* End of fields used in the performance code paths. */6831 6832	unsigned int		current_interval;6833#define BNX2_TIMER_INTERVAL		HZ6834#define BNX2_SERDES_AN_TIMEOUT		(HZ / 3)6835#define BNX2_SERDES_FORCED_TIMEOUT	(HZ / 10)6836 6837	struct			timer_list timer;6838	struct work_struct	reset_task;6839 6840	/* Used to synchronize phy accesses. */6841	spinlock_t		phy_lock;6842	spinlock_t		indirect_lock;6843 6844	u32			phy_flags;6845#define BNX2_PHY_FLAG_SERDES			0x000000016846#define BNX2_PHY_FLAG_CRC_FIX			0x000000026847#define BNX2_PHY_FLAG_PARALLEL_DETECT		0x000000046848#define BNX2_PHY_FLAG_2_5G_CAPABLE		0x000000086849#define BNX2_PHY_FLAG_INT_MODE_MASK		0x000003006850#define BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING	0x000001006851#define BNX2_PHY_FLAG_INT_MODE_LINK_READY	0x000002006852#define BNX2_PHY_FLAG_DIS_EARLY_DAC		0x000004006853#define BNX2_PHY_FLAG_REMOTE_PHY_CAP		0x000008006854#define BNX2_PHY_FLAG_FORCED_DOWN		0x000010006855#define BNX2_PHY_FLAG_NO_PARALLEL		0x000020006856#define BNX2_PHY_FLAG_MDIX			0x000040006857 6858	u32			mii_bmcr;6859	u32			mii_bmsr;6860	u32			mii_bmsr1;6861	u32			mii_adv;6862	u32			mii_lpa;6863	u32			mii_up1;6864 6865	u32			chip_id;6866	/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */6867#define BNX2_CHIP(bp)			(((bp)->chip_id) & 0xffff0000)6868#define BNX2_CHIP_5706			0x570600006869#define BNX2_CHIP_5708			0x570800006870#define BNX2_CHIP_5709			0x570900006871 6872#define BNX2_CHIP_REV(bp)		(((bp)->chip_id) & 0x0000f000)6873#define BNX2_CHIP_REV_Ax		0x000000006874#define BNX2_CHIP_REV_Bx		0x000010006875#define BNX2_CHIP_REV_Cx		0x000020006876 6877#define BNX2_CHIP_METAL(bp)		(((bp)->chip_id) & 0x00000ff0)6878#define BNX2_CHIP_BOND(bp)		(((bp)->chip_id) & 0x0000000f)6879 6880#define BNX2_CHIP_ID(bp)		(((bp)->chip_id) & 0xfffffff0)6881#define BNX2_CHIP_ID_5706_A0		0x570600006882#define BNX2_CHIP_ID_5706_A1			0x570600106883#define BNX2_CHIP_ID_5706_A2			0x570600206884#define BNX2_CHIP_ID_5708_A0			0x570800006885#define BNX2_CHIP_ID_5708_B0			0x570810006886#define BNX2_CHIP_ID_5708_B1			0x570810106887#define BNX2_CHIP_ID_5709_A0			0x570900006888#define BNX2_CHIP_ID_5709_A1			0x570900106889 6890/* A serdes chip will have the first bit of the bond id set. */6891#define BNX2_CHIP_BOND_SERDES_BIT		0x016892 6893	u32			phy_addr;6894	u32			phy_id;6895 6896	u16			bus_speed_mhz;6897	u8			wol;6898 6899	u8			pad;6900 6901	u16			fw_wr_seq;6902	u16			fw_drv_pulse_wr_seq;6903	u32			fw_last_msg;6904 6905	int			rx_max_ring;6906	int			rx_ring_size;6907 6908	int			rx_max_pg_ring;6909	int			rx_pg_ring_size;6910 6911	u16			tx_quick_cons_trip;6912	u16			tx_quick_cons_trip_int;6913	u16			rx_quick_cons_trip;6914	u16			rx_quick_cons_trip_int;6915	u16			comp_prod_trip;6916	u16			comp_prod_trip_int;6917	u16			tx_ticks;6918	u16			tx_ticks_int;6919	u16			com_ticks;6920	u16			com_ticks_int;6921	u16			cmd_ticks;6922	u16			cmd_ticks_int;6923	u16			rx_ticks;6924	u16			rx_ticks_int;6925 6926	u32			stats_ticks;6927 6928	dma_addr_t		status_blk_mapping;6929 6930	void *status_blk;6931	struct statistics_block	*stats_blk;6932	struct statistics_block	*temp_stats_blk;6933	dma_addr_t		stats_blk_mapping;6934 6935	int			ctx_pages;6936	void			*ctx_blk[4];6937	dma_addr_t		ctx_blk_mapping[4];6938 6939	u32			hc_cmd;6940	u32			rx_mode;6941 6942	u16			req_line_speed;6943	u8			req_duplex;6944 6945	u8			phy_port;6946	u8			link_up;6947 6948	u16			line_speed;6949	u8			duplex;6950	u8			flow_ctrl;	/* actual flow ctrl settings */6951						/* may be different from     */6952						/* req_flow_ctrl if autoneg  */6953	u32			advertising;6954 6955	u8			req_flow_ctrl;	/* flow ctrl advertisement */6956						/* settings or forced      */6957						/* settings                */6958	u8			autoneg;6959#define AUTONEG_SPEED		16960#define AUTONEG_FLOW_CTRL	26961 6962	u8			loopback;6963#define MAC_LOOPBACK		16964#define PHY_LOOPBACK		26965 6966	u8			serdes_an_pending;6967 6968	u8			mac_addr[8];6969 6970	u32			shmem_base;6971 6972	char			fw_version[32];6973 6974	int			pm_cap;6975	int			pcix_cap;6976 6977	const struct flash_spec	*flash_info;6978	u32			flash_size;6979 6980	int			status_stats_size;6981 6982	struct bnx2_irq		irq_tbl[BNX2_MAX_MSIX_VEC];6983	int			irq_nvecs;6984 6985	u8			func;6986 6987	u8			num_tx_rings;6988	u8			num_rx_rings;6989 6990	int			num_req_tx_rings;6991	int			num_req_rx_rings;6992 6993	u32 			leds_save;6994	u32			idle_chk_status_idx;6995 6996#ifdef BCM_CNIC6997	struct mutex		cnic_lock;6998	struct cnic_eth_dev	cnic_eth_dev;6999	struct cnic_eth_dev	*(*cnic_probe)(struct net_device *);7000#endif7001 7002	const struct firmware	*mips_firmware;7003	const struct firmware	*rv2p_firmware;7004};7005 7006#define BNX2_RD(bp, offset)					\7007	readl(bp->regview + offset)7008 7009#define BNX2_WR(bp, offset, val)					\7010	writel(val, bp->regview + offset)7011 7012#define BNX2_WR16(bp, offset, val)				\7013	writew(val, bp->regview + offset)7014 7015struct cpu_reg {7016	u32 mode;7017	u32 mode_value_halt;7018	u32 mode_value_sstep;7019 7020	u32 state;7021	u32 state_value_clear;7022 7023	u32 gpr0;7024	u32 evmask;7025	u32 pc;7026	u32 inst;7027	u32 bp;7028 7029	u32 spad_base;7030 7031	u32 mips_view_base;7032};7033 7034struct bnx2_fw_file_section {7035	__be32 addr;7036	__be32 len;7037	__be32 offset;7038};7039 7040struct bnx2_mips_fw_file_entry {7041	__be32 start_addr;7042	struct bnx2_fw_file_section text;7043	struct bnx2_fw_file_section data;7044	struct bnx2_fw_file_section rodata;7045};7046 7047struct bnx2_rv2p_fw_file_entry {7048	struct bnx2_fw_file_section rv2p;7049	__be32 fixup[8];7050};7051 7052struct bnx2_mips_fw_file {7053	struct bnx2_mips_fw_file_entry com;7054	struct bnx2_mips_fw_file_entry cp;7055	struct bnx2_mips_fw_file_entry rxp;7056	struct bnx2_mips_fw_file_entry tpat;7057	struct bnx2_mips_fw_file_entry txp;7058};7059 7060struct bnx2_rv2p_fw_file {7061	struct bnx2_rv2p_fw_file_entry proc1;7062	struct bnx2_rv2p_fw_file_entry proc2;7063};7064 7065#define RV2P_P1_FIXUP_PAGE_SIZE_IDX		07066#define RV2P_BD_PAGE_SIZE_MSK			0xffff7067#define RV2P_BD_PAGE_SIZE			((BNX2_PAGE_SIZE / 16) - 1)7068 7069#define RV2P_PROC1                              07070#define RV2P_PROC2                              17071 7072 7073/* This value (in milliseconds) determines the frequency of the driver7074 * issuing the PULSE message code.  The firmware monitors this periodic7075 * pulse to determine when to switch to an OS-absent mode. */7076#define BNX2_DRV_PULSE_PERIOD_MS                 2507077 7078/* This value (in milliseconds) determines how long the driver should7079 * wait for an acknowledgement from the firmware before timing out.  Once7080 * the firmware has timed out, the driver will assume there is no firmware7081 * running and there won't be any firmware-driver synchronization during a7082 * driver reset. */7083#define BNX2_FW_ACK_TIME_OUT_MS                  10007084 7085 7086#define BNX2_DRV_RESET_SIGNATURE		0x000000007087#define BNX2_DRV_RESET_SIGNATURE_MAGIC		 0x4841564b /* HAVK */7088//#define DRV_RESET_SIGNATURE_MAGIC		 0x47495352 /* RSIG */7089 7090#define BNX2_DRV_MB				0x000000047091#define BNX2_DRV_MSG_CODE			 0xff0000007092#define BNX2_DRV_MSG_CODE_RESET			 0x010000007093#define BNX2_DRV_MSG_CODE_UNLOAD		 0x020000007094#define BNX2_DRV_MSG_CODE_SHUTDOWN		 0x030000007095#define BNX2_DRV_MSG_CODE_SUSPEND_WOL		 0x040000007096#define BNX2_DRV_MSG_CODE_FW_TIMEOUT		 0x050000007097#define BNX2_DRV_MSG_CODE_PULSE			 0x060000007098#define BNX2_DRV_MSG_CODE_DIAG			 0x070000007099#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL	 0x090000007100#define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN		 0x0b0000007101#define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE	 0x0d0000007102#define BNX2_DRV_MSG_CODE_CMD_SET_LINK		 0x100000007103 7104#define BNX2_DRV_MSG_DATA			 0x00ff00007105#define BNX2_DRV_MSG_DATA_WAIT0			 0x000100007106#define BNX2_DRV_MSG_DATA_WAIT1			 0x000200007107#define BNX2_DRV_MSG_DATA_WAIT2			 0x000300007108#define BNX2_DRV_MSG_DATA_WAIT3			 0x000400007109 7110#define BNX2_DRV_MSG_SEQ			 0x0000ffff7111 7112#define BNX2_FW_MB				0x000000087113#define BNX2_FW_MSG_ACK				 0x0000ffff7114#define BNX2_FW_MSG_STATUS_MASK			 0x00ff00007115#define BNX2_FW_MSG_STATUS_OK			 0x000000007116#define BNX2_FW_MSG_STATUS_FAILURE		 0x00ff00007117 7118#define BNX2_LINK_STATUS			0x0000000c7119#define BNX2_LINK_STATUS_INIT_VALUE		 0xffffffff7120#define BNX2_LINK_STATUS_LINK_UP		 0x17121#define BNX2_LINK_STATUS_LINK_DOWN		 0x07122#define BNX2_LINK_STATUS_SPEED_MASK		 0x1e7123#define BNX2_LINK_STATUS_AN_INCOMPLETE		 (0<<1)7124#define BNX2_LINK_STATUS_10HALF			 (1<<1)7125#define BNX2_LINK_STATUS_10FULL			 (2<<1)7126#define BNX2_LINK_STATUS_100HALF		 (3<<1)7127#define BNX2_LINK_STATUS_100BASE_T4		 (4<<1)7128#define BNX2_LINK_STATUS_100FULL		 (5<<1)7129#define BNX2_LINK_STATUS_1000HALF		 (6<<1)7130#define BNX2_LINK_STATUS_1000FULL		 (7<<1)7131#define BNX2_LINK_STATUS_2500HALF		 (8<<1)7132#define BNX2_LINK_STATUS_2500FULL		 (9<<1)7133#define BNX2_LINK_STATUS_AN_ENABLED		 (1<<5)7134#define BNX2_LINK_STATUS_AN_COMPLETE		 (1<<6)7135#define BNX2_LINK_STATUS_PARALLEL_DET		 (1<<7)7136#define BNX2_LINK_STATUS_RESERVED		 (1<<8)7137#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL	 (1<<9)7138#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF	 (1<<10)7139#define BNX2_LINK_STATUS_PARTNER_AD_100BT4	 (1<<11)7140#define BNX2_LINK_STATUS_PARTNER_AD_100FULL	 (1<<12)7141#define BNX2_LINK_STATUS_PARTNER_AD_100HALF	 (1<<13)7142#define BNX2_LINK_STATUS_PARTNER_AD_10FULL	 (1<<14)7143#define BNX2_LINK_STATUS_PARTNER_AD_10HALF	 (1<<15)7144#define BNX2_LINK_STATUS_TX_FC_ENABLED		 (1<<16)7145#define BNX2_LINK_STATUS_RX_FC_ENABLED		 (1<<17)7146#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP	 (1<<18)7147#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP	 (1<<19)7148#define BNX2_LINK_STATUS_SERDES_LINK		 (1<<20)7149#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL	 (1<<21)7150#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF	 (1<<22)7151#define BNX2_LINK_STATUS_HEART_BEAT_EXPIRED	 (1<<31)7152 7153#define BNX2_DRV_PULSE_MB			0x000000107154#define BNX2_DRV_PULSE_SEQ_MASK			 0x00007fff7155 7156/* Indicate to the firmware not to go into the7157 * OS absent when it is not getting driver pulse.7158 * This is used for debugging. */7159#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE	 0x000800007160 7161#define BNX2_DRV_MB_ARG0			0x000000147162#define BNX2_NETLINK_SET_LINK_SPEED_10HALF	 (1<<0)7163#define BNX2_NETLINK_SET_LINK_SPEED_10FULL	 (1<<1)7164#define BNX2_NETLINK_SET_LINK_SPEED_10		 \7165	(BNX2_NETLINK_SET_LINK_SPEED_10HALF |	 \7166	 BNX2_NETLINK_SET_LINK_SPEED_10FULL)7167#define BNX2_NETLINK_SET_LINK_SPEED_100HALF	 (1<<2)7168#define BNX2_NETLINK_SET_LINK_SPEED_100FULL	 (1<<3)7169#define BNX2_NETLINK_SET_LINK_SPEED_100		 \7170	(BNX2_NETLINK_SET_LINK_SPEED_100HALF |	 \7171	 BNX2_NETLINK_SET_LINK_SPEED_100FULL)7172#define BNX2_NETLINK_SET_LINK_SPEED_1GHALF	 (1<<4)7173#define BNX2_NETLINK_SET_LINK_SPEED_1GFULL	 (1<<5)7174#define BNX2_NETLINK_SET_LINK_SPEED_2G5HALF	 (1<<6)7175#define BNX2_NETLINK_SET_LINK_SPEED_2G5FULL	 (1<<7)7176#define BNX2_NETLINK_SET_LINK_SPEED_10GHALF	 (1<<8)7177#define BNX2_NETLINK_SET_LINK_SPEED_10GFULL	 (1<<9)7178#define BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG	 (1<<10)7179#define BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE	 (1<<11)7180#define BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE	 (1<<12)7181#define BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE	 (1<<13)7182#define BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED	 (1<<14)7183#define BNX2_NETLINK_SET_LINK_PHY_RESET		 (1<<15)7184 7185#define BNX2_DEV_INFO_SIGNATURE			0x000000207186#define BNX2_DEV_INFO_SIGNATURE_MAGIC		 0x445649007187#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK	 0xffffff007188#define BNX2_DEV_INFO_FEATURE_CFG_VALID		 0x017189#define BNX2_DEV_INFO_SECONDARY_PORT		 0x807190#define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE		 0x407191 7192#define BNX2_SHARED_HW_CFG_PART_NUM		0x000000247193 7194#define BNX2_SHARED_HW_CFG_POWER_DISSIPATED	0x000000347195#define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK	 0xff0000007196#define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK	 0xff00007197#define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK	 0xff007198#define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK	 0xff7199 7200#define BNX2_SHARED_HW_CFG POWER_CONSUMED	0x000000387201#define BNX2_SHARED_HW_CFG_CONFIG		0x0000003c7202#define BNX2_SHARED_HW_CFG_DESIGN_NIC		 07203#define BNX2_SHARED_HW_CFG_DESIGN_LOM		 0x17204#define BNX2_SHARED_HW_CFG_PHY_COPPER		 07205#define BNX2_SHARED_HW_CFG_PHY_FIBER		 0x27206#define BNX2_SHARED_HW_CFG_PHY_2_5G		 0x207207#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE	 0x407208#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS	 87209#define BNX2_SHARED_HW_CFG_LED_MODE_MASK	 0x3007210#define BNX2_SHARED_HW_CFG_LED_MODE_MAC		 07211#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1	 0x1007212#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2	 0x2007213#define BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX	 0x80007214 7215#define BNX2_SHARED_HW_CFG_CONFIG2		0x000000407216#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK	 0x00fff0007217 7218#define BNX2_DEV_INFO_BC_REV			0x0000004c7219 7220#define BNX2_PORT_HW_CFG_MAC_UPPER		0x000000507221#define BNX2_PORT_HW_CFG_UPPERMAC_MASK		 0xffff7222 7223#define BNX2_PORT_HW_CFG_MAC_LOWER		0x000000547224#define BNX2_PORT_HW_CFG_CONFIG			0x000000587225#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK	 0x0000ffff7226#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK	 0x001f00007227#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN	 0x000000007228#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G	 0x000300007229#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G	 0x000400007230 7231#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER	0x000000687232#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER	0x0000006c7233#define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER	0x000000707234#define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER	0x000000747235#define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER	0x000000787236#define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER	0x0000007c7237 7238#define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2	0x000000b47239 7240#define BNX2_DEV_INFO_FORMAT_REV		0x000000c47241#define BNX2_DEV_INFO_FORMAT_REV_MASK		 0xff0000007242#define BNX2_DEV_INFO_FORMAT_REV_ID		 ('A' << 24)7243 7244#define BNX2_SHARED_FEATURE			0x000000c87245#define BNX2_SHARED_FEATURE_MASK		 0xffffffff7246 7247#define BNX2_PORT_FEATURE			0x000000d87248#define BNX2_PORT2_FEATURE			0x00000014c7249#define BNX2_PORT_FEATURE_WOL_ENABLED		 0x010000007250#define BNX2_PORT_FEATURE_MBA_ENABLED		 0x020000007251#define BNX2_PORT_FEATURE_ASF_ENABLED		 0x040000007252#define BNX2_PORT_FEATURE_IMD_ENABLED		 0x080000007253#define BNX2_PORT_FEATURE_BAR1_SIZE_MASK	 0xf7254#define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED	 0x07255#define BNX2_PORT_FEATURE_BAR1_SIZE_64K		 0x17256#define BNX2_PORT_FEATURE_BAR1_SIZE_128K	 0x27257#define BNX2_PORT_FEATURE_BAR1_SIZE_256K	 0x37258#define BNX2_PORT_FEATURE_BAR1_SIZE_512K	 0x47259#define BNX2_PORT_FEATURE_BAR1_SIZE_1M		 0x57260#define BNX2_PORT_FEATURE_BAR1_SIZE_2M		 0x67261#define BNX2_PORT_FEATURE_BAR1_SIZE_4M		 0x77262#define BNX2_PORT_FEATURE_BAR1_SIZE_8M		 0x87263#define BNX2_PORT_FEATURE_BAR1_SIZE_16M		 0x97264#define BNX2_PORT_FEATURE_BAR1_SIZE_32M		 0xa7265#define BNX2_PORT_FEATURE_BAR1_SIZE_64M		 0xb7266#define BNX2_PORT_FEATURE_BAR1_SIZE_128M	 0xc7267#define BNX2_PORT_FEATURE_BAR1_SIZE_256M	 0xd7268#define BNX2_PORT_FEATURE_BAR1_SIZE_512M	 0xe7269#define BNX2_PORT_FEATURE_BAR1_SIZE_1G		 0xf7270 7271#define BNX2_PORT_FEATURE_WOL			0xdc7272#define BNX2_PORT2_FEATURE_WOL			0x1507273#define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS	 47274#define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK	 0x307275#define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE	 07276#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC	 0x107277#define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI	 0x207278#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI	 0x307279#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK	 0xf7280#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG	 07281#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF	 17282#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL	 27283#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 37284#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 47285#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF	 57286#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL	 67287#define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000	 0x407288#define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x4007289#define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP	 0x8007290 7291#define BNX2_PORT_FEATURE_MBA			0xe07292#define BNX2_PORT2_FEATURE_MBA			0x1547293#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS	 07294#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK	 0x37295#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE	 07296#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL	 17297#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP	 27298#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS	 27299#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK	 0x3c7300#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG	 07301#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF	 0x47302#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL	 0x87303#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF	 0xc7304#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL	 0x107305#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF	 0x147306#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL	 0x187307#define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE	 0x407308#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S	 07309#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B	 0x807310#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS	 87311#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK	 0xff007312#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED	 07313#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K	 0x1007314#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K	 0x2007315#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K	 0x3007316#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K	 0x4007317#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K	 0x5007318#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K	 0x6007319#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K	 0x7007320#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K	 0x8007321#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K	 0x9007322#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K	 0xa007323#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M	 0xb007324#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M	 0xc007325#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M	 0xd007326#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M	 0xe007327#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M	 0xf007328#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS	 167329#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK	 0xf00007330#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS	 207331#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK	 0x3000007332#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO	 07333#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS	 0x1000007334#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H	 0x2000007335#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H	 0x3000007336 7337#define BNX2_PORT_FEATURE_IMD			0xe47338#define BNX2_PORT2_FEATURE_IMD			0x1587339#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT	 07340#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE	 17341 7342#define BNX2_PORT_FEATURE_VLAN			0xe87343#define BNX2_PORT2_FEATURE_VLAN			0x15c7344#define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK	 0xffff7345#define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE	 0x100007346 7347#define BNX2_MFW_VER_PTR			0x00000014c7348 7349#define BNX2_BC_STATE_RESET_TYPE		0x000001c07350#define BNX2_BC_STATE_RESET_TYPE_SIG		 0x000052547351#define BNX2_BC_STATE_RESET_TYPE_SIG_MASK	 0x0000ffff7352#define BNX2_BC_STATE_RESET_TYPE_NONE	 (BNX2_BC_STATE_RESET_TYPE_SIG | \7353					  0x00010000)7354#define BNX2_BC_STATE_RESET_TYPE_PCI	 (BNX2_BC_STATE_RESET_TYPE_SIG | \7355					  0x00020000)7356#define BNX2_BC_STATE_RESET_TYPE_VAUX	 (BNX2_BC_STATE_RESET_TYPE_SIG | \7357					  0x00030000)7358#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK	 DRV_MSG_CODE7359#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \7360					    DRV_MSG_CODE_RESET)7361#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \7362					     DRV_MSG_CODE_UNLOAD)7363#define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \7364					       DRV_MSG_CODE_SHUTDOWN)7365#define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \7366					  DRV_MSG_CODE_WOL)7367#define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \7368					   DRV_MSG_CODE_DIAG)7369#define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \7370					     (msg))7371 7372#define BNX2_BC_RESET_TYPE			0x000001c07373 7374#define BNX2_BC_STATE				0x000001c47375#define BNX2_BC_STATE_ERR_MASK			 0x0000ff007376#define BNX2_BC_STATE_SIGN			 0x425300007377#define BNX2_BC_STATE_SIGN_MASK			 0xffff00007378#define BNX2_BC_STATE_BC1_START			 (BNX2_BC_STATE_SIGN | 0x1)7379#define BNX2_BC_STATE_GET_NVM_CFG1		 (BNX2_BC_STATE_SIGN | 0x2)7380#define BNX2_BC_STATE_PROG_BAR			 (BNX2_BC_STATE_SIGN | 0x3)7381#define BNX2_BC_STATE_INIT_VID			 (BNX2_BC_STATE_SIGN | 0x4)7382#define BNX2_BC_STATE_GET_NVM_CFG2		 (BNX2_BC_STATE_SIGN | 0x5)7383#define BNX2_BC_STATE_APPLY_WKARND		 (BNX2_BC_STATE_SIGN | 0x6)7384#define BNX2_BC_STATE_LOAD_BC2			 (BNX2_BC_STATE_SIGN | 0x7)7385#define BNX2_BC_STATE_GOING_BC2			 (BNX2_BC_STATE_SIGN | 0x8)7386#define BNX2_BC_STATE_GOING_DIAG		 (BNX2_BC_STATE_SIGN | 0x9)7387#define BNX2_BC_STATE_RT_FINAL_INIT		 (BNX2_BC_STATE_SIGN | 0x81)7388#define BNX2_BC_STATE_RT_WKARND			 (BNX2_BC_STATE_SIGN | 0x82)7389#define BNX2_BC_STATE_RT_DRV_PULSE		 (BNX2_BC_STATE_SIGN | 0x83)7390#define BNX2_BC_STATE_RT_FIOEVTS		 (BNX2_BC_STATE_SIGN | 0x84)7391#define BNX2_BC_STATE_RT_DRV_CMD		 (BNX2_BC_STATE_SIGN | 0x85)7392#define BNX2_BC_STATE_RT_LOW_POWER		 (BNX2_BC_STATE_SIGN | 0x86)7393#define BNX2_BC_STATE_RT_SET_WOL		 (BNX2_BC_STATE_SIGN | 0x87)7394#define BNX2_BC_STATE_RT_OTHER_FW		 (BNX2_BC_STATE_SIGN | 0x88)7395#define BNX2_BC_STATE_RT_GOING_D3		 (BNX2_BC_STATE_SIGN | 0x89)7396#define BNX2_BC_STATE_ERR_BAD_VERSION		 (BNX2_BC_STATE_SIGN | 0x0100)7397#define BNX2_BC_STATE_ERR_BAD_BC2_CRC		 (BNX2_BC_STATE_SIGN | 0x0200)7398#define BNX2_BC_STATE_ERR_BC1_LOOP		 (BNX2_BC_STATE_SIGN | 0x0300)7399#define BNX2_BC_STATE_ERR_UNKNOWN_CMD		 (BNX2_BC_STATE_SIGN | 0x0400)7400#define BNX2_BC_STATE_ERR_DRV_DEAD		 (BNX2_BC_STATE_SIGN | 0x0500)7401#define BNX2_BC_STATE_ERR_NO_RXP		 (BNX2_BC_STATE_SIGN | 0x0600)7402#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF		 (BNX2_BC_STATE_SIGN | 0x0700)7403 7404#define BNX2_BC_STATE_CONDITION			0x000001c87405#define BNX2_CONDITION_MFW_RUN_UNKNOWN		 0x000000007406#define BNX2_CONDITION_MFW_RUN_IPMI		 0x000020007407#define BNX2_CONDITION_MFW_RUN_UMP		 0x000040007408#define BNX2_CONDITION_MFW_RUN_NCSI		 0x000060007409#define BNX2_CONDITION_MFW_RUN_NONE		 0x0000e0007410#define BNX2_CONDITION_MFW_RUN_MASK		 0x0000e0007411#define BNX2_CONDITION_PM_STATE_MASK		 0x000300007412#define BNX2_CONDITION_PM_STATE_FULL		 0x000300007413#define BNX2_CONDITION_PM_STATE_PREP		 0x000200007414#define BNX2_CONDITION_PM_STATE_UNPREP		 0x000100007415 7416#define BNX2_BC_STATE_DEBUG_CMD			0x1dc7417#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE	 0x424400007418#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK	 0xffff00007419#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK	 0xffff7420#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE	 0xffff7421 7422#define BNX2_FW_EVT_CODE_MB			0x3547423#define BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT 0x000000007424#define BNX2_FW_EVT_CODE_LINK_EVENT		 0x000000017425 7426#define BNX2_DRV_ACK_CAP_MB			0x3647427#define BNX2_DRV_ACK_CAP_SIGNATURE		 0x354500007428#define BNX2_CAPABILITY_SIGNATURE_MASK		 0xFFFF00007429 7430#define BNX2_FW_CAP_MB				0x3687431#define BNX2_FW_CAP_SIGNATURE			 0xaa5500007432#define BNX2_FW_ACK_DRV_SIGNATURE		 0x525000007433#define BNX2_FW_CAP_SIGNATURE_MASK		 0xffff00007434#define BNX2_FW_CAP_REMOTE_PHY_CAPABLE		 0x000000017435#define BNX2_FW_CAP_REMOTE_PHY_PRESENT		 0x000000027436#define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN		 0x000000087437#define BNX2_FW_CAP_BC_CAN_KEEP_VLAN		 0x000000107438#define BNX2_FW_CAP_CAN_KEEP_VLAN	(BNX2_FW_CAP_BC_CAN_KEEP_VLAN | \7439					 BNX2_FW_CAP_MFW_CAN_KEEP_VLAN)7440 7441#define BNX2_RPHY_SIGNATURE			0x36c7442#define BNX2_RPHY_LOAD_SIGNATURE		 0x5a5a5a5a7443 7444#define BNX2_RPHY_FLAGS				0x3707445#define BNX2_RPHY_SERDES_LINK			0x3747446#define BNX2_RPHY_COPPER_LINK			0x3787447 7448#define BNX2_ISCSI_INITIATOR			0x3dc7449#define BNX2_ISCSI_INITIATOR_EN			 0x000800007450 7451#define BNX2_ISCSI_MAX_CONN			0x3e47452#define BNX2_ISCSI_MAX_CONN_MASK		 0xffff00007453#define BNX2_ISCSI_MAX_CONN_SHIFT		 167454 7455#define HOST_VIEW_SHMEM_BASE			0x167c007456 7457#define DP_SHMEM_LINE(bp, offset)					\7458	netdev_err(bp->dev, "DEBUG: %08x: %08x %08x %08x %08x\n",	\7459		   offset,						\7460		   bnx2_shmem_rd(bp, offset),				\7461		   bnx2_shmem_rd(bp, offset + 4),			\7462		   bnx2_shmem_rd(bp, offset + 8),			\7463		   bnx2_shmem_rd(bp, offset + 12))7464 7465#endif7466