brintos / linux-shallow public Read only

1/* bnx2x_hsi.h: Qlogic Everest network driver.2 *3 * Copyright (c) 2007-2013 Broadcom Corporation4 * Copyright (c) 2014 QLogic Corporation5 * All rights reserved6 *7 * This program is free software; you can redistribute it and/or modify8 * it under the terms of the GNU General Public License as published by9 * the Free Software Foundation.10 */11#ifndef BNX2X_HSI_H12#define BNX2X_HSI_H13 14#include "bnx2x_fw_defs.h"15#include "bnx2x_mfw_req.h"16 17#define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e18 19struct license_key {20	u32 reserved[6];21 22	u32 max_iscsi_conn;23#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK	0xFFFF24#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT	025#define BNX2X_MAX_ISCSI_INIT_CONN_MASK	0xFFFF000026#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT	1627 28	u32 reserved_a;29 30	u32 max_fcoe_conn;31#define BNX2X_MAX_FCOE_TRGT_CONN_MASK	0xFFFF32#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT	033#define BNX2X_MAX_FCOE_INIT_CONN_MASK	0xFFFF000034#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT	1635 36	u32 reserved_b[4];37};38 39/****************************************************************************40 * Shared HW configuration                                                  *41 ****************************************************************************/42#define PIN_CFG_NA                          0x0000000043#define PIN_CFG_GPIO0_P0                    0x0000000144#define PIN_CFG_GPIO1_P0                    0x0000000245#define PIN_CFG_GPIO2_P0                    0x0000000346#define PIN_CFG_GPIO3_P0                    0x0000000447#define PIN_CFG_GPIO0_P1                    0x0000000548#define PIN_CFG_GPIO1_P1                    0x0000000649#define PIN_CFG_GPIO2_P1                    0x0000000750#define PIN_CFG_GPIO3_P1                    0x0000000851#define PIN_CFG_EPIO0                       0x0000000952#define PIN_CFG_EPIO1                       0x0000000a53#define PIN_CFG_EPIO2                       0x0000000b54#define PIN_CFG_EPIO3                       0x0000000c55#define PIN_CFG_EPIO4                       0x0000000d56#define PIN_CFG_EPIO5                       0x0000000e57#define PIN_CFG_EPIO6                       0x0000000f58#define PIN_CFG_EPIO7                       0x0000001059#define PIN_CFG_EPIO8                       0x0000001160#define PIN_CFG_EPIO9                       0x0000001261#define PIN_CFG_EPIO10                      0x0000001362#define PIN_CFG_EPIO11                      0x0000001463#define PIN_CFG_EPIO12                      0x0000001564#define PIN_CFG_EPIO13                      0x0000001665#define PIN_CFG_EPIO14                      0x0000001766#define PIN_CFG_EPIO15                      0x0000001867#define PIN_CFG_EPIO16                      0x0000001968#define PIN_CFG_EPIO17                      0x0000001a69#define PIN_CFG_EPIO18                      0x0000001b70#define PIN_CFG_EPIO19                      0x0000001c71#define PIN_CFG_EPIO20                      0x0000001d72#define PIN_CFG_EPIO21                      0x0000001e73#define PIN_CFG_EPIO22                      0x0000001f74#define PIN_CFG_EPIO23                      0x0000002075#define PIN_CFG_EPIO24                      0x0000002176#define PIN_CFG_EPIO25                      0x0000002277#define PIN_CFG_EPIO26                      0x0000002378#define PIN_CFG_EPIO27                      0x0000002479#define PIN_CFG_EPIO28                      0x0000002580#define PIN_CFG_EPIO29                      0x0000002681#define PIN_CFG_EPIO30                      0x0000002782#define PIN_CFG_EPIO31                      0x0000002883 84/* EPIO definition */85#define EPIO_CFG_NA                         0x0000000086#define EPIO_CFG_EPIO0                      0x0000000187#define EPIO_CFG_EPIO1                      0x0000000288#define EPIO_CFG_EPIO2                      0x0000000389#define EPIO_CFG_EPIO3                      0x0000000490#define EPIO_CFG_EPIO4                      0x0000000591#define EPIO_CFG_EPIO5                      0x0000000692#define EPIO_CFG_EPIO6                      0x0000000793#define EPIO_CFG_EPIO7                      0x0000000894#define EPIO_CFG_EPIO8                      0x0000000995#define EPIO_CFG_EPIO9                      0x0000000a96#define EPIO_CFG_EPIO10                     0x0000000b97#define EPIO_CFG_EPIO11                     0x0000000c98#define EPIO_CFG_EPIO12                     0x0000000d99#define EPIO_CFG_EPIO13                     0x0000000e100#define EPIO_CFG_EPIO14                     0x0000000f101#define EPIO_CFG_EPIO15                     0x00000010102#define EPIO_CFG_EPIO16                     0x00000011103#define EPIO_CFG_EPIO17                     0x00000012104#define EPIO_CFG_EPIO18                     0x00000013105#define EPIO_CFG_EPIO19                     0x00000014106#define EPIO_CFG_EPIO20                     0x00000015107#define EPIO_CFG_EPIO21                     0x00000016108#define EPIO_CFG_EPIO22                     0x00000017109#define EPIO_CFG_EPIO23                     0x00000018110#define EPIO_CFG_EPIO24                     0x00000019111#define EPIO_CFG_EPIO25                     0x0000001a112#define EPIO_CFG_EPIO26                     0x0000001b113#define EPIO_CFG_EPIO27                     0x0000001c114#define EPIO_CFG_EPIO28                     0x0000001d115#define EPIO_CFG_EPIO29                     0x0000001e116#define EPIO_CFG_EPIO30                     0x0000001f117#define EPIO_CFG_EPIO31                     0x00000020118 119struct mac_addr {120	u32 upper;121	u32 lower;122};123 124struct shared_hw_cfg {			 /* NVRAM Offset */125	/* Up to 16 bytes of NULL-terminated string */126	u8  part_num[16];		    /* 0x104 */127 128	u32 config;			/* 0x114 */129	#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001130		#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0131		#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000132		#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001133	#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002134 135	#define SHARED_HW_CFG_PORT_SWAP                     0x00000004136 137	#define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008138 139	#define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000140	#define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010141 142	#define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700143		#define SHARED_HW_CFG_MFW_SELECT_SHIFT               8144	/* Whatever MFW found in NVM145	   (if multiple found, priority order is: NC-SI, UMP, IPMI) */146		#define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000147		#define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100148		#define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200149		#define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300150	/* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI151	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */152		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400153	/* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI154	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */155		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500156	/* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP157	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */158		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600159 160	#define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000161		#define SHARED_HW_CFG_LED_MODE_SHIFT                 16162		#define SHARED_HW_CFG_LED_MAC1                       0x00000000163		#define SHARED_HW_CFG_LED_PHY1                       0x00010000164		#define SHARED_HW_CFG_LED_PHY2                       0x00020000165		#define SHARED_HW_CFG_LED_PHY3                       0x00030000166		#define SHARED_HW_CFG_LED_MAC2                       0x00040000167		#define SHARED_HW_CFG_LED_PHY4                       0x00050000168		#define SHARED_HW_CFG_LED_PHY5                       0x00060000169		#define SHARED_HW_CFG_LED_PHY6                       0x00070000170		#define SHARED_HW_CFG_LED_MAC3                       0x00080000171		#define SHARED_HW_CFG_LED_PHY7                       0x00090000172		#define SHARED_HW_CFG_LED_PHY9                       0x000a0000173		#define SHARED_HW_CFG_LED_PHY11                      0x000b0000174		#define SHARED_HW_CFG_LED_MAC4                       0x000c0000175		#define SHARED_HW_CFG_LED_PHY8                       0x000d0000176		#define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000177		#define SHARED_HW_CFG_LED_EXTPHY2                    0x000f0000178 179 180	#define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000181		#define SHARED_HW_CFG_AN_ENABLE_SHIFT                24182		#define SHARED_HW_CFG_AN_ENABLE_CL37                 0x01000000183		#define SHARED_HW_CFG_AN_ENABLE_CL73                 0x02000000184		#define SHARED_HW_CFG_AN_ENABLE_BAM                  0x04000000185		#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION   0x08000000186		#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT  0x10000000187		#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY           0x20000000188 189	#define SHARED_HW_CFG_SRIOV_MASK                    0x40000000190		#define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000191		#define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000192 193	#define SHARED_HW_CFG_ATC_MASK                      0x80000000194		#define SHARED_HW_CFG_ATC_DISABLED                   0x00000000195		#define SHARED_HW_CFG_ATC_ENABLED                    0x80000000196 197	u32 config2;			    /* 0x118 */198	/* one time auto detect grace period (in sec) */199	#define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff200	#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0201 202	#define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100203	#define SHARED_HW_CFG_PCIE_GEN2_DISABLED            0x00000000204 205	/* The default value for the core clock is 250MHz and it is206	   achieved by setting the clock change to 4 */207	#define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00208	#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT                     9209 210	#define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000211		#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000212		#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000213 214	#define SHARED_HW_CFG_HIDE_PORT1                    0x00002000215 216	#define SHARED_HW_CFG_WOL_CAPABLE_MASK              0x00004000217		#define SHARED_HW_CFG_WOL_CAPABLE_DISABLED           0x00000000218		#define SHARED_HW_CFG_WOL_CAPABLE_ENABLED            0x00004000219 220		/* Output low when PERST is asserted */221	#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000222		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000223		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000224 225	#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000226		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16227		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000228		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000229		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000230		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000231 232	/*  The fan failure mechanism is usually related to the PHY type233	      since the power consumption of the board is determined by the PHY.234	      Currently, fan is required for most designs with SFX7101, BCM8727235	      and BCM8481. If a fan is not required for a board which uses one236	      of those PHYs, this field should be set to "Disabled". If a fan is237	      required for a different PHY type, this option should be set to238	      "Enabled". The fan failure indication is expected on SPIO5 */239	#define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000240		#define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19241		#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000242		#define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000243		#define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000244 245		/* ASPM Power Management support */246	#define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000247		#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21248		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000249		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000250		#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000251		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000252 253	/* The value of PM_TL_IGNORE_REQS (bit0) in PCI register254	   tl_control_0 (register 0x2800) */255	#define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000256		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000257		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000258 259	#define SHARED_HW_CFG_PORT_MODE_MASK                0x01000000260		#define SHARED_HW_CFG_PORT_MODE_2                    0x00000000261		#define SHARED_HW_CFG_PORT_MODE_4                    0x01000000262 263	#define SHARED_HW_CFG_PATH_SWAP_MASK                0x02000000264		#define SHARED_HW_CFG_PATH_SWAP_DISABLED             0x00000000265		#define SHARED_HW_CFG_PATH_SWAP_ENABLED              0x02000000266 267	/*  Set the MDC/MDIO access for the first external phy */268	#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000269		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26270		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000271		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000272		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000273		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000274		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000275 276	/*  Set the MDC/MDIO access for the second external phy */277	#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000278		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29279		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000280		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000281		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000282		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000283		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000284 285	u32 config_3;				/* 0x11C */286	#define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK         0x00000F00287		#define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT              8288		#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5        0x00000000289		#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0        0x00000100290 291	u32 ump_nc_si_config;			/* 0x120 */292	#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003293		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0294		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000295		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001296		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000297		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002298 299	#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00300		#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT       8301 302	#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000303		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT   16304		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000305		#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000306 307	u32 board;			/* 0x124 */308	#define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F309	#define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0310	#define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0311	#define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6312	/* Use the PIN_CFG_XXX defines on top */313	#define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000314	#define SHARED_HW_CFG_BOARD_REV_SHIFT                        16315 316	#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0f000000317	#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24318 319	#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000320	#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28321 322	u32 wc_lane_config;				    /* 0x128 */323	#define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF324		#define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0325		#define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b326		#define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4327		#define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b328		#define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4329	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF330	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0331	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00332	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8333 334	/* TX lane Polarity swap */335	#define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000336	#define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000337	#define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000338	#define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000339	/* TX lane Polarity swap */340	#define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000341	#define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000342	#define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000343	#define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000344 345	/*  Selects the port layout of the board */346	#define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000347		#define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24348		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000349		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000350		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000351		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000352		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000353		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000354};355 356 357/****************************************************************************358 * Port HW configuration                                                    *359 ****************************************************************************/360struct port_hw_cfg {		    /* port 0: 0x12c  port 1: 0x2bc */361 362	u32 pci_id;363	#define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000364	#define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff365 366	u32 pci_sub_id;367	#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000368	#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff369 370	u32 power_dissipated;371	#define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff372	#define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0373	#define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00374	#define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8375	#define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000376	#define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16377	#define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000378	#define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24379 380	u32 power_consumed;381	#define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff382	#define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0383	#define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00384	#define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8385	#define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000386	#define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16387	#define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000388	#define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24389 390	u32 mac_upper;391	#define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff392	#define PORT_HW_CFG_UPPERMAC_SHIFT                           0393	u32 mac_lower;394 395	u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */396	u32 iscsi_mac_lower;397 398	u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */399	u32 rdma_mac_lower;400 401	u32 serdes_config;402	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff403	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0404 405	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000406	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16407 408 409	/*  Default values: 2P-64, 4P-32 */410	u32 pf_config;					    /* 0x158 */411	#define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F412	#define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0413 414	/*  Default values: 17 */415	#define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK        0x00007F00416	#define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT                8417 418	#define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000419	#define PORT_HW_CFG_FLR_ENABLED                     0x00010000420 421	u32 vf_config;					    /* 0x15C */422	#define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F423	#define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0424 425	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000426	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16427 428	u32 mf_pci_id;					    /* 0x160 */429	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF430	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0431 432	/*  Controls the TX laser of the SFP+ module */433	u32 sfp_ctrl;					    /* 0x164 */434	#define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF435		#define PORT_HW_CFG_TX_LASER_SHIFT                   0436		#define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000437		#define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001438		#define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002439		#define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003440		#define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004441 442	/*  Controls the fault module LED of the SFP+ */443	#define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00444		#define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8445		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000446		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100447		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200448		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300449		#define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400450 451	/*  The output pin TX_DIS that controls the TX laser of the SFP+452	  module. Use the PIN_CFG_XXX defines on top */453	u32 e3_sfp_ctrl;				    /* 0x168 */454	#define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF455	#define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0456 457	/*  The output pin for SFPP_TYPE which turns on the Fault module LED */458	#define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00459	#define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8460 461	/*  The input pin MOD_ABS that indicates whether SFP+ module is462	  present or not. Use the PIN_CFG_XXX defines on top */463	#define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000464	#define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16465 466	/*  The output pin PWRDIS_SFP_X which disable the power of the SFP+467	  module. Use the PIN_CFG_XXX defines on top */468	#define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000469	#define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24470 471	/*472	 * The input pin which signals module transmit fault. Use the473	 * PIN_CFG_XXX defines on top474	 */475	u32 e3_cmn_pin_cfg;				    /* 0x16C */476	#define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF477	#define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0478 479	/*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on480	 top */481	#define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00482	#define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8483 484	/*485	 * The output pin which powers down the PHY. Use the PIN_CFG_XXX486	 * defines on top487	 */488	#define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000489	#define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16490 491	/*  The output pin values BSC_SEL which selects the I2C for this port492	  in the I2C Mux */493	#define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000494	#define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000495 496 497	/*498	 * The input pin I_FAULT which indicate over-current has occurred.499	 * Use the PIN_CFG_XXX defines on top500	 */501	u32 e3_cmn_pin_cfg1;				    /* 0x170 */502	#define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF503	#define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0504 505	/*  pause on host ring */506	u32 generic_features;                               /* 0x174 */507	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001508	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0509	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000510	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED                0x00000001511 512	/* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2513	 * LOM recommended and tested value is 0xBEB2. Using a different514	 * value means using a value not tested by BRCM515	 */516	u32 sfi_tap_values;                                 /* 0x178 */517	#define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF518	#define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0519 520	/* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested521	 * value is 0x2. LOM recommended and tested value is 0x2. Using a522	 * different value means using a value not tested by BRCM523	 */524	#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000525	#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16526	/*  Set non-default values for TXFIR in SFP mode. */527	#define PORT_HW_CFG_TX_DRV_IFIR_MASK                          0x00F00000528	#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT                         20529 530	/*  Set non-default values for IPREDRIVER in SFP mode. */531	#define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK                    0x0F000000532	#define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT                   24533 534	/*  Set non-default values for POST2 in SFP mode. */535	#define PORT_HW_CFG_TX_DRV_POST2_MASK                         0xF0000000536	#define PORT_HW_CFG_TX_DRV_POST2_SHIFT                        28537 538	u32 reserved0[5];				    /* 0x17c */539 540	u32 aeu_int_mask;				    /* 0x190 */541 542	u32 media_type;					    /* 0x194 */543	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF544	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0545 546	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00547	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8548 549	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000550	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16551 552	/*  4 times 16 bits for all 4 lanes. In case external PHY is present553	      (not direct mode), those values will not take effect on the 4 XGXS554	      lanes. For some external PHYs (such as 8706 and 8726) the values555	      will be used to configure the external PHY  in those cases, not556	      all 4 values are needed. */557	u16 xgxs_config_rx[4];			/* 0x198 */558	u16 xgxs_config_tx[4];			/* 0x1A0 */559 560	/* For storing FCOE mac on shared memory */561	u32 fcoe_fip_mac_upper;562	#define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff563	#define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0564	u32 fcoe_fip_mac_lower;565 566	u32 fcoe_wwn_port_name_upper;567	u32 fcoe_wwn_port_name_lower;568 569	u32 fcoe_wwn_node_name_upper;570	u32 fcoe_wwn_node_name_lower;571 572	u32 Reserved1[49];				    /* 0x1C0 */573 574	/*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),575	      84833 only */576	u32 xgbt_phy_cfg;				    /* 0x284 */577	#define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF578	#define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0579 580		u32 default_cfg;			    /* 0x288 */581	#define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003582		#define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0583		#define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000584		#define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001585		#define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002586		#define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003587 588	#define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C589		#define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2590		#define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000591		#define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004592		#define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008593		#define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c594 595	#define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030596		#define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4597		#define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000598		#define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010599		#define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020600		#define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030601 602	#define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0603		#define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6604		#define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000605		#define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040606		#define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080607		#define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0608 609	/*  When KR link is required to be set to force which is not610	      KR-compliant, this parameter determine what is the trigger for it.611	      When GPIO is selected, low input will force the speed. Currently612	      default speed is 1G. In the future, it may be widen to select the613	      forced speed in with another parameter. Note when force-1G is614	      enabled, it override option 56: Link Speed option. */615	#define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00616		#define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8617		#define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000618		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100619		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200620		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300621		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400622		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500623		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600624		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700625		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800626		#define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900627	/*  Enable to determine with which GPIO to reset the external phy */628	#define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000629		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16630		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000631		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000632		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000633		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000634		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000635		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000636		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000637		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000638		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000639 640	/*  Enable BAM on KR */641	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000642	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20643	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000644	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000645 646	/*  Enable Common Mode Sense */647	#define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000648	#define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21649	#define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000650	#define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000651 652	/*  Determine the Serdes electrical interface   */653	#define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000654	#define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24655	#define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000656	#define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000657	#define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000658	#define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000659	#define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000660	#define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000661 662 663	u32 speed_capability_mask2;			    /* 0x28C */664	#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF665		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0666		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001667		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3__           0x00000002668		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3___          0x00000004669		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008670		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010671		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G    0x00000020672		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040673		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080674 675	#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000676		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16677		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000678		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0__           0x00020000679		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0___          0x00040000680		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000681		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000682		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G    0x00200000683		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000684		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000685 686 687	/*  In the case where two media types (e.g. copper and fiber) are688	      present and electrically active at the same time, PHY Selection689	      will determine which of the two PHYs will be designated as the690	      Active PHY and used for a connection to the network.  */691	u32 multi_phy_config;				    /* 0x290 */692	#define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007693		#define PORT_HW_CFG_PHY_SELECTION_SHIFT              0694		#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000695		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001696		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002697		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003698		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004699 700	/*  When enabled, all second phy nvram parameters will be swapped701	      with the first phy parameters */702	#define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008703		#define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3704		#define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000705		#define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008706 707 708	/*  Address of the second external phy */709	u32 external_phy_config2;			    /* 0x294 */710	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF711	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0712 713	/*  The second XGXS external PHY type */714	#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00715		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8716		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000717		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100718		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200719		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300720		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400721		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500722		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600723		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700724		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800725		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900726		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00727		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00728		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00729		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00730		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00731		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00732		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000733		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834      0x00001100734		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858      0x00001200735		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00736		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00737 738 739	/*  4 times 16 bits for all 4 lanes. For some external PHYs (such as740	      8706, 8726 and 8727) not all 4 values are needed. */741	u16 xgxs_config2_rx[4];				    /* 0x296 */742	u16 xgxs_config2_tx[4];				    /* 0x2A0 */743 744	u32 lane_config;745	#define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff746		#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0747		/* AN and forced */748		#define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b749		/* forced only */750		#define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4751		/* forced only */752		#define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8753		/* forced only */754		#define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4755	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff756	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0757	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00758	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8759	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000760	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14761 762	/*  Indicate whether to swap the external phy polarity */763	#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000764		#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000765		#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000766 767 768	u32 external_phy_config;769	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff770	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0771 772	#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00773		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8774		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000775		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100776		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200777		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300778		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400779		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500780		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600781		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700782		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800783		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900784		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00785		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00786		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00787		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00788		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00789		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00790		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000791		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834       0x00001100792		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858       0x00001200793		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00794		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00795		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00796 797	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000798	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16799 800	#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000801		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24802		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000803		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000804		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000805		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000806 807	u32 speed_capability_mask;808	#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff809		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0810		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001811		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002812		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004813		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008814		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010815		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020816		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040817		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080818		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000819 820	#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000821		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16822		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000823		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000824		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000825		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000826		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000827		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000828		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000829		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000830		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000831 832	/*  A place to hold the original MAC address as a backup */833	u32 backup_mac_upper;			/* 0x2B4 */834	u32 backup_mac_lower;			/* 0x2B8 */835 836};837 838 839/****************************************************************************840 * Shared Feature configuration                                             *841 ****************************************************************************/842struct shared_feat_cfg {		 /* NVRAM Offset */843 844	u32 config;			/* 0x450 */845	#define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001846 847	/* Use NVRAM values instead of HW default values */848	#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \849							    0x00000002850		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \851								     0x00000000852		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \853								     0x00000002854 855	#define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008856		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000857		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008858 859	#define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030860	#define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4861 862	/*  Override the OTP back to single function mode. When using GPIO,863	      high means only SF, 0 is according to CLP configuration */864	#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700865		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8866		#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000867		#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100868		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200869		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300870		#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400871		#define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE        0x00000500872		#define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE       0x00000600873		#define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE  0x00000700874 875	/* The interval in seconds between sending LLDP packets. Set to zero876	   to disable the feature */877	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00ff0000878	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16879 880	/* The assigned device type ID for LLDP usage */881	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xff000000882	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24883 884};885 886 887/****************************************************************************888 * Port Feature configuration                                               *889 ****************************************************************************/890struct port_feat_cfg {		    /* port 0: 0x454  port 1: 0x4c8 */891 892	u32 config;893	#define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f894		#define PORT_FEATURE_BAR1_SIZE_SHIFT                 0895		#define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000896		#define PORT_FEATURE_BAR1_SIZE_64K                   0x00000001897		#define PORT_FEATURE_BAR1_SIZE_128K                  0x00000002898		#define PORT_FEATURE_BAR1_SIZE_256K                  0x00000003899		#define PORT_FEATURE_BAR1_SIZE_512K                  0x00000004900		#define PORT_FEATURE_BAR1_SIZE_1M                    0x00000005901		#define PORT_FEATURE_BAR1_SIZE_2M                    0x00000006902		#define PORT_FEATURE_BAR1_SIZE_4M                    0x00000007903		#define PORT_FEATURE_BAR1_SIZE_8M                    0x00000008904		#define PORT_FEATURE_BAR1_SIZE_16M                   0x00000009905		#define PORT_FEATURE_BAR1_SIZE_32M                   0x0000000a906		#define PORT_FEATURE_BAR1_SIZE_64M                   0x0000000b907		#define PORT_FEATURE_BAR1_SIZE_128M                  0x0000000c908		#define PORT_FEATURE_BAR1_SIZE_256M                  0x0000000d909		#define PORT_FEATURE_BAR1_SIZE_512M                  0x0000000e910		#define PORT_FEATURE_BAR1_SIZE_1G                    0x0000000f911	#define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0912		#define PORT_FEATURE_BAR2_SIZE_SHIFT                 4913		#define PORT_FEATURE_BAR2_SIZE_DISABLED              0x00000000914		#define PORT_FEATURE_BAR2_SIZE_64K                   0x00000010915		#define PORT_FEATURE_BAR2_SIZE_128K                  0x00000020916		#define PORT_FEATURE_BAR2_SIZE_256K                  0x00000030917		#define PORT_FEATURE_BAR2_SIZE_512K                  0x00000040918		#define PORT_FEATURE_BAR2_SIZE_1M                    0x00000050919		#define PORT_FEATURE_BAR2_SIZE_2M                    0x00000060920		#define PORT_FEATURE_BAR2_SIZE_4M                    0x00000070921		#define PORT_FEATURE_BAR2_SIZE_8M                    0x00000080922		#define PORT_FEATURE_BAR2_SIZE_16M                   0x00000090923		#define PORT_FEATURE_BAR2_SIZE_32M                   0x000000a0924		#define PORT_FEATURE_BAR2_SIZE_64M                   0x000000b0925		#define PORT_FEATURE_BAR2_SIZE_128M                  0x000000c0926		#define PORT_FEATURE_BAR2_SIZE_256M                  0x000000d0927		#define PORT_FEATURE_BAR2_SIZE_512M                  0x000000e0928		#define PORT_FEATURE_BAR2_SIZE_1G                    0x000000f0929 930	#define PORT_FEAT_CFG_DCBX_MASK                     0x00000100931		#define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000932		#define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100933 934		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK        0x00000C00935		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE        0x00000400936		#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI       0x00000800937 938	#define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000939	#define PORT_FEATURE_EN_SIZE_SHIFT                           24940	#define PORT_FEATURE_WOL_ENABLED                             0x01000000941	#define PORT_FEATURE_MBA_ENABLED                             0x02000000942	#define PORT_FEATURE_MFW_ENABLED                             0x04000000943 944	/* Advertise expansion ROM even if MBA is disabled */945	#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000946		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000947		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000948 949	/* Check the optic vendor via i2c against a list of approved modules950	   in a separate nvram image */951	#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xe0000000952		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29953		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \954								     0x00000000955		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \956								     0x20000000957		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000958		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000959 960	u32 wol_config;961	/* Default is used when driver sets to "auto" mode */962	#define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003963		#define PORT_FEATURE_WOL_DEFAULT_SHIFT               0964		#define PORT_FEATURE_WOL_DEFAULT_DISABLE             0x00000000965		#define PORT_FEATURE_WOL_DEFAULT_MAGIC               0x00000001966		#define PORT_FEATURE_WOL_DEFAULT_ACPI                0x00000002967		#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x00000003968	#define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004969	#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008970	#define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010971 972	u32 mba_config;973	#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007974		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0975		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000976		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001977		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002978		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003979		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004980		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007981 982	#define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038983	#define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3984 985	#define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100986	#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200987	#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400988	#define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800989		#define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000990		#define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800991	#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000992		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12993		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000994		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000995		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000996		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000997		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000998		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000999		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x000060001000		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x000070001001		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x000080001002		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x000090001003		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a0001004		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b0001005		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c0001006		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d0001007		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e0001008		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f0001009	#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f000001010	#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   201011	#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x030000001012		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        241013		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x000000001014		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x010000001015		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x020000001016		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x030000001017	#define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c0000001018		#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            261019		#define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x000000001020		#define PORT_FEATURE_MBA_LINK_SPEED_10HD             0x040000001021		#define PORT_FEATURE_MBA_LINK_SPEED_10FD             0x080000001022		#define PORT_FEATURE_MBA_LINK_SPEED_100HD            0x0c0000001023		#define PORT_FEATURE_MBA_LINK_SPEED_100FD            0x100000001024		#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS            0x140000001025		#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x180000001026		#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c0000001027		#define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x200000001028	u32 bmc_config;1029	#define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x000000011030		#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x000000001031		#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x000000011032 1033	u32 mba_vlan_cfg;1034	#define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff1035	#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      01036	#define PORT_FEATURE_MBA_VLAN_EN                    0x000100001037 1038	u32 resource_cfg;1039	#define PORT_FEATURE_RESOURCE_CFG_VALID             0x000000011040	#define PORT_FEATURE_RESOURCE_CFG_DIAG              0x000000021041	#define PORT_FEATURE_RESOURCE_CFG_L2                0x000000041042	#define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x000000081043	#define PORT_FEATURE_RESOURCE_CFG_RDMA              0x000000101044 1045	u32 smbus_config;1046	#define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe1047	#define PORT_FEATURE_SMBUS_ADDR_SHIFT                        11048 1049	u32 vf_config;1050	#define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f1051		#define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             01052		#define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x000000001053		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x000000011054		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x000000021055		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x000000031056		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x000000041057		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x000000051058		#define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x000000061059		#define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x000000071060		#define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x000000081061		#define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x000000091062		#define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a1063		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b1064		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c1065		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d1066		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e1067		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f1068 1069	u32 link_config;    /* Used as HW defaults for the driver */1070	#define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x030000001071		#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          241072		/* (forced) low speed switch (< 10G) */1073		#define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x000000001074		/* (forced) high speed switch (>= 10G) */1075		#define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x010000001076		#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x020000001077		#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x030000001078 1079	#define PORT_FEATURE_LINK_SPEED_MASK                0x000f00001080		#define PORT_FEATURE_LINK_SPEED_SHIFT                161081		#define PORT_FEATURE_LINK_SPEED_AUTO                 0x000000001082		#define PORT_FEATURE_LINK_SPEED_10M_FULL             0x000100001083		#define PORT_FEATURE_LINK_SPEED_10M_HALF             0x000200001084		#define PORT_FEATURE_LINK_SPEED_100M_HALF            0x000300001085		#define PORT_FEATURE_LINK_SPEED_100M_FULL            0x000400001086		#define PORT_FEATURE_LINK_SPEED_1G                   0x000500001087		#define PORT_FEATURE_LINK_SPEED_2_5G                 0x000600001088		#define PORT_FEATURE_LINK_SPEED_10G_CX4              0x000700001089		#define PORT_FEATURE_LINK_SPEED_20G                  0x000800001090 1091	#define PORT_FEATURE_FLOW_CONTROL_MASK              0x000007001092		#define PORT_FEATURE_FLOW_CONTROL_SHIFT              81093		#define PORT_FEATURE_FLOW_CONTROL_AUTO               0x000000001094		#define PORT_FEATURE_FLOW_CONTROL_TX                 0x000001001095		#define PORT_FEATURE_FLOW_CONTROL_RX                 0x000002001096		#define PORT_FEATURE_FLOW_CONTROL_BOTH               0x000003001097		#define PORT_FEATURE_FLOW_CONTROL_NONE               0x000004001098 1099	/* The default for MCP link configuration,1100	   uses the same defines as link_config */1101	u32 mfw_wol_link_cfg;1102 1103	/* The default for the driver of the second external phy,1104	   uses the same defines as link_config */1105	u32 link_config2;				    /* 0x47C */1106 1107	/* The default for MCP of the second external phy,1108	   uses the same defines as link_config */1109	u32 mfw_wol_link_cfg2;				    /* 0x480 */1110 1111 1112	/*  EEE power saving mode */1113	u32 eee_power_mode;                                 /* 0x484 */1114	#define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF1115	#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    01116	#define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x000000001117	#define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x000000011118	#define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x000000021119	#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x000000031120 1121 1122	u32 Reserved2[16];                                  /* 0x488 */1123};1124 1125 1126/****************************************************************************1127 * Device Information                                                       *1128 ****************************************************************************/1129struct shm_dev_info {				/* size */1130 1131	u32    bc_rev; /* 8 bits each: major, minor, build */	       /* 4 */1132 1133	struct shared_hw_cfg     shared_hw_config;	      /* 40 */1134 1135	struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */1136 1137	struct shared_feat_cfg   shared_feature_config;		   /* 4 */1138 1139	struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */1140 1141};1142 1143struct extended_dev_info_shared_cfg {1144	u32 reserved[18];1145	u32 mbi_version;1146	u32 mbi_date;1147};1148 1149#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)1150	#error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."1151#endif1152 1153#define FUNC_0              01154#define FUNC_1              11155#define FUNC_2              21156#define FUNC_3              31157#define FUNC_4              41158#define FUNC_5              51159#define FUNC_6              61160#define FUNC_7              71161#define E1_FUNC_MAX         21162#define E1H_FUNC_MAX            81163#define E2_FUNC_MAX         4   /* per path */1164 1165#define VN_0                01166#define VN_1                11167#define VN_2                21168#define VN_3                31169#define E1VN_MAX            11170#define E1HVN_MAX           41171 1172#define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */1173/* This value (in milliseconds) determines the frequency of the driver1174 * issuing the PULSE message code.  The firmware monitors this periodic1175 * pulse to determine when to switch to an OS-absent mode. */1176#define DRV_PULSE_PERIOD_MS     2501177 1178/* This value (in milliseconds) determines how long the driver should1179 * wait for an acknowledgement from the firmware before timing out.  Once1180 * the firmware has timed out, the driver will assume there is no firmware1181 * running and there won't be any firmware-driver synchronization during a1182 * driver reset. */1183#define FW_ACK_TIME_OUT_MS      50001184 1185#define FW_ACK_POLL_TIME_MS     11186 1187#define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)1188 1189#define MFW_TRACE_SIGNATURE     0x545243421190 1191/****************************************************************************1192 * Driver <-> FW Mailbox                                                    *1193 ****************************************************************************/1194struct drv_port_mb {1195 1196	u32 link_status;1197	/* Driver should update this field on any link change event */1198 1199	#define LINK_STATUS_NONE				(0<<0)1200	#define LINK_STATUS_LINK_FLAG_MASK			0x000000011201	#define LINK_STATUS_LINK_UP				0x000000011202	#define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001E1203	#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE	(0<<1)1204	#define LINK_STATUS_SPEED_AND_DUPLEX_10THD		(1<<1)1205	#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD		(2<<1)1206	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD		(3<<1)1207	#define LINK_STATUS_SPEED_AND_DUPLEX_100T4		(4<<1)1208	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD		(5<<1)1209	#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD		(6<<1)1210	#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(7<<1)1211	#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD		(7<<1)1212	#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD		(8<<1)1213	#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD		(9<<1)1214	#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD		(9<<1)1215	#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD		(10<<1)1216	#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD		(10<<1)1217	#define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD		(11<<1)1218	#define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD		(11<<1)1219 1220	#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK		0x000000201221	#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x000000201222 1223	#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x000000401224	#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK	0x000000801225	#define LINK_STATUS_PARALLEL_DETECTION_USED		0x000000801226 1227	#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x000002001228	#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x000004001229	#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE		0x000008001230	#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE	0x000010001231	#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE	0x000020001232	#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE		0x000040001233	#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE		0x000080001234 1235	#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK		0x000100001236	#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x000100001237 1238	#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK		0x000200001239	#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x000200001240 1241	#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C00001242	#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0<<18)1243	#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1<<18)1244	#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2<<18)1245	#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3<<18)1246 1247	#define LINK_STATUS_SERDES_LINK				0x001000001248 1249	#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE	0x002000001250	#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE	0x004000001251	#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE		0x008000001252	#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE		0x100000001253 1254	#define LINK_STATUS_PFC_ENABLED				0x200000001255 1256	#define LINK_STATUS_PHYSICAL_LINK_FLAG			0x400000001257	#define LINK_STATUS_SFP_TX_FAULT			0x800000001258 1259	u32 port_stx;1260 1261	u32 stat_nig_timer;1262 1263	/* MCP firmware does not use this field */1264	u32 ext_phy_fw_version;1265 1266};1267 1268 1269struct drv_func_mb {1270 1271	u32 drv_mb_header;1272	#define DRV_MSG_CODE_MASK                       0xffff00001273	#define DRV_MSG_CODE_LOAD_REQ                   0x100000001274	#define DRV_MSG_CODE_LOAD_DONE                  0x110000001275	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x200000001276	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x200100001277	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x200200001278	#define DRV_MSG_CODE_UNLOAD_DONE                0x210000001279	#define DRV_MSG_CODE_DCC_OK                     0x300000001280	#define DRV_MSG_CODE_DCC_FAILURE                0x310000001281	#define DRV_MSG_CODE_DIAG_ENTER_REQ             0x500000001282	#define DRV_MSG_CODE_DIAG_EXIT_REQ              0x600000001283	#define DRV_MSG_CODE_VALIDATE_KEY               0x700000001284	#define DRV_MSG_CODE_GET_CURR_KEY               0x800000001285	#define DRV_MSG_CODE_GET_UPGRADE_KEY            0x810000001286	#define DRV_MSG_CODE_GET_MANUF_KEY              0x820000001287	#define DRV_MSG_CODE_LOAD_L2B_PRAM              0x900000001288	#define DRV_MSG_CODE_OEM_OK			0x000100001289	#define DRV_MSG_CODE_OEM_FAILURE		0x000200001290	#define DRV_MSG_CODE_OEM_UPDATE_SVID_OK		0x000300001291	#define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE	0x000400001292	/*1293	 * The optic module verification command requires bootcode1294	 * v5.0.6 or later, te specific optic module verification command1295	 * requires bootcode v5.2.12 or later1296	 */1297	#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa00000001298	#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x000500061299	#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa10000001300	#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x000502341301	#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa20000001302	#define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x000700021303	#define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x000700141304	#define REQ_BC_VER_4_MT_SUPPORTED               0x000702011305	#define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x000702011306	#define REQ_BC_VER_4_FCOE_FEATURES              0x000702091307 1308	#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb00000001309	#define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb20000001310	#define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x000704011311 1312	#define DRV_MSG_CODE_VF_DISABLED_DONE           0xc00000001313 1314	#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd00000001315	#define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd10000001316	#define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd20000001317	#define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd30000001318	#define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd40000001319 1320	#define DRV_MSG_CODE_DRV_INFO_ACK               0xd80000001321	#define DRV_MSG_CODE_DRV_INFO_NACK              0xd90000001322 1323	#define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda0000001324 1325	#define DRV_MSG_CODE_RMMOD                      0xdb0000001326	#define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f1327 1328	#define DRV_MSG_CODE_SET_MF_BW                  0xe00000001329	#define REQ_BC_VER_4_SET_MF_BW                  0x000602021330	#define DRV_MSG_CODE_SET_MF_BW_ACK              0xe10000001331 1332	#define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x010000001333 1334	#define DRV_MSG_CODE_INITIATE_FLR               0x020000001335	#define REQ_BC_VER_4_INITIATE_FLR               0x000702131336 1337	#define BIOS_MSG_CODE_LIC_CHALLENGE             0xff0100001338	#define BIOS_MSG_CODE_LIC_RESPONSE              0xff0200001339	#define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff0300001340	#define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff0400001341 1342	#define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff1343 1344	u32 drv_mb_param;1345	#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff00001346	#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff0000001347 1348	#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x000000021349 1350	#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a1351	#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x000020001352 1353	u32 fw_mb_header;1354	#define FW_MSG_CODE_MASK                        0xffff00001355	#define FW_MSG_CODE_DRV_LOAD_COMMON             0x101000001356	#define FW_MSG_CODE_DRV_LOAD_PORT               0x101100001357	#define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x101200001358	/* Load common chip is supported from bc 6.0.0  */1359	#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x000600001360	#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x101300001361 1362	#define FW_MSG_CODE_DRV_LOAD_REFUSED            0x102000001363	#define FW_MSG_CODE_DRV_LOAD_DONE               0x111000001364	#define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x201000001365	#define FW_MSG_CODE_DRV_UNLOAD_PORT             0x201100001366	#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x201200001367	#define FW_MSG_CODE_DRV_UNLOAD_DONE             0x211000001368	#define FW_MSG_CODE_DCC_DONE                    0x301000001369	#define FW_MSG_CODE_LLDP_DONE                   0x401000001370	#define FW_MSG_CODE_DIAG_ENTER_DONE             0x501000001371	#define FW_MSG_CODE_DIAG_REFUSE                 0x502000001372	#define FW_MSG_CODE_DIAG_EXIT_DONE              0x601000001373	#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x701000001374	#define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x702000001375	#define FW_MSG_CODE_GET_KEY_DONE                0x801000001376	#define FW_MSG_CODE_NO_KEY                      0x80f000001377	#define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f800001378	#define FW_MSG_CODE_L2B_PRAM_LOADED             0x901000001379	#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x902100001380	#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x902200001381	#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x902300001382	#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x902400001383	#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa01000001384	#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa02000001385	#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa03000001386	#define FW_MSG_CODE_VF_DISABLED_DONE            0xb00000001387	#define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb01000001388 1389	#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd01000001390	#define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd11000001391	#define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd21000001392	#define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd31000001393	#define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd41000001394 1395	#define FW_MSG_CODE_DRV_INFO_ACK                0xd81000001396	#define FW_MSG_CODE_DRV_INFO_NACK               0xd91000001397 1398	#define FW_MSG_CODE_EEE_RESULS_ACK              0xda1000001399 1400	#define FW_MSG_CODE_RMMOD_ACK                   0xdb1000001401 1402	#define FW_MSG_CODE_SET_MF_BW_SENT              0xe00000001403	#define FW_MSG_CODE_SET_MF_BW_DONE              0xe10000001404 1405	#define FW_MSG_CODE_LINK_CHANGED_ACK            0x011000001406 1407	#define FW_MSG_CODE_LIC_CHALLENGE               0xff0100001408	#define FW_MSG_CODE_LIC_RESPONSE                0xff0200001409	#define FW_MSG_CODE_VIRT_MAC_PRIM               0xff0300001410	#define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff0400001411 1412	#define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff1413 1414	u32 fw_mb_param;1415 1416	u32 drv_pulse_mb;1417	#define DRV_PULSE_SEQ_MASK                      0x00007fff1418	#define DRV_PULSE_SYSTEM_TIME_MASK              0xffff00001419	/*1420	 * The system time is in the format of1421	 * (year-2001)*12*32 + month*32 + day.1422	 */1423	#define DRV_PULSE_ALWAYS_ALIVE                  0x000080001424	/*1425	 * Indicate to the firmware not to go into the1426	 * OS-absent when it is not getting driver pulse.1427	 * This is used for debugging as well for PXE(MBA).1428	 */1429 1430	u32 mcp_pulse_mb;1431	#define MCP_PULSE_SEQ_MASK                      0x00007fff1432	#define MCP_PULSE_ALWAYS_ALIVE                  0x000080001433	/* Indicates to the driver not to assert due to lack1434	 * of MCP response */1435	#define MCP_EVENT_MASK                          0xffff00001436	#define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x000100001437 1438	u32 iscsi_boot_signature;1439	u32 iscsi_boot_block_offset;1440 1441	u32 drv_status;1442	#define DRV_STATUS_PMF                          0x000000011443	#define DRV_STATUS_VF_DISABLED                  0x000000021444	#define DRV_STATUS_SET_MF_BW                    0x000000041445	#define DRV_STATUS_LINK_EVENT                   0x000000081446 1447	#define DRV_STATUS_OEM_EVENT_MASK               0x000000701448	#define DRV_STATUS_OEM_DISABLE_ENABLE_PF        0x000000101449	#define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION     0x000000201450 1451	#define DRV_STATUS_OEM_UPDATE_SVID              0x000000801452 1453	#define DRV_STATUS_DCC_EVENT_MASK               0x0000ff001454	#define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x000001001455	#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x000002001456	#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x000004001457	#define DRV_STATUS_DCC_RESERVED1                0x000008001458	#define DRV_STATUS_DCC_SET_PROTOCOL             0x000010001459	#define DRV_STATUS_DCC_SET_PRIORITY             0x000020001460 1461	#define DRV_STATUS_DCBX_EVENT_MASK              0x000f00001462	#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x000100001463	#define DRV_STATUS_AFEX_EVENT_MASK              0x03f000001464	#define DRV_STATUS_AFEX_LISTGET_REQ             0x001000001465	#define DRV_STATUS_AFEX_LISTSET_REQ             0x002000001466	#define DRV_STATUS_AFEX_STATSGET_REQ            0x004000001467	#define DRV_STATUS_AFEX_VIFSET_REQ              0x008000001468 1469	#define DRV_STATUS_DRV_INFO_REQ                 0x040000001470 1471	#define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x080000001472 1473	u32 virt_mac_upper;1474	#define VIRT_MAC_SIGN_MASK                      0xffff00001475	#define VIRT_MAC_SIGNATURE                      0x564d00001476	u32 virt_mac_lower;1477 1478};1479 1480 1481/****************************************************************************1482 * Management firmware state                                                *1483 ****************************************************************************/1484/* Allocate 440 bytes for management firmware */1485#define MGMTFW_STATE_WORD_SIZE                          1101486 1487struct mgmtfw_state {1488	u32 opaque[MGMTFW_STATE_WORD_SIZE];1489};1490 1491 1492/****************************************************************************1493 * Multi-Function configuration                                             *1494 ****************************************************************************/1495struct shared_mf_cfg {1496 1497	u32 clp_mb;1498	#define SHARED_MF_CLP_SET_DEFAULT               0x000000001499	/* set by CLP */1500	#define SHARED_MF_CLP_EXIT                      0x000000011501	/* set by MCP */1502	#define SHARED_MF_CLP_EXIT_DONE                 0x000100001503 1504};1505 1506struct port_mf_cfg {1507 1508	u32 dynamic_cfg;    /* device control channel */1509	#define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff1510	#define PORT_MF_CFG_E1HOV_TAG_SHIFT             01511	#define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK1512 1513	u32 reserved[1];1514 1515};1516 1517struct func_mf_cfg {1518 1519	u32 config;1520	/* E/R/I/D */1521	/* function 0 of each port cannot be hidden */1522	#define FUNC_MF_CFG_FUNC_HIDE                   0x000000011523 1524	#define FUNC_MF_CFG_PROTOCOL_MASK               0x000000061525	#define FUNC_MF_CFG_PROTOCOL_FCOE               0x000000001526	#define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x000000021527	#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x000000041528	#define FUNC_MF_CFG_PROTOCOL_ISCSI              0x000000061529	#define FUNC_MF_CFG_PROTOCOL_DEFAULT \1530				FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA1531 1532	#define FUNC_MF_CFG_FUNC_DISABLED               0x000000081533	#define FUNC_MF_CFG_FUNC_DELETED                0x000000101534 1535	/* PRI */1536	/* 0 - low priority, 3 - high priority */1537	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x000003001538	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     81539	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x000000001540 1541	/* MINBW, MAXBW */1542	/* value range - 0..100, increments in 100Mbps */1543	#define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff00001544	#define FUNC_MF_CFG_MIN_BW_SHIFT                161545	#define FUNC_MF_CFG_MIN_BW_DEFAULT              0x000000001546	#define FUNC_MF_CFG_MAX_BW_MASK                 0xff0000001547	#define FUNC_MF_CFG_MAX_BW_SHIFT                241548	#define FUNC_MF_CFG_MAX_BW_DEFAULT              0x640000001549 1550	u32 mac_upper;	    /* MAC */1551	#define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff1552	#define FUNC_MF_CFG_UPPERMAC_SHIFT              01553	#define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK1554	u32 mac_lower;1555	#define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff1556 1557	u32 e1hov_tag;	/* VNI */1558	#define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff1559	#define FUNC_MF_CFG_E1HOV_TAG_SHIFT             01560	#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK1561 1562	/* afex default VLAN ID - 12 bits */1563	#define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff00001564	#define FUNC_MF_CFG_AFEX_VLAN_SHIFT             161565 1566	u32 afex_config;1567	#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff1568	#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    01569	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff001570	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   81571	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x000001001572	#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f00001573	#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     161574 1575	u32 reserved;1576};1577 1578enum mf_cfg_afex_vlan_mode {1579	FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,1580	FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,1581	FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE1582};1583 1584/* This structure is not applicable and should not be accessed on 57711 */1585struct func_ext_cfg {1586	u32 func_cfg;1587	#define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F1588	#define MACP_FUNC_CFG_FLAGS_SHIFT               01589	#define MACP_FUNC_CFG_FLAGS_ENABLED             0x000000011590	#define MACP_FUNC_CFG_FLAGS_ETHERNET            0x000000021591	#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x000000041592	#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x000000081593	#define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x000000801594 1595	u32 iscsi_mac_addr_upper;1596	u32 iscsi_mac_addr_lower;1597 1598	u32 fcoe_mac_addr_upper;1599	u32 fcoe_mac_addr_lower;1600 1601	u32 fcoe_wwn_port_name_upper;1602	u32 fcoe_wwn_port_name_lower;1603 1604	u32 fcoe_wwn_node_name_upper;1605	u32 fcoe_wwn_node_name_lower;1606 1607	u32 preserve_data;1608	#define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)1609	#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)1610	#define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)1611	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)1612	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)1613	#define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)1614};1615 1616struct mf_cfg {1617 1618	struct shared_mf_cfg    shared_mf_config;       /* 0x4 */1619							/* 0x8*2*2=0x20 */1620	struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];1621	/* for all chips, there are 8 mf functions */1622	struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */1623	/*1624	 * Extended configuration per function  - this array does not exist and1625	 * should not be accessed on 577111626	 */1627	struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/1628}; /* 0x224 */1629 1630/****************************************************************************1631 * Shared Memory Region                                                     *1632 ****************************************************************************/1633struct shmem_region {		       /*   SharedMem Offset (size) */1634 1635	u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */1636	#define SHR_MEM_FORMAT_REV_MASK                     0xff0000001637	#define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)1638	/* validity bits */1639	#define SHR_MEM_VALIDITY_PCI_CFG                    0x001000001640	#define SHR_MEM_VALIDITY_MB                         0x002000001641	#define SHR_MEM_VALIDITY_DEV_INFO                   0x004000001642	#define SHR_MEM_VALIDITY_RESERVED                   0x000000071643	/* One licensing bit should be set */1644	#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x000000381645	#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x000000081646	#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x000000101647	#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x000000201648	/* Active MFW */1649	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x000000001650	#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c01651	#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x000000401652	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x000000801653	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c01654	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c01655 1656	struct shm_dev_info dev_info;	     /* 0x8     (0x438) */1657 1658	struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */1659 1660	/* FW information (for internal FW use) */1661	u32         fw_info_fio_offset;		/* 0x4a8       (0x4) */1662	struct mgmtfw_state mgmtfw_state;	/* 0x4ac     (0x1b8) */1663 1664	struct drv_port_mb  port_mb[PORT_MAX];	/* 0x664 (16*2=0x20) */1665 1666#ifdef BMAPI1667	/* This is a variable length array */1668	/* the number of function depends on the chip type */1669	struct drv_func_mb func_mb[1];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */1670#else1671	/* the number of function depends on the chip type */1672	struct drv_func_mb  func_mb[];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */1673#endif /* BMAPI */1674 1675}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */1676 1677/****************************************************************************1678 * Shared Memory 2 Region                                                   *1679 ****************************************************************************/1680/* The fw_flr_ack is actually built in the following way:                   */1681/* 8 bit:  PF ack                                                           */1682/* 64 bit: VF ack                                                           */1683/* 8 bit:  ios_dis_ack                                                      */1684/* In order to maintain endianity in the mailbox hsi, we want to keep using */1685/* u32. The fw must have the VF right after the PF since this is how it     */1686/* access arrays(it expects always the VF to reside after the PF, and that  */1687/* makes the calculation much easier for it. )                              */1688/* In order to answer both limitations, and keep the struct small, the code */1689/* will abuse the structure defined here to achieve the actual partition    */1690/* above                                                                    */1691/****************************************************************************/1692struct fw_flr_ack {1693	u32         pf_ack;1694	u32         vf_ack[1];1695	u32         iov_dis_ack;1696};1697 1698struct fw_flr_mb {1699	u32         aggint;1700	u32         opgen_addr;1701	struct fw_flr_ack ack;1702};1703 1704struct eee_remote_vals {1705	u32         tx_tw;1706	u32         rx_tw;1707};1708 1709/**** SUPPORT FOR SHMEM ARRRAYS ***1710 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to1711 * define arrays with storage types smaller then unsigned dwords.1712 * The macros below add generic support for SHMEM arrays with numeric elements1713 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword1714 * array with individual bit-filed elements accessed using shifts and masks.1715 *1716 */1717 1718/* eb is the bitwidth of a single element */1719#define SHMEM_ARRAY_MASK(eb)		((1<<(eb))-1)1720#define SHMEM_ARRAY_ENTRY(i, eb)	((i)/(32/(eb)))1721 1722/* the bit-position macro allows the used to flip the order of the arrays1723 * elements on a per byte or word boundary.1724 *1725 * example: an array with 8 entries each 4 bit wide. This array will fit into1726 * a single dword. The diagrmas below show the array order of the nibbles.1727 *1728 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:1729 *1730 *                |                |                |               |1731 *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |1732 *                |                |                |               |1733 *1734 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:1735 *1736 *                |                |                |               |1737 *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |1738 *                |                |                |               |1739 *1740 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:1741 *1742 *                |                |                |               |1743 *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |1744 *                |                |                |               |1745 */1746#define SHMEM_ARRAY_BITPOS(i, eb, fb)	\1747	((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \1748	(((i)%((fb)/(eb))) * (eb)))1749 1750#define SHMEM_ARRAY_GET(a, i, eb, fb)					\1751	((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \1752	SHMEM_ARRAY_MASK(eb))1753 1754#define SHMEM_ARRAY_SET(a, i, eb, fb, val)				\1755do {									   \1756	a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<	   \1757	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \1758	a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \1759	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \1760} while (0)1761 1762 1763/****START OF DCBX STRUCTURES DECLARATIONS****/1764#define DCBX_MAX_NUM_PRI_PG_ENTRIES	81765#define DCBX_PRI_PG_BITWIDTH		41766#define DCBX_PRI_PG_FBITS		81767#define DCBX_PRI_PG_GET(a, i)		\1768	SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)1769#define DCBX_PRI_PG_SET(a, i, val)	\1770	SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)1771#define DCBX_MAX_NUM_PG_BW_ENTRIES	81772#define DCBX_BW_PG_BITWIDTH		81773#define DCBX_PG_BW_GET(a, i)		\1774	SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)1775#define DCBX_PG_BW_SET(a, i, val)	\1776	SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)1777#define DCBX_STRICT_PRI_PG		151778#define DCBX_MAX_APP_PROTOCOL		161779#define FCOE_APP_IDX			01780#define ISCSI_APP_IDX			11781#define PREDEFINED_APP_IDX_MAX		21782 1783 1784/* Big/Little endian have the same representation. */1785struct dcbx_ets_feature {1786	/*1787	 * For Admin MIB - is this feature supported by the1788	 * driver | For Local MIB - should this feature be enabled.1789	 */1790	u32 enabled;1791	u32  pg_bw_tbl[2];1792	u32  pri_pg_tbl[1];1793};1794 1795/* Driver structure in LE */1796struct dcbx_pfc_feature {1797#ifdef __BIG_ENDIAN1798	u8 pri_en_bitmap;1799	#define DCBX_PFC_PRI_0 0x011800	#define DCBX_PFC_PRI_1 0x021801	#define DCBX_PFC_PRI_2 0x041802	#define DCBX_PFC_PRI_3 0x081803	#define DCBX_PFC_PRI_4 0x101804	#define DCBX_PFC_PRI_5 0x201805	#define DCBX_PFC_PRI_6 0x401806	#define DCBX_PFC_PRI_7 0x801807	u8 pfc_caps;1808	u8 reserved;1809	u8 enabled;1810#elif defined(__LITTLE_ENDIAN)1811	u8 enabled;1812	u8 reserved;1813	u8 pfc_caps;1814	u8 pri_en_bitmap;1815	#define DCBX_PFC_PRI_0 0x011816	#define DCBX_PFC_PRI_1 0x021817	#define DCBX_PFC_PRI_2 0x041818	#define DCBX_PFC_PRI_3 0x081819	#define DCBX_PFC_PRI_4 0x101820	#define DCBX_PFC_PRI_5 0x201821	#define DCBX_PFC_PRI_6 0x401822	#define DCBX_PFC_PRI_7 0x801823#endif1824};1825 1826struct dcbx_app_priority_entry {1827#ifdef __BIG_ENDIAN1828	u16  app_id;1829	u8  pri_bitmap;1830	u8  appBitfield;1831	#define DCBX_APP_ENTRY_VALID         0x011832	#define DCBX_APP_ENTRY_SF_MASK       0xF01833	#define DCBX_APP_ENTRY_SF_SHIFT      41834	#define DCBX_APP_SF_ETH_TYPE         0x101835	#define DCBX_APP_SF_PORT             0x201836	#define DCBX_APP_SF_UDP              0x401837	#define DCBX_APP_SF_DEFAULT          0x801838#elif defined(__LITTLE_ENDIAN)1839	u8 appBitfield;1840	#define DCBX_APP_ENTRY_VALID         0x011841	#define DCBX_APP_ENTRY_SF_MASK       0xF01842	#define DCBX_APP_ENTRY_SF_SHIFT      41843	#define DCBX_APP_ENTRY_VALID         0x011844	#define DCBX_APP_SF_ETH_TYPE         0x101845	#define DCBX_APP_SF_PORT             0x201846	#define DCBX_APP_SF_UDP              0x401847	#define DCBX_APP_SF_DEFAULT          0x801848	u8  pri_bitmap;1849	u16  app_id;1850#endif1851};1852 1853 1854/* FW structure in BE */1855struct dcbx_app_priority_feature {1856#ifdef __BIG_ENDIAN1857	u8 reserved;1858	u8 default_pri;1859	u8 tc_supported;1860	u8 enabled;1861#elif defined(__LITTLE_ENDIAN)1862	u8 enabled;1863	u8 tc_supported;1864	u8 default_pri;1865	u8 reserved;1866#endif1867	struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];1868};1869 1870/* FW structure in BE */1871struct dcbx_features {1872	/* PG feature */1873	struct dcbx_ets_feature ets;1874	/* PFC feature */1875	struct dcbx_pfc_feature pfc;1876	/* APP feature */1877	struct dcbx_app_priority_feature app;1878};1879 1880/* LLDP protocol parameters */1881/* FW structure in BE */1882struct lldp_params {1883#ifdef __BIG_ENDIAN1884	u8  msg_fast_tx_interval;1885	u8  msg_tx_hold;1886	u8  msg_tx_interval;1887	u8  admin_status;1888	#define LLDP_TX_ONLY  0x011889	#define LLDP_RX_ONLY  0x021890	#define LLDP_TX_RX    0x031891	#define LLDP_DISABLED 0x041892	u8  reserved1;1893	u8  tx_fast;1894	u8  tx_crd_max;1895	u8  tx_crd;1896#elif defined(__LITTLE_ENDIAN)1897	u8  admin_status;1898	#define LLDP_TX_ONLY  0x011899	#define LLDP_RX_ONLY  0x021900	#define LLDP_TX_RX    0x031901	#define LLDP_DISABLED 0x041902	u8  msg_tx_interval;1903	u8  msg_tx_hold;1904	u8  msg_fast_tx_interval;1905	u8  tx_crd;1906	u8  tx_crd_max;1907	u8  tx_fast;1908	u8  reserved1;1909#endif1910	#define REM_CHASSIS_ID_STAT_LEN 41911	#define REM_PORT_ID_STAT_LEN 41912	/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */1913	u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];1914	/* Holds remote Port ID TLV header, subtype and 9B of payload. */1915	u32 peer_port_id[REM_PORT_ID_STAT_LEN];1916};1917 1918struct lldp_dcbx_stat {1919	#define LOCAL_CHASSIS_ID_STAT_LEN 21920	#define LOCAL_PORT_ID_STAT_LEN 21921	/* Holds local Chassis ID 8B payload of constant subtype 4. */1922	u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];1923	/* Holds local Port ID 8B payload of constant subtype 3. */1924	u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];1925	/* Number of DCBX frames transmitted. */1926	u32 num_tx_dcbx_pkts;1927	/* Number of DCBX frames received. */1928	u32 num_rx_dcbx_pkts;1929};1930 1931/* ADMIN MIB - DCBX local machine default configuration. */1932struct lldp_admin_mib {1933	u32     ver_cfg_flags;1934	#define DCBX_ETS_CONFIG_TX_ENABLED       0x000000011935	#define DCBX_PFC_CONFIG_TX_ENABLED       0x000000021936	#define DCBX_APP_CONFIG_TX_ENABLED       0x000000041937	#define DCBX_ETS_RECO_TX_ENABLED         0x000000081938	#define DCBX_ETS_RECO_VALID              0x000000101939	#define DCBX_ETS_WILLING                 0x000000201940	#define DCBX_PFC_WILLING                 0x000000401941	#define DCBX_APP_WILLING                 0x000000801942	#define DCBX_VERSION_CEE                 0x000001001943	#define DCBX_VERSION_IEEE                0x000002001944	#define DCBX_DCBX_ENABLED                0x000004001945	#define DCBX_CEE_VERSION_MASK            0x0000f0001946	#define DCBX_CEE_VERSION_SHIFT           121947	#define DCBX_CEE_MAX_VERSION_MASK        0x000f00001948	#define DCBX_CEE_MAX_VERSION_SHIFT       161949	struct dcbx_features     features;1950};1951 1952/* REMOTE MIB - remote machine DCBX configuration. */1953struct lldp_remote_mib {1954	u32 prefix_seq_num;1955	u32 flags;1956	#define DCBX_ETS_TLV_RX                  0x000000011957	#define DCBX_PFC_TLV_RX                  0x000000021958	#define DCBX_APP_TLV_RX                  0x000000041959	#define DCBX_ETS_RX_ERROR                0x000000101960	#define DCBX_PFC_RX_ERROR                0x000000201961	#define DCBX_APP_RX_ERROR                0x000000401962	#define DCBX_ETS_REM_WILLING             0x000001001963	#define DCBX_PFC_REM_WILLING             0x000002001964	#define DCBX_APP_REM_WILLING             0x000004001965	#define DCBX_REMOTE_ETS_RECO_VALID       0x000010001966	#define DCBX_REMOTE_MIB_VALID            0x000020001967	struct dcbx_features features;1968	u32 suffix_seq_num;1969};1970 1971/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */1972struct lldp_local_mib {1973	u32 prefix_seq_num;1974	/* Indicates if there is mismatch with negotiation results. */1975	u32 error;1976	#define DCBX_LOCAL_ETS_ERROR             0x000000011977	#define DCBX_LOCAL_PFC_ERROR             0x000000021978	#define DCBX_LOCAL_APP_ERROR             0x000000041979	#define DCBX_LOCAL_PFC_MISMATCH          0x000000101980	#define DCBX_LOCAL_APP_MISMATCH          0x000000201981	#define DCBX_REMOTE_MIB_ERROR		 0x000000401982	#define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x000000801983	#define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x000001001984	#define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x000002001985	struct dcbx_features   features;1986	u32 suffix_seq_num;1987};1988/***END OF DCBX STRUCTURES DECLARATIONS***/1989 1990/***********************************************************/1991/*                         Elink section                   */1992/***********************************************************/1993#define SHMEM_LINK_CONFIG_SIZE 21994struct shmem_lfa {1995	u32 req_duplex;1996	#define REQ_DUPLEX_PHY0_MASK        0x0000ffff1997	#define REQ_DUPLEX_PHY0_SHIFT       01998	#define REQ_DUPLEX_PHY1_MASK        0xffff00001999	#define REQ_DUPLEX_PHY1_SHIFT       162000	u32 req_flow_ctrl;2001	#define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff2002	#define REQ_FLOW_CTRL_PHY0_SHIFT    02003	#define REQ_FLOW_CTRL_PHY1_MASK     0xffff00002004	#define REQ_FLOW_CTRL_PHY1_SHIFT    162005	u32 req_line_speed; /* Also determine AutoNeg */2006	#define REQ_LINE_SPD_PHY0_MASK      0x0000ffff2007	#define REQ_LINE_SPD_PHY0_SHIFT     02008	#define REQ_LINE_SPD_PHY1_MASK      0xffff00002009	#define REQ_LINE_SPD_PHY1_SHIFT     162010	u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];2011	u32 additional_config;2012	#define REQ_FC_AUTO_ADV_MASK        0x0000ffff2013	#define REQ_FC_AUTO_ADV0_SHIFT      02014	#define NO_LFA_DUE_TO_DCC_MASK      0x000100002015	u32 lfa_sts;2016	#define LFA_LINK_FLAP_REASON_OFFSET		02017	#define LFA_LINK_FLAP_REASON_MASK		0x000000ff2018		#define LFA_LINK_DOWN			    0x12019		#define LFA_LOOPBACK_ENABLED		0x22020		#define LFA_DUPLEX_MISMATCH		    0x32021		#define LFA_MFW_IS_TOO_OLD		    0x42022		#define LFA_LINK_SPEED_MISMATCH		0x52023		#define LFA_FLOW_CTRL_MISMATCH		0x62024		#define LFA_SPEED_CAP_MISMATCH		0x72025		#define LFA_DCC_LFA_DISABLED		0x82026		#define LFA_EEE_MISMATCH		0x92027 2028	#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET	82029	#define LINK_FLAP_AVOIDANCE_COUNT_MASK		0x0000ff002030 2031	#define LINK_FLAP_COUNT_OFFSET			162032	#define LINK_FLAP_COUNT_MASK			0x00ff00002033 2034	#define LFA_FLAGS_MASK				0xff0000002035	#define SHMEM_LFA_DONT_CLEAR_STAT		(1<<24)2036};2037 2038/* Used to support NSCI get OS driver version2039 * on driver load the version value will be set2040 * on driver unload driver value of 0x0 will be set.2041 */2042struct os_drv_ver {2043#define DRV_VER_NOT_LOADED			02044 2045	/* personalties order is important */2046#define DRV_PERS_ETHERNET			02047#define DRV_PERS_ISCSI				12048#define DRV_PERS_FCOE				22049 2050	/* shmem2 struct is constant can't add more personalties here */2051#define MAX_DRV_PERS				32052	u32 versions[MAX_DRV_PERS];2053};2054 2055struct ncsi_oem_fcoe_features {2056	u32 fcoe_features1;2057	#define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF2058	#define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        02059 2060	#define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF00002061	#define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           162062 2063	u32 fcoe_features2;2064	#define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF2065	#define FCOE_FEATURES2_EXCHANGES_OFFSET                 02066 2067	#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF00002068	#define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         162069 2070	u32 fcoe_features3;2071	#define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF2072	#define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         02073 2074	#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF00002075	#define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      162076 2077	u32 fcoe_features4;2078	#define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F2079	#define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          02080};2081 2082enum curr_cfg_method_e {2083	CURR_CFG_MET_NONE = 0,  /* default config */2084	CURR_CFG_MET_OS = 1,2085	CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */2086};2087 2088#define FC_NPIV_WWPN_SIZE 82089#define FC_NPIV_WWNN_SIZE 82090struct bdn_npiv_settings {2091	u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];2092	u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];2093};2094 2095struct bdn_fc_npiv_cfg {2096	/* hdr used internally by the MFW */2097	u32 hdr;2098	u32 num_of_npiv;2099};2100 2101#define MAX_NUMBER_NPIV 642102struct bdn_fc_npiv_tbl {2103	struct bdn_fc_npiv_cfg fc_npiv_cfg;2104	struct bdn_npiv_settings settings[MAX_NUMBER_NPIV];2105};2106 2107struct mdump_driver_info {2108	u32 epoc;2109	u32 drv_ver;2110	u32 fw_ver;2111 2112	u32 valid_dump;2113	#define FIRST_DUMP_VALID        (1 << 0)2114	#define SECOND_DUMP_VALID       (1 << 1)2115 2116	u32 flags;2117	#define ENABLE_ALL_TRIGGERS     (0x7fffffff)2118	#define TRIGGER_MDUMP_ONCE      (1 << 31)2119};2120 2121struct ncsi_oem_data {2122	u32 driver_version[4];2123	struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;2124};2125 2126struct shmem2_region {2127 2128	u32 size;					/* 0x0000 */2129 2130	u32 dcc_support;				/* 0x0004 */2131	#define SHMEM_DCC_SUPPORT_NONE                      0x000000002132	#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x000000012133	#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x000000042134	#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x000000082135	#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x000000402136	#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x000000802137 2138	u32 ext_phy_fw_version2[PORT_MAX];		/* 0x0008 */2139	/*2140	 * For backwards compatibility, if the mf_cfg_addr does not exist2141	 * (the size filed is smaller than 0xc) the mf_cfg resides at the2142	 * end of struct shmem_region2143	 */2144	u32 mf_cfg_addr;				/* 0x0010 */2145	#define SHMEM_MF_CFG_ADDR_NONE                  0x000000002146 2147	struct fw_flr_mb flr_mb;			/* 0x0014 */2148	u32 dcbx_lldp_params_offset;			/* 0x0028 */2149	#define SHMEM_LLDP_DCBX_PARAMS_NONE             0x000000002150	u32 dcbx_neg_res_offset;			/* 0x002c */2151	#define SHMEM_DCBX_NEG_RES_NONE			0x000000002152	u32 dcbx_remote_mib_offset;			/* 0x0030 */2153	#define SHMEM_DCBX_REMOTE_MIB_NONE              0x000000002154	/*2155	 * The other shmemX_base_addr holds the other path's shmem address2156	 * required for example in case of common phy init, or for path1 to know2157	 * the address of mcp debug trace which is located in offset from shmem2158	 * of path02159	 */2160	u32 other_shmem_base_addr;			/* 0x0034 */2161	u32 other_shmem2_base_addr;			/* 0x0038 */2162	/*2163	 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs2164	 * which were disabled/flred2165	 */2166	u32 mcp_vf_disabled[E2_VF_MAX / 32];		/* 0x003c */2167 2168	/*2169	 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled2170	 * VFs2171	 */2172	u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */2173 2174	u32 dcbx_lldp_dcbx_stat_offset;			/* 0x0064 */2175	#define SHMEM_LLDP_DCBX_STAT_NONE               0x000000002176 2177	/*2178	 * edebug_driver_if field is used to transfer messages between edebug2179	 * app to the driver through shmem2.2180	 *2181	 * message format:2182	 * bits 0-2 -  function number / instance of driver to perform request2183	 * bits 3-5 -  op code / is_ack?2184	 * bits 6-63 - data2185	 */2186	u32 edebug_driver_if[2];			/* 0x0068 */2187	#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  12188	#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   22189	#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   32190 2191	u32 nvm_retain_bitmap_addr;			/* 0x0070 */2192 2193	/* afex support of that driver */2194	u32 afex_driver_support;			/* 0x0074 */2195	#define SHMEM_AFEX_VERSION_MASK                  0x100f2196	#define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x10012197	#define SHMEM_AFEX_REDUCED_DRV_LOADED            0x80002198 2199	/* driver receives addr in scratchpad to which it should respond */2200	u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];2201 2202	/* generic params from MCP to driver (value depends on the msg sent2203	 * to driver2204	 */2205	u32 afex_param1_to_driver[E2_FUNC_MAX];		/* 0x0088 */2206	u32 afex_param2_to_driver[E2_FUNC_MAX];		/* 0x0098 */2207 2208	u32 swim_base_addr;				/* 0x0108 */2209	u32 swim_funcs;2210	u32 swim_main_cb;2211 2212	/* bitmap notifying which VIF profiles stored in nvram are enabled by2213	 * switch2214	 */2215	u32 afex_profiles_enabled[2];2216 2217	/* generic flags controlled by the driver */2218	u32 drv_flags;2219	#define DRV_FLAGS_DCB_CONFIGURED		0x02220	#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED	0x12221	#define DRV_FLAGS_DCB_MFW_CONFIGURED	0x22222 2223	#define DRV_FLAGS_PORT_MASK	((1 << DRV_FLAGS_DCB_CONFIGURED) | \2224			(1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \2225			(1 << DRV_FLAGS_DCB_MFW_CONFIGURED))2226	/* pointer to extended dev_info shared data copied from nvm image */2227	u32 extended_dev_info_shared_addr;2228	u32 ncsi_oem_data_addr;2229 2230	u32 ocsd_host_addr; /* initialized by option ROM */2231	u32 ocbb_host_addr; /* initialized by option ROM */2232	u32 ocsd_req_update_interval; /* initialized by option ROM */2233	u32 temperature_in_half_celsius;2234	u32 glob_struct_in_host;2235 2236	u32 dcbx_neg_res_ext_offset;2237#define SHMEM_DCBX_NEG_RES_EXT_NONE			0x000000002238 2239	u32 drv_capabilities_flag[E2_FUNC_MAX];2240#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x000000012241#define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x000000022242#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x000000042243#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x000000082244#define DRV_FLAGS_MTU_MASK			0xffff00002245#define DRV_FLAGS_MTU_SHIFT			162246 2247	u32 extended_dev_info_shared_cfg_size;2248 2249	u32 dcbx_en[PORT_MAX];2250 2251	/* The offset points to the multi threaded meta structure */2252	u32 multi_thread_data_offset;2253 2254	/* address of DMAable host address holding values from the drivers */2255	u32 drv_info_host_addr_lo;2256	u32 drv_info_host_addr_hi;2257 2258	/* general values written by the MFW (such as current version) */2259	u32 drv_info_control;2260#define DRV_INFO_CONTROL_VER_MASK          0x000000ff2261#define DRV_INFO_CONTROL_VER_SHIFT         02262#define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff002263#define DRV_INFO_CONTROL_OP_CODE_SHIFT     82264	u32 ibft_host_addr; /* initialized by option ROM */2265	struct eee_remote_vals eee_remote_vals[PORT_MAX];2266	u32 reserved[E2_FUNC_MAX];2267 2268 2269	/* the status of EEE auto-negotiation2270	 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.2271	 * bits 19:16 the supported modes for EEE.2272	 * bits 23:20 the speeds advertised for EEE.2273	 * bits 27:24 the speeds the Link partner advertised for EEE.2274	 * The supported/adv. modes in bits 27:19 originate from the2275	 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).2276	 * bit 28 when 1'b1 EEE was requested.2277	 * bit 29 when 1'b1 tx lpi was requested.2278	 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff2279	 * 30:29 are 2'b11.2280	 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as2281	 * value. When 1'b1 those bits contains a value times 16 microseconds.2282	 */2283	u32 eee_status[PORT_MAX];2284	#define SHMEM_EEE_TIMER_MASK		   0x0000ffff2285	#define SHMEM_EEE_SUPPORTED_MASK	   0x000f00002286	#define SHMEM_EEE_SUPPORTED_SHIFT	   162287	#define SHMEM_EEE_ADV_STATUS_MASK	   0x00f000002288		#define SHMEM_EEE_100M_ADV	   (1<<0)2289		#define SHMEM_EEE_1G_ADV	   (1<<1)2290		#define SHMEM_EEE_10G_ADV	   (1<<2)2291	#define SHMEM_EEE_ADV_STATUS_SHIFT	   202292	#define	SHMEM_EEE_LP_ADV_STATUS_MASK	   0x0f0000002293	#define SHMEM_EEE_LP_ADV_STATUS_SHIFT	   242294	#define SHMEM_EEE_REQUESTED_BIT		   0x100000002295	#define SHMEM_EEE_LPI_REQUESTED_BIT	   0x200000002296	#define SHMEM_EEE_ACTIVE_BIT		   0x400000002297	#define SHMEM_EEE_TIME_OUTPUT_BIT	   0x800000002298 2299	u32 sizeof_port_stats;2300 2301	/* Link Flap Avoidance */2302	u32 lfa_host_addr[PORT_MAX];2303	u32 reserved1;2304 2305	u32 reserved2;				/* Offset 0x148 */2306	u32 reserved3;				/* Offset 0x14C */2307	u32 reserved4;				/* Offset 0x150 */2308	u32 link_attr_sync[PORT_MAX];		/* Offset 0x154 */2309	#define LINK_ATTR_SYNC_KR2_ENABLE	0x000000012310	#define LINK_ATTR_84858			0x000000022311	#define LINK_SFP_EEPROM_COMP_CODE_MASK	0x0000ff002312	#define LINK_SFP_EEPROM_COMP_CODE_SHIFT		 82313	#define LINK_SFP_EEPROM_COMP_CODE_SR	0x000010002314	#define LINK_SFP_EEPROM_COMP_CODE_LR	0x000020002315	#define LINK_SFP_EEPROM_COMP_CODE_LRM	0x000040002316 2317	u32 reserved5[2];2318	u32 link_change_count[PORT_MAX];        /* Offset 0x160-0x164 */2319	#define LINK_CHANGE_COUNT_MASK 0xff     /* Offset 0x168 */2320	/* driver version for each personality */2321	struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */2322 2323	/* Flag to the driver that PF's drv_info_host_addr buffer was read  */2324	u32 mfw_drv_indication;2325 2326	/* We use indication for each PF (0..3) */2327#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))2328	union { /* For various OEMs */			/* Offset 0x1a0 */2329		u8 storage_boot_prog[E2_FUNC_MAX];2330	#define STORAGE_BOOT_PROG_MASK				0x000000FF2331	#define STORAGE_BOOT_PROG_NONE				0x000000002332	#define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED		0x000000022333	#define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS	0x000000022334	#define STORAGE_BOOT_PROG_TARGET_FOUND			0x000000042335	#define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS		0x000000082336	#define STORAGE_BOOT_PROG_FCOE_LUN_FOUND		0x000000082337	#define STORAGE_BOOT_PROG_LOGGED_INTO_TGT		0x000000102338	#define STORAGE_BOOT_PROG_IMG_DOWNLOADED		0x000000202339	#define STORAGE_BOOT_PROG_OS_HANDOFF			0x000000402340	#define STORAGE_BOOT_PROG_COMPLETED			0x000000802341 2342		u32 oem_i2c_data_addr;2343	};2344 2345	/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */2346	/* For PCP values 0-3 use the map lower */2347	/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,2348	 * 0x0000FF00 - PCP 2, 0x000000FF PCP 32349	 */2350	u32 c2s_pcp_map_lower[E2_FUNC_MAX];			/* 0x1a4 */2351 2352	/* For PCP values 4-7 use the map upper */2353	/* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,2354	 * 0x0000FF00 - PCP 6, 0x000000FF PCP 72355	 */2356	u32 c2s_pcp_map_upper[E2_FUNC_MAX];			/* 0x1b4 */2357 2358	/* For PCP default value get the MSB byte of the map default */2359	u32 c2s_pcp_map_default[E2_FUNC_MAX];			/* 0x1c4 */2360 2361	/* FC_NPIV table offset in NVRAM */2362	u32 fc_npiv_nvram_tbl_addr[PORT_MAX];			/* 0x1d4 */2363 2364	/* Shows last method that changed configuration of this device */2365	enum curr_cfg_method_e curr_cfg;			/* 0x1dc */2366 2367	/* Storm FW version, shold be kept in the format 0xMMmmbbdd:2368	 * MM - Major, mm - Minor, bb - Build ,dd - Drop2369	 */2370	u32 netproc_fw_ver;					/* 0x1e0 */2371 2372	/* Option ROM SMASH CLP version */2373	u32 clp_ver;						/* 0x1e4 */2374 2375	u32 pcie_bus_num;					/* 0x1e8 */2376 2377	u32 sriov_switch_mode;					/* 0x1ec */2378	#define SRIOV_SWITCH_MODE_NONE		0x02379	#define SRIOV_SWITCH_MODE_VEB		0x12380	#define SRIOV_SWITCH_MODE_VEPA		0x22381 2382	u8  rsrv2[E2_FUNC_MAX];					/* 0x1f0 */2383 2384	u32 img_inv_table_addr;	/* Address to INV_TABLE_P */	/* 0x1f4 */2385 2386	u32 mtu_size[E2_FUNC_MAX];				/* 0x1f8 */2387 2388	u32 os_driver_state[E2_FUNC_MAX];			/* 0x208 */2389	#define OS_DRIVER_STATE_NOT_LOADED	0 /* not installed */2390	#define OS_DRIVER_STATE_LOADING		1 /* transition state */2391	#define OS_DRIVER_STATE_DISABLED	2 /* installed but disabled */2392	#define OS_DRIVER_STATE_ACTIVE		3 /* installed and active */2393 2394	/* mini dump driver info */2395	struct mdump_driver_info drv_info;			/* 0x218 */2396};2397 2398 2399struct emac_stats {2400	u32     rx_stat_ifhcinoctets;2401	u32     rx_stat_ifhcinbadoctets;2402	u32     rx_stat_etherstatsfragments;2403	u32     rx_stat_ifhcinucastpkts;2404	u32     rx_stat_ifhcinmulticastpkts;2405	u32     rx_stat_ifhcinbroadcastpkts;2406	u32     rx_stat_dot3statsfcserrors;2407	u32     rx_stat_dot3statsalignmenterrors;2408	u32     rx_stat_dot3statscarriersenseerrors;2409	u32     rx_stat_xonpauseframesreceived;2410	u32     rx_stat_xoffpauseframesreceived;2411	u32     rx_stat_maccontrolframesreceived;2412	u32     rx_stat_xoffstateentered;2413	u32     rx_stat_dot3statsframestoolong;2414	u32     rx_stat_etherstatsjabbers;2415	u32     rx_stat_etherstatsundersizepkts;2416	u32     rx_stat_etherstatspkts64octets;2417	u32     rx_stat_etherstatspkts65octetsto127octets;2418	u32     rx_stat_etherstatspkts128octetsto255octets;2419	u32     rx_stat_etherstatspkts256octetsto511octets;2420	u32     rx_stat_etherstatspkts512octetsto1023octets;2421	u32     rx_stat_etherstatspkts1024octetsto1522octets;2422	u32     rx_stat_etherstatspktsover1522octets;2423 2424	u32     rx_stat_falsecarriererrors;2425 2426	u32     tx_stat_ifhcoutoctets;2427	u32     tx_stat_ifhcoutbadoctets;2428	u32     tx_stat_etherstatscollisions;2429	u32     tx_stat_outxonsent;2430	u32     tx_stat_outxoffsent;2431	u32     tx_stat_flowcontroldone;2432	u32     tx_stat_dot3statssinglecollisionframes;2433	u32     tx_stat_dot3statsmultiplecollisionframes;2434	u32     tx_stat_dot3statsdeferredtransmissions;2435	u32     tx_stat_dot3statsexcessivecollisions;2436	u32     tx_stat_dot3statslatecollisions;2437	u32     tx_stat_ifhcoutucastpkts;2438	u32     tx_stat_ifhcoutmulticastpkts;2439	u32     tx_stat_ifhcoutbroadcastpkts;2440	u32     tx_stat_etherstatspkts64octets;2441	u32     tx_stat_etherstatspkts65octetsto127octets;2442	u32     tx_stat_etherstatspkts128octetsto255octets;2443	u32     tx_stat_etherstatspkts256octetsto511octets;2444	u32     tx_stat_etherstatspkts512octetsto1023octets;2445	u32     tx_stat_etherstatspkts1024octetsto1522octets;2446	u32     tx_stat_etherstatspktsover1522octets;2447	u32     tx_stat_dot3statsinternalmactransmiterrors;2448};2449 2450 2451struct bmac1_stats {2452	u32	tx_stat_gtpkt_lo;2453	u32	tx_stat_gtpkt_hi;2454	u32	tx_stat_gtxpf_lo;2455	u32	tx_stat_gtxpf_hi;2456	u32	tx_stat_gtfcs_lo;2457	u32	tx_stat_gtfcs_hi;2458	u32	tx_stat_gtmca_lo;2459	u32	tx_stat_gtmca_hi;2460	u32	tx_stat_gtbca_lo;2461	u32	tx_stat_gtbca_hi;2462	u32	tx_stat_gtfrg_lo;2463	u32	tx_stat_gtfrg_hi;2464	u32	tx_stat_gtovr_lo;2465	u32	tx_stat_gtovr_hi;2466	u32	tx_stat_gt64_lo;2467	u32	tx_stat_gt64_hi;2468	u32	tx_stat_gt127_lo;2469	u32	tx_stat_gt127_hi;2470	u32	tx_stat_gt255_lo;2471	u32	tx_stat_gt255_hi;2472	u32	tx_stat_gt511_lo;2473	u32	tx_stat_gt511_hi;2474	u32	tx_stat_gt1023_lo;2475	u32	tx_stat_gt1023_hi;2476	u32	tx_stat_gt1518_lo;2477	u32	tx_stat_gt1518_hi;2478	u32	tx_stat_gt2047_lo;2479	u32	tx_stat_gt2047_hi;2480	u32	tx_stat_gt4095_lo;2481	u32	tx_stat_gt4095_hi;2482	u32	tx_stat_gt9216_lo;2483	u32	tx_stat_gt9216_hi;2484	u32	tx_stat_gt16383_lo;2485	u32	tx_stat_gt16383_hi;2486	u32	tx_stat_gtmax_lo;2487	u32	tx_stat_gtmax_hi;2488	u32	tx_stat_gtufl_lo;2489	u32	tx_stat_gtufl_hi;2490	u32	tx_stat_gterr_lo;2491	u32	tx_stat_gterr_hi;2492	u32	tx_stat_gtbyt_lo;2493	u32	tx_stat_gtbyt_hi;2494 2495	u32	rx_stat_gr64_lo;2496	u32	rx_stat_gr64_hi;2497	u32	rx_stat_gr127_lo;2498	u32	rx_stat_gr127_hi;2499	u32	rx_stat_gr255_lo;2500	u32	rx_stat_gr255_hi;2501	u32	rx_stat_gr511_lo;2502	u32	rx_stat_gr511_hi;2503	u32	rx_stat_gr1023_lo;2504	u32	rx_stat_gr1023_hi;2505	u32	rx_stat_gr1518_lo;2506	u32	rx_stat_gr1518_hi;2507	u32	rx_stat_gr2047_lo;2508	u32	rx_stat_gr2047_hi;2509	u32	rx_stat_gr4095_lo;2510	u32	rx_stat_gr4095_hi;2511	u32	rx_stat_gr9216_lo;2512	u32	rx_stat_gr9216_hi;2513	u32	rx_stat_gr16383_lo;2514	u32	rx_stat_gr16383_hi;2515	u32	rx_stat_grmax_lo;2516	u32	rx_stat_grmax_hi;2517	u32	rx_stat_grpkt_lo;2518	u32	rx_stat_grpkt_hi;2519	u32	rx_stat_grfcs_lo;2520	u32	rx_stat_grfcs_hi;2521	u32	rx_stat_grmca_lo;2522	u32	rx_stat_grmca_hi;2523	u32	rx_stat_grbca_lo;2524	u32	rx_stat_grbca_hi;2525	u32	rx_stat_grxcf_lo;2526	u32	rx_stat_grxcf_hi;2527	u32	rx_stat_grxpf_lo;2528	u32	rx_stat_grxpf_hi;2529	u32	rx_stat_grxuo_lo;2530	u32	rx_stat_grxuo_hi;2531	u32	rx_stat_grjbr_lo;2532	u32	rx_stat_grjbr_hi;2533	u32	rx_stat_grovr_lo;2534	u32	rx_stat_grovr_hi;2535	u32	rx_stat_grflr_lo;2536	u32	rx_stat_grflr_hi;2537	u32	rx_stat_grmeg_lo;2538	u32	rx_stat_grmeg_hi;2539	u32	rx_stat_grmeb_lo;2540	u32	rx_stat_grmeb_hi;2541	u32	rx_stat_grbyt_lo;2542	u32	rx_stat_grbyt_hi;2543	u32	rx_stat_grund_lo;2544	u32	rx_stat_grund_hi;2545	u32	rx_stat_grfrg_lo;2546	u32	rx_stat_grfrg_hi;2547	u32	rx_stat_grerb_lo;2548	u32	rx_stat_grerb_hi;2549	u32	rx_stat_grfre_lo;2550	u32	rx_stat_grfre_hi;2551	u32	rx_stat_gripj_lo;2552	u32	rx_stat_gripj_hi;2553};2554 2555struct bmac2_stats {2556	u32	tx_stat_gtpk_lo; /* gtpok */2557	u32	tx_stat_gtpk_hi; /* gtpok */2558	u32	tx_stat_gtxpf_lo; /* gtpf */2559	u32	tx_stat_gtxpf_hi; /* gtpf */2560	u32	tx_stat_gtpp_lo; /* NEW BMAC2 */2561	u32	tx_stat_gtpp_hi; /* NEW BMAC2 */2562	u32	tx_stat_gtfcs_lo;2563	u32	tx_stat_gtfcs_hi;2564	u32	tx_stat_gtuca_lo; /* NEW BMAC2 */2565	u32	tx_stat_gtuca_hi; /* NEW BMAC2 */2566	u32	tx_stat_gtmca_lo;2567	u32	tx_stat_gtmca_hi;2568	u32	tx_stat_gtbca_lo;2569	u32	tx_stat_gtbca_hi;2570	u32	tx_stat_gtovr_lo;2571	u32	tx_stat_gtovr_hi;2572	u32	tx_stat_gtfrg_lo;2573	u32	tx_stat_gtfrg_hi;2574	u32	tx_stat_gtpkt1_lo; /* gtpkt */2575	u32	tx_stat_gtpkt1_hi; /* gtpkt */2576	u32	tx_stat_gt64_lo;2577	u32	tx_stat_gt64_hi;2578	u32	tx_stat_gt127_lo;2579	u32	tx_stat_gt127_hi;2580	u32	tx_stat_gt255_lo;2581	u32	tx_stat_gt255_hi;2582	u32	tx_stat_gt511_lo;2583	u32	tx_stat_gt511_hi;2584	u32	tx_stat_gt1023_lo;2585	u32	tx_stat_gt1023_hi;2586	u32	tx_stat_gt1518_lo;2587	u32	tx_stat_gt1518_hi;2588	u32	tx_stat_gt2047_lo;2589	u32	tx_stat_gt2047_hi;2590	u32	tx_stat_gt4095_lo;2591	u32	tx_stat_gt4095_hi;2592	u32	tx_stat_gt9216_lo;2593	u32	tx_stat_gt9216_hi;2594	u32	tx_stat_gt16383_lo;2595	u32	tx_stat_gt16383_hi;2596	u32	tx_stat_gtmax_lo;2597	u32	tx_stat_gtmax_hi;2598	u32	tx_stat_gtufl_lo;2599	u32	tx_stat_gtufl_hi;2600	u32	tx_stat_gterr_lo;2601	u32	tx_stat_gterr_hi;2602	u32	tx_stat_gtbyt_lo;2603	u32	tx_stat_gtbyt_hi;2604 2605	u32	rx_stat_gr64_lo;2606	u32	rx_stat_gr64_hi;2607	u32	rx_stat_gr127_lo;2608	u32	rx_stat_gr127_hi;2609	u32	rx_stat_gr255_lo;2610	u32	rx_stat_gr255_hi;2611	u32	rx_stat_gr511_lo;2612	u32	rx_stat_gr511_hi;2613	u32	rx_stat_gr1023_lo;2614	u32	rx_stat_gr1023_hi;2615	u32	rx_stat_gr1518_lo;2616	u32	rx_stat_gr1518_hi;2617	u32	rx_stat_gr2047_lo;2618	u32	rx_stat_gr2047_hi;2619	u32	rx_stat_gr4095_lo;2620	u32	rx_stat_gr4095_hi;2621	u32	rx_stat_gr9216_lo;2622	u32	rx_stat_gr9216_hi;2623	u32	rx_stat_gr16383_lo;2624	u32	rx_stat_gr16383_hi;2625	u32	rx_stat_grmax_lo;2626	u32	rx_stat_grmax_hi;2627	u32	rx_stat_grpkt_lo;2628	u32	rx_stat_grpkt_hi;2629	u32	rx_stat_grfcs_lo;2630	u32	rx_stat_grfcs_hi;2631	u32	rx_stat_gruca_lo;2632	u32	rx_stat_gruca_hi;2633	u32	rx_stat_grmca_lo;2634	u32	rx_stat_grmca_hi;2635	u32	rx_stat_grbca_lo;2636	u32	rx_stat_grbca_hi;2637	u32	rx_stat_grxpf_lo; /* grpf */2638	u32	rx_stat_grxpf_hi; /* grpf */2639	u32	rx_stat_grpp_lo;2640	u32	rx_stat_grpp_hi;2641	u32	rx_stat_grxuo_lo; /* gruo */2642	u32	rx_stat_grxuo_hi; /* gruo */2643	u32	rx_stat_grjbr_lo;2644	u32	rx_stat_grjbr_hi;2645	u32	rx_stat_grovr_lo;2646	u32	rx_stat_grovr_hi;2647	u32	rx_stat_grxcf_lo; /* grcf */2648	u32	rx_stat_grxcf_hi; /* grcf */2649	u32	rx_stat_grflr_lo;2650	u32	rx_stat_grflr_hi;2651	u32	rx_stat_grpok_lo;2652	u32	rx_stat_grpok_hi;2653	u32	rx_stat_grmeg_lo;2654	u32	rx_stat_grmeg_hi;2655	u32	rx_stat_grmeb_lo;2656	u32	rx_stat_grmeb_hi;2657	u32	rx_stat_grbyt_lo;2658	u32	rx_stat_grbyt_hi;2659	u32	rx_stat_grund_lo;2660	u32	rx_stat_grund_hi;2661	u32	rx_stat_grfrg_lo;2662	u32	rx_stat_grfrg_hi;2663	u32	rx_stat_grerb_lo; /* grerrbyt */2664	u32	rx_stat_grerb_hi; /* grerrbyt */2665	u32	rx_stat_grfre_lo; /* grfrerr */2666	u32	rx_stat_grfre_hi; /* grfrerr */2667	u32	rx_stat_gripj_lo;2668	u32	rx_stat_gripj_hi;2669};2670 2671struct mstat_stats {2672	struct {2673		/* OTE MSTAT on E3 has a bug where this register's contents are2674		 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp2675		 */2676		u32 tx_gtxpok_lo;2677		u32 tx_gtxpok_hi;2678		u32 tx_gtxpf_lo;2679		u32 tx_gtxpf_hi;2680		u32 tx_gtxpp_lo;2681		u32 tx_gtxpp_hi;2682		u32 tx_gtfcs_lo;2683		u32 tx_gtfcs_hi;2684		u32 tx_gtuca_lo;2685		u32 tx_gtuca_hi;2686		u32 tx_gtmca_lo;2687		u32 tx_gtmca_hi;2688		u32 tx_gtgca_lo;2689		u32 tx_gtgca_hi;2690		u32 tx_gtpkt_lo;2691		u32 tx_gtpkt_hi;2692		u32 tx_gt64_lo;2693		u32 tx_gt64_hi;2694		u32 tx_gt127_lo;2695		u32 tx_gt127_hi;2696		u32 tx_gt255_lo;2697		u32 tx_gt255_hi;2698		u32 tx_gt511_lo;2699		u32 tx_gt511_hi;2700		u32 tx_gt1023_lo;2701		u32 tx_gt1023_hi;2702		u32 tx_gt1518_lo;2703		u32 tx_gt1518_hi;2704		u32 tx_gt2047_lo;2705		u32 tx_gt2047_hi;2706		u32 tx_gt4095_lo;2707		u32 tx_gt4095_hi;2708		u32 tx_gt9216_lo;2709		u32 tx_gt9216_hi;2710		u32 tx_gt16383_lo;2711		u32 tx_gt16383_hi;2712		u32 tx_gtufl_lo;2713		u32 tx_gtufl_hi;2714		u32 tx_gterr_lo;2715		u32 tx_gterr_hi;2716		u32 tx_gtbyt_lo;2717		u32 tx_gtbyt_hi;2718		u32 tx_collisions_lo;2719		u32 tx_collisions_hi;2720		u32 tx_singlecollision_lo;2721		u32 tx_singlecollision_hi;2722		u32 tx_multiplecollisions_lo;2723		u32 tx_multiplecollisions_hi;2724		u32 tx_deferred_lo;2725		u32 tx_deferred_hi;2726		u32 tx_excessivecollisions_lo;2727		u32 tx_excessivecollisions_hi;2728		u32 tx_latecollisions_lo;2729		u32 tx_latecollisions_hi;2730	} stats_tx;2731 2732	struct {2733		u32 rx_gr64_lo;2734		u32 rx_gr64_hi;2735		u32 rx_gr127_lo;2736		u32 rx_gr127_hi;2737		u32 rx_gr255_lo;2738		u32 rx_gr255_hi;2739		u32 rx_gr511_lo;2740		u32 rx_gr511_hi;2741		u32 rx_gr1023_lo;2742		u32 rx_gr1023_hi;2743		u32 rx_gr1518_lo;2744		u32 rx_gr1518_hi;2745		u32 rx_gr2047_lo;2746		u32 rx_gr2047_hi;2747		u32 rx_gr4095_lo;2748		u32 rx_gr4095_hi;2749		u32 rx_gr9216_lo;2750		u32 rx_gr9216_hi;2751		u32 rx_gr16383_lo;2752		u32 rx_gr16383_hi;2753		u32 rx_grpkt_lo;2754		u32 rx_grpkt_hi;2755		u32 rx_grfcs_lo;2756		u32 rx_grfcs_hi;2757		u32 rx_gruca_lo;2758		u32 rx_gruca_hi;2759		u32 rx_grmca_lo;2760		u32 rx_grmca_hi;2761		u32 rx_grbca_lo;2762		u32 rx_grbca_hi;2763		u32 rx_grxpf_lo;2764		u32 rx_grxpf_hi;2765		u32 rx_grxpp_lo;2766		u32 rx_grxpp_hi;2767		u32 rx_grxuo_lo;2768		u32 rx_grxuo_hi;2769		u32 rx_grovr_lo;2770		u32 rx_grovr_hi;2771		u32 rx_grxcf_lo;2772		u32 rx_grxcf_hi;2773		u32 rx_grflr_lo;2774		u32 rx_grflr_hi;2775		u32 rx_grpok_lo;2776		u32 rx_grpok_hi;2777		u32 rx_grbyt_lo;2778		u32 rx_grbyt_hi;2779		u32 rx_grund_lo;2780		u32 rx_grund_hi;2781		u32 rx_grfrg_lo;2782		u32 rx_grfrg_hi;2783		u32 rx_grerb_lo;2784		u32 rx_grerb_hi;2785		u32 rx_grfre_lo;2786		u32 rx_grfre_hi;2787 2788		u32 rx_alignmenterrors_lo;2789		u32 rx_alignmenterrors_hi;2790		u32 rx_falsecarrier_lo;2791		u32 rx_falsecarrier_hi;2792		u32 rx_llfcmsgcnt_lo;2793		u32 rx_llfcmsgcnt_hi;2794	} stats_rx;2795};2796 2797union mac_stats {2798	struct emac_stats	emac_stats;2799	struct bmac1_stats	bmac1_stats;2800	struct bmac2_stats	bmac2_stats;2801	struct mstat_stats	mstat_stats;2802};2803 2804 2805struct mac_stx {2806	/* in_bad_octets */2807	u32     rx_stat_ifhcinbadoctets_hi;2808	u32     rx_stat_ifhcinbadoctets_lo;2809 2810	/* out_bad_octets */2811	u32     tx_stat_ifhcoutbadoctets_hi;2812	u32     tx_stat_ifhcoutbadoctets_lo;2813 2814	/* crc_receive_errors */2815	u32     rx_stat_dot3statsfcserrors_hi;2816	u32     rx_stat_dot3statsfcserrors_lo;2817	/* alignment_errors */2818	u32     rx_stat_dot3statsalignmenterrors_hi;2819	u32     rx_stat_dot3statsalignmenterrors_lo;2820	/* carrier_sense_errors */2821	u32     rx_stat_dot3statscarriersenseerrors_hi;2822	u32     rx_stat_dot3statscarriersenseerrors_lo;2823	/* false_carrier_detections */2824	u32     rx_stat_falsecarriererrors_hi;2825	u32     rx_stat_falsecarriererrors_lo;2826 2827	/* runt_packets_received */2828	u32     rx_stat_etherstatsundersizepkts_hi;2829	u32     rx_stat_etherstatsundersizepkts_lo;2830	/* jabber_packets_received */2831	u32     rx_stat_dot3statsframestoolong_hi;2832	u32     rx_stat_dot3statsframestoolong_lo;2833 2834	/* error_runt_packets_received */2835	u32     rx_stat_etherstatsfragments_hi;2836	u32     rx_stat_etherstatsfragments_lo;2837	/* error_jabber_packets_received */2838	u32     rx_stat_etherstatsjabbers_hi;2839	u32     rx_stat_etherstatsjabbers_lo;2840 2841	/* control_frames_received */2842	u32     rx_stat_maccontrolframesreceived_hi;2843	u32     rx_stat_maccontrolframesreceived_lo;2844	u32     rx_stat_mac_xpf_hi;2845	u32     rx_stat_mac_xpf_lo;2846	u32     rx_stat_mac_xcf_hi;2847	u32     rx_stat_mac_xcf_lo;2848 2849	/* xoff_state_entered */2850	u32     rx_stat_xoffstateentered_hi;2851	u32     rx_stat_xoffstateentered_lo;2852	/* pause_xon_frames_received */2853	u32     rx_stat_xonpauseframesreceived_hi;2854	u32     rx_stat_xonpauseframesreceived_lo;2855	/* pause_xoff_frames_received */2856	u32     rx_stat_xoffpauseframesreceived_hi;2857	u32     rx_stat_xoffpauseframesreceived_lo;2858	/* pause_xon_frames_transmitted */2859	u32     tx_stat_outxonsent_hi;2860	u32     tx_stat_outxonsent_lo;2861	/* pause_xoff_frames_transmitted */2862	u32     tx_stat_outxoffsent_hi;2863	u32     tx_stat_outxoffsent_lo;2864	/* flow_control_done */2865	u32     tx_stat_flowcontroldone_hi;2866	u32     tx_stat_flowcontroldone_lo;2867 2868	/* ether_stats_collisions */2869	u32     tx_stat_etherstatscollisions_hi;2870	u32     tx_stat_etherstatscollisions_lo;2871	/* single_collision_transmit_frames */2872	u32     tx_stat_dot3statssinglecollisionframes_hi;2873	u32     tx_stat_dot3statssinglecollisionframes_lo;2874	/* multiple_collision_transmit_frames */2875	u32     tx_stat_dot3statsmultiplecollisionframes_hi;2876	u32     tx_stat_dot3statsmultiplecollisionframes_lo;2877	/* deferred_transmissions */2878	u32     tx_stat_dot3statsdeferredtransmissions_hi;2879	u32     tx_stat_dot3statsdeferredtransmissions_lo;2880	/* excessive_collision_frames */2881	u32     tx_stat_dot3statsexcessivecollisions_hi;2882	u32     tx_stat_dot3statsexcessivecollisions_lo;2883	/* late_collision_frames */2884	u32     tx_stat_dot3statslatecollisions_hi;2885	u32     tx_stat_dot3statslatecollisions_lo;2886 2887	/* frames_transmitted_64_bytes */2888	u32     tx_stat_etherstatspkts64octets_hi;2889	u32     tx_stat_etherstatspkts64octets_lo;2890	/* frames_transmitted_65_127_bytes */2891	u32     tx_stat_etherstatspkts65octetsto127octets_hi;2892	u32     tx_stat_etherstatspkts65octetsto127octets_lo;2893	/* frames_transmitted_128_255_bytes */2894	u32     tx_stat_etherstatspkts128octetsto255octets_hi;2895	u32     tx_stat_etherstatspkts128octetsto255octets_lo;2896	/* frames_transmitted_256_511_bytes */2897	u32     tx_stat_etherstatspkts256octetsto511octets_hi;2898	u32     tx_stat_etherstatspkts256octetsto511octets_lo;2899	/* frames_transmitted_512_1023_bytes */2900	u32     tx_stat_etherstatspkts512octetsto1023octets_hi;2901	u32     tx_stat_etherstatspkts512octetsto1023octets_lo;2902	/* frames_transmitted_1024_1522_bytes */2903	u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;2904	u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;2905	/* frames_transmitted_1523_9022_bytes */2906	u32     tx_stat_etherstatspktsover1522octets_hi;2907	u32     tx_stat_etherstatspktsover1522octets_lo;2908	u32     tx_stat_mac_2047_hi;2909	u32     tx_stat_mac_2047_lo;2910	u32     tx_stat_mac_4095_hi;2911	u32     tx_stat_mac_4095_lo;2912	u32     tx_stat_mac_9216_hi;2913	u32     tx_stat_mac_9216_lo;2914	u32     tx_stat_mac_16383_hi;2915	u32     tx_stat_mac_16383_lo;2916 2917	/* internal_mac_transmit_errors */2918	u32     tx_stat_dot3statsinternalmactransmiterrors_hi;2919	u32     tx_stat_dot3statsinternalmactransmiterrors_lo;2920 2921	/* if_out_discards */2922	u32     tx_stat_mac_ufl_hi;2923	u32     tx_stat_mac_ufl_lo;2924};2925 2926 2927#define MAC_STX_IDX_MAX                     22928 2929struct host_port_stats {2930	u32            host_port_stats_counter;2931 2932	struct mac_stx mac_stx[MAC_STX_IDX_MAX];2933 2934	u32            brb_drop_hi;2935	u32            brb_drop_lo;2936 2937	u32            not_used; /* obsolete */2938	u32            pfc_frames_tx_hi;2939	u32            pfc_frames_tx_lo;2940	u32            pfc_frames_rx_hi;2941	u32            pfc_frames_rx_lo;2942 2943	u32            eee_lpi_count_hi;2944	u32            eee_lpi_count_lo;2945};2946 2947 2948struct host_func_stats {2949	u32     host_func_stats_start;2950 2951	u32     total_bytes_received_hi;2952	u32     total_bytes_received_lo;2953 2954	u32     total_bytes_transmitted_hi;2955	u32     total_bytes_transmitted_lo;2956 2957	u32     total_unicast_packets_received_hi;2958	u32     total_unicast_packets_received_lo;2959 2960	u32     total_multicast_packets_received_hi;2961	u32     total_multicast_packets_received_lo;2962 2963	u32     total_broadcast_packets_received_hi;2964	u32     total_broadcast_packets_received_lo;2965 2966	u32     total_unicast_packets_transmitted_hi;2967	u32     total_unicast_packets_transmitted_lo;2968 2969	u32     total_multicast_packets_transmitted_hi;2970	u32     total_multicast_packets_transmitted_lo;2971 2972	u32     total_broadcast_packets_transmitted_hi;2973	u32     total_broadcast_packets_transmitted_lo;2974 2975	u32     valid_bytes_received_hi;2976	u32     valid_bytes_received_lo;2977 2978	u32     host_func_stats_end;2979};2980 2981/* VIC definitions */2982#define VICSTATST_UIF_INDEX 22983 2984 2985/* stats collected for afex.2986 * NOTE: structure is exactly as expected to be received by the switch.2987 *       order must remain exactly as is unless protocol changes !2988 */2989struct afex_stats {2990	u32 tx_unicast_frames_hi;2991	u32 tx_unicast_frames_lo;2992	u32 tx_unicast_bytes_hi;2993	u32 tx_unicast_bytes_lo;2994	u32 tx_multicast_frames_hi;2995	u32 tx_multicast_frames_lo;2996	u32 tx_multicast_bytes_hi;2997	u32 tx_multicast_bytes_lo;2998	u32 tx_broadcast_frames_hi;2999	u32 tx_broadcast_frames_lo;3000	u32 tx_broadcast_bytes_hi;3001	u32 tx_broadcast_bytes_lo;3002	u32 tx_frames_discarded_hi;3003	u32 tx_frames_discarded_lo;3004	u32 tx_frames_dropped_hi;3005	u32 tx_frames_dropped_lo;3006 3007	u32 rx_unicast_frames_hi;3008	u32 rx_unicast_frames_lo;3009	u32 rx_unicast_bytes_hi;3010	u32 rx_unicast_bytes_lo;3011	u32 rx_multicast_frames_hi;3012	u32 rx_multicast_frames_lo;3013	u32 rx_multicast_bytes_hi;3014	u32 rx_multicast_bytes_lo;3015	u32 rx_broadcast_frames_hi;3016	u32 rx_broadcast_frames_lo;3017	u32 rx_broadcast_bytes_hi;3018	u32 rx_broadcast_bytes_lo;3019	u32 rx_frames_discarded_hi;3020	u32 rx_frames_discarded_lo;3021	u32 rx_frames_dropped_hi;3022	u32 rx_frames_dropped_lo;3023};3024 3025#define BCM_5710_FW_MAJOR_VERSION			73026#define BCM_5710_FW_MINOR_VERSION			133027#define BCM_5710_FW_REVISION_VERSION		213028#define BCM_5710_FW_REVISION_VERSION_V15	153029#define BCM_5710_FW_ENGINEERING_VERSION		03030#define BCM_5710_FW_COMPILE_FLAGS			13031 3032 3033/*3034 * attention bits3035 */3036struct atten_sp_status_block {3037	__le32 attn_bits;3038	__le32 attn_bits_ack;3039	u8 status_block_id;3040	u8 reserved0;3041	__le16 attn_bits_index;3042	__le32 reserved1;3043};3044 3045 3046/*3047 * The eth aggregative context of Cstorm3048 */3049struct cstorm_eth_ag_context {3050	u32 __reserved0[10];3051};3052 3053 3054/*3055 * dmae command structure3056 */3057struct dmae_command {3058	u32 opcode;3059#define DMAE_COMMAND_SRC (0x1<<0)3060#define DMAE_COMMAND_SRC_SHIFT 03061#define DMAE_COMMAND_DST (0x3<<1)3062#define DMAE_COMMAND_DST_SHIFT 13063#define DMAE_COMMAND_C_DST (0x1<<3)3064#define DMAE_COMMAND_C_DST_SHIFT 33065#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)3066#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 43067#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)3068#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 53069#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)3070#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 63071#define DMAE_COMMAND_ENDIANITY (0x3<<9)3072#define DMAE_COMMAND_ENDIANITY_SHIFT 93073#define DMAE_COMMAND_PORT (0x1<<11)3074#define DMAE_COMMAND_PORT_SHIFT 113075#define DMAE_COMMAND_CRC_RESET (0x1<<12)3076#define DMAE_COMMAND_CRC_RESET_SHIFT 123077#define DMAE_COMMAND_SRC_RESET (0x1<<13)3078#define DMAE_COMMAND_SRC_RESET_SHIFT 133079#define DMAE_COMMAND_DST_RESET (0x1<<14)3080#define DMAE_COMMAND_DST_RESET_SHIFT 143081#define DMAE_COMMAND_E1HVN (0x3<<15)3082#define DMAE_COMMAND_E1HVN_SHIFT 153083#define DMAE_COMMAND_DST_VN (0x3<<17)3084#define DMAE_COMMAND_DST_VN_SHIFT 173085#define DMAE_COMMAND_C_FUNC (0x1<<19)3086#define DMAE_COMMAND_C_FUNC_SHIFT 193087#define DMAE_COMMAND_ERR_POLICY (0x3<<20)3088#define DMAE_COMMAND_ERR_POLICY_SHIFT 203089#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)3090#define DMAE_COMMAND_RESERVED0_SHIFT 223091	u32 src_addr_lo;3092	u32 src_addr_hi;3093	u32 dst_addr_lo;3094	u32 dst_addr_hi;3095#if defined(__BIG_ENDIAN)3096	u16 opcode_iov;3097#define DMAE_COMMAND_SRC_VFID (0x3F<<0)3098#define DMAE_COMMAND_SRC_VFID_SHIFT 03099#define DMAE_COMMAND_SRC_VFPF (0x1<<6)3100#define DMAE_COMMAND_SRC_VFPF_SHIFT 63101#define DMAE_COMMAND_RESERVED1 (0x1<<7)3102#define DMAE_COMMAND_RESERVED1_SHIFT 73103#define DMAE_COMMAND_DST_VFID (0x3F<<8)3104#define DMAE_COMMAND_DST_VFID_SHIFT 83105#define DMAE_COMMAND_DST_VFPF (0x1<<14)3106#define DMAE_COMMAND_DST_VFPF_SHIFT 143107#define DMAE_COMMAND_RESERVED2 (0x1<<15)3108#define DMAE_COMMAND_RESERVED2_SHIFT 153109	u16 len;3110#elif defined(__LITTLE_ENDIAN)3111	u16 len;3112	u16 opcode_iov;3113#define DMAE_COMMAND_SRC_VFID (0x3F<<0)3114#define DMAE_COMMAND_SRC_VFID_SHIFT 03115#define DMAE_COMMAND_SRC_VFPF (0x1<<6)3116#define DMAE_COMMAND_SRC_VFPF_SHIFT 63117#define DMAE_COMMAND_RESERVED1 (0x1<<7)3118#define DMAE_COMMAND_RESERVED1_SHIFT 73119#define DMAE_COMMAND_DST_VFID (0x3F<<8)3120#define DMAE_COMMAND_DST_VFID_SHIFT 83121#define DMAE_COMMAND_DST_VFPF (0x1<<14)3122#define DMAE_COMMAND_DST_VFPF_SHIFT 143123#define DMAE_COMMAND_RESERVED2 (0x1<<15)3124#define DMAE_COMMAND_RESERVED2_SHIFT 153125#endif3126	u32 comp_addr_lo;3127	u32 comp_addr_hi;3128	u32 comp_val;3129	u32 crc32;3130	u32 crc32_c;3131#if defined(__BIG_ENDIAN)3132	u16 crc16_c;3133	u16 crc16;3134#elif defined(__LITTLE_ENDIAN)3135	u16 crc16;3136	u16 crc16_c;3137#endif3138#if defined(__BIG_ENDIAN)3139	u16 reserved3;3140	u16 crc_t10;3141#elif defined(__LITTLE_ENDIAN)3142	u16 crc_t10;3143	u16 reserved3;3144#endif3145#if defined(__BIG_ENDIAN)3146	u16 xsum8;3147	u16 xsum16;3148#elif defined(__LITTLE_ENDIAN)3149	u16 xsum16;3150	u16 xsum8;3151#endif3152};3153 3154 3155/*3156 * common data for all protocols3157 */3158struct doorbell_hdr {3159	u8 header;3160#define DOORBELL_HDR_RX (0x1<<0)3161#define DOORBELL_HDR_RX_SHIFT 03162#define DOORBELL_HDR_DB_TYPE (0x1<<1)3163#define DOORBELL_HDR_DB_TYPE_SHIFT 13164#define DOORBELL_HDR_DPM_SIZE (0x3<<2)3165#define DOORBELL_HDR_DPM_SIZE_SHIFT 23166#define DOORBELL_HDR_CONN_TYPE (0xF<<4)3167#define DOORBELL_HDR_CONN_TYPE_SHIFT 43168};3169 3170/*3171 * Ethernet doorbell3172 */3173struct eth_tx_doorbell {3174#if defined(__BIG_ENDIAN)3175	u16 npackets;3176	u8 params;3177#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)3178#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 03179#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)3180#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 63181#define ETH_TX_DOORBELL_SPARE (0x1<<7)3182#define ETH_TX_DOORBELL_SPARE_SHIFT 73183	struct doorbell_hdr hdr;3184#elif defined(__LITTLE_ENDIAN)3185	struct doorbell_hdr hdr;3186	u8 params;3187#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)3188#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 03189#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)3190#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 63191#define ETH_TX_DOORBELL_SPARE (0x1<<7)3192#define ETH_TX_DOORBELL_SPARE_SHIFT 73193	u16 npackets;3194#endif3195};3196 3197 3198/*3199 * 3 lines. status block3200 */3201struct hc_status_block_e1x {3202	__le16 index_values[HC_SB_MAX_INDICES_E1X];3203	__le16 running_index[HC_SB_MAX_SM];3204	__le32 rsrv[11];3205};3206 3207/*3208 * host status block3209 */3210struct host_hc_status_block_e1x {3211	struct hc_status_block_e1x sb;3212};3213 3214 3215/*3216 * 3 lines. status block3217 */3218struct hc_status_block_e2 {3219	__le16 index_values[HC_SB_MAX_INDICES_E2];3220	__le16 running_index[HC_SB_MAX_SM];3221	__le32 reserved[11];3222};3223 3224/*3225 * host status block3226 */3227struct host_hc_status_block_e2 {3228	struct hc_status_block_e2 sb;3229};3230 3231 3232/*3233 * 5 lines. slow-path status block3234 */3235struct hc_sp_status_block {3236	__le16 index_values[HC_SP_SB_MAX_INDICES];3237	__le16 running_index;3238	__le16 rsrv;3239	u32 rsrv1;3240};3241 3242/*3243 * host status block3244 */3245struct host_sp_status_block {3246	struct atten_sp_status_block atten_status_block;3247	struct hc_sp_status_block sp_sb;3248};3249 3250 3251/*3252 * IGU driver acknowledgment register3253 */3254struct igu_ack_register {3255#if defined(__BIG_ENDIAN)3256	u16 sb_id_and_flags;3257#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)3258#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 03259#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)3260#define IGU_ACK_REGISTER_STORM_ID_SHIFT 53261#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)3262#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 83263#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)3264#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 93265#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)3266#define IGU_ACK_REGISTER_RESERVED_SHIFT 113267	u16 status_block_index;3268#elif defined(__LITTLE_ENDIAN)3269	u16 status_block_index;3270	u16 sb_id_and_flags;3271#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)3272#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 03273#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)3274#define IGU_ACK_REGISTER_STORM_ID_SHIFT 53275#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)3276#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 83277#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)3278#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 93279#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)3280#define IGU_ACK_REGISTER_RESERVED_SHIFT 113281#endif3282};3283 3284 3285/*3286 * IGU driver acknowledgement register3287 */3288struct igu_backward_compatible {3289	u32 sb_id_and_flags;3290#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)3291#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 03292#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)3293#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 163294#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)3295#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 213296#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)3297#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 243298#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)3299#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 253300#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)3301#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 273302	u32 reserved_2;3303};3304 3305 3306/*3307 * IGU driver acknowledgement register3308 */3309struct igu_regular {3310	u32 sb_id_and_flags;3311#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)3312#define IGU_REGULAR_SB_INDEX_SHIFT 03313#define IGU_REGULAR_RESERVED0 (0x1<<20)3314#define IGU_REGULAR_RESERVED0_SHIFT 203315#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)3316#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 213317#define IGU_REGULAR_BUPDATE (0x1<<24)3318#define IGU_REGULAR_BUPDATE_SHIFT 243319#define IGU_REGULAR_ENABLE_INT (0x3<<25)3320#define IGU_REGULAR_ENABLE_INT_SHIFT 253321#define IGU_REGULAR_RESERVED_1 (0x1<<27)3322#define IGU_REGULAR_RESERVED_1_SHIFT 273323#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)3324#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 283325#define IGU_REGULAR_CLEANUP_SET (0x1<<30)3326#define IGU_REGULAR_CLEANUP_SET_SHIFT 303327#define IGU_REGULAR_BCLEANUP (0x1<<31)3328#define IGU_REGULAR_BCLEANUP_SHIFT 313329	u32 reserved_2;3330};3331 3332/*3333 * IGU driver acknowledgement register3334 */3335union igu_consprod_reg {3336	struct igu_regular regular;3337	struct igu_backward_compatible backward_compatible;3338};3339 3340 3341/*3342 * Igu control commands3343 */3344enum igu_ctrl_cmd {3345	IGU_CTRL_CMD_TYPE_RD,3346	IGU_CTRL_CMD_TYPE_WR,3347	MAX_IGU_CTRL_CMD3348};3349 3350 3351/*3352 * Control register for the IGU command register3353 */3354struct igu_ctrl_reg {3355	u32 ctrl_data;3356#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)3357#define IGU_CTRL_REG_ADDRESS_SHIFT 03358#define IGU_CTRL_REG_FID (0x7F<<12)3359#define IGU_CTRL_REG_FID_SHIFT 123360#define IGU_CTRL_REG_RESERVED (0x1<<19)3361#define IGU_CTRL_REG_RESERVED_SHIFT 193362#define IGU_CTRL_REG_TYPE (0x1<<20)3363#define IGU_CTRL_REG_TYPE_SHIFT 203364#define IGU_CTRL_REG_UNUSED (0x7FF<<21)3365#define IGU_CTRL_REG_UNUSED_SHIFT 213366};3367 3368 3369/*3370 * Igu interrupt command3371 */3372enum igu_int_cmd {3373	IGU_INT_ENABLE,3374	IGU_INT_DISABLE,3375	IGU_INT_NOP,3376	IGU_INT_NOP2,3377	MAX_IGU_INT_CMD3378};3379 3380 3381/*3382 * Igu segments3383 */3384enum igu_seg_access {3385	IGU_SEG_ACCESS_NORM,3386	IGU_SEG_ACCESS_DEF,3387	IGU_SEG_ACCESS_ATTN,3388	MAX_IGU_SEG_ACCESS3389};3390 3391 3392/*3393 * Parser parsing flags field3394 */3395struct parsing_flags {3396	__le16 flags;3397#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)3398#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 03399#define PARSING_FLAGS_VLAN (0x1<<1)3400#define PARSING_FLAGS_VLAN_SHIFT 13401#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)3402#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 23403#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)3404#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 33405#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)3406#define PARSING_FLAGS_IP_OPTIONS_SHIFT 53407#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)3408#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 63409#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)3410#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 73411#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)3412#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 93413#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)3414#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 103415#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)3416#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 113417#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)3418#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 123419#define PARSING_FLAGS_LLC_SNAP (0x1<<13)3420#define PARSING_FLAGS_LLC_SNAP_SHIFT 133421#define PARSING_FLAGS_RESERVED0 (0x3<<14)3422#define PARSING_FLAGS_RESERVED0_SHIFT 143423};3424 3425 3426/*3427 * Parsing flags for TCP ACK type3428 */3429enum prs_flags_ack_type {3430	PRS_FLAG_PUREACK_PIGGY,3431	PRS_FLAG_PUREACK_PURE,3432	MAX_PRS_FLAGS_ACK_TYPE3433};3434 3435 3436/*3437 * Parsing flags for Ethernet address type3438 */3439enum prs_flags_eth_addr_type {3440	PRS_FLAG_ETHTYPE_NON_UNICAST,3441	PRS_FLAG_ETHTYPE_UNICAST,3442	MAX_PRS_FLAGS_ETH_ADDR_TYPE3443};3444 3445 3446/*3447 * Parsing flags for over-ethernet protocol3448 */3449enum prs_flags_over_eth {3450	PRS_FLAG_OVERETH_UNKNOWN,3451	PRS_FLAG_OVERETH_IPV4,3452	PRS_FLAG_OVERETH_IPV6,3453	PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,3454	MAX_PRS_FLAGS_OVER_ETH3455};3456 3457 3458/*3459 * Parsing flags for over-IP protocol3460 */3461enum prs_flags_over_ip {3462	PRS_FLAG_OVERIP_UNKNOWN,3463	PRS_FLAG_OVERIP_TCP,3464	PRS_FLAG_OVERIP_UDP,3465	MAX_PRS_FLAGS_OVER_IP3466};3467 3468 3469/*3470 * SDM operation gen command (generate aggregative interrupt)3471 */3472struct sdm_op_gen {3473	__le32 command;3474#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)3475#define SDM_OP_GEN_COMP_PARAM_SHIFT 03476#define SDM_OP_GEN_COMP_TYPE (0x7<<5)3477#define SDM_OP_GEN_COMP_TYPE_SHIFT 53478#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)3479#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 83480#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)3481#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 163482#define SDM_OP_GEN_RESERVED (0x7FFF<<17)3483#define SDM_OP_GEN_RESERVED_SHIFT 173484};3485 3486 3487/*3488 * Timers connection context3489 */3490struct timers_block_context {3491	u32 __reserved_0;3492	u32 __reserved_1;3493	u32 __reserved_2;3494	u32 flags;3495#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)3496#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 03497#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)3498#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 23499#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)3500#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 33501};3502 3503 3504/*3505 * The eth aggregative context of Tstorm3506 */3507struct tstorm_eth_ag_context {3508	u32 __reserved0[14];3509};3510 3511 3512/*3513 * The eth aggregative context of Ustorm3514 */3515struct ustorm_eth_ag_context {3516	u32 __reserved0;3517#if defined(__BIG_ENDIAN)3518	u8 cdu_usage;3519	u8 __reserved2;3520	u16 __reserved1;3521#elif defined(__LITTLE_ENDIAN)3522	u16 __reserved1;3523	u8 __reserved2;3524	u8 cdu_usage;3525#endif3526	u32 __reserved3[6];3527};3528 3529 3530/*3531 * The eth aggregative context of Xstorm3532 */3533struct xstorm_eth_ag_context {3534	u32 reserved0;3535#if defined(__BIG_ENDIAN)3536	u8 cdu_reserved;3537	u8 reserved2;3538	u16 reserved1;3539#elif defined(__LITTLE_ENDIAN)3540	u16 reserved1;3541	u8 reserved2;3542	u8 cdu_reserved;3543#endif3544	u32 reserved3[30];3545};3546 3547 3548/*3549 * doorbell message sent to the chip3550 */3551struct doorbell {3552#if defined(__BIG_ENDIAN)3553	u16 zero_fill2;3554	u8 zero_fill1;3555	struct doorbell_hdr header;3556#elif defined(__LITTLE_ENDIAN)3557	struct doorbell_hdr header;3558	u8 zero_fill1;3559	u16 zero_fill2;3560#endif3561};3562 3563 3564/*3565 * doorbell message sent to the chip3566 */3567struct doorbell_set_prod {3568#if defined(__BIG_ENDIAN)3569	u16 prod;3570	u8 zero_fill1;3571	struct doorbell_hdr header;3572#elif defined(__LITTLE_ENDIAN)3573	struct doorbell_hdr header;3574	u8 zero_fill1;3575	u16 prod;3576#endif3577};3578 3579 3580struct regpair {3581	__le32 lo;3582	__le32 hi;3583};3584 3585struct regpair_native {3586	u32 lo;3587	u32 hi;3588};3589 3590/*3591 * Classify rule opcodes in E2/E33592 */3593enum classify_rule {3594	CLASSIFY_RULE_OPCODE_MAC,3595	CLASSIFY_RULE_OPCODE_VLAN,3596	CLASSIFY_RULE_OPCODE_PAIR,3597	CLASSIFY_RULE_OPCODE_IMAC_VNI,3598	MAX_CLASSIFY_RULE3599};3600 3601 3602/*3603 * Classify rule types in E2/E33604 */3605enum classify_rule_action_type {3606	CLASSIFY_RULE_REMOVE,3607	CLASSIFY_RULE_ADD,3608	MAX_CLASSIFY_RULE_ACTION_TYPE3609};3610 3611 3612/*3613 * client init ramrod data3614 */3615struct client_init_general_data {3616	u8 client_id;3617	u8 statistics_counter_id;3618	u8 statistics_en_flg;3619	u8 is_fcoe_flg;3620	u8 activate_flg;3621	u8 sp_client_id;3622	__le16 mtu;3623	u8 statistics_zero_flg;3624	u8 func_id;3625	u8 cos;3626	u8 traffic_type;3627	u8 fp_hsi_ver;3628	u8 reserved0[3];3629};3630 3631 3632/*3633 * client init rx data3634 */3635struct client_init_rx_data {3636	u8 tpa_en;3637#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)3638#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 03639#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)3640#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 13641#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)3642#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 23643#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1<<3)3644#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE_SHIFT 33645#define CLIENT_INIT_RX_DATA_RESERVED5 (0xF<<4)3646#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 43647	u8 vmqueue_mode_en_flg;3648	u8 extra_data_over_sgl_en_flg;3649	u8 cache_line_alignment_log_size;3650	u8 enable_dynamic_hc;3651	u8 max_sges_for_packet;3652	u8 client_qzone_id;3653	u8 drop_ip_cs_err_flg;3654	u8 drop_tcp_cs_err_flg;3655	u8 drop_ttl0_flg;3656	u8 drop_udp_cs_err_flg;3657	u8 inner_vlan_removal_enable_flg;3658	u8 outer_vlan_removal_enable_flg;3659	u8 status_block_id;3660	u8 rx_sb_index_number;3661	u8 dont_verify_rings_pause_thr_flg;3662	u8 max_tpa_queues;3663	u8 silent_vlan_removal_flg;3664	__le16 max_bytes_on_bd;3665	__le16 sge_buff_size;3666	u8 approx_mcast_engine_id;3667	u8 rss_engine_id;3668	struct regpair bd_page_base;3669	struct regpair sge_page_base;3670	struct regpair cqe_page_base;3671	u8 is_leading_rss;3672	u8 is_approx_mcast;3673	__le16 max_agg_size;3674	__le16 state;3675#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)3676#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 03677#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)3678#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 13679#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)3680#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 23681#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)3682#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 33683#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)3684#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 43685#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)3686#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 53687#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)3688#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 63689#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)3690#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 73691	__le16 cqe_pause_thr_low;3692	__le16 cqe_pause_thr_high;3693	__le16 bd_pause_thr_low;3694	__le16 bd_pause_thr_high;3695	__le16 sge_pause_thr_low;3696	__le16 sge_pause_thr_high;3697	__le16 rx_cos_mask;3698	__le16 silent_vlan_value;3699	__le16 silent_vlan_mask;3700	u8 handle_ptp_pkts_flg;3701	u8 reserved6[3];3702	__le32 reserved7;3703};3704 3705/*3706 * client init tx data3707 */3708struct client_init_tx_data {3709	u8 enforce_security_flg;3710	u8 tx_status_block_id;3711	u8 tx_sb_index_number;3712	u8 tss_leading_client_id;3713	u8 tx_switching_flg;3714	u8 anti_spoofing_flg;3715	__le16 default_vlan;3716	struct regpair tx_bd_page_base;3717	__le16 state;3718#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)3719#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 03720#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)3721#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 13722#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)3723#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 23724#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)3725#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 33726#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)3727#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 43728	u8 default_vlan_flg;3729	u8 force_default_pri_flg;3730	u8 tunnel_lso_inc_ip_id;3731	u8 refuse_outband_vlan_flg;3732	u8 tunnel_non_lso_pcsum_location;3733	u8 tunnel_non_lso_outer_ip_csum_location;3734};3735 3736/*3737 * client init ramrod data3738 */3739struct client_init_ramrod_data {3740	struct client_init_general_data general;3741	struct client_init_rx_data rx;3742	struct client_init_tx_data tx;3743};3744 3745 3746/*3747 * client update ramrod data3748 */3749struct client_update_ramrod_data {3750	u8 client_id;3751	u8 func_id;3752	u8 inner_vlan_removal_enable_flg;3753	u8 inner_vlan_removal_change_flg;3754	u8 outer_vlan_removal_enable_flg;3755	u8 outer_vlan_removal_change_flg;3756	u8 anti_spoofing_enable_flg;3757	u8 anti_spoofing_change_flg;3758	u8 activate_flg;3759	u8 activate_change_flg;3760	__le16 default_vlan;3761	u8 default_vlan_enable_flg;3762	u8 default_vlan_change_flg;3763	__le16 silent_vlan_value;3764	__le16 silent_vlan_mask;3765	u8 silent_vlan_removal_flg;3766	u8 silent_vlan_change_flg;3767	u8 refuse_outband_vlan_flg;3768	u8 refuse_outband_vlan_change_flg;3769	u8 tx_switching_flg;3770	u8 tx_switching_change_flg;3771	u8 handle_ptp_pkts_flg;3772	u8 handle_ptp_pkts_change_flg;3773	__le16 reserved1;3774	__le32 echo;3775};3776 3777 3778/*3779 * The eth storm context of Cstorm3780 */3781struct cstorm_eth_st_context {3782	u32 __reserved0[4];3783};3784 3785 3786struct double_regpair {3787	u32 regpair0_lo;3788	u32 regpair0_hi;3789	u32 regpair1_lo;3790	u32 regpair1_hi;3791};3792 3793/* 2nd parse bd type used in ethernet tx BDs */3794enum eth_2nd_parse_bd_type {3795	ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,3796	MAX_ETH_2ND_PARSE_BD_TYPE3797};3798 3799/*3800 * Ethernet address typesm used in ethernet tx BDs3801 */3802enum eth_addr_type {3803	UNKNOWN_ADDRESS,3804	UNICAST_ADDRESS,3805	MULTICAST_ADDRESS,3806	BROADCAST_ADDRESS,3807	MAX_ETH_ADDR_TYPE3808};3809 3810 3811/*3812 *3813 */3814struct eth_classify_cmd_header {3815	u8 cmd_general_data;3816#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)3817#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 03818#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)3819#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 13820#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)3821#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 23822#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)3823#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 43824#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)3825#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 53826	u8 func_id;3827	u8 client_id;3828	u8 reserved1;3829};3830 3831 3832/*3833 * header for eth classification config ramrod3834 */3835struct eth_classify_header {3836	u8 rule_cnt;3837	u8 warning_on_error;3838	__le16 reserved1;3839	__le32 echo;3840};3841 3842/*3843 * Command for adding/removing a Inner-MAC/VNI classification rule3844 */3845struct eth_classify_imac_vni_cmd {3846	struct eth_classify_cmd_header header;3847	__le32 vni;3848	__le16 imac_lsb;3849	__le16 imac_mid;3850	__le16 imac_msb;3851	__le16 reserved1;3852};3853 3854/*3855 * Command for adding/removing a MAC classification rule3856 */3857struct eth_classify_mac_cmd {3858	struct eth_classify_cmd_header header;3859	__le16 reserved0;3860	__le16 inner_mac;3861	__le16 mac_lsb;3862	__le16 mac_mid;3863	__le16 mac_msb;3864	__le16 reserved1;3865};3866 3867 3868/*3869 * Command for adding/removing a MAC-VLAN pair classification rule3870 */3871struct eth_classify_pair_cmd {3872	struct eth_classify_cmd_header header;3873	__le16 reserved0;3874	__le16 inner_mac;3875	__le16 mac_lsb;3876	__le16 mac_mid;3877	__le16 mac_msb;3878	__le16 vlan;3879};3880 3881 3882/*3883 * Command for adding/removing a VLAN classification rule3884 */3885struct eth_classify_vlan_cmd {3886	struct eth_classify_cmd_header header;3887	__le32 reserved0;3888	__le32 reserved1;3889	__le16 reserved2;3890	__le16 vlan;3891};3892 3893/*3894 * Command for adding/removing a VXLAN classification rule3895 */3896 3897/*3898 * union for eth classification rule3899 */3900union eth_classify_rule_cmd {3901	struct eth_classify_mac_cmd mac;3902	struct eth_classify_vlan_cmd vlan;3903	struct eth_classify_pair_cmd pair;3904	struct eth_classify_imac_vni_cmd imac_vni;3905};3906 3907/*3908 * parameters for eth classification configuration ramrod3909 */3910struct eth_classify_rules_ramrod_data {3911	struct eth_classify_header header;3912	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];3913};3914 3915 3916/*3917 * The data contain client ID need to the ramrod3918 */3919struct eth_common_ramrod_data {3920	__le32 client_id;3921	__le32 reserved1;3922};3923 3924 3925/*3926 * The eth storm context of Ustorm3927 */3928struct ustorm_eth_st_context {3929	u32 reserved0[52];3930};3931 3932/*3933 * The eth storm context of Tstorm3934 */3935struct tstorm_eth_st_context {3936	u32 __reserved0[28];3937};3938 3939/*3940 * The eth storm context of Xstorm3941 */3942struct xstorm_eth_st_context {3943	u32 reserved0[60];3944};3945 3946/*3947 * Ethernet connection context3948 */3949struct eth_context {3950	struct ustorm_eth_st_context ustorm_st_context;3951	struct tstorm_eth_st_context tstorm_st_context;3952	struct xstorm_eth_ag_context xstorm_ag_context;3953	struct tstorm_eth_ag_context tstorm_ag_context;3954	struct cstorm_eth_ag_context cstorm_ag_context;3955	struct ustorm_eth_ag_context ustorm_ag_context;3956	struct timers_block_context timers_context;3957	struct xstorm_eth_st_context xstorm_st_context;3958	struct cstorm_eth_st_context cstorm_st_context;3959};3960 3961 3962/*3963 * union for sgl and raw data.3964 */3965union eth_sgl_or_raw_data {3966	__le16 sgl[8];3967	u32 raw_data[4];3968};3969 3970/*3971 * eth FP end aggregation CQE parameters struct3972 */3973struct eth_end_agg_rx_cqe {3974	u8 type_error_flags;3975#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)3976#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 03977#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)3978#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 23979#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)3980#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 33981	u8 reserved1;3982	u8 queue_index;3983	u8 reserved2;3984	__le32 timestamp_delta;3985	__le16 num_of_coalesced_segs;3986	__le16 pkt_len;3987	u8 pure_ack_count;3988	u8 reserved3;3989	__le16 reserved4;3990	union eth_sgl_or_raw_data sgl_or_raw_data;3991	__le32 reserved5[8];3992};3993 3994 3995/*3996 * regular eth FP CQE parameters struct3997 */3998struct eth_fast_path_rx_cqe {3999	u8 type_error_flags;4000#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)4001#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 04002#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)4003#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 24004#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)4005#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 34006#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)4007#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 44008#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)4009#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 54010#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)4011#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 64012#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)4013#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 74014	u8 status_flags;4015#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)4016#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 04017#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)4018#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 34019#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)4020#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 44021#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)4022#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 54023#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)4024#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 64025#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)4026#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 74027	u8 queue_index;4028	u8 placement_offset;4029	__le32 rss_hash_result;4030	__le16 vlan_tag;4031	__le16 pkt_len_or_gro_seg_len;4032	__le16 len_on_bd;4033	struct parsing_flags pars_flags;4034	union eth_sgl_or_raw_data sgl_or_raw_data;4035	u8 tunn_type;4036	u8 tunn_inner_hdrs_offset;4037	__le16 reserved1;4038	__le32 tunn_tenant_id;4039	__le32 padding[5];4040	u32 marker;4041};4042 4043 4044/*4045 * Command for setting classification flags for a client4046 */4047struct eth_filter_rules_cmd {4048	u8 cmd_general_data;4049#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)4050#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 04051#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)4052#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 14053#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)4054#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 24055	u8 func_id;4056	u8 client_id;4057	u8 reserved1;4058	__le16 state;4059#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)4060#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 04061#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)4062#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 14063#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)4064#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 24065#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)4066#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 34067#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)4068#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 44069#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)4070#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 54071#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)4072#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 64073#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)4074#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 74075	__le16 reserved3;4076	struct regpair reserved4;4077};4078 4079 4080/*4081 * parameters for eth classification filters ramrod4082 */4083struct eth_filter_rules_ramrod_data {4084	struct eth_classify_header header;4085	struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];4086};4087 4088/* Hsi version */4089enum eth_fp_hsi_ver {4090	ETH_FP_HSI_VER_0,4091	ETH_FP_HSI_VER_1,4092	ETH_FP_HSI_VER_2,4093	MAX_ETH_FP_HSI_VER4094};4095 4096/*4097 * parameters for eth classification configuration ramrod4098 */4099struct eth_general_rules_ramrod_data {4100	struct eth_classify_header header;4101	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];4102};4103 4104 4105/*4106 * The data for Halt ramrod4107 */4108struct eth_halt_ramrod_data {4109	__le32 client_id;4110	__le32 reserved0;4111};4112 4113 4114/*4115 * destination and source mac address.4116 */4117struct eth_mac_addresses {4118#if defined(__BIG_ENDIAN)4119	__le16 dst_mid;4120	__le16 dst_lo;4121#elif defined(__LITTLE_ENDIAN)4122	__le16 dst_lo;4123	__le16 dst_mid;4124#endif4125#if defined(__BIG_ENDIAN)4126	__le16 src_lo;4127	__le16 dst_hi;4128#elif defined(__LITTLE_ENDIAN)4129	__le16 dst_hi;4130	__le16 src_lo;4131#endif4132#if defined(__BIG_ENDIAN)4133	__le16 src_hi;4134	__le16 src_mid;4135#elif defined(__LITTLE_ENDIAN)4136	__le16 src_mid;4137	__le16 src_hi;4138#endif4139};4140 4141/* tunneling related data */4142struct eth_tunnel_data {4143	__le16 dst_lo;4144	__le16 dst_mid;4145	__le16 dst_hi;4146	__le16 fw_ip_hdr_csum;4147	__le16 pseudo_csum;4148	u8 ip_hdr_start_inner_w;4149	u8 flags;4150#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)4151#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 04152#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)4153#define ETH_TUNNEL_DATA_RESERVED_SHIFT 14154};4155 4156/* union for mac addresses and for tunneling data.4157 * considered as tunneling data only if (tunnel_exist == 1).4158 */4159union eth_mac_addr_or_tunnel_data {4160	struct eth_mac_addresses mac_addr;4161	struct eth_tunnel_data tunnel_data;4162};4163 4164/*Command for setting multicast classification for a client */4165struct eth_multicast_rules_cmd {4166	u8 cmd_general_data;4167#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)4168#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 04169#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)4170#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 14171#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)4172#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 24173#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)4174#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 34175	u8 func_id;4176	u8 bin_id;4177	u8 engine_id;4178	__le32 reserved2;4179	struct regpair reserved3;4180};4181 4182/*4183 * parameters for multicast classification ramrod4184 */4185struct eth_multicast_rules_ramrod_data {4186	struct eth_classify_header header;4187	struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];4188};4189 4190/*4191 * Place holder for ramrods protocol specific data4192 */4193struct ramrod_data {4194	__le32 data_lo;4195	__le32 data_hi;4196};4197 4198/*4199 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)4200 */4201union eth_ramrod_data {4202	struct ramrod_data general;4203};4204 4205 4206/*4207 * RSS toeplitz hash type, as reported in CQE4208 */4209enum eth_rss_hash_type {4210	DEFAULT_HASH_TYPE,4211	IPV4_HASH_TYPE,4212	TCP_IPV4_HASH_TYPE,4213	IPV6_HASH_TYPE,4214	TCP_IPV6_HASH_TYPE,4215	VLAN_PRI_HASH_TYPE,4216	E1HOV_PRI_HASH_TYPE,4217	DSCP_HASH_TYPE,4218	MAX_ETH_RSS_HASH_TYPE4219};4220 4221 4222/*4223 * Ethernet RSS mode4224 */4225enum eth_rss_mode {4226	ETH_RSS_MODE_DISABLED,4227	ETH_RSS_MODE_REGULAR,4228	ETH_RSS_MODE_VLAN_PRI,4229	ETH_RSS_MODE_E1HOV_PRI,4230	ETH_RSS_MODE_IP_DSCP,4231	MAX_ETH_RSS_MODE4232};4233 4234 4235/*4236 * parameters for RSS update ramrod (E2)4237 */4238struct eth_rss_update_ramrod_data {4239	u8 rss_engine_id;4240	u8 rss_mode;4241	__le16 capabilities;4242#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)4243#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 04244#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)4245#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 14246#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)4247#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 24248#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)4249#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 34250#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)4251#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 44252#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)4253#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 54254#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)4255#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 64256#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)4257#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 74258#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)4259#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 84260#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)4261#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 94262#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)4263#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 104264	u8 rss_result_mask;4265	u8 reserved3;4266	__le16 reserved4;4267	u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];4268	__le32 rss_key[T_ETH_RSS_KEY];4269	__le32 echo;4270	__le32 reserved5;4271};4272 4273 4274/*4275 * The eth Rx Buffer Descriptor4276 */4277struct eth_rx_bd {4278	__le32 addr_lo;4279	__le32 addr_hi;4280};4281 4282 4283/*4284 * Eth Rx Cqe structure- general structure for ramrods4285 */4286struct common_ramrod_eth_rx_cqe {4287	u8 ramrod_type;4288#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)4289#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 04290#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)4291#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 24292#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)4293#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 34294	u8 conn_type;4295	__le16 reserved1;4296	__le32 conn_and_cmd_data;4297#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)4298#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 04299#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)4300#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 244301	struct ramrod_data protocol_data;4302	__le32 echo;4303	__le32 reserved2[11];4304};4305 4306/*4307 * Rx Last CQE in page (in ETH)4308 */4309struct eth_rx_cqe_next_page {4310	__le32 addr_lo;4311	__le32 addr_hi;4312	__le32 reserved[14];4313};4314 4315/*4316 * union for all eth rx cqe types (fix their sizes)4317 */4318union eth_rx_cqe {4319	struct eth_fast_path_rx_cqe fast_path_cqe;4320	struct common_ramrod_eth_rx_cqe ramrod_cqe;4321	struct eth_rx_cqe_next_page next_page_cqe;4322	struct eth_end_agg_rx_cqe end_agg_cqe;4323};4324 4325 4326/*4327 * Values for RX ETH CQE type field4328 */4329enum eth_rx_cqe_type {4330	RX_ETH_CQE_TYPE_ETH_FASTPATH,4331	RX_ETH_CQE_TYPE_ETH_RAMROD,4332	RX_ETH_CQE_TYPE_ETH_START_AGG,4333	RX_ETH_CQE_TYPE_ETH_STOP_AGG,4334	MAX_ETH_RX_CQE_TYPE4335};4336 4337 4338/*4339 * Type of SGL/Raw field in ETH RX fast path CQE4340 */4341enum eth_rx_fp_sel {4342	ETH_FP_CQE_REGULAR,4343	ETH_FP_CQE_RAW,4344	MAX_ETH_RX_FP_SEL4345};4346 4347 4348/*4349 * The eth Rx SGE Descriptor4350 */4351struct eth_rx_sge {4352	__le32 addr_lo;4353	__le32 addr_hi;4354};4355 4356 4357/*4358 * common data for all protocols4359 */4360struct spe_hdr {4361	__le32 conn_and_cmd_data;4362#define SPE_HDR_CID (0xFFFFFF<<0)4363#define SPE_HDR_CID_SHIFT 04364#define SPE_HDR_CMD_ID (0xFF<<24)4365#define SPE_HDR_CMD_ID_SHIFT 244366	__le16 type;4367#define SPE_HDR_CONN_TYPE (0xFF<<0)4368#define SPE_HDR_CONN_TYPE_SHIFT 04369#define SPE_HDR_FUNCTION_ID (0xFF<<8)4370#define SPE_HDR_FUNCTION_ID_SHIFT 84371	__le16 reserved1;4372};4373 4374/*4375 * specific data for ethernet slow path element4376 */4377union eth_specific_data {4378	u8 protocol_data[8];4379	struct regpair client_update_ramrod_data;4380	struct regpair client_init_ramrod_init_data;4381	struct eth_halt_ramrod_data halt_ramrod_data;4382	struct regpair update_data_addr;4383	struct eth_common_ramrod_data common_ramrod_data;4384	struct regpair classify_cfg_addr;4385	struct regpair filter_cfg_addr;4386	struct regpair mcast_cfg_addr;4387};4388 4389/*4390 * Ethernet slow path element4391 */4392struct eth_spe {4393	struct spe_hdr hdr;4394	union eth_specific_data data;4395};4396 4397 4398/*4399 * Ethernet command ID for slow path elements4400 */4401enum eth_spqe_cmd_id {4402	RAMROD_CMD_ID_ETH_UNUSED,4403	RAMROD_CMD_ID_ETH_CLIENT_SETUP,4404	RAMROD_CMD_ID_ETH_HALT,4405	RAMROD_CMD_ID_ETH_FORWARD_SETUP,4406	RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,4407	RAMROD_CMD_ID_ETH_CLIENT_UPDATE,4408	RAMROD_CMD_ID_ETH_EMPTY,4409	RAMROD_CMD_ID_ETH_TERMINATE,4410	RAMROD_CMD_ID_ETH_TPA_UPDATE,4411	RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,4412	RAMROD_CMD_ID_ETH_FILTER_RULES,4413	RAMROD_CMD_ID_ETH_MULTICAST_RULES,4414	RAMROD_CMD_ID_ETH_RSS_UPDATE,4415	RAMROD_CMD_ID_ETH_SET_MAC,4416	MAX_ETH_SPQE_CMD_ID4417};4418 4419 4420/*4421 * eth tpa update command4422 */4423enum eth_tpa_update_command {4424	TPA_UPDATE_NONE_COMMAND,4425	TPA_UPDATE_ENABLE_COMMAND,4426	TPA_UPDATE_DISABLE_COMMAND,4427	MAX_ETH_TPA_UPDATE_COMMAND4428};4429 4430/* In case of LSO over IPv4 tunnel, whether to increment4431 * IP ID on external IP header or internal IP header4432 */4433enum eth_tunnel_lso_inc_ip_id {4434	EXT_HEADER,4435	INT_HEADER,4436	MAX_ETH_TUNNEL_LSO_INC_IP_ID4437};4438 4439/* In case tunnel exist and L4 checksum offload,4440 * the pseudo checksum location, on packet or on BD.4441 */4442enum eth_tunnel_non_lso_csum_location {4443	CSUM_ON_PKT,4444	CSUM_ON_BD,4445	MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION4446};4447 4448enum eth_tunn_type {4449	TUNN_TYPE_NONE,4450	TUNN_TYPE_VXLAN,4451	TUNN_TYPE_L2_GRE,4452	TUNN_TYPE_IPV4_GRE,4453	TUNN_TYPE_IPV6_GRE,4454	TUNN_TYPE_L2_GENEVE,4455	TUNN_TYPE_IPV4_GENEVE,4456	TUNN_TYPE_IPV6_GENEVE,4457	MAX_ETH_TUNN_TYPE4458};4459 4460/*4461 * Tx regular BD structure4462 */4463struct eth_tx_bd {4464	__le32 addr_lo;4465	__le32 addr_hi;4466	__le16 total_pkt_bytes;4467	__le16 nbytes;4468	u8 reserved[4];4469};4470 4471 4472/*4473 * structure for easy accessibility to assembler4474 */4475struct eth_tx_bd_flags {4476	u8 as_bitfield;4477#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)4478#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 04479#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)4480#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 14481#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)4482#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 24483#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)4484#define ETH_TX_BD_FLAGS_START_BD_SHIFT 44485#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)4486#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 54487#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)4488#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 64489#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)4490#define ETH_TX_BD_FLAGS_IPV6_SHIFT 74491};4492 4493/*4494 * The eth Tx Buffer Descriptor4495 */4496struct eth_tx_start_bd {4497	__le32 addr_lo;4498	__le32 addr_hi;4499	__le16 nbd;4500	__le16 nbytes;4501	__le16 vlan_or_ethertype;4502	struct eth_tx_bd_flags bd_flags;4503	u8 general_data;4504#define ETH_TX_START_BD_HDR_NBDS (0x7<<0)4505#define ETH_TX_START_BD_HDR_NBDS_SHIFT 04506#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)4507#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 34508#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)4509#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 44510#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)4511#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 54512#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)4513#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 74514};4515 4516/*4517 * Tx parsing BD structure for ETH E1/E1h4518 */4519struct eth_tx_parse_bd_e1x {4520	__le16 global_data;4521#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)4522#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 04523#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)4524#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 44525#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)4526#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 64527#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)4528#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 74529#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)4530#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 84531#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)4532#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 94533	u8 tcp_flags;4534#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)4535#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 04536#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)4537#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 14538#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)4539#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 24540#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)4541#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 34542#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)4543#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 44544#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)4545#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 54546#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)4547#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 64548#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)4549#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 74550	u8 ip_hlen_w;4551	__le16 total_hlen_w;4552	__le16 tcp_pseudo_csum;4553	__le16 lso_mss;4554	__le16 ip_id;4555	__le32 tcp_send_seq;4556};4557 4558/*4559 * Tx parsing BD structure for ETH E24560 */4561struct eth_tx_parse_bd_e2 {4562	union eth_mac_addr_or_tunnel_data data;4563	__le32 parsing_data;4564#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)4565#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 04566#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)4567#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 114568#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)4569#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 154570#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)4571#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 164572#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)4573#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 304574};4575 4576/*4577 * Tx 2nd parsing BD structure for ETH packet4578 */4579struct eth_tx_parse_2nd_bd {4580	__le16 global_data;4581#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)4582#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 04583#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)4584#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 44585#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)4586#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 54587#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)4588#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 64589#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)4590#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 74591#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)4592#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 84593#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)4594#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 134595	u8 bd_type;4596#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)4597#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 04598#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)4599#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 44600	u8 reserved3;4601	u8 tcp_flags;4602#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)4603#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 04604#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)4605#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 14606#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)4607#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 24608#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)4609#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 34610#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)4611#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 44612#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)4613#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 54614#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)4615#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 64616#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)4617#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 74618	u8 reserved4;4619	u8 tunnel_udp_hdr_start_w;4620	u8 fw_ip_hdr_to_payload_w;4621	__le16 fw_ip_csum_wo_len_flags_frag;4622	__le16 hw_ip_id;4623	__le32 tcp_send_seq;4624};4625 4626/* The last BD in the BD memory will hold a pointer to the next BD memory */4627struct eth_tx_next_bd {4628	__le32 addr_lo;4629	__le32 addr_hi;4630	u8 reserved[8];4631};4632 4633/*4634 * union for 4 Bd types4635 */4636union eth_tx_bd_types {4637	struct eth_tx_start_bd start_bd;4638	struct eth_tx_bd reg_bd;4639	struct eth_tx_parse_bd_e1x parse_bd_e1x;4640	struct eth_tx_parse_bd_e2 parse_bd_e2;4641	struct eth_tx_parse_2nd_bd parse_2nd_bd;4642	struct eth_tx_next_bd next_bd;4643};4644 4645/*4646 * array of 13 bds as appears in the eth xstorm context4647 */4648struct eth_tx_bds_array {4649	union eth_tx_bd_types bds[13];4650};4651 4652 4653/*4654 * VLAN mode on TX BDs4655 */4656enum eth_tx_vlan_type {4657	X_ETH_NO_VLAN,4658	X_ETH_OUTBAND_VLAN,4659	X_ETH_INBAND_VLAN,4660	X_ETH_FW_ADDED_VLAN,4661	MAX_ETH_TX_VLAN_TYPE4662};4663 4664 4665/*4666 * Ethernet VLAN filtering mode in E1x4667 */4668enum eth_vlan_filter_mode {4669	ETH_VLAN_FILTER_ANY_VLAN,4670	ETH_VLAN_FILTER_SPECIFIC_VLAN,4671	ETH_VLAN_FILTER_CLASSIFY,4672	MAX_ETH_VLAN_FILTER_MODE4673};4674 4675 4676/*4677 * MAC filtering configuration command header4678 */4679struct mac_configuration_hdr {4680	u8 length;4681	u8 offset;4682	__le16 client_id;4683	__le32 echo;4684};4685 4686/*4687 * MAC address in list for ramrod4688 */4689struct mac_configuration_entry {4690	__le16 lsb_mac_addr;4691	__le16 middle_mac_addr;4692	__le16 msb_mac_addr;4693	__le16 vlan_id;4694	u8 pf_id;4695	u8 flags;4696#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)4697#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 04698#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)4699#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 14700#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)4701#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 24702#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)4703#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 44704#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)4705#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 54706#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)4707#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 64708	__le16 reserved0;4709	__le32 clients_bit_vector;4710};4711 4712/*4713 * MAC filtering configuration command4714 */4715struct mac_configuration_cmd {4716	struct mac_configuration_hdr hdr;4717	struct mac_configuration_entry config_table[64];4718};4719 4720 4721/*4722 * Set-MAC command type (in E1x)4723 */4724enum set_mac_action_type {4725	T_ETH_MAC_COMMAND_INVALIDATE,4726	T_ETH_MAC_COMMAND_SET,4727	MAX_SET_MAC_ACTION_TYPE4728};4729 4730 4731/*4732 * Ethernet TPA Modes4733 */4734enum tpa_mode {4735	TPA_LRO,4736	TPA_GRO,4737	MAX_TPA_MODE};4738 4739 4740/*4741 * tpa update ramrod data4742 */4743struct tpa_update_ramrod_data {4744	u8 update_ipv4;4745	u8 update_ipv6;4746	u8 client_id;4747	u8 max_tpa_queues;4748	u8 max_sges_for_packet;4749	u8 complete_on_both_clients;4750	u8 dont_verify_rings_pause_thr_flg;4751	u8 tpa_mode;4752	__le16 sge_buff_size;4753	__le16 max_agg_size;4754	__le32 sge_page_base_lo;4755	__le32 sge_page_base_hi;4756	__le16 sge_pause_thr_low;4757	__le16 sge_pause_thr_high;4758	u8 tpa_over_vlan_disable;4759	u8 reserved[7];4760};4761 4762 4763/*4764 * approximate-match multicast filtering for E1H per function in Tstorm4765 */4766struct tstorm_eth_approximate_match_multicast_filtering {4767	u32 mcast_add_hash_bit_array[8];4768};4769 4770 4771/*4772 * Common configuration parameters per function in Tstorm4773 */4774struct tstorm_eth_function_common_config {4775	__le16 config_flags;4776#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)4777#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 04778#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)4779#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 14780#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)4781#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 24782#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)4783#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 34784#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)4785#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 44786#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)4787#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 74788#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)4789#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 84790	u8 rss_result_mask;4791	u8 reserved1;4792	__le16 vlan_id[2];4793};4794 4795 4796/*4797 * MAC filtering configuration parameters per port in Tstorm4798 */4799struct tstorm_eth_mac_filter_config {4800	u32 ucast_drop_all;4801	u32 ucast_accept_all;4802	u32 mcast_drop_all;4803	u32 mcast_accept_all;4804	u32 bcast_accept_all;4805	u32 vlan_filter[2];4806	u32 unmatched_unicast;4807};4808 4809 4810/*4811 * tx only queue init ramrod data4812 */4813struct tx_queue_init_ramrod_data {4814	struct client_init_general_data general;4815	struct client_init_tx_data tx;4816};4817 4818 4819/*4820 * Three RX producers for ETH4821 */4822struct ustorm_eth_rx_producers {4823#if defined(__BIG_ENDIAN)4824	u16 bd_prod;4825	u16 cqe_prod;4826#elif defined(__LITTLE_ENDIAN)4827	u16 cqe_prod;4828	u16 bd_prod;4829#endif4830#if defined(__BIG_ENDIAN)4831	u16 reserved;4832	u16 sge_prod;4833#elif defined(__LITTLE_ENDIAN)4834	u16 sge_prod;4835	u16 reserved;4836#endif4837};4838 4839 4840/*4841 * FCoE RX statistics parameters section#04842 */4843struct fcoe_rx_stat_params_section0 {4844	__le32 fcoe_rx_pkt_cnt;4845	__le32 fcoe_rx_byte_cnt;4846};4847 4848 4849/*4850 * FCoE RX statistics parameters section#14851 */4852struct fcoe_rx_stat_params_section1 {4853	__le32 fcoe_ver_cnt;4854	__le32 fcoe_rx_drop_pkt_cnt;4855};4856 4857 4858/*4859 * FCoE RX statistics parameters section#24860 */4861struct fcoe_rx_stat_params_section2 {4862	__le32 fc_crc_cnt;4863	__le32 eofa_del_cnt;4864	__le32 miss_frame_cnt;4865	__le32 seq_timeout_cnt;4866	__le32 drop_seq_cnt;4867	__le32 fcoe_rx_drop_pkt_cnt;4868	__le32 fcp_rx_pkt_cnt;4869	__le32 reserved0;4870};4871 4872 4873/*4874 * FCoE TX statistics parameters4875 */4876struct fcoe_tx_stat_params {4877	__le32 fcoe_tx_pkt_cnt;4878	__le32 fcoe_tx_byte_cnt;4879	__le32 fcp_tx_pkt_cnt;4880	__le32 reserved0;4881};4882 4883/*4884 * FCoE statistics parameters4885 */4886struct fcoe_statistics_params {4887	struct fcoe_tx_stat_params tx_stat;4888	struct fcoe_rx_stat_params_section0 rx_stat0;4889	struct fcoe_rx_stat_params_section1 rx_stat1;4890	struct fcoe_rx_stat_params_section2 rx_stat2;4891};4892 4893 4894/*4895 * The data afex vif list ramrod need4896 */4897struct afex_vif_list_ramrod_data {4898	u8 afex_vif_list_command;4899	u8 func_bit_map;4900	__le16 vif_list_index;4901	u8 func_to_clear;4902	u8 echo;4903	__le16 reserved1;4904};4905 4906struct c2s_pri_trans_table_entry {4907	u8 val[MAX_VLAN_PRIORITIES];4908};4909 4910/*4911 * cfc delete event data4912 */4913struct cfc_del_event_data {4914	__le32 cid;4915	__le32 reserved0;4916	__le32 reserved1;4917};4918 4919 4920/*4921 * per-port SAFC demo variables4922 */4923struct cmng_flags_per_port {4924	u32 cmng_enables;4925#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)4926#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 04927#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)4928#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 14929#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)4930#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 24931#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)4932#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 34933#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)4934#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 44935	u32 __reserved1;4936};4937 4938 4939/*4940 * per-port rate shaping variables4941 */4942struct rate_shaping_vars_per_port {4943	u32 rs_periodic_timeout;4944	u32 rs_threshold;4945};4946 4947/*4948 * per-port fairness variables4949 */4950struct fairness_vars_per_port {4951	u32 upper_bound;4952	u32 fair_threshold;4953	u32 fairness_timeout;4954	u32 size_thr;4955};4956 4957/*4958 * per-port SAFC variables4959 */4960struct safc_struct_per_port {4961#if defined(__BIG_ENDIAN)4962	u16 __reserved1;4963	u8 __reserved0;4964	u8 safc_timeout_usec;4965#elif defined(__LITTLE_ENDIAN)4966	u8 safc_timeout_usec;4967	u8 __reserved0;4968	u16 __reserved1;4969#endif4970	u8 cos_to_traffic_types[MAX_COS_NUMBER];4971	u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];4972};4973 4974/*4975 * Per-port congestion management variables4976 */4977struct cmng_struct_per_port {4978	struct rate_shaping_vars_per_port rs_vars;4979	struct fairness_vars_per_port fair_vars;4980	struct safc_struct_per_port safc_vars;4981	struct cmng_flags_per_port flags;4982};4983 4984/*4985 * a single rate shaping counter. can be used as protocol or vnic counter4986 */4987struct rate_shaping_counter {4988	u32 quota;4989#if defined(__BIG_ENDIAN)4990	u16 __reserved0;4991	u16 rate;4992#elif defined(__LITTLE_ENDIAN)4993	u16 rate;4994	u16 __reserved0;4995#endif4996};4997 4998/*4999 * per-vnic rate shaping variables5000 */5001struct rate_shaping_vars_per_vn {5002	struct rate_shaping_counter vn_counter;5003};5004 5005/*5006 * per-vnic fairness variables5007 */5008struct fairness_vars_per_vn {5009	u32 cos_credit_delta[MAX_COS_NUMBER];5010	u32 vn_credit_delta;5011	u32 __reserved0;5012};5013 5014/*5015 * cmng port init state5016 */5017struct cmng_vnic {5018	struct rate_shaping_vars_per_vn vnic_max_rate[4];5019	struct fairness_vars_per_vn vnic_min_rate[4];5020};5021 5022/*5023 * cmng port init state5024 */5025struct cmng_init {5026	struct cmng_struct_per_port port;5027	struct cmng_vnic vnic;5028};5029 5030 5031/*5032 * driver parameters for congestion management init, all rates are in Mbps5033 */5034struct cmng_init_input {5035	u32 port_rate;5036	u16 vnic_min_rate[4];5037	u16 vnic_max_rate[4];5038	u16 cos_min_rate[MAX_COS_NUMBER];5039	u16 cos_to_pause_mask[MAX_COS_NUMBER];5040	struct cmng_flags_per_port flags;5041};5042 5043 5044/*5045 * Protocol-common command ID for slow path elements5046 */5047enum common_spqe_cmd_id {5048	RAMROD_CMD_ID_COMMON_UNUSED,5049	RAMROD_CMD_ID_COMMON_FUNCTION_START,5050	RAMROD_CMD_ID_COMMON_FUNCTION_STOP,5051	RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,5052	RAMROD_CMD_ID_COMMON_CFC_DEL,5053	RAMROD_CMD_ID_COMMON_CFC_DEL_WB,5054	RAMROD_CMD_ID_COMMON_STAT_QUERY,5055	RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,5056	RAMROD_CMD_ID_COMMON_START_TRAFFIC,5057	RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,5058	RAMROD_CMD_ID_COMMON_SET_TIMESYNC,5059	MAX_COMMON_SPQE_CMD_ID5060};5061 5062/*5063 * Per-protocol connection types5064 */5065enum connection_type {5066	ETH_CONNECTION_TYPE,5067	TOE_CONNECTION_TYPE,5068	RDMA_CONNECTION_TYPE,5069	ISCSI_CONNECTION_TYPE,5070	FCOE_CONNECTION_TYPE,5071	RESERVED_CONNECTION_TYPE_0,5072	RESERVED_CONNECTION_TYPE_1,5073	RESERVED_CONNECTION_TYPE_2,5074	NONE_CONNECTION_TYPE,5075	MAX_CONNECTION_TYPE5076};5077 5078 5079/*5080 * Cos modes5081 */5082enum cos_mode {5083	OVERRIDE_COS,5084	STATIC_COS,5085	FW_WRR,5086	MAX_COS_MODE5087};5088 5089 5090/*5091 * Dynamic HC counters set by the driver5092 */5093struct hc_dynamic_drv_counter {5094	u32 val[HC_SB_MAX_DYNAMIC_INDICES];5095};5096 5097/*5098 * zone A per-queue data5099 */5100struct cstorm_queue_zone_data {5101	struct hc_dynamic_drv_counter hc_dyn_drv_cnt;5102	struct regpair reserved[2];5103};5104 5105 5106/*5107 * Vf-PF channel data in cstorm ram (non-triggered zone)5108 */5109struct vf_pf_channel_zone_data {5110	u32 msg_addr_lo;5111	u32 msg_addr_hi;5112};5113 5114/*5115 * zone for VF non-triggered data5116 */5117struct non_trigger_vf_zone {5118	struct vf_pf_channel_zone_data vf_pf_channel;5119};5120 5121/*5122 * Vf-PF channel trigger zone in cstorm ram5123 */5124struct vf_pf_channel_zone_trigger {5125	u8 addr_valid;5126};5127 5128/*5129 * zone that triggers the in-bound interrupt5130 */5131struct trigger_vf_zone {5132	struct vf_pf_channel_zone_trigger vf_pf_channel;5133	u8 reserved0;5134	u16 reserved1;5135	u32 reserved2;5136};5137 5138/*5139 * zone B per-VF data5140 */5141struct cstorm_vf_zone_data {5142	struct non_trigger_vf_zone non_trigger;5143	struct trigger_vf_zone trigger;5144};5145 5146 5147/*5148 * Dynamic host coalescing init parameters, per state machine5149 */5150struct dynamic_hc_sm_config {5151	u32 threshold[3];5152	u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];5153	u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];5154	u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];5155	u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];5156	u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];5157};5158 5159/*5160 * Dynamic host coalescing init parameters5161 */5162struct dynamic_hc_config {5163	struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];5164};5165 5166 5167struct e2_integ_data {5168#if defined(__BIG_ENDIAN)5169	u8 flags;5170#define E2_INTEG_DATA_TESTING_EN (0x1<<0)5171#define E2_INTEG_DATA_TESTING_EN_SHIFT 05172#define E2_INTEG_DATA_LB_TX (0x1<<1)5173#define E2_INTEG_DATA_LB_TX_SHIFT 15174#define E2_INTEG_DATA_COS_TX (0x1<<2)5175#define E2_INTEG_DATA_COS_TX_SHIFT 25176#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)5177#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 35178#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)5179#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 45180#define E2_INTEG_DATA_RESERVED (0x7<<5)5181#define E2_INTEG_DATA_RESERVED_SHIFT 55182	u8 cos;5183	u8 voq;5184	u8 pbf_queue;5185#elif defined(__LITTLE_ENDIAN)5186	u8 pbf_queue;5187	u8 voq;5188	u8 cos;5189	u8 flags;5190#define E2_INTEG_DATA_TESTING_EN (0x1<<0)5191#define E2_INTEG_DATA_TESTING_EN_SHIFT 05192#define E2_INTEG_DATA_LB_TX (0x1<<1)5193#define E2_INTEG_DATA_LB_TX_SHIFT 15194#define E2_INTEG_DATA_COS_TX (0x1<<2)5195#define E2_INTEG_DATA_COS_TX_SHIFT 25196#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)5197#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 35198#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)5199#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 45200#define E2_INTEG_DATA_RESERVED (0x7<<5)5201#define E2_INTEG_DATA_RESERVED_SHIFT 55202#endif5203#if defined(__BIG_ENDIAN)5204	u16 reserved3;5205	u8 reserved2;5206	u8 ramEn;5207#elif defined(__LITTLE_ENDIAN)5208	u8 ramEn;5209	u8 reserved2;5210	u16 reserved3;5211#endif5212};5213 5214 5215/*5216 * set mac event data5217 */5218struct eth_event_data {5219	__le32 echo;5220	__le32 reserved0;5221	__le32 reserved1;5222};5223 5224 5225/*5226 * pf-vf event data5227 */5228struct vf_pf_event_data {5229	u8 vf_id;5230	u8 reserved0;5231	__le16 reserved1;5232	__le32 msg_addr_lo;5233	__le32 msg_addr_hi;5234};5235 5236/*5237 * VF FLR event data5238 */5239struct vf_flr_event_data {5240	u8 vf_id;5241	u8 reserved0;5242	__le16 reserved1;5243	__le32 reserved2;5244	__le32 reserved3;5245};5246 5247/*5248 * malicious VF event data5249 */5250struct malicious_vf_event_data {5251	u8 vf_id;5252	u8 err_id;5253	__le16 reserved1;5254	__le32 reserved2;5255	__le32 reserved3;5256};5257 5258/*5259 * vif list event data5260 */5261struct vif_list_event_data {5262	u8 func_bit_map;5263	u8 echo;5264	__le16 reserved0;5265	__le32 reserved1;5266	__le32 reserved2;5267};5268 5269/* function update event data */5270struct function_update_event_data {5271	u8 echo;5272	u8 reserved;5273	__le16 reserved0;5274	__le32 reserved1;5275	__le32 reserved2;5276};5277 5278 5279/* union for all event ring message types */5280union event_data {5281	struct vf_pf_event_data vf_pf_event;5282	struct eth_event_data eth_event;5283	struct cfc_del_event_data cfc_del_event;5284	struct vf_flr_event_data vf_flr_event;5285	struct malicious_vf_event_data malicious_vf_event;5286	struct vif_list_event_data vif_list_event;5287	struct function_update_event_data function_update_event;5288};5289 5290 5291/*5292 * per PF event ring data5293 */5294struct event_ring_data {5295	struct regpair_native base_addr;5296#if defined(__BIG_ENDIAN)5297	u8 index_id;5298	u8 sb_id;5299	u16 producer;5300#elif defined(__LITTLE_ENDIAN)5301	u16 producer;5302	u8 sb_id;5303	u8 index_id;5304#endif5305	u32 reserved0;5306};5307 5308 5309/*5310 * event ring message element (each element is 128 bits)5311 */5312struct event_ring_msg {5313	u8 opcode;5314	u8 error;5315	u16 reserved1;5316	union event_data data;5317};5318 5319/*5320 * event ring next page element (128 bits)5321 */5322struct event_ring_next {5323	struct regpair addr;5324	u32 reserved[2];5325};5326 5327/*5328 * union for event ring element types (each element is 128 bits)5329 */5330union event_ring_elem {5331	struct event_ring_msg message;5332	struct event_ring_next next_page;5333};5334 5335 5336/*5337 * Common event ring opcodes5338 */5339enum event_ring_opcode {5340	EVENT_RING_OPCODE_VF_PF_CHANNEL,5341	EVENT_RING_OPCODE_FUNCTION_START,5342	EVENT_RING_OPCODE_FUNCTION_STOP,5343	EVENT_RING_OPCODE_CFC_DEL,5344	EVENT_RING_OPCODE_CFC_DEL_WB,5345	EVENT_RING_OPCODE_STAT_QUERY,5346	EVENT_RING_OPCODE_STOP_TRAFFIC,5347	EVENT_RING_OPCODE_START_TRAFFIC,5348	EVENT_RING_OPCODE_VF_FLR,5349	EVENT_RING_OPCODE_MALICIOUS_VF,5350	EVENT_RING_OPCODE_FORWARD_SETUP,5351	EVENT_RING_OPCODE_RSS_UPDATE_RULES,5352	EVENT_RING_OPCODE_FUNCTION_UPDATE,5353	EVENT_RING_OPCODE_AFEX_VIF_LISTS,5354	EVENT_RING_OPCODE_SET_MAC,5355	EVENT_RING_OPCODE_CLASSIFICATION_RULES,5356	EVENT_RING_OPCODE_FILTERS_RULES,5357	EVENT_RING_OPCODE_MULTICAST_RULES,5358	EVENT_RING_OPCODE_SET_TIMESYNC,5359	MAX_EVENT_RING_OPCODE5360};5361 5362/*5363 * Modes for fairness algorithm5364 */5365enum fairness_mode {5366	FAIRNESS_COS_WRR_MODE,5367	FAIRNESS_COS_ETS_MODE,5368	MAX_FAIRNESS_MODE5369};5370 5371 5372/*5373 * Priority and cos5374 */5375struct priority_cos {5376	u8 priority;5377	u8 cos;5378	__le16 reserved1;5379};5380 5381/*5382 * The data for flow control configuration5383 */5384struct flow_control_configuration {5385	struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];5386	u8 dcb_enabled;5387	u8 dcb_version;5388	u8 dont_add_pri_0_en;5389	u8 reserved1;5390	__le32 reserved2;5391	u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];5392};5393 5394 5395/*5396 *5397 */5398struct function_start_data {5399	u8 function_mode;5400	u8 allow_npar_tx_switching;5401	__le16 sd_vlan_tag;5402	__le16 vif_id;5403	u8 path_id;5404	u8 network_cos_mode;5405	u8 dmae_cmd_id;5406	u8 no_added_tags;5407	__le16 reserved0;5408	__le32 reserved1;5409	u8 inner_clss_vxlan;5410	u8 inner_clss_l2gre;5411	u8 inner_clss_l2geneve;5412	u8 inner_rss;5413	__le16 vxlan_dst_port;5414	__le16 geneve_dst_port;5415	u8 sd_accept_mf_clss_fail;5416	u8 sd_accept_mf_clss_fail_match_ethtype;5417	__le16 sd_accept_mf_clss_fail_ethtype;5418	__le16 sd_vlan_eth_type;5419	u8 sd_vlan_force_pri_flg;5420	u8 sd_vlan_force_pri_val;5421	u8 c2s_pri_tt_valid;5422	u8 c2s_pri_default;5423	u8 tx_vlan_filtering_enable;5424	u8 tx_vlan_filtering_use_pvid;5425	u8 reserved2[4];5426	struct c2s_pri_trans_table_entry c2s_pri_trans_table;5427};5428 5429struct function_update_data {5430	u8 vif_id_change_flg;5431	u8 afex_default_vlan_change_flg;5432	u8 allowed_priorities_change_flg;5433	u8 network_cos_mode_change_flg;5434	__le16 vif_id;5435	__le16 afex_default_vlan;5436	u8 allowed_priorities;5437	u8 network_cos_mode;5438	u8 lb_mode_en_change_flg;5439	u8 lb_mode_en;5440	u8 tx_switch_suspend_change_flg;5441	u8 tx_switch_suspend;5442	u8 echo;5443	u8 update_tunn_cfg_flg;5444	u8 inner_clss_vxlan;5445	u8 inner_clss_l2gre;5446	u8 inner_clss_l2geneve;5447	u8 inner_rss;5448	__le16 vxlan_dst_port;5449	__le16 geneve_dst_port;5450	u8 sd_vlan_force_pri_change_flg;5451	u8 sd_vlan_force_pri_flg;5452	u8 sd_vlan_force_pri_val;5453	u8 sd_vlan_tag_change_flg;5454	u8 sd_vlan_eth_type_change_flg;5455	u8 reserved1;5456	__le16 sd_vlan_tag;5457	__le16 sd_vlan_eth_type;5458	u8 tx_vlan_filtering_pvid_change_flg;5459	u8 reserved0;5460	__le32 reserved2;5461};5462 5463/*5464 * FW version stored in the Xstorm RAM5465 */5466struct fw_version {5467#if defined(__BIG_ENDIAN)5468	u8 engineering;5469	u8 revision;5470	u8 minor;5471	u8 major;5472#elif defined(__LITTLE_ENDIAN)5473	u8 major;5474	u8 minor;5475	u8 revision;5476	u8 engineering;5477#endif5478	u32 flags;5479#define FW_VERSION_OPTIMIZED (0x1<<0)5480#define FW_VERSION_OPTIMIZED_SHIFT 05481#define FW_VERSION_BIG_ENDIEN (0x1<<1)5482#define FW_VERSION_BIG_ENDIEN_SHIFT 15483#define FW_VERSION_CHIP_VERSION (0x3<<2)5484#define FW_VERSION_CHIP_VERSION_SHIFT 25485#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)5486#define __FW_VERSION_RESERVED_SHIFT 45487};5488 5489/*5490 * Dynamic Host-Coalescing - Driver(host) counters5491 */5492struct hc_dynamic_sb_drv_counters {5493	u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];5494};5495 5496 5497/*5498 * 2 bytes. configuration/state parameters for a single protocol index5499 */5500struct hc_index_data {5501#if defined(__BIG_ENDIAN)5502	u8 flags;5503#define HC_INDEX_DATA_SM_ID (0x1<<0)5504#define HC_INDEX_DATA_SM_ID_SHIFT 05505#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)5506#define HC_INDEX_DATA_HC_ENABLED_SHIFT 15507#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)5508#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 25509#define HC_INDEX_DATA_RESERVE (0x1F<<3)5510#define HC_INDEX_DATA_RESERVE_SHIFT 35511	u8 timeout;5512#elif defined(__LITTLE_ENDIAN)5513	u8 timeout;5514	u8 flags;5515#define HC_INDEX_DATA_SM_ID (0x1<<0)5516#define HC_INDEX_DATA_SM_ID_SHIFT 05517#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)5518#define HC_INDEX_DATA_HC_ENABLED_SHIFT 15519#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)5520#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 25521#define HC_INDEX_DATA_RESERVE (0x1F<<3)5522#define HC_INDEX_DATA_RESERVE_SHIFT 35523#endif5524};5525 5526 5527/*5528 * HC state-machine5529 */5530struct hc_status_block_sm {5531#if defined(__BIG_ENDIAN)5532	u8 igu_seg_id;5533	u8 igu_sb_id;5534	u8 timer_value;5535	u8 __flags;5536#elif defined(__LITTLE_ENDIAN)5537	u8 __flags;5538	u8 timer_value;5539	u8 igu_sb_id;5540	u8 igu_seg_id;5541#endif5542	u32 time_to_expire;5543};5544 5545/*5546 * hold PCI identification variables- used in various places in firmware5547 */5548struct pci_entity {5549#if defined(__BIG_ENDIAN)5550	u8 vf_valid;5551	u8 vf_id;5552	u8 vnic_id;5553	u8 pf_id;5554#elif defined(__LITTLE_ENDIAN)5555	u8 pf_id;5556	u8 vnic_id;5557	u8 vf_id;5558	u8 vf_valid;5559#endif5560};5561 5562/*5563 * The fast-path status block meta-data, common to all chips5564 */5565struct hc_sb_data {5566	struct regpair_native host_sb_addr;5567	struct hc_status_block_sm state_machine[HC_SB_MAX_SM];5568	struct pci_entity p_func;5569#if defined(__BIG_ENDIAN)5570	u8 rsrv0;5571	u8 state;5572	u8 dhc_qzone_id;5573	u8 same_igu_sb_1b;5574#elif defined(__LITTLE_ENDIAN)5575	u8 same_igu_sb_1b;5576	u8 dhc_qzone_id;5577	u8 state;5578	u8 rsrv0;5579#endif5580	struct regpair_native rsrv1[2];5581};5582 5583 5584/*5585 * Segment types for host coaslescing5586 */5587enum hc_segment {5588	HC_REGULAR_SEGMENT,5589	HC_DEFAULT_SEGMENT,5590	MAX_HC_SEGMENT5591};5592 5593 5594/*5595 * The fast-path status block meta-data5596 */5597struct hc_sp_status_block_data {5598	struct regpair_native host_sb_addr;5599#if defined(__BIG_ENDIAN)5600	u8 rsrv1;5601	u8 state;5602	u8 igu_seg_id;5603	u8 igu_sb_id;5604#elif defined(__LITTLE_ENDIAN)5605	u8 igu_sb_id;5606	u8 igu_seg_id;5607	u8 state;5608	u8 rsrv1;5609#endif5610	struct pci_entity p_func;5611};5612 5613 5614/*5615 * The fast-path status block meta-data5616 */5617struct hc_status_block_data_e1x {5618	struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];5619	struct hc_sb_data common;5620};5621 5622 5623/*5624 * The fast-path status block meta-data5625 */5626struct hc_status_block_data_e2 {5627	struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];5628	struct hc_sb_data common;5629};5630 5631 5632/*5633 * IGU block operartion modes (in Everest2)5634 */5635enum igu_mode {5636	HC_IGU_BC_MODE,5637	HC_IGU_NBC_MODE,5638	MAX_IGU_MODE5639};5640 5641/*5642 * Inner Headers Classification Type5643 */5644enum inner_clss_type {5645	INNER_CLSS_DISABLED,5646	INNER_CLSS_USE_VLAN,5647	INNER_CLSS_USE_VNI,5648	MAX_INNER_CLSS_TYPE};5649 5650/*5651 * IP versions5652 */5653enum ip_ver {5654	IP_V4,5655	IP_V6,5656	MAX_IP_VER5657};5658 5659/*5660 * Malicious VF error ID5661 */5662enum malicious_vf_error_id {5663	MALICIOUS_VF_NO_ERROR,5664	VF_PF_CHANNEL_NOT_READY,5665	ETH_ILLEGAL_BD_LENGTHS,5666	ETH_PACKET_TOO_SHORT,5667	ETH_PAYLOAD_TOO_BIG,5668	ETH_ILLEGAL_ETH_TYPE,5669	ETH_ILLEGAL_LSO_HDR_LEN,5670	ETH_TOO_MANY_BDS,5671	ETH_ZERO_HDR_NBDS,5672	ETH_START_BD_NOT_SET,5673	ETH_ILLEGAL_PARSE_NBDS,5674	ETH_IPV6_AND_CHECKSUM,5675	ETH_VLAN_FLG_INCORRECT,5676	ETH_ILLEGAL_LSO_MSS,5677	ETH_TUNNEL_NOT_SUPPORTED,5678	MAX_MALICIOUS_VF_ERROR_ID5679};5680 5681/*5682 * Multi-function modes5683 */5684enum mf_mode {5685	SINGLE_FUNCTION,5686	MULTI_FUNCTION_SD,5687	MULTI_FUNCTION_SI,5688	MULTI_FUNCTION_AFEX,5689	MAX_MF_MODE5690};5691 5692/*5693 * Protocol-common statistics collected by the Tstorm (per pf)5694 */5695struct tstorm_per_pf_stats {5696	struct regpair rcv_error_bytes;5697};5698 5699/*5700 *5701 */5702struct per_pf_stats {5703	struct tstorm_per_pf_stats tstorm_pf_statistics;5704};5705 5706 5707/*5708 * Protocol-common statistics collected by the Tstorm (per port)5709 */5710struct tstorm_per_port_stats {5711	__le32 mac_discard;5712	__le32 mac_filter_discard;5713	__le32 brb_truncate_discard;5714	__le32 mf_tag_discard;5715	__le32 packet_drop;5716	__le32 reserved;5717};5718 5719/*5720 *5721 */5722struct per_port_stats {5723	struct tstorm_per_port_stats tstorm_port_statistics;5724};5725 5726 5727/*5728 * Protocol-common statistics collected by the Tstorm (per client)5729 */5730struct tstorm_per_queue_stats {5731	struct regpair rcv_ucast_bytes;5732	__le32 rcv_ucast_pkts;5733	__le32 checksum_discard;5734	struct regpair rcv_bcast_bytes;5735	__le32 rcv_bcast_pkts;5736	__le32 pkts_too_big_discard;5737	struct regpair rcv_mcast_bytes;5738	__le32 rcv_mcast_pkts;5739	__le32 ttl0_discard;5740	__le16 no_buff_discard;5741	__le16 reserved0;5742	__le32 reserved1;5743};5744 5745/*5746 * Protocol-common statistics collected by the Ustorm (per client)5747 */5748struct ustorm_per_queue_stats {5749	struct regpair ucast_no_buff_bytes;5750	struct regpair mcast_no_buff_bytes;5751	struct regpair bcast_no_buff_bytes;5752	__le32 ucast_no_buff_pkts;5753	__le32 mcast_no_buff_pkts;5754	__le32 bcast_no_buff_pkts;5755	__le32 coalesced_pkts;5756	struct regpair coalesced_bytes;5757	__le32 coalesced_events;5758	__le32 coalesced_aborts;5759};5760 5761/*5762 * Protocol-common statistics collected by the Xstorm (per client)5763 */5764struct xstorm_per_queue_stats {5765	struct regpair ucast_bytes_sent;5766	struct regpair mcast_bytes_sent;5767	struct regpair bcast_bytes_sent;5768	__le32 ucast_pkts_sent;5769	__le32 mcast_pkts_sent;5770	__le32 bcast_pkts_sent;5771	__le32 error_drop_pkts;5772};5773 5774/*5775 *5776 */5777struct per_queue_stats {5778	struct tstorm_per_queue_stats tstorm_queue_statistics;5779	struct ustorm_per_queue_stats ustorm_queue_statistics;5780	struct xstorm_per_queue_stats xstorm_queue_statistics;5781};5782 5783 5784/*5785 * FW version stored in first line of pram5786 */5787struct pram_fw_version {5788	u8 major;5789	u8 minor;5790	u8 revision;5791	u8 engineering;5792	u8 flags;5793#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)5794#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 05795#define PRAM_FW_VERSION_STORM_ID (0x3<<1)5796#define PRAM_FW_VERSION_STORM_ID_SHIFT 15797#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)5798#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 35799#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)5800#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 45801#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)5802#define __PRAM_FW_VERSION_RESERVED0_SHIFT 65803};5804 5805 5806/*5807 * Ethernet slow path element5808 */5809union protocol_common_specific_data {5810	u8 protocol_data[8];5811	struct regpair phy_address;5812	struct regpair mac_config_addr;5813	struct afex_vif_list_ramrod_data afex_vif_list_data;5814};5815 5816/*5817 * The send queue element5818 */5819struct protocol_common_spe {5820	struct spe_hdr hdr;5821	union protocol_common_specific_data data;5822};5823 5824/* The data for the Set Timesync Ramrod */5825struct set_timesync_ramrod_data {5826	u8 drift_adjust_cmd;5827	u8 offset_cmd;5828	u8 add_sub_drift_adjust_value;5829	u8 drift_adjust_value;5830	u32 drift_adjust_period;5831	struct regpair offset_delta;5832};5833 5834/*5835 * The send queue element5836 */5837struct slow_path_element {5838	struct spe_hdr hdr;5839	struct regpair protocol_data;5840};5841 5842 5843/*5844 * Protocol-common statistics counter5845 */5846struct stats_counter {5847	__le16 xstats_counter;5848	__le16 reserved0;5849	__le32 reserved1;5850	__le16 tstats_counter;5851	__le16 reserved2;5852	__le32 reserved3;5853	__le16 ustats_counter;5854	__le16 reserved4;5855	__le32 reserved5;5856	__le16 cstats_counter;5857	__le16 reserved6;5858	__le32 reserved7;5859};5860 5861 5862/*5863 *5864 */5865struct stats_query_entry {5866	u8 kind;5867	u8 index;5868	__le16 funcID;5869	__le32 reserved;5870	struct regpair address;5871};5872 5873/*5874 * statistic command5875 */5876struct stats_query_cmd_group {5877	struct stats_query_entry query[STATS_QUERY_CMD_COUNT];5878};5879 5880 5881/*5882 * statistic command header5883 */5884struct stats_query_header {5885	u8 cmd_num;5886	u8 reserved0;5887	__le16 drv_stats_counter;5888	__le32 reserved1;5889	struct regpair stats_counters_addrs;5890};5891 5892 5893/*5894 * Types of statistcis query entry5895 */5896enum stats_query_type {5897	STATS_TYPE_QUEUE,5898	STATS_TYPE_PORT,5899	STATS_TYPE_PF,5900	STATS_TYPE_TOE,5901	STATS_TYPE_FCOE,5902	MAX_STATS_QUERY_TYPE5903};5904 5905 5906/*5907 * Indicate of the function status block state5908 */5909enum status_block_state {5910	SB_DISABLED,5911	SB_ENABLED,5912	SB_CLEANED,5913	MAX_STATUS_BLOCK_STATE5914};5915 5916 5917/*5918 * Storm IDs (including attentions for IGU related enums)5919 */5920enum storm_id {5921	USTORM_ID,5922	CSTORM_ID,5923	XSTORM_ID,5924	TSTORM_ID,5925	ATTENTION_ID,5926	MAX_STORM_ID5927};5928 5929 5930/*5931 * Taffic types used in ETS and flow control algorithms5932 */5933enum traffic_type {5934	LLFC_TRAFFIC_TYPE_NW,5935	LLFC_TRAFFIC_TYPE_FCOE,5936	LLFC_TRAFFIC_TYPE_ISCSI,5937	MAX_TRAFFIC_TYPE5938};5939 5940 5941/*5942 * zone A per-queue data5943 */5944struct tstorm_queue_zone_data {5945	struct regpair reserved[4];5946};5947 5948 5949/*5950 * zone B per-VF data5951 */5952struct tstorm_vf_zone_data {5953	struct regpair reserved;5954};5955 5956/* Add or Subtract Value for Set Timesync Ramrod */5957enum ts_add_sub_value {5958	TS_SUB_VALUE,5959	TS_ADD_VALUE,5960	MAX_TS_ADD_SUB_VALUE5961};5962 5963/* Drift-Adjust Commands for Set Timesync Ramrod */5964enum ts_drift_adjust_cmd {5965	TS_DRIFT_ADJUST_KEEP,5966	TS_DRIFT_ADJUST_SET,5967	TS_DRIFT_ADJUST_RESET,5968	MAX_TS_DRIFT_ADJUST_CMD5969};5970 5971/* Offset Commands for Set Timesync Ramrod */5972enum ts_offset_cmd {5973	TS_OFFSET_KEEP,5974	TS_OFFSET_INC,5975	TS_OFFSET_DEC,5976	MAX_TS_OFFSET_CMD5977};5978 5979 /* zone A per-queue data */5980struct ustorm_queue_zone_data {5981	struct ustorm_eth_rx_producers eth_rx_producers;5982	struct regpair reserved[3];5983};5984 5985 5986/*5987 * zone B per-VF data5988 */5989struct ustorm_vf_zone_data {5990	struct regpair reserved;5991};5992 5993 5994/*5995 * data per VF-PF channel5996 */5997struct vf_pf_channel_data {5998#if defined(__BIG_ENDIAN)5999	u16 reserved0;6000	u8 valid;6001	u8 state;6002#elif defined(__LITTLE_ENDIAN)6003	u8 state;6004	u8 valid;6005	u16 reserved0;6006#endif6007	u32 reserved1;6008};6009 6010 6011/*6012 * State of VF-PF channel6013 */6014enum vf_pf_channel_state {6015	VF_PF_CHANNEL_STATE_READY,6016	VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,6017	MAX_VF_PF_CHANNEL_STATE6018};6019 6020 6021/*6022 * vif_list_rule_kind6023 */6024enum vif_list_rule_kind {6025	VIF_LIST_RULE_SET,6026	VIF_LIST_RULE_GET,6027	VIF_LIST_RULE_CLEAR_ALL,6028	VIF_LIST_RULE_CLEAR_FUNC,6029	MAX_VIF_LIST_RULE_KIND6030};6031 6032 6033/*6034 * zone A per-queue data6035 */6036struct xstorm_queue_zone_data {6037	struct regpair reserved[4];6038};6039 6040 6041/*6042 * zone B per-VF data6043 */6044struct xstorm_vf_zone_data {6045	struct regpair reserved;6046};6047 6048#endif /* BNX2X_HSI_H */6049