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1/* bnx2x_reg.h: Qlogic Everest network driver.2 *3 * Copyright (c) 2007-2013 Broadcom Corporation4 * Copyright (c) 2014 QLogic Corporation5 * All rights reserved6 *7 * This program is free software; you can redistribute it and/or modify8 * it under the terms of the GNU General Public License as published by9 * the Free Software Foundation.10 *11 * The registers description starts with the register Access type followed12 * by size in bits. For example [RW 32]. The access types are:13 * R - Read only14 * RC - Clear on read15 * RW - Read/Write16 * ST - Statistics register (clear on read)17 * W - Write only18 * WB - Wide bus register - the size is over 32 bits and it should be19 * read/write in consecutive 32 bits accesses20 * WR - Write Clear (write 1 to clear the bit)21 *22 */23#ifndef BNX2X_REG_H24#define BNX2X_REG_H25 26#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)27#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)28#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)29#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)30#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)31#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)32/* [RW 1] Initiate the ATC array - reset all the valid bits */33#define ATC_REG_ATC_INIT_ARRAY 0x1100b834/* [R 1] ATC initialization done */35#define ATC_REG_ATC_INIT_DONE 0x1100bc36/* [RC 6] Interrupt register #0 read clear */37#define ATC_REG_ATC_INT_STS_CLR 0x1101c038/* [RW 5] Parity mask register #0 read/write */39#define ATC_REG_ATC_PRTY_MASK 0x1101d840/* [R 5] Parity register #0 read */41#define ATC_REG_ATC_PRTY_STS 0x1101cc42/* [RC 5] Parity register #0 read clear */43#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d044/* [RW 19] Interrupt mask register #0 read/write */45#define BRB1_REG_BRB1_INT_MASK 0x6012846/* [R 19] Interrupt register #0 read */47#define BRB1_REG_BRB1_INT_STS 0x6011c48/* [RW 4] Parity mask register #0 read/write */49#define BRB1_REG_BRB1_PRTY_MASK 0x6013850/* [R 4] Parity register #0 read */51#define BRB1_REG_BRB1_PRTY_STS 0x6012c52/* [RC 4] Parity register #0 read clear */53#define BRB1_REG_BRB1_PRTY_STS_CLR 0x6013054/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At55 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -57 * following reset the first rbc access to this reg must be write; there can58 * be no more rbc writes after the first one; there can be any number of rbc59 * read following the first write; rbc access not following these rules will60 * result in hang condition. */61#define BRB1_REG_FREE_LIST_PRS_CRDT 0x6020062/* [RW 10] The number of free blocks below which the full signal to class 063 * is asserted */64#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d065#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x6023066/* [RW 11] The number of free blocks above which the full signal to class 067 * is de-asserted */68#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d469#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x6023470/* [RW 11] The number of free blocks below which the full signal to class 171 * is asserted */72#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d873#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x6023874/* [RW 11] The number of free blocks above which the full signal to class 175 * is de-asserted */76#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc77#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c78/* [RW 11] The number of free blocks below which the full signal to the LB79 * port is asserted */80#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e081/* [RW 10] The number of free blocks above which the full signal to the LB82 * port is de-asserted */83#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e484/* [RW 10] The number of free blocks above which the High_llfc signal to85 interface #n is de-asserted. */86#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c87/* [RW 10] The number of free blocks below which the High_llfc signal to88 interface #n is asserted. */89#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c90/* [RW 11] The number of blocks guarantied for the LB port */91#define BRB1_REG_LB_GUARANTIED 0x601ec92/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port93 * before signaling XON. */94#define BRB1_REG_LB_GUARANTIED_HYST 0x6026495/* [RW 24] LL RAM data. */96#define BRB1_REG_LL_RAM 0x6100097/* [RW 10] The number of free blocks above which the Low_llfc signal to98 interface #n is de-asserted. */99#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c100/* [RW 10] The number of free blocks below which the Low_llfc signal to101 interface #n is asserted. */102#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c103/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The104 * register is applicable only when per_class_guaranty_mode is set. */105#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244106/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC107 * 1 before signaling XON. The register is applicable only when108 * per_class_guaranty_mode is set. */109#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254110/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The111 * register is applicable only when per_class_guaranty_mode is set. */112#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248113/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0114 * before signaling XON. The register is applicable only when115 * per_class_guaranty_mode is set. */116#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258117/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register118 * is applicable only when per_class_guaranty_mode is set. */119#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c120/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC121 * 1 before signaling XON. The register is applicable only when122 * per_class_guaranty_mode is set. */123#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c124/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The125 * register is applicable only when per_class_guaranty_mode is set. */126#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250127/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC128 * 1 before signaling XON. The register is applicable only when129 * per_class_guaranty_mode is set. */130#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260131/* [RW 11] The number of blocks guarantied for the MAC port. The register is132 * applicable only when per_class_guaranty_mode is reset. */133#define BRB1_REG_MAC_GUARANTIED_0 0x601e8134#define BRB1_REG_MAC_GUARANTIED_1 0x60240135/* [R 24] The number of full blocks. */136#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090137/* [ST 32] The number of cycles that the write_full signal towards MAC #0138 was asserted. */139#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8140#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc141#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8142/* [ST 32] The number of cycles that the pause signal towards MAC #0 was143 asserted. */144#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8145#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc146/* [RW 10] The number of free blocks below which the pause signal to class 0147 * is asserted */148#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0149#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220150/* [RW 11] The number of free blocks above which the pause signal to class 0151 * is de-asserted */152#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4153#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224154/* [RW 11] The number of free blocks below which the pause signal to class 1155 * is asserted */156#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8157#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228158/* [RW 11] The number of free blocks above which the pause signal to class 1159 * is de-asserted */160#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc161#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c162/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */163#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078164#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c165/* [RW 10] Write client 0: Assert pause threshold. */166#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068167/* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC168 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC169 * mode). 1=per-class guaranty mode (new mode). */170#define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268171/* [R 24] The number of full blocks occpied by port. */172#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094173/* [RW 1] Reset the design by software. */174#define BRB1_REG_SOFT_RESET 0x600dc175/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */176#define CCM_REG_CAM_OCCUP 0xd0188177/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;178 acknowledge output is deasserted; all other signals are treated as usual;179 if 1 - normal activity. */180#define CCM_REG_CCM_CFC_IFEN 0xd003c181/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is182 disregarded; valid is deasserted; all other signals are treated as usual;183 if 1 - normal activity. */184#define CCM_REG_CCM_CQM_IFEN 0xd000c185/* [RW 1] If set the Q index; received from the QM is inserted to event ID.186 Otherwise 0 is inserted. */187#define CCM_REG_CCM_CQM_USE_Q 0xd00c0188/* [RW 11] Interrupt mask register #0 read/write */189#define CCM_REG_CCM_INT_MASK 0xd01e4190/* [R 11] Interrupt register #0 read */191#define CCM_REG_CCM_INT_STS 0xd01d8192/* [RW 27] Parity mask register #0 read/write */193#define CCM_REG_CCM_PRTY_MASK 0xd01f4194/* [R 27] Parity register #0 read */195#define CCM_REG_CCM_PRTY_STS 0xd01e8196/* [RC 27] Parity register #0 read clear */197#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec198/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS199 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).200 Is used to determine the number of the AG context REG-pairs written back;201 when the input message Reg1WbFlg isn't set. */202#define CCM_REG_CCM_REG0_SZ 0xd00c4203/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is204 disregarded; valid is deasserted; all other signals are treated as usual;205 if 1 - normal activity. */206#define CCM_REG_CCM_STORM0_IFEN 0xd0004207/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is208 disregarded; valid is deasserted; all other signals are treated as usual;209 if 1 - normal activity. */210#define CCM_REG_CCM_STORM1_IFEN 0xd0008211/* [RW 1] CDU AG read Interface enable. If 0 - the request input is212 disregarded; valid output is deasserted; all other signals are treated as213 usual; if 1 - normal activity. */214#define CCM_REG_CDU_AG_RD_IFEN 0xd0030215/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input216 are disregarded; all other signals are treated as usual; if 1 - normal217 activity. */218#define CCM_REG_CDU_AG_WR_IFEN 0xd002c219/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is220 disregarded; valid output is deasserted; all other signals are treated as221 usual; if 1 - normal activity. */222#define CCM_REG_CDU_SM_RD_IFEN 0xd0038223/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid224 input is disregarded; all other signals are treated as usual; if 1 -225 normal activity. */226#define CCM_REG_CDU_SM_WR_IFEN 0xd0034227/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes228 the initial credit value; read returns the current value of the credit229 counter. Must be initialized to 1 at start-up. */230#define CCM_REG_CFC_INIT_CRD 0xd0204231/* [RW 2] Auxiliary counter flag Q number 1. */232#define CCM_REG_CNT_AUX1_Q 0xd00c8233/* [RW 2] Auxiliary counter flag Q number 2. */234#define CCM_REG_CNT_AUX2_Q 0xd00cc235/* [RW 28] The CM header value for QM request (primary). */236#define CCM_REG_CQM_CCM_HDR_P 0xd008c237/* [RW 28] The CM header value for QM request (secondary). */238#define CCM_REG_CQM_CCM_HDR_S 0xd0090239/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;240 acknowledge output is deasserted; all other signals are treated as usual;241 if 1 - normal activity. */242#define CCM_REG_CQM_CCM_IFEN 0xd0014243/* [RW 6] QM output initial credit. Max credit available - 32. Write writes244 the initial credit value; read returns the current value of the credit245 counter. Must be initialized to 32 at start-up. */246#define CCM_REG_CQM_INIT_CRD 0xd020c247/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0248 stands for weight 8 (the most prioritised); 1 stands for weight 1(least249 prioritised); 2 stands for weight 2; tc. */250#define CCM_REG_CQM_P_WEIGHT 0xd00b8251/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0252 stands for weight 8 (the most prioritised); 1 stands for weight 1(least253 prioritised); 2 stands for weight 2; tc. */254#define CCM_REG_CQM_S_WEIGHT 0xd00bc255/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;256 acknowledge output is deasserted; all other signals are treated as usual;257 if 1 - normal activity. */258#define CCM_REG_CSDM_IFEN 0xd0018259/* [RC 1] Set when the message length mismatch (relative to last indication)260 at the SDM interface is detected. */261#define CCM_REG_CSDM_LENGTH_MIS 0xd0170262/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for263 weight 8 (the most prioritised); 1 stands for weight 1(least264 prioritised); 2 stands for weight 2; tc. */265#define CCM_REG_CSDM_WEIGHT 0xd00b4266/* [RW 28] The CM header for QM formatting in case of an error in the QM267 inputs. */268#define CCM_REG_ERR_CCM_HDR 0xd0094269/* [RW 8] The Event ID in case the input message ErrorFlg is set. */270#define CCM_REG_ERR_EVNT_ID 0xd0098271/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write272 writes the initial credit value; read returns the current value of the273 credit counter. Must be initialized to 64 at start-up. */274#define CCM_REG_FIC0_INIT_CRD 0xd0210275/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write276 writes the initial credit value; read returns the current value of the277 credit counter. Must be initialized to 64 at start-up. */278#define CCM_REG_FIC1_INIT_CRD 0xd0214279/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1280 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;281 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and282 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and283 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */284#define CCM_REG_GR_ARB_TYPE 0xd015c285/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the286 highest priority is 3. It is supposed; that the Store channel priority is287 the complement to 4 of the rest priorities - Aggregation channel; Load288 (FIC0) channel and Load (FIC1). */289#define CCM_REG_GR_LD0_PR 0xd0164290/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the291 highest priority is 3. It is supposed; that the Store channel priority is292 the complement to 4 of the rest priorities - Aggregation channel; Load293 (FIC0) channel and Load (FIC1). */294#define CCM_REG_GR_LD1_PR 0xd0168295/* [RW 2] General flags index. */296#define CCM_REG_INV_DONE_Q 0xd0108297/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM298 context and sent to STORM; for a specific connection type. The double299 REG-pairs are used in order to align to STORM context row size of 128300 bits. The offset of these data in the STORM context is always 0. Index301 _(0..15) stands for the connection type (one of 16). */302#define CCM_REG_N_SM_CTX_LD_0 0xd004c303#define CCM_REG_N_SM_CTX_LD_1 0xd0050304#define CCM_REG_N_SM_CTX_LD_2 0xd0054305#define CCM_REG_N_SM_CTX_LD_3 0xd0058306#define CCM_REG_N_SM_CTX_LD_4 0xd005c307/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;308 acknowledge output is deasserted; all other signals are treated as usual;309 if 1 - normal activity. */310#define CCM_REG_PBF_IFEN 0xd0028311/* [RC 1] Set when the message length mismatch (relative to last indication)312 at the pbf interface is detected. */313#define CCM_REG_PBF_LENGTH_MIS 0xd0180314/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for315 weight 8 (the most prioritised); 1 stands for weight 1(least316 prioritised); 2 stands for weight 2; tc. */317#define CCM_REG_PBF_WEIGHT 0xd00ac318#define CCM_REG_PHYS_QNUM1_0 0xd0134319#define CCM_REG_PHYS_QNUM1_1 0xd0138320#define CCM_REG_PHYS_QNUM2_0 0xd013c321#define CCM_REG_PHYS_QNUM2_1 0xd0140322#define CCM_REG_PHYS_QNUM3_0 0xd0144323#define CCM_REG_PHYS_QNUM3_1 0xd0148324#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114325#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118326#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c327#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120328#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124329#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128330#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c331#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130332/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is333 disregarded; acknowledge output is deasserted; all other signals are334 treated as usual; if 1 - normal activity. */335#define CCM_REG_STORM_CCM_IFEN 0xd0010336/* [RC 1] Set when the message length mismatch (relative to last indication)337 at the STORM interface is detected. */338#define CCM_REG_STORM_LENGTH_MIS 0xd016c339/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)340 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for341 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);342 tc. */343#define CCM_REG_STORM_WEIGHT 0xd009c344/* [RW 1] Input tsem Interface enable. If 0 - the valid input is345 disregarded; acknowledge output is deasserted; all other signals are346 treated as usual; if 1 - normal activity. */347#define CCM_REG_TSEM_IFEN 0xd001c348/* [RC 1] Set when the message length mismatch (relative to last indication)349 at the tsem interface is detected. */350#define CCM_REG_TSEM_LENGTH_MIS 0xd0174351/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for352 weight 8 (the most prioritised); 1 stands for weight 1(least353 prioritised); 2 stands for weight 2; tc. */354#define CCM_REG_TSEM_WEIGHT 0xd00a0355/* [RW 1] Input usem Interface enable. If 0 - the valid input is356 disregarded; acknowledge output is deasserted; all other signals are357 treated as usual; if 1 - normal activity. */358#define CCM_REG_USEM_IFEN 0xd0024359/* [RC 1] Set when message length mismatch (relative to last indication) at360 the usem interface is detected. */361#define CCM_REG_USEM_LENGTH_MIS 0xd017c362/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for363 weight 8 (the most prioritised); 1 stands for weight 1(least364 prioritised); 2 stands for weight 2; tc. */365#define CCM_REG_USEM_WEIGHT 0xd00a8366/* [RW 1] Input xsem Interface enable. If 0 - the valid input is367 disregarded; acknowledge output is deasserted; all other signals are368 treated as usual; if 1 - normal activity. */369#define CCM_REG_XSEM_IFEN 0xd0020370/* [RC 1] Set when the message length mismatch (relative to last indication)371 at the xsem interface is detected. */372#define CCM_REG_XSEM_LENGTH_MIS 0xd0178373/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for374 weight 8 (the most prioritised); 1 stands for weight 1(least375 prioritised); 2 stands for weight 2; tc. */376#define CCM_REG_XSEM_WEIGHT 0xd00a4377/* [RW 19] Indirect access to the descriptor table of the XX protection378 mechanism. The fields are: [5:0] - message length; [12:6] - message379 pointer; 18:13] - next pointer. */380#define CCM_REG_XX_DESCR_TABLE 0xd0300381#define CCM_REG_XX_DESCR_TABLE_SIZE 24382/* [R 7] Used to read the value of XX protection Free counter. */383#define CCM_REG_XX_FREE 0xd0184384/* [RW 6] Initial value for the credit counter; responsible for fulfilling385 of the Input Stage XX protection buffer by the XX protection pending386 messages. Max credit available - 127. Write writes the initial credit387 value; read returns the current value of the credit counter. Must be388 initialized to maximum XX protected message size - 2 at start-up. */389#define CCM_REG_XX_INIT_CRD 0xd0220390/* [RW 7] The maximum number of pending messages; which may be stored in XX391 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.392 At write comprises the start value of the ~ccm_registers_xx_free.xx_free393 counter. */394#define CCM_REG_XX_MSG_NUM 0xd0224395/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */396#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044397/* [RW 18] Indirect access to the XX table of the XX protection mechanism.398 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -399 header pointer. */400#define CCM_REG_XX_TABLE 0xd0280401#define CDU_REG_CDU_CHK_MASK0 0x101000402#define CDU_REG_CDU_CHK_MASK1 0x101004403#define CDU_REG_CDU_CONTROL0 0x101008404#define CDU_REG_CDU_DEBUG 0x101010405#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020406/* [RW 7] Interrupt mask register #0 read/write */407#define CDU_REG_CDU_INT_MASK 0x10103c408/* [R 7] Interrupt register #0 read */409#define CDU_REG_CDU_INT_STS 0x101030410/* [RW 5] Parity mask register #0 read/write */411#define CDU_REG_CDU_PRTY_MASK 0x10104c412/* [R 5] Parity register #0 read */413#define CDU_REG_CDU_PRTY_STS 0x101040414/* [RC 5] Parity register #0 read clear */415#define CDU_REG_CDU_PRTY_STS_CLR 0x101044416/* [RC 32] logging of error data in case of a CDU load error:417 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;418 ype_error; ctual_active; ctual_compressed_context}; */419#define CDU_REG_ERROR_DATA 0x101014420/* [WB 216] L1TT ram access. each entry has the following format :421 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];422 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */423#define CDU_REG_L1TT 0x101800424/* [WB 24] MATT ram access. each entry has the following425 format:{RegionLength[11:0]; egionOffset[11:0]} */426#define CDU_REG_MATT 0x101100427/* [RW 1] when this bit is set the CDU operates in e1hmf mode */428#define CDU_REG_MF_MODE 0x101050429/* [R 1] indication the initializing the activity counter by the hardware430 was done. */431#define CFC_REG_AC_INIT_DONE 0x104078432/* [RW 13] activity counter ram access */433#define CFC_REG_ACTIVITY_COUNTER 0x104400434#define CFC_REG_ACTIVITY_COUNTER_SIZE 256435/* [R 1] indication the initializing the cams by the hardware was done. */436#define CFC_REG_CAM_INIT_DONE 0x10407c437/* [RW 2] Interrupt mask register #0 read/write */438#define CFC_REG_CFC_INT_MASK 0x104108439/* [R 2] Interrupt register #0 read */440#define CFC_REG_CFC_INT_STS 0x1040fc441/* [RC 2] Interrupt register #0 read clear */442#define CFC_REG_CFC_INT_STS_CLR 0x104100443/* [RW 4] Parity mask register #0 read/write */444#define CFC_REG_CFC_PRTY_MASK 0x104118445/* [R 4] Parity register #0 read */446#define CFC_REG_CFC_PRTY_STS 0x10410c447/* [RC 4] Parity register #0 read clear */448#define CFC_REG_CFC_PRTY_STS_CLR 0x104110449/* [RW 21] CID cam access (21:1 - Data; alid - 0) */450#define CFC_REG_CID_CAM 0x104800451#define CFC_REG_CONTROL0 0x104028452#define CFC_REG_DEBUG0 0x104050453/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error454 vector) whether the cfc should be disabled upon it */455#define CFC_REG_DISABLE_ON_ERROR 0x104044456/* [RC 14] CFC error vector. when the CFC detects an internal error it will457 set one of these bits. the bit description can be found in CFC458 specifications */459#define CFC_REG_ERROR_VECTOR 0x10403c460/* [WB 93] LCID info ram access */461#define CFC_REG_INFO_RAM 0x105000462#define CFC_REG_INFO_RAM_SIZE 1024463#define CFC_REG_INIT_REG 0x10404c464#define CFC_REG_INTERFACES 0x104058465/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this466 field allows changing the priorities of the weighted-round-robin arbiter467 which selects which CFC load client should be served next */468#define CFC_REG_LCREQ_WEIGHTS 0x104084469/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */470#define CFC_REG_LINK_LIST 0x104c00471#define CFC_REG_LINK_LIST_SIZE 256472/* [R 1] indication the initializing the link list by the hardware was done. */473#define CFC_REG_LL_INIT_DONE 0x104074474/* [R 9] Number of allocated LCIDs which are at empty state */475#define CFC_REG_NUM_LCIDS_ALLOC 0x104020476/* [R 9] Number of Arriving LCIDs in Link List Block */477#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004478#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120479/* [R 9] Number of Leaving LCIDs in Link List Block */480#define CFC_REG_NUM_LCIDS_LEAVING 0x104018481#define CFC_REG_WEAK_ENABLE_PF 0x104124482/* [RW 8] The event id for aggregated interrupt 0 */483#define CSDM_REG_AGG_INT_EVENT_0 0xc2038484#define CSDM_REG_AGG_INT_EVENT_10 0xc2060485#define CSDM_REG_AGG_INT_EVENT_11 0xc2064486#define CSDM_REG_AGG_INT_EVENT_12 0xc2068487#define CSDM_REG_AGG_INT_EVENT_13 0xc206c488#define CSDM_REG_AGG_INT_EVENT_14 0xc2070489#define CSDM_REG_AGG_INT_EVENT_15 0xc2074490#define CSDM_REG_AGG_INT_EVENT_16 0xc2078491#define CSDM_REG_AGG_INT_EVENT_2 0xc2040492#define CSDM_REG_AGG_INT_EVENT_3 0xc2044493#define CSDM_REG_AGG_INT_EVENT_4 0xc2048494#define CSDM_REG_AGG_INT_EVENT_5 0xc204c495#define CSDM_REG_AGG_INT_EVENT_6 0xc2050496#define CSDM_REG_AGG_INT_EVENT_7 0xc2054497#define CSDM_REG_AGG_INT_EVENT_8 0xc2058498#define CSDM_REG_AGG_INT_EVENT_9 0xc205c499/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)500 or auto-mask-mode (1) */501#define CSDM_REG_AGG_INT_MODE_10 0xc21e0502#define CSDM_REG_AGG_INT_MODE_11 0xc21e4503#define CSDM_REG_AGG_INT_MODE_12 0xc21e8504#define CSDM_REG_AGG_INT_MODE_13 0xc21ec505#define CSDM_REG_AGG_INT_MODE_14 0xc21f0506#define CSDM_REG_AGG_INT_MODE_15 0xc21f4507#define CSDM_REG_AGG_INT_MODE_16 0xc21f8508#define CSDM_REG_AGG_INT_MODE_6 0xc21d0509#define CSDM_REG_AGG_INT_MODE_7 0xc21d4510#define CSDM_REG_AGG_INT_MODE_8 0xc21d8511#define CSDM_REG_AGG_INT_MODE_9 0xc21dc512/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */513#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008514/* [RW 16] The maximum value of the completion counter #0 */515#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c516/* [RW 16] The maximum value of the completion counter #1 */517#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020518/* [RW 16] The maximum value of the completion counter #2 */519#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024520/* [RW 16] The maximum value of the completion counter #3 */521#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028522/* [RW 13] The start address in the internal RAM for the completion523 counters. */524#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c525/* [RW 32] Interrupt mask register #0 read/write */526#define CSDM_REG_CSDM_INT_MASK_0 0xc229c527#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac528/* [R 32] Interrupt register #0 read */529#define CSDM_REG_CSDM_INT_STS_0 0xc2290530#define CSDM_REG_CSDM_INT_STS_1 0xc22a0531/* [RW 11] Parity mask register #0 read/write */532#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc533/* [R 11] Parity register #0 read */534#define CSDM_REG_CSDM_PRTY_STS 0xc22b0535/* [RC 11] Parity register #0 read clear */536#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4537#define CSDM_REG_ENABLE_IN1 0xc2238538#define CSDM_REG_ENABLE_IN2 0xc223c539#define CSDM_REG_ENABLE_OUT1 0xc2240540#define CSDM_REG_ENABLE_OUT2 0xc2244541/* [RW 4] The initial number of messages that can be sent to the pxp control542 interface without receiving any ACK. */543#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc544/* [ST 32] The number of ACK after placement messages received */545#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c546/* [ST 32] The number of packet end messages received from the parser */547#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274548/* [ST 32] The number of requests received from the pxp async if */549#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278550/* [ST 32] The number of commands received in queue 0 */551#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248552/* [ST 32] The number of commands received in queue 10 */553#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c554/* [ST 32] The number of commands received in queue 11 */555#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270556/* [ST 32] The number of commands received in queue 1 */557#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c558/* [ST 32] The number of commands received in queue 3 */559#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250560/* [ST 32] The number of commands received in queue 4 */561#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254562/* [ST 32] The number of commands received in queue 5 */563#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258564/* [ST 32] The number of commands received in queue 6 */565#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c566/* [ST 32] The number of commands received in queue 7 */567#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260568/* [ST 32] The number of commands received in queue 8 */569#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264570/* [ST 32] The number of commands received in queue 9 */571#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268572/* [RW 13] The start address in the internal RAM for queue counters */573#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010574/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */575#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548576/* [R 1] parser fifo empty in sdm_sync block */577#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550578/* [R 1] parser serial fifo empty in sdm_sync block */579#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558580/* [RW 32] Tick for timer counter. Applicable only when581 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */582#define CSDM_REG_TIMER_TICK 0xc2000583/* [RW 5] The number of time_slots in the arbitration cycle */584#define CSEM_REG_ARB_CYCLE_SIZE 0x200034585/* [RW 3] The source that is associated with arbitration element 0. Source586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-587 sleeping thread with priority 1; 4- sleeping thread with priority 2 */588#define CSEM_REG_ARB_ELEMENT0 0x200020589/* [RW 3] The source that is associated with arbitration element 1. Source590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-591 sleeping thread with priority 1; 4- sleeping thread with priority 2.592 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */593#define CSEM_REG_ARB_ELEMENT1 0x200024594/* [RW 3] The source that is associated with arbitration element 2. Source595 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-596 sleeping thread with priority 1; 4- sleeping thread with priority 2.597 Could not be equal to register ~csem_registers_arb_element0.arb_element0598 and ~csem_registers_arb_element1.arb_element1 */599#define CSEM_REG_ARB_ELEMENT2 0x200028600/* [RW 3] The source that is associated with arbitration element 3. Source601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-602 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could603 not be equal to register ~csem_registers_arb_element0.arb_element0 and604 ~csem_registers_arb_element1.arb_element1 and605 ~csem_registers_arb_element2.arb_element2 */606#define CSEM_REG_ARB_ELEMENT3 0x20002c607/* [RW 3] The source that is associated with arbitration element 4. Source608 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-609 sleeping thread with priority 1; 4- sleeping thread with priority 2.610 Could not be equal to register ~csem_registers_arb_element0.arb_element0611 and ~csem_registers_arb_element1.arb_element1 and612 ~csem_registers_arb_element2.arb_element2 and613 ~csem_registers_arb_element3.arb_element3 */614#define CSEM_REG_ARB_ELEMENT4 0x200030615/* [RW 32] Interrupt mask register #0 read/write */616#define CSEM_REG_CSEM_INT_MASK_0 0x200110617#define CSEM_REG_CSEM_INT_MASK_1 0x200120618/* [R 32] Interrupt register #0 read */619#define CSEM_REG_CSEM_INT_STS_0 0x200104620#define CSEM_REG_CSEM_INT_STS_1 0x200114621/* [RW 32] Parity mask register #0 read/write */622#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130623#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140624/* [R 32] Parity register #0 read */625#define CSEM_REG_CSEM_PRTY_STS_0 0x200124626#define CSEM_REG_CSEM_PRTY_STS_1 0x200134627/* [RC 32] Parity register #0 read clear */628#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128629#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138630#define CSEM_REG_ENABLE_IN 0x2000a4631#define CSEM_REG_ENABLE_OUT 0x2000a8632/* [RW 32] This address space contains all registers and memories that are633 placed in SEM_FAST block. The SEM_FAST registers are described in634 appendix B. In order to access the sem_fast registers the base address635 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */636#define CSEM_REG_FAST_MEMORY 0x220000637/* [RW 1] Disables input messages from FIC0 May be updated during run_time638 by the microcode */639#define CSEM_REG_FIC0_DISABLE 0x200224640/* [RW 1] Disables input messages from FIC1 May be updated during run_time641 by the microcode */642#define CSEM_REG_FIC1_DISABLE 0x200234643/* [RW 15] Interrupt table Read and write access to it is not possible in644 the middle of the work */645#define CSEM_REG_INT_TABLE 0x200400646/* [ST 24] Statistics register. The number of messages that entered through647 FIC0 */648#define CSEM_REG_MSG_NUM_FIC0 0x200000649/* [ST 24] Statistics register. The number of messages that entered through650 FIC1 */651#define CSEM_REG_MSG_NUM_FIC1 0x200004652/* [ST 24] Statistics register. The number of messages that were sent to653 FOC0 */654#define CSEM_REG_MSG_NUM_FOC0 0x200008655/* [ST 24] Statistics register. The number of messages that were sent to656 FOC1 */657#define CSEM_REG_MSG_NUM_FOC1 0x20000c658/* [ST 24] Statistics register. The number of messages that were sent to659 FOC2 */660#define CSEM_REG_MSG_NUM_FOC2 0x200010661/* [ST 24] Statistics register. The number of messages that were sent to662 FOC3 */663#define CSEM_REG_MSG_NUM_FOC3 0x200014664/* [RW 1] Disables input messages from the passive buffer May be updated665 during run_time by the microcode */666#define CSEM_REG_PAS_DISABLE 0x20024c667/* [WB 128] Debug only. Passive buffer memory */668#define CSEM_REG_PASSIVE_BUFFER 0x202000669/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */670#define CSEM_REG_PRAM 0x240000671/* [R 16] Valid sleeping threads indication have bit per thread */672#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c673/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */674#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0675/* [RW 16] List of free threads . There is a bit per thread. */676#define CSEM_REG_THREADS_LIST 0x2002e4677/* [RW 3] The arbitration scheme of time_slot 0 */678#define CSEM_REG_TS_0_AS 0x200038679/* [RW 3] The arbitration scheme of time_slot 10 */680#define CSEM_REG_TS_10_AS 0x200060681/* [RW 3] The arbitration scheme of time_slot 11 */682#define CSEM_REG_TS_11_AS 0x200064683/* [RW 3] The arbitration scheme of time_slot 12 */684#define CSEM_REG_TS_12_AS 0x200068685/* [RW 3] The arbitration scheme of time_slot 13 */686#define CSEM_REG_TS_13_AS 0x20006c687/* [RW 3] The arbitration scheme of time_slot 14 */688#define CSEM_REG_TS_14_AS 0x200070689/* [RW 3] The arbitration scheme of time_slot 15 */690#define CSEM_REG_TS_15_AS 0x200074691/* [RW 3] The arbitration scheme of time_slot 16 */692#define CSEM_REG_TS_16_AS 0x200078693/* [RW 3] The arbitration scheme of time_slot 17 */694#define CSEM_REG_TS_17_AS 0x20007c695/* [RW 3] The arbitration scheme of time_slot 18 */696#define CSEM_REG_TS_18_AS 0x200080697/* [RW 3] The arbitration scheme of time_slot 1 */698#define CSEM_REG_TS_1_AS 0x20003c699/* [RW 3] The arbitration scheme of time_slot 2 */700#define CSEM_REG_TS_2_AS 0x200040701/* [RW 3] The arbitration scheme of time_slot 3 */702#define CSEM_REG_TS_3_AS 0x200044703/* [RW 3] The arbitration scheme of time_slot 4 */704#define CSEM_REG_TS_4_AS 0x200048705/* [RW 3] The arbitration scheme of time_slot 5 */706#define CSEM_REG_TS_5_AS 0x20004c707/* [RW 3] The arbitration scheme of time_slot 6 */708#define CSEM_REG_TS_6_AS 0x200050709/* [RW 3] The arbitration scheme of time_slot 7 */710#define CSEM_REG_TS_7_AS 0x200054711/* [RW 3] The arbitration scheme of time_slot 8 */712#define CSEM_REG_TS_8_AS 0x200058713/* [RW 3] The arbitration scheme of time_slot 9 */714#define CSEM_REG_TS_9_AS 0x20005c715/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64716 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */717#define CSEM_REG_VFPF_ERR_NUM 0x200380718/* [RW 1] Parity mask register #0 read/write */719#define DBG_REG_DBG_PRTY_MASK 0xc0a8720/* [R 1] Parity register #0 read */721#define DBG_REG_DBG_PRTY_STS 0xc09c722/* [RC 1] Parity register #0 read clear */723#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0724/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The725 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;726 * 4.Completion function=0; 5.Error handling=0 */727#define DMAE_REG_BACKWARD_COMP_EN 0x10207c728/* [RW 32] Commands memory. The address to command X; row Y is to calculated729 as 14*X+Y. */730#define DMAE_REG_CMD_MEM 0x102400731#define DMAE_REG_CMD_MEM_SIZE 224732/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c733 initial value is all ones. */734#define DMAE_REG_CRC16C_INIT 0x10201c735/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the736 CRC-16 T10 initial value is all ones. */737#define DMAE_REG_CRC16T10_INIT 0x102020738/* [RW 2] Interrupt mask register #0 read/write */739#define DMAE_REG_DMAE_INT_MASK 0x102054740/* [RW 4] Parity mask register #0 read/write */741#define DMAE_REG_DMAE_PRTY_MASK 0x102064742/* [R 4] Parity register #0 read */743#define DMAE_REG_DMAE_PRTY_STS 0x102058744/* [RC 4] Parity register #0 read clear */745#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c746/* [RW 1] Command 0 go. */747#define DMAE_REG_GO_C0 0x102080748/* [RW 1] Command 1 go. */749#define DMAE_REG_GO_C1 0x102084750/* [RW 1] Command 10 go. */751#define DMAE_REG_GO_C10 0x102088752/* [RW 1] Command 11 go. */753#define DMAE_REG_GO_C11 0x10208c754/* [RW 1] Command 12 go. */755#define DMAE_REG_GO_C12 0x102090756/* [RW 1] Command 13 go. */757#define DMAE_REG_GO_C13 0x102094758/* [RW 1] Command 14 go. */759#define DMAE_REG_GO_C14 0x102098760/* [RW 1] Command 15 go. */761#define DMAE_REG_GO_C15 0x10209c762/* [RW 1] Command 2 go. */763#define DMAE_REG_GO_C2 0x1020a0764/* [RW 1] Command 3 go. */765#define DMAE_REG_GO_C3 0x1020a4766/* [RW 1] Command 4 go. */767#define DMAE_REG_GO_C4 0x1020a8768/* [RW 1] Command 5 go. */769#define DMAE_REG_GO_C5 0x1020ac770/* [RW 1] Command 6 go. */771#define DMAE_REG_GO_C6 0x1020b0772/* [RW 1] Command 7 go. */773#define DMAE_REG_GO_C7 0x1020b4774/* [RW 1] Command 8 go. */775#define DMAE_REG_GO_C8 0x1020b8776/* [RW 1] Command 9 go. */777#define DMAE_REG_GO_C9 0x1020bc778/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge779 input is disregarded; valid is deasserted; all other signals are treated780 as usual; if 1 - normal activity. */781#define DMAE_REG_GRC_IFEN 0x102008782/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the783 acknowledge input is disregarded; valid is deasserted; full is asserted;784 all other signals are treated as usual; if 1 - normal activity. */785#define DMAE_REG_PCI_IFEN 0x102004786/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the787 initial value to the credit counter; related to the address. Read returns788 the current value of the counter. */789#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0790/* [RW 8] Aggregation command. */791#define DORQ_REG_AGG_CMD0 0x170060792/* [RW 8] Aggregation command. */793#define DORQ_REG_AGG_CMD1 0x170064794/* [RW 8] Aggregation command. */795#define DORQ_REG_AGG_CMD2 0x170068796/* [RW 8] Aggregation command. */797#define DORQ_REG_AGG_CMD3 0x17006c798/* [RW 28] UCM Header. */799#define DORQ_REG_CMHEAD_RX 0x170050800/* [RW 32] Doorbell address for RBC doorbells (function 0). */801#define DORQ_REG_DB_ADDR0 0x17008c802/* [RW 5] Interrupt mask register #0 read/write */803#define DORQ_REG_DORQ_INT_MASK 0x170180804/* [R 5] Interrupt register #0 read */805#define DORQ_REG_DORQ_INT_STS 0x170174806/* [RC 5] Interrupt register #0 read clear */807#define DORQ_REG_DORQ_INT_STS_CLR 0x170178808/* [RW 2] Parity mask register #0 read/write */809#define DORQ_REG_DORQ_PRTY_MASK 0x170190810/* [R 2] Parity register #0 read */811#define DORQ_REG_DORQ_PRTY_STS 0x170184812/* [RC 2] Parity register #0 read clear */813#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188814/* [RW 8] The address to write the DPM CID to STORM. */815#define DORQ_REG_DPM_CID_ADDR 0x170044816/* [RW 5] The DPM mode CID extraction offset. */817#define DORQ_REG_DPM_CID_OFST 0x170030818/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */819#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c820/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */821#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078822/* [R 13] Current value of the DQ FIFO fill level according to following823 pointer. The range is 0 - 256 FIFO rows; where each row stands for the824 doorbell. */825#define DORQ_REG_DQ_FILL_LVLF 0x1700a4826/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or827 equal to full threshold; reset on full clear. */828#define DORQ_REG_DQ_FULL_ST 0x1700c0829/* [RW 28] The value sent to CM header in the case of CFC load error. */830#define DORQ_REG_ERR_CMHEAD 0x170058831#define DORQ_REG_IF_EN 0x170004832#define DORQ_REG_MAX_RVFID_SIZE 0x1701ec833#define DORQ_REG_MODE_ACT 0x170008834/* [RW 5] The normal mode CID extraction offset. */835#define DORQ_REG_NORM_CID_OFST 0x17002c836/* [RW 28] TCM Header when only TCP context is loaded. */837#define DORQ_REG_NORM_CMHEAD_TX 0x17004c838/* [RW 3] The number of simultaneous outstanding requests to Context Fetch839 Interface. */840#define DORQ_REG_OUTST_REQ 0x17003c841#define DORQ_REG_PF_USAGE_CNT 0x1701d0842#define DORQ_REG_REGN 0x170038843/* [R 4] Current value of response A counter credit. Initial credit is844 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd845 register. */846#define DORQ_REG_RSPA_CRD_CNT 0x1700ac847/* [R 4] Current value of response B counter credit. Initial credit is848 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd849 register. */850#define DORQ_REG_RSPB_CRD_CNT 0x1700b0851/* [RW 4] The initial credit at the Doorbell Response Interface. The write852 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The853 read reads this written value. */854#define DORQ_REG_RSP_INIT_CRD 0x170048855#define DORQ_REG_RSPB_CRD_CNT 0x1700b0856#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0857#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4858#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4859#define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4860#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8861/* [RW 10] VF type validation mask value */862#define DORQ_REG_VF_TYPE_MASK_0 0x170218863/* [RW 17] VF type validation Min MCID value */864#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8865/* [RW 17] VF type validation Max MCID value */866#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298867/* [RW 10] VF type validation comp value */868#define DORQ_REG_VF_TYPE_VALUE_0 0x170258869#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340870 871extern const u32 dmae_reg_go_c[];872 873/* [RW 4] Initial activity counter value on the load request; when the874 shortcut is done. */875#define DORQ_REG_SHRT_ACT_CNT 0x170070876/* [RW 28] TCM Header when both ULP and TCP context is loaded. */877#define DORQ_REG_SHRT_CMHEAD 0x170054878#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)879#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)880#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)881#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)882#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)883#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)884#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)885#define DORQ_REG_VF_USAGE_CNT 0x170320886#define HC_REG_AGG_INT_0 0x108050887#define HC_REG_AGG_INT_1 0x108054888#define HC_REG_ATTN_BIT 0x108120889#define HC_REG_ATTN_IDX 0x108100890#define HC_REG_ATTN_MSG0_ADDR_L 0x108018891#define HC_REG_ATTN_MSG1_ADDR_L 0x108020892#define HC_REG_ATTN_NUM_P0 0x108038893#define HC_REG_ATTN_NUM_P1 0x10803c894#define HC_REG_COMMAND_REG 0x108180895#define HC_REG_CONFIG_0 0x108000896#define HC_REG_CONFIG_1 0x108004897#define HC_REG_FUNC_NUM_P0 0x1080ac898#define HC_REG_FUNC_NUM_P1 0x1080b0899/* [RW 3] Parity mask register #0 read/write */900#define HC_REG_HC_PRTY_MASK 0x1080a0901/* [R 3] Parity register #0 read */902#define HC_REG_HC_PRTY_STS 0x108094903/* [RC 3] Parity register #0 read clear */904#define HC_REG_HC_PRTY_STS_CLR 0x108098905#define HC_REG_INT_MASK 0x108108906#define HC_REG_LEADING_EDGE_0 0x108040907#define HC_REG_LEADING_EDGE_1 0x108048908#define HC_REG_MAIN_MEMORY 0x108800909#define HC_REG_MAIN_MEMORY_SIZE 152910#define HC_REG_P0_PROD_CONS 0x108200911#define HC_REG_P1_PROD_CONS 0x108400912#define HC_REG_PBA_COMMAND 0x108140913#define HC_REG_PCI_CONFIG_0 0x108010914#define HC_REG_PCI_CONFIG_1 0x108014915#define HC_REG_STATISTIC_COUNTERS 0x109000916#define HC_REG_TRAILING_EDGE_0 0x108044917#define HC_REG_TRAILING_EDGE_1 0x10804c918#define HC_REG_UC_RAM_ADDR_0 0x108028919#define HC_REG_UC_RAM_ADDR_1 0x108030920#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068921#define HC_REG_VQID_0 0x108008922#define HC_REG_VQID_1 0x10800c923#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)924#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)925#define IGU_REG_ATTENTION_ACK_BITS 0x130108926/* [R 4] Debug: attn_fsm */927#define IGU_REG_ATTN_FSM 0x130054928#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c929#define IGU_REG_ATTN_MSG_ADDR_L 0x130120930/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;931 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but932 * write done didn't receive. */933#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030934#define IGU_REG_BLOCK_CONFIGURATION 0x130000935#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124936#define IGU_REG_COMMAND_REG_CTRL 0x13012c937/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit938 * is clear. The bits in this registers are set and clear via the producer939 * command. Data valid only in addresses 0-4. all the rest are zero. */940#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200941/* [R 5] Debug: ctrl_fsm */942#define IGU_REG_CTRL_FSM 0x130064943/* [R 1] data available for error memory. If this bit is clear do not red944 * from error_handling_memory. */945#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130946/* [RW 11] Parity mask register #0 read/write */947#define IGU_REG_IGU_PRTY_MASK 0x1300a8948/* [R 11] Parity register #0 read */949#define IGU_REG_IGU_PRTY_STS 0x13009c950/* [RC 11] Parity register #0 read clear */951#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0952/* [R 4] Debug: int_handle_fsm */953#define IGU_REG_INT_HANDLE_FSM 0x130050954#define IGU_REG_LEADING_EDGE_LATCH 0x130134955/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.956 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF957 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */958#define IGU_REG_MAPPING_MEMORY 0x131000959#define IGU_REG_MAPPING_MEMORY_SIZE 136960#define IGU_REG_PBA_STATUS_LSB 0x130138961#define IGU_REG_PBA_STATUS_MSB 0x13013c962#define IGU_REG_PCI_PF_MSI_EN 0x130140963#define IGU_REG_PCI_PF_MSIX_EN 0x130144964#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148965/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no966 * pending; 1 = pending. Pendings means interrupt was asserted; and write967 * done was not received. Data valid only in addresses 0-4. all the rest are968 * zero. */969#define IGU_REG_PENDING_BITS_STATUS 0x130300970#define IGU_REG_PF_CONFIGURATION 0x130154971/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping972 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default973 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;974 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode975 * - In backward compatible mode; for non default SB; each even line in the976 * memory holds the U producer and each odd line hold the C producer. The977 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The978 * last 20 producers are for the DSB for each PF. each PF has five segments979 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;980 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */981#define IGU_REG_PROD_CONS_MEMORY 0x132000982/* [R 3] Debug: pxp_arb_fsm */983#define IGU_REG_PXP_ARB_FSM 0x130068984/* [RW 6] Write one for each bit will reset the appropriate memory. When the985 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping986 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3987 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */988#define IGU_REG_RESET_MEMORIES 0x130158989/* [R 4] Debug: sb_ctrl_fsm */990#define IGU_REG_SB_CTRL_FSM 0x13004c991#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c992#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160993#define IGU_REG_SB_MASK_LSB 0x130164994#define IGU_REG_SB_MASK_MSB 0x130168995/* [RW 16] Number of command that were dropped without causing an interrupt996 * due to: read access for WO BAR address; or write access for RO BAR997 * address or any access for reserved address or PCI function error is set998 * and address is not MSIX; PBA or cleanup */999#define IGU_REG_SILENT_DROP 0x13016c1000/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -1001 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per1002 * PF; 68-71 number of ATTN messages per PF */1003#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x1308001004/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a1005 * timer mask command arrives. Value must be bigger than 100. */1006#define IGU_REG_TIMER_MASKING_VALUE 0x13003c1007#define IGU_REG_TRAILING_EDGE_LATCH 0x1301041008#define IGU_REG_VF_CONFIGURATION 0x1301701009/* [WB_R 32] Each bit represent write done pending bits status for that SB1010 * (MSI/MSIX message was sent and write done was not received yet). 0 =1011 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */1012#define IGU_REG_WRITE_DONE_PENDING 0x1304801013#define MCP_A_REG_MCPR_SCRATCH 0x3a00001014#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c1015#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c1016#define MCP_REG_MCPR_GP_INPUTS 0x800c01017#define MCP_REG_MCPR_GP_OENABLE 0x800c81018#define MCP_REG_MCPR_GP_OUTPUTS 0x800c41019#define MCP_REG_MCPR_IMC_COMMAND 0x859001020#define MCP_REG_MCPR_IMC_DATAREG0 0x859201021#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x859041022#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c1023#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x864241024#define MCP_REG_MCPR_NVM_ADDR 0x8640c1025#define MCP_REG_MCPR_NVM_CFG4 0x8642c1026#define MCP_REG_MCPR_NVM_COMMAND 0x864001027#define MCP_REG_MCPR_NVM_READ 0x864101028#define MCP_REG_MCPR_NVM_SW_ARB 0x864201029#define MCP_REG_MCPR_NVM_WRITE 0x864081030#define MCP_REG_MCPR_SCRATCH 0xa00001031#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)1032#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)1033/* [R 32] read first 32 bit after inversion of function 0. mapped as1034 follows: [0] NIG attention for function0; [1] NIG attention for1035 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;1036 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]1037 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE1038 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;1039 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]1040 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB1041 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw1042 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity1043 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw1044 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF1045 Parity error; [31] PBF Hw interrupt; */1046#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c1047#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa4301048/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]1049 NIG attention for function0; [1] NIG attention for function1; [2] GPIO11050 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;1051 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]1052 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event1053 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP1054 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for1055 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]1056 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC1057 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw1058 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI1059 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw1060 interrupt; */1061#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa4341062/* [R 32] read second 32 bit after inversion of function 0. mapped as1063 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM1064 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw1065 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity1066 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw1067 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]1068 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;1069 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw1070 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM1071 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI1072 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM1073 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw1074 interrupt; */1075#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa4381076#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c1077/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]1078 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;1079 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;1080 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]1081 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]1082 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity1083 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux1084 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;1085 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;1086 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;1087 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;1088 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */1089#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa4401090/* [R 32] read third 32 bit after inversion of function 0. mapped as1091 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity1092 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]1093 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw1094 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity1095 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)1096 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]1097 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]1098 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]1099 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW1100 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_31101 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General1102 attn1; */1103#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa4441104#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa4481105/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]1106 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP1107 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient1108 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity1109 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw1110 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]1111 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]1112 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW1113 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_31114 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_11115 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW1116 timers attn_4 func1; [30] General attn0; [31] General attn1; */1117#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c1118/* [R 32] read fourth 32 bit after inversion of function 0. mapped as1119 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]1120 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;1121 [7] General attn9; [8] General attn10; [9] General attn11; [10] General1122 attn12; [11] General attn13; [12] General attn14; [13] General attn15;1123 [14] General attn16; [15] General attn17; [16] General attn18; [17]1124 General attn19; [18] General attn20; [19] General attn21; [20] Main power1125 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN1126 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC1127 Latched timeout attention; [27] GRC Latched reserved access attention;1128 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP1129 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */1130#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa4501131#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa4541132/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]1133 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;1134 [4] General attn6; [5] General attn7; [6] General attn8; [7] General1135 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]1136 General attn13; [12] General attn14; [13] General attn15; [14] General1137 attn16; [15] General attn17; [16] General attn18; [17] General attn19;1138 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]1139 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]1140 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout1141 attention; [27] GRC Latched reserved access attention; [28] MCP Latched1142 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched1143 ump_tx_parity; [31] MCP Latched scpad_parity; */1144#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa4581145/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as1146 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC1147 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]1148 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */1149#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa7001150/* [W 14] write to this register results with the clear of the latched1151 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in1152 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP1153 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears1154 GRC Latched reserved access attention; one in d7 clears Latched1155 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears1156 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both1157 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears1158 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read1159 from this register return zero */1160#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c1161/* [RW 32] first 32b for enabling the output for function 0 output0. mapped1162 as follows: [0] NIG attention for function0; [1] NIG attention for1163 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function1164 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]1165 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event1166 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP1167 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]1168 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X1169 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;1170 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]1171 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]1172 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]1173 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */1174#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c1175#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c1176#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c1177#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c1178#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc1179#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc1180#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc1181/* [RW 32] first 32b for enabling the output for function 1 output0. mapped1182 as follows: [0] NIG attention for function0; [1] NIG attention for1183 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function1184 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]1185 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event1186 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP1187 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]1188 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X1189 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;1190 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]1191 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]1192 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]1193 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */1194#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c1195#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c1196#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c1197#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c1198#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c1199#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c1200#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c1201/* [RW 32] first 32b for enabling the output for close the gate nig. mapped1202 as follows: [0] NIG attention for function0; [1] NIG attention for1203 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function1204 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]1205 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event1206 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP1207 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]1208 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X1209 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;1210 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]1211 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]1212 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]1213 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */1214#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec1215#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c1216/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped1217 as follows: [0] NIG attention for function0; [1] NIG attention for1218 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function1219 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]1220 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event1221 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP1222 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]1223 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X1224 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;1225 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]1226 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]1227 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]1228 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */1229#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc1230#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c1231/* [RW 32] second 32b for enabling the output for function 0 output0. mapped1232 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM1233 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw1234 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity1235 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw1236 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]1237 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;1238 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw1239 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM1240 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI1241 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM1242 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw1243 interrupt; */1244#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa0701245#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa0801246/* [RW 32] second 32b for enabling the output for function 1 output0. mapped1247 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM1248 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw1249 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity1250 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw1251 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]1252 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;1253 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw1254 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM1255 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI1256 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM1257 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw1258 interrupt; */1259#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa1101260#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa1201261/* [RW 32] second 32b for enabling the output for close the gate nig. mapped1262 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM1263 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw1264 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity1265 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw1266 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]1267 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;1268 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw1269 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM1270 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI1271 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM1272 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw1273 interrupt; */1274#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f01275#define MISC_REG_AEU_ENABLE2_NIG_1 0xa1901276/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped1277 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM1278 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw1279 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity1280 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw1281 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]1282 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;1283 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw1284 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM1285 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI1286 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM1287 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw1288 interrupt; */1289#define MISC_REG_AEU_ENABLE2_PXP_0 0xa1001290#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a01291/* [RW 32] third 32b for enabling the output for function 0 output0. mapped1292 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP1293 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;1294 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw1295 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity1296 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)1297 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]1298 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]1299 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]1300 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW1301 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_31302 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General1303 attn1; */1304#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa0741305#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa0841306/* [RW 32] third 32b for enabling the output for function 1 output0. mapped1307 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP1308 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;1309 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw1310 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity1311 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)1312 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]1313 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]1314 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]1315 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW1316 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_31317 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General1318 attn1; */1319#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa1141320#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa1241321/* [RW 32] third 32b for enabling the output for close the gate nig. mapped1322 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP1323 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;1324 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw1325 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity1326 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)1327 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]1328 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]1329 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]1330 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW1331 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_31332 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General1333 attn1; */1334#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f41335#define MISC_REG_AEU_ENABLE3_NIG_1 0xa1941336/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped1337 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP1338 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;1339 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw1340 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity1341 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)1342 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]1343 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]1344 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]1345 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW1346 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_31347 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General1348 attn1; */1349#define MISC_REG_AEU_ENABLE3_PXP_0 0xa1041350#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a41351/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped1352 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]1353 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;1354 [7] General attn9; [8] General attn10; [9] General attn11; [10] General1355 attn12; [11] General attn13; [12] General attn14; [13] General attn15;1356 [14] General attn16; [15] General attn17; [16] General attn18; [17]1357 General attn19; [18] General attn20; [19] General attn21; [20] Main power1358 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN1359 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC1360 Latched timeout attention; [27] GRC Latched reserved access attention;1361 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP1362 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */1363#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa0781364#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa0981365#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b81366#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c81367#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d81368#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e81369/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped1370 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]1371 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;1372 [7] General attn9; [8] General attn10; [9] General attn11; [10] General1373 attn12; [11] General attn13; [12] General attn14; [13] General attn15;1374 [14] General attn16; [15] General attn17; [16] General attn18; [17]1375 General attn19; [18] General attn20; [19] General attn21; [20] Main power1376 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN1377 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC1378 Latched timeout attention; [27] GRC Latched reserved access attention;1379 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP1380 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */1381#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa1181382#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa1381383#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa1581384#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa1681385#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa1781386#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa1881387/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped1388 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]1389 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;1390 [7] General attn9; [8] General attn10; [9] General attn11; [10] General1391 attn12; [11] General attn13; [12] General attn14; [13] General attn15;1392 [14] General attn16; [15] General attn17; [16] General attn18; [17]1393 General attn19; [18] General attn20; [19] General attn21; [20] Main power1394 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN1395 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC1396 Latched timeout attention; [27] GRC Latched reserved access attention;1397 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP1398 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */1399#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f81400#define MISC_REG_AEU_ENABLE4_NIG_1 0xa1981401/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped1402 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]1403 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;1404 [7] General attn9; [8] General attn10; [9] General attn11; [10] General1405 attn12; [11] General attn13; [12] General attn14; [13] General attn15;1406 [14] General attn16; [15] General attn17; [16] General attn18; [17]1407 General attn19; [18] General attn20; [19] General attn21; [20] Main power1408 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN1409 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC1410 Latched timeout attention; [27] GRC Latched reserved access attention;1411 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP1412 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */1413#define MISC_REG_AEU_ENABLE4_PXP_0 0xa1081414#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a81415/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped1416 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC1417 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]1418 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat11419 * parity; [31-10] Reserved; */1420#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa6881421/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped1422 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC1423 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]1424 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat11425 * parity; [31-10] Reserved; */1426#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b01427/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu1428 128 bit vector */1429#define MISC_REG_AEU_GENERAL_ATTN_0 0xa0001430#define MISC_REG_AEU_GENERAL_ATTN_1 0xa0041431#define MISC_REG_AEU_GENERAL_ATTN_10 0xa0281432#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c1433#define MISC_REG_AEU_GENERAL_ATTN_12 0xa0301434#define MISC_REG_AEU_GENERAL_ATTN_2 0xa0081435#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c1436#define MISC_REG_AEU_GENERAL_ATTN_4 0xa0101437#define MISC_REG_AEU_GENERAL_ATTN_5 0xa0141438#define MISC_REG_AEU_GENERAL_ATTN_6 0xa0181439#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c1440#define MISC_REG_AEU_GENERAL_ATTN_8 0xa0201441#define MISC_REG_AEU_GENERAL_ATTN_9 0xa0241442#define MISC_REG_AEU_GENERAL_MASK 0xa61c1443/* [RW 32] first 32b for inverting the input for function 0; for each bit:1444 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for1445 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;1446 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;1447 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event1448 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP1449 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]1450 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication1451 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS1452 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw1453 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM1454 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI1455 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */1456#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c1457#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c1458/* [RW 32] second 32b for inverting the input for function 0; for each bit:1459 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity1460 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw1461 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM1462 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw1463 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]1464 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity1465 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux1466 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;1467 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;1468 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;1469 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;1470 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */1471#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa2301472#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa2401473/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;1474 [9:8] = raserved. Zero = mask; one = unmask */1475#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa0601476#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa0641477/* [RW 1] If set a system kill occurred */1478#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa6101479/* [RW 32] Represent the status of the input vector to the AEU when a system1480 kill occurred. The register is reset in por reset. Mapped as follows: [0]1481 NIG attention for function0; [1] NIG attention for function1; [2] GPIO11482 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;1483 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]1484 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event1485 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP1486 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for1487 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]1488 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC1489 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw1490 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI1491 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw1492 interrupt; */1493#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa6001494#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa6041495#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa6081496#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c1497/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 11498 Port. */1499#define MISC_REG_BOND_ID 0xa4001500/* [R 16] These bits indicate the part number for the chip. */1501#define MISC_REG_CHIP_NUM 0xa4081502/* [R 4] These bits indicate the base revision of the chip. This value1503 starts at 0x0 for the A0 tape-out and increments by one for each1504 all-layer tape-out. */1505#define MISC_REG_CHIP_REV 0xa40c1506/* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-1507 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];1508 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */1509#define MISC_REG_CHIP_TYPE 0xac601510#define MISC_REG_CHIP_TYPE_57811_MASK (1<<1)1511#define MISC_REG_CPMU_LP_DR_ENABLE 0xa8581512/* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled1513 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk1514 * 25MHz. Reset on hard reset. */1515#define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c1516/* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI1517 * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */1518#define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a01519/* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that1520 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM1521 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that1522 * the FW command that all Queues are empty is disabled. When 0 indicates1523 * that the FW command that all Queues are empty is enabled. [2] - FW Early1524 * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early1525 * Exit command is disabled. When 0 indicates that the FW Early Exit command1526 * is enabled. This bit applicable only in the EXIT Events Mask registers.1527 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication1528 * is disabled. When 0 indicates that the PBF Request indication is enabled.1529 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF1530 * Request indication is disabled. When 0 indicates that the Tx Other Than1531 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 11532 * indicates that the RX EEE LPI Status indication is disabled. When 01533 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT1534 * Events Masks registers; this bit masks the falling edge detect of the LPI1535 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that1536 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause1537 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the1538 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY1539 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM1540 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication1541 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When1542 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 01543 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L11544 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE1545 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication1546 * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this1547 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]1548 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE1549 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI1550 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =11551 * indicates that the P0 EEE LPI REQ indication is disabled. When =01552 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE1553 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is1554 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is1555 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE1556 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ1557 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L11558 * REQ indication is disabled. When =0 indicates that the L1 indication is1559 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates1560 * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx1561 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status1562 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This1563 * bit is applicable only in the EXIT Events Masks registers. [17] - L11564 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling1565 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).1566 * When =0 indicates that the L1 Status Falling Edge Detect indication from1567 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in1568 * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */1569#define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa8801570/* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates1571 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain1572 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates1573 * that the FW command that all Queues are empty is disabled. When 01574 * indicates that the FW command that all Queues are empty is enabled. [2] -1575 * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW1576 * Early Exit command is disabled. When 0 indicates that the FW Early Exit1577 * command is enabled. This bit applicable only in the EXIT Events Mask1578 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request1579 * indication is disabled. When 0 indicates that the PBF Request indication1580 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other1581 * Than PBF Request indication is disabled. When 0 indicates that the Tx1582 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status1583 * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.1584 * When 0 indicates that the RX LPI Status indication is enabled. In the1585 * EXIT Events Masks registers; this bit masks the falling edge detect of1586 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 11587 * indicates that the Tx Pause indication is disabled. When 0 indicates that1588 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 11589 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates1590 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 11591 * indicates that the QM IDLE indication is disabled. When 0 indicates that1592 * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]1593 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for1594 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for1595 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L11596 * Status indication from the PCIE CORE is disabled. When 0 indicates that1597 * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the1598 * EXIT Events Masks registers; this bit masks the falling edge detect of1599 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When1600 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When1601 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P11602 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication1603 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is1604 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE1605 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ1606 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates1607 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that1608 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =11609 * indicates that the L1 REQ indication is disabled. When =0 indicates that1610 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.1611 * When =1 indicates that the RX EEE LPI Status Falling Edge Detect1612 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that1613 * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE1614 * LPI is on - off). This bit is applicable only in the EXIT Events Masks1615 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the1616 * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled1617 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge1618 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This1619 * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.1620 * Reset on hard reset. */1621#define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa8881622/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number1623 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only1624 * register. Reset on hard reset. */1625#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b81626/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number1627 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only1628 * register. Reset on hard reset. */1629#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc1630/* [RW 32] The following driver registers(1...16) represent 16 drivers and1631 32 clients. Each client can be controlled by one driver only. One in each1632 bit represent that this driver control the appropriate client (Ex: bit 51633 is set means this driver control client number 5). addr1 = set; addr0 =1634 clear; read from both addresses will give the same result = status. write1635 to address 1 will set a request to control all the clients that their1636 appropriate bit (in the write command) is set. if the client is free (the1637 appropriate bit in all the other drivers is clear) one will be written to1638 that driver register; if the client isn't free the bit will remain zero.1639 if the appropriate bit is set (the driver request to gain control on a1640 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW1641 interrupt will be asserted). write to address 0 will set a request to1642 free all the clients that their appropriate bit (in the write command) is1643 set. if the appropriate bit is clear (the driver request to free a client1644 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will1645 be asserted). */1646#define MISC_REG_DRIVER_CONTROL_1 0xa5101647#define MISC_REG_DRIVER_CONTROL_7 0xa3c81648/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 01649 only. */1650#define MISC_REG_E1HMF_MODE 0xa5f81651/* [R 1] Status of four port mode path swap input pin. */1652#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c1653/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -1654 the path_swap output is equal to 4 port mode path swap input pin; if it1655 is 1 - the path_swap output is equal to bit[1] of this register; [1] -1656 Overwrite value. If bit[0] of this register is 1 this is the value that1657 receives the path_swap output. Reset on Hard reset. */1658#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa7381659/* [R 1] Status of 4 port mode port swap input pin. */1660#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa7541661/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -1662 the port_swap output is equal to 4 port mode port swap input pin; if it1663 is 1 - the port_swap output is equal to bit[1] of this register; [1] -1664 Overwrite value. If bit[0] of this register is 1 this is the value that1665 receives the port_swap output. Reset on Hard reset. */1666#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa7341667/* [RW 32] Debug only: spare RW register reset by core reset */1668#define MISC_REG_GENERIC_CR_0 0xa4601669#define MISC_REG_GENERIC_CR_1 0xa4641670/* [RW 32] Debug only: spare RW register reset by por reset */1671#define MISC_REG_GENERIC_POR_1 0xa4741672/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to1673 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO1674 can not be configured as an output. Each output has its output enable in1675 the MCP register space; but this bit needs to be set to make use of that.1676 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When1677 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.1678 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change1679 the i/o to an output and will drive the TimeSync output. Bit[31:7]:1680 spare. Global register. Reset by hard reset. */1681#define MISC_REG_GEN_PURP_HWG 0xa9a01682/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of1683 these bits is written as a '1'; the corresponding SPIO bit will turn off1684 it's drivers and become an input. This is the reset state of all GPIO1685 pins. The read value of these bits will be a '1' if that last command1686 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).1687 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written1688 as a '1'; the corresponding GPIO bit will drive low. The read value of1689 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for1690 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;1691 SET When any of these bits is written as a '1'; the corresponding GPIO1692 bit will drive high (if it has that capability). The read value of these1693 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this1694 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;1695 RO; These bits indicate the read value of each of the eight GPIO pins.1696 This is the result value of the pin; not the drive value. Writing these1697 bits will have not effect. */1698#define MISC_REG_GPIO 0xa4901699/* [RW 8] These bits enable the GPIO_INTs to signals event to the1700 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]1701 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;1702 [7] p1_gpio_3; */1703#define MISC_REG_GPIO_EVENT_EN 0xa2bc1704/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a1705 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.1706 This will acknowledge an interrupt on the falling edge of corresponding1707 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;1708 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE1709 register. This will acknowledge an interrupt on the rising edge of1710 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;1711 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input1712 value. When the ~INT_STATE bit is set; this bit indicates the OLD value1713 of the pin such that if ~INT_STATE is set and this bit is '0'; then the1714 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit1715 is '1'; then the interrupt is due to a high to low edge (reset value 0).1716 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the1717 current GPIO interrupt state for each GPIO pin. This bit is cleared when1718 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is1719 set when the GPIO input does not match the current value in #OLD_VALUE1720 (reset value 0). */1721#define MISC_REG_GPIO_INT 0xa4941722/* [R 28] this field hold the last information that caused reserved1723 attention. bits [19:0] - address; [22:20] function; [23] reserved;1724 [27:24] the master that caused the attention - according to the following1725 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =1726 dbu; 8 = dmae */1727#define MISC_REG_GRC_RSV_ATTN 0xa3c01728/* [R 28] this field hold the last information that caused timeout1729 attention. bits [19:0] - address; [22:20] function; [23] reserved;1730 [27:24] the master that caused the attention - according to the following1731 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =1732 dbu; 8 = dmae */1733#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c41734/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any1735 access that does not finish within1736 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is1737 cleared; this timeout is disabled. If this timeout occurs; the GRC shall1738 assert it attention output. */1739#define MISC_REG_GRC_TIMEOUT_EN 0xa2801740/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of1741 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;1742 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl1743 (reset value 001) Charge pump current control; 111 for 720u; 011 for1744 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)1745 Global bias control; When bit 7 is high bias current will be 10 0gh; When1746 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]1747 Pll_observe (reset value 010) Bits to control observability. bit 10 is1748 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl1749 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V1750 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning1751 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted1752 internally). [14] reserved (reset value 0) Reset for VCO sequencer is1753 connected to RESET input directly. [15] capRetry_en (reset value 0)1754 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset1755 value 0) bit to continuously monitor vco freq (inverted). [17]1756 freqDetRestart_en (reset value 0) bit to enable restart when not freq1757 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable1758 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value1759 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]1760 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass1761 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value1762 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)1763 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to1764 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force1765 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to1766 restart. [27] capSelectM_en (reset value 0) bit to enable cap select1767 register bits. */1768#define MISC_REG_LCPLL_CTRL_1 0xa2a41769#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a81770/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR1771 * reset. */1772#define MISC_REG_LCPLL_E40_PWRDWN 0xaa741773/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */1774#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa781775/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR1776 * reset. */1777#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c1778/* [RW 4] Interrupt mask register #0 read/write */1779#define MISC_REG_MISC_INT_MASK 0xa3881780/* [RW 1] Parity mask register #0 read/write */1781#define MISC_REG_MISC_PRTY_MASK 0xa3981782/* [R 1] Parity register #0 read */1783#define MISC_REG_MISC_PRTY_STS 0xa38c1784/* [RC 1] Parity register #0 read clear */1785#define MISC_REG_MISC_PRTY_STS_CLR 0xa3901786#define MISC_REG_NIG_WOL_P0 0xa2701787#define MISC_REG_NIG_WOL_P1 0xa2741788/* [R 1] If set indicate that the pcie_rst_b was asserted without perst1789 assertion */1790#define MISC_REG_PCIE_HOT_RESET 0xa6181791/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.1792 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P11793 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P11794 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P21795 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P21796 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]1797 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]1798 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value1799 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]1800 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset1801 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value1802 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);1803 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]1804 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]1805 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]1806 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]1807 testa_en (reset value 0); */1808#define MISC_REG_PLL_STORM_CTRL_1 0xa2941809#define MISC_REG_PLL_STORM_CTRL_2 0xa2981810#define MISC_REG_PLL_STORM_CTRL_3 0xa29c1811#define MISC_REG_PLL_STORM_CTRL_4 0xa2a01812/* [R 1] Status of 4 port mode enable input pin. */1813#define MISC_REG_PORT4MODE_EN 0xa7501814/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -1815 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -1816 * the port4mode_en output is equal to bit[1] of this register; [1] -1817 * Overwrite value. If bit[0] of this register is 1 this is the value that1818 * receives the port4mode_en output . */1819#define MISC_REG_PORT4MODE_EN_OVWR 0xa7201820/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;1821 write/read zero = the specific block is in reset; addr 0-wr- the write1822 value will be written to the register; addr 1-set - one will be written1823 to all the bits that have the value of one in the data written (bits that1824 have the value of zero will not be change) ; addr 2-clear - zero will be1825 written to all the bits that have the value of one in the data written1826 (bits that have the value of zero will not be change); addr 3-ignore;1827 read ignore from all addr except addr 00; inside order of the bits is:1828 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;1829 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]1830 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;1831 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]1832 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]1833 rst_pxp_rq_rd_wr; 31:17] reserved */1834#define MISC_REG_RESET_REG_1 0xa5801835#define MISC_REG_RESET_REG_2 0xa5901836/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is1837 shared with the driver resides */1838#define MISC_REG_SHARED_MEM_ADDR 0xa2b41839/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';1840 the corresponding SPIO bit will turn off it's drivers and become an1841 input. This is the reset state of all SPIO pins. The read value of these1842 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this1843 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits1844 is written as a '1'; the corresponding SPIO bit will drive low. The read1845 value of these bits will be a '1' if that last command (#SET; #CLR; or1846#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of1847 these bits is written as a '1'; the corresponding SPIO bit will drive1848 high (if it has that capability). The read value of these bits will be a1849 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.1850 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of1851 each of the eight SPIO pins. This is the result value of the pin; not the1852 drive value. Writing these bits will have not effect. Each 8 bits field1853 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply1854 from VAUX. (This is an output pin only; the FLOAT field is not applicable1855 for this pin); [1] VAUX Disable; when pulsed low; disables supply form1856 VAUX. (This is an output pin only; FLOAT field is not applicable for this1857 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to1858 select VAUX supply. (This is an output pin only; it is not controlled by1859 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT1860 field is not applicable for this pin; only the VALUE fields is relevant -1861 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]1862 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP1863 device ID select; read by UMP firmware. */1864#define MISC_REG_SPIO 0xa4fc1865/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.1866 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;1867 [7:0] reserved */1868#define MISC_REG_SPIO_EVENT_EN 0xa2b81869/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the1870 corresponding bit in the #OLD_VALUE register. This will acknowledge an1871 interrupt on the falling edge of corresponding SPIO input (reset value1872 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit1873 in the #OLD_VALUE register. This will acknowledge an interrupt on the1874 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE1875 RO; These bits indicate the old value of the SPIO input value. When the1876 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such1877 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due1878 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the1879 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE1880 RO; These bits indicate the current SPIO interrupt state for each SPIO1881 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR1882 command bit is written. This bit is set when the SPIO input does not1883 match the current value in #OLD_VALUE (reset value 0). */1884#define MISC_REG_SPIO_INT 0xa5001885/* [RW 32] reload value for counter 4 if reload; the value will be reload if1886 the counter reached zero and the reload bit1887 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */1888#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc1889/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses1890 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -1891 timer 8 */1892#define MISC_REG_SW_TIMER_VAL 0xa5c01893/* [R 1] Status of two port mode path swap input pin. */1894#define MISC_REG_TWO_PORT_PATH_SWAP 0xa7581895/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the1896 path_swap output is equal to 2 port mode path swap input pin; if it is 11897 - the path_swap output is equal to bit[1] of this register; [1] -1898 Overwrite value. If bit[0] of this register is 1 this is the value that1899 receives the path_swap output. Reset on Hard reset. */1900#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c1901/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are1902 loaded; 0-prepare; -unprepare */1903#define MISC_REG_UNPREPARED 0xa4241904#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)1905#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)1906#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)1907#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)1908#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)1909/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or1910 * not it is the recipient of the message on the MDIO interface. The value1911 * is compared to the value on ctrl_md_devad. Drives output1912 * misc_xgxs0_phy_addr. Global register. */1913#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc1914#define MISC_REG_WC0_RESET 0xac301915/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system1916 side. This should be less than or equal to phy_port_mode; if some of the1917 ports are not used. This enables reduction of frequency on the core side.1918 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -1919 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap1920 input for the XMAC_MP core; and should be changed only while reset is1921 held low. Reset on Hard reset. */1922#define MISC_REG_XMAC_CORE_PORT_MODE 0xa9641923/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp1924 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;1925 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the1926 XMAC_MP core; and should be changed only while reset is held low. Reset1927 on Hard reset. */1928#define MISC_REG_XMAC_PHY_PORT_MODE 0xa9601929/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.1930 * Reads from this register will clear bits 31:0. */1931#define MSTAT_REG_RX_STAT_GR64_LO 0x2001932/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits1933 * 31:0. Reads from this register will clear bits 31:0. */1934#define MSTAT_REG_TX_STAT_GTXPOK_LO 01935#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)1936#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)1937#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)1938#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)1939#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)1940#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)1941#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)1942#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)1943#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)1944#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)1945#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)1946/* [RW 1] Input enable for RX_BMAC0 IF */1947#define NIG_REG_BMAC0_IN_EN 0x100ac1948/* [RW 1] output enable for TX_BMAC0 IF */1949#define NIG_REG_BMAC0_OUT_EN 0x100e01950/* [RW 1] output enable for TX BMAC pause port 0 IF */1951#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x101101952/* [RW 1] output enable for RX_BMAC0_REGS IF */1953#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e81954/* [RW 1] output enable for RX BRB1 port0 IF */1955#define NIG_REG_BRB0_OUT_EN 0x100f81956/* [RW 1] Input enable for TX BRB1 pause port 0 IF */1957#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c41958/* [RW 1] output enable for RX BRB1 port1 IF */1959#define NIG_REG_BRB1_OUT_EN 0x100fc1960/* [RW 1] Input enable for TX BRB1 pause port 1 IF */1961#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c81962/* [RW 1] output enable for RX BRB1 LP IF */1963#define NIG_REG_BRB_LB_OUT_EN 0x101001964/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]1965 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;1966 72:73]-vnic_num; 81:74]-sideband_info */1967#define NIG_REG_DEBUG_PACKET_LB 0x108001968/* [RW 1] Input enable for TX Debug packet */1969#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc1970/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all1971 packets from PBFare not forwarded to the MAC and just deleted from FIFO.1972 First packet may be deleted from the middle. And last packet will be1973 always deleted till the end. */1974#define NIG_REG_EGRESS_DRAIN0_MODE 0x100601975/* [RW 1] Output enable to EMAC0 */1976#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x101201977/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs1978 to emac for port0; other way to bmac for port0 */1979#define NIG_REG_EGRESS_EMAC0_PORT 0x100581980/* [RW 1] Input enable for TX PBF user packet port0 IF */1981#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc1982/* [RW 1] Input enable for TX PBF user packet port1 IF */1983#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d01984/* [RW 1] Input enable for TX UMP management packet port0 IF */1985#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d41986/* [RW 1] Input enable for RX_EMAC0 IF */1987#define NIG_REG_EMAC0_IN_EN 0x100a41988/* [RW 1] output enable for TX EMAC pause port 0 IF */1989#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x101181990/* [R 1] status from emac0. This bit is set when MDINT from either the1991 EXT_MDINT pin or from the Copper PHY is driven low. This condition must1992 be cleared in the attached PHY device that is driving the MINT pin. */1993#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x104941994/* [WB 48] This address space contains BMAC0 registers. The BMAC registers1995 are described in appendix A. In order to access the BMAC0 registers; the1996 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be1997 added to each BMAC register offset */1998#define NIG_REG_INGRESS_BMAC0_MEM 0x10c001999/* [WB 48] This address space contains BMAC1 registers. The BMAC registers2000 are described in appendix A. In order to access the BMAC0 registers; the2001 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be2002 added to each BMAC register offset */2003#define NIG_REG_INGRESS_BMAC1_MEM 0x110002004/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */2005#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e02006/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data2007 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */2008#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e42009/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch2010 logic for interrupts must be used. Enable per bit of interrupt of2011 ~latch_status.latch_status */2012#define NIG_REG_LATCH_BC_0 0x162102013/* [RW 27] Latch for each interrupt from Unicore.b[0]2014 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;2015 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;2016 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;2017 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;2018 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;2019 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;2020 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;2021 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;2022 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;2023 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;2024 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;2025 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */2026#define NIG_REG_LATCH_STATUS_0 0x180002027/* [RW 1] led 10g for port 0 */2028#define NIG_REG_LED_10G_P0 0x103202029/* [RW 1] led 10g for port 1 */2030#define NIG_REG_LED_10G_P1 0x103242031/* [RW 1] Port0: This bit is set to enable the use of the2032 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field2033 defined below. If this bit is cleared; then the blink rate will be about2034 8Hz. */2035#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x103182036/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for2037 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field2038 is reset to 0x080; giving a default blink period of approximately 8Hz. */2039#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x103102040/* [RW 1] Port0: If set along with the2041 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p02042 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED2043 bit; the Traffic LED will blink with the blink rate specified in2044 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and2045 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p02046 fields. */2047#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x103082048/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The2049 Traffic LED will then be controlled via bit ~nig_registers_2050 led_control_traffic_p0.led_control_traffic_p0 and bit2051 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */2052#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f82053/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;2054 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also2055 set; the LED will blink with blink rate specified in2056 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and2057 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p02058 fields. */2059#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x103002060/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;2061 9-11PHY7; 12 MAC4; 13-15 PHY10; */2062#define NIG_REG_LED_MODE_P0 0x102f02063/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-2064 tsdm enable; b2- usdm enable */2065#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x160702066#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x160742067/* [RW 1] SAFC enable for port0. This register may get 1 only when2068 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same2069 port */2070#define NIG_REG_LLFC_ENABLE_0 0x162082071#define NIG_REG_LLFC_ENABLE_1 0x1620c2072/* [RW 16] classes are high-priority for port0 */2073#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x160582074#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c2075/* [RW 16] classes are low-priority for port0 */2076#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x160602077#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x160642078/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */2079#define NIG_REG_LLFC_OUT_EN_0 0x160c82080#define NIG_REG_LLFC_OUT_EN_1 0x160cc2081#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c2082#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x101542083#define NIG_REG_LLH0_BRB1_DRV_MASK 0x102442084#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x160482085/* [RW 1] send to BRB1 if no match on any of RMP rules. */2086#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c2087/* [RW 2] Determine the classification participants. 0: no classification.1:2088 classification upon VLAN id. 2: classification upon MAC address. 3:2089 classification upon both VLAN id & MAC addr. */2090#define NIG_REG_LLH0_CLS_TYPE 0x160802091/* [RW 32] cm header for llh0 */2092#define NIG_REG_LLH0_CM_HEADER 0x1007c2093#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc2094#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c02095/* [RW 16] destination TCP address 1. The LLH will look for this address in2096 all incoming packets. */2097#define NIG_REG_LLH0_DEST_TCP_0 0x102202098/* [RW 16] destination UDP address 1 The LLH will look for this address in2099 all incoming packets. */2100#define NIG_REG_LLH0_DEST_UDP_0 0x102142101#define NIG_REG_LLH0_ERROR_MASK 0x1008c2102/* [RW 8] event id for llh0 */2103#define NIG_REG_LLH0_EVENT_ID 0x100842104#define NIG_REG_LLH0_FUNC_EN 0x160fc2105#define NIG_REG_LLH0_FUNC_MEM 0x161802106#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x161402107#define NIG_REG_LLH0_FUNC_VLAN_ID 0x161002108/* [RW 1] Determine the IP version to look for in2109 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */2110#define NIG_REG_LLH0_IPV4_IPV6_0 0x102082111/* [RW 1] t bit for llh0 */2112#define NIG_REG_LLH0_T_BIT 0x100742113/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */2114#define NIG_REG_LLH0_VLAN_ID_0 0x1022c2115/* [RW 8] init credit counter for port0 in LLH */2116#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x105542117#define NIG_REG_LLH0_XCM_MASK 0x101302118#define NIG_REG_LLH1_BRB1_DRV_MASK 0x102482119/* [RW 1] send to BRB1 if no match on any of RMP rules. */2120#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc2121/* [RW 2] Determine the classification participants. 0: no classification.1:2122 classification upon VLAN id. 2: classification upon MAC address. 3:2123 classification upon both VLAN id & MAC addr. */2124#define NIG_REG_LLH1_CLS_TYPE 0x160842125/* [RW 32] cm header for llh1 */2126#define NIG_REG_LLH1_CM_HEADER 0x100802127#define NIG_REG_LLH1_ERROR_MASK 0x100902128/* [RW 8] event id for llh1 */2129#define NIG_REG_LLH1_EVENT_ID 0x100882130#define NIG_REG_LLH1_FUNC_EN 0x161042131#define NIG_REG_LLH1_FUNC_MEM 0x161c02132#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x161602133#define NIG_REG_LLH1_FUNC_MEM_SIZE 162134/* [RW 1] When this bit is set; the LLH will classify the packet before2135 * sending it to the BRB or calculating WoL on it. This bit controls port 12136 * only. The legacy llh_multi_function_mode bit controls port 0. */2137#define NIG_REG_LLH1_MF_MODE 0x186142138/* [RW 8] init credit counter for port1 in LLH */2139#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x105642140#define NIG_REG_LLH1_XCM_MASK 0x101342141/* [RW 1] When this bit is set; the LLH will expect all packets to be with2142 e1hov */2143#define NIG_REG_LLH_E1HOV_MODE 0x160d82144/* [RW 16] Outer VLAN type identifier for multi-function mode. In non2145 * multi-function mode; it will hold the inner VLAN type. Typically 0x8100.2146 */2147#define NIG_REG_LLH_E1HOV_TYPE_1 0x160282148/* [RW 1] When this bit is set; the LLH will classify the packet before2149 sending it to the BRB or calculating WoL on it. */2150#define NIG_REG_LLH_MF_MODE 0x160242151#define NIG_REG_MASK_INTERRUPT_PORT0 0x103302152#define NIG_REG_MASK_INTERRUPT_PORT1 0x103342153/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */2154#define NIG_REG_NIG_EMAC0_EN 0x1003c2155/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */2156#define NIG_REG_NIG_EMAC1_EN 0x100402157/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the2158 EMAC0 to strip the CRC from the ingress packets. */2159#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x100442160/* [R 32] Interrupt register #0 read */2161#define NIG_REG_NIG_INT_STS_0 0x103b02162#define NIG_REG_NIG_INT_STS_1 0x103c02163/* [RC 32] Interrupt register #0 read clear */2164#define NIG_REG_NIG_INT_STS_CLR_0 0x103b42165/* [R 32] Legacy E1 and E1H location for parity error mask register. */2166#define NIG_REG_NIG_PRTY_MASK 0x103dc2167/* [RW 32] Parity mask register #0 read/write */2168#define NIG_REG_NIG_PRTY_MASK_0 0x183c82169#define NIG_REG_NIG_PRTY_MASK_1 0x183d82170/* [R 32] Legacy E1 and E1H location for parity error status register. */2171#define NIG_REG_NIG_PRTY_STS 0x103d02172/* [R 32] Parity register #0 read */2173#define NIG_REG_NIG_PRTY_STS_0 0x183bc2174#define NIG_REG_NIG_PRTY_STS_1 0x183cc2175/* [R 32] Legacy E1 and E1H location for parity error status clear register. */2176#define NIG_REG_NIG_PRTY_STS_CLR 0x103d42177/* [RC 32] Parity register #0 read clear */2178#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c02179#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d02180#define MCPR_IMC_COMMAND_ENABLE (1L<<31)2181#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 162182#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 282183#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 82184/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic2185 * Ethernet header. */2186#define NIG_REG_P0_HDRS_AFTER_BASIC 0x180382187/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in2188 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be2189 * disabled when this bit is set. */2190#define NIG_REG_P0_HWPFC_ENABLE 0x180782191#define NIG_REG_P0_LLH_FUNC_MEM2 0x184802192#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x184402193/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for2194 * the host. Bits [15:0] return the sequence ID of the packet. Bit 162195 * indicates the validity of the data in the buffer. Writing a 1 to bit 162196 * will clear the buffer.2197 */2198#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c2199/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2200 * the host. This location returns the lower 32 bits of timestamp value.2201 */2202#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x187542203/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2204 * the host. This location returns the upper 32 bits of timestamp value.2205 */2206#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x187582207/* [RW 11] Mask register for the various parameters used in determining PTP2208 * packet presence. Set each bit to 1 to mask out the particular parameter.2209 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of2210 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP2211 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC2212 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of2213 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable2214 * MAC DA 2. The reset default is set to mask out all parameters.2215 */2216#define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a02217/* [RW 14] Mask register for the rules used in detecting PTP packets. Set2218 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .2219 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP2220 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;2221 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC2222 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype2223 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset2224 * default is to mask out all of the rules. Note that rules 0-3 are for IPv42225 * packets only and require that the packet is IPv4 for the rules to match.2226 * Note that rules 4-7 are for IPv6 packets only and require that the packet2227 * is IPv6 for the rules to match.2228 */2229#define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a42230/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */2231#define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac2232/* [RW 1] Input enable for RX MAC interface. */2233#define NIG_REG_P0_MAC_IN_EN 0x185ac2234/* [RW 1] Output enable for TX MAC interface */2235#define NIG_REG_P0_MAC_OUT_EN 0x185b02236/* [RW 1] Output enable for TX PAUSE signal to the MAC. */2237#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b42238/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for2239 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the2240 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit2241 * priority field is extracted from the outer-most VLAN in receive packet.2242 * Only COS 0 and COS 1 are supported in E2. */2243#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x180542244/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits2245 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables2246 * V1 frame format in timesync event detection on RX side. Bit 2 enables V22247 * frame format in timesync event detection on RX side. Bit 3 enables2248 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event2249 * detection on TX side. Bit 5 enables V2 frame format in timesync event2250 * detection on TX side. Note that for HW to detect PTP packet and extract2251 * data from the packet, at least one of the version bits of that traffic2252 * direction has to be enabled.2253 */2254#define NIG_REG_P0_PTP_EN 0x187882255/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A2256 * priority is mapped to COS 0 when the corresponding mask bit is 1. More2257 * than one bit may be set; allowing multiple priorities to be mapped to one2258 * COS. */2259#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x180582260/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A2261 * priority is mapped to COS 1 when the corresponding mask bit is 1. More2262 * than one bit may be set; allowing multiple priorities to be mapped to one2263 * COS. */2264#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c2265/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A2266 * priority is mapped to COS 2 when the corresponding mask bit is 1. More2267 * than one bit may be set; allowing multiple priorities to be mapped to one2268 * COS. */2269#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b02270/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A2271 * priority is mapped to COS 3 when the corresponding mask bit is 1. More2272 * than one bit may be set; allowing multiple priorities to be mapped to one2273 * COS. */2274#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b42275/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A2276 * priority is mapped to COS 4 when the corresponding mask bit is 1. More2277 * than one bit may be set; allowing multiple priorities to be mapped to one2278 * COS. */2279#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b82280/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A2281 * priority is mapped to COS 5 when the corresponding mask bit is 1. More2282 * than one bit may be set; allowing multiple priorities to be mapped to one2283 * COS. */2284#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc2285/* [R 1] RX FIFO for receiving data from MAC is empty. */2286/* [RW 15] Specify which of the credit registers the client is to be mapped2287 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For2288 * clients that are not subject to WFQ credit blocking - their2289 * specifications here are not used. */2290#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f02291/* [RW 32] Specify which of the credit registers the client is to be mapped2292 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are2293 * for client 0; bits [35:32] are for client 8. For clients that are not2294 * subject to WFQ credit blocking - their specifications here are not used.2295 * This is a new register (with 2_) added in E3 B0 to accommodate the 92296 * input clients to ETS arbiter. The reset default is set for management and2297 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to2298 * use credit registers 0-5 respectively (0x543210876). Note that credit2299 * registers can not be shared between clients. */2300#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186882301/* [RW 4] Specify which of the credit registers the client is to be mapped2302 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are2303 * for client 0; bits [35:32] are for client 8. For clients that are not2304 * subject to WFQ credit blocking - their specifications here are not used.2305 * This is a new register (with 2_) added in E3 B0 to accommodate the 92306 * input clients to ETS arbiter. The reset default is set for management and2307 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to2308 * use credit registers 0-5 respectively (0x543210876). Note that credit2309 * registers can not be shared between clients. */2310#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c2311/* [RW 5] Specify whether the client competes directly in the strict2312 * priority arbiter. The bits are mapped according to client ID (client IDs2313 * are defined in tx_arb_priority_client). Default value is set to enable2314 * strict priorities for clients 0-2 -- management and debug traffic. */2315#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e82316/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The2317 * bits are mapped according to client ID (client IDs are defined in2318 * tx_arb_priority_client). Default value is 0 for not using WFQ credit2319 * blocking. */2320#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec2321/* [RW 32] Specify the upper bound that credit register 0 is allowed to2322 * reach. */2323#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c2324#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x181102325#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x181142326#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x181182327#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c2328#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a02329#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a42330#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a82331#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac2332/* [RW 32] Specify the weight (in bytes) to be added to credit register 02333 * when it is time to increment. */2334#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f82335#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc2336#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x181002337#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x181042338#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x181082339#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x186902340#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x186942341#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x186982342#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c2343/* [RW 12] Specify the number of strict priority arbitration slots between2344 * two round-robin arbitration slots to avoid starvation. A value of 0 means2345 * no strict priority cycles - the strict priority with anti-starvation2346 * arbiter becomes a round-robin arbiter. */2347#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f42348/* [RW 15] Specify the client number to be assigned to each priority of the2349 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]2350 * are for priority 0 client; bits [14:12] are for priority 4 client. The2351 * clients are assigned the following IDs: 0-management; 1-debug traffic2352 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS12353 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)2354 * for management at priority 0; debug traffic at priorities 1 and 2; COS02355 * traffic at priority 3; and COS1 traffic at priority 4. */2356#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e42357/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic2358 * Ethernet header. */2359#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c2360#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c02361#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460a2362/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for2363 * the host. Bits [15:0] return the sequence ID of the packet. Bit 162364 * indicates the validity of the data in the buffer. Writing a 1 to bit 162365 * will clear the buffer.2366 */2367#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x187742368/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2369 * the host. This location returns the lower 32 bits of timestamp value.2370 */2371#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c2372/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2373 * the host. This location returns the upper 32 bits of timestamp value.2374 */2375#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x187702376/* [RW 11] Mask register for the various parameters used in determining PTP2377 * packet presence. Set each bit to 1 to mask out the particular parameter.2378 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of2379 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP2380 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC2381 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of2382 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable2383 * MAC DA 2. The reset default is set to mask out all parameters.2384 */2385#define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c82386/* [RW 14] Mask register for the rules used in detecting PTP packets. Set2387 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .2388 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP2389 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;2390 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC2391 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype2392 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset2393 * default is to mask out all of the rules. Note that rules 0-3 are for IPv42394 * packets only and require that the packet is IPv4 for the rules to match.2395 * Note that rules 4-7 are for IPv6 packets only and require that the packet2396 * is IPv6 for the rules to match.2397 */2398#define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc2399/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */2400#define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d42401/* [RW 32] Specify the client number to be assigned to each priority of the2402 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit2403 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 02404 * client; bits [35-32] are for priority 8 client. The clients are assigned2405 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug2406 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;2407 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is2408 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to2409 * accommodate the 9 input clients to ETS arbiter. */2410#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x186802411/* [RW 4] Specify the client number to be assigned to each priority of the2412 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit2413 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 02414 * client; bits [35-32] are for priority 8 client. The clients are assigned2415 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug2416 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;2417 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is2418 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to2419 * accommodate the 9 input clients to ETS arbiter. */2420#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x186842421/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP2422 * packets to BRB LB interface to forward the packet to the host. All2423 * packets from MCP are forwarded to the network when this bit is cleared -2424 * regardless of the configured destination in tx_mng_destination register.2425 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter2426 * for BRB LB interface is bypassed and PBF LB traffic is always selected to2427 * send to BRB LB.2428 */2429#define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f42430#define NIG_REG_P1_HWPFC_ENABLE 0x181d02431#define NIG_REG_P1_MAC_IN_EN 0x185c02432/* [RW 1] Output enable for TX MAC interface */2433#define NIG_REG_P1_MAC_OUT_EN 0x185c42434/* [RW 1] Output enable for TX PAUSE signal to the MAC. */2435#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c82436/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for2437 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the2438 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit2439 * priority field is extracted from the outer-most VLAN in receive packet.2440 * Only COS 0 and COS 1 are supported in E2. */2441#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a82442/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits2443 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables2444 * V1 frame format in timesync event detection on RX side. Bit 2 enables V22445 * frame format in timesync event detection on RX side. Bit 3 enables2446 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event2447 * detection on TX side. Bit 5 enables V2 frame format in timesync event2448 * detection on TX side. Note that for HW to detect PTP packet and extract2449 * data from the packet, at least one of the version bits of that traffic2450 * direction has to be enabled.2451 */2452#define NIG_REG_P1_PTP_EN 0x187b02453/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A2454 * priority is mapped to COS 0 when the corresponding mask bit is 1. More2455 * than one bit may be set; allowing multiple priorities to be mapped to one2456 * COS. */2457#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac2458/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A2459 * priority is mapped to COS 1 when the corresponding mask bit is 1. More2460 * than one bit may be set; allowing multiple priorities to be mapped to one2461 * COS. */2462#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b02463/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A2464 * priority is mapped to COS 2 when the corresponding mask bit is 1. More2465 * than one bit may be set; allowing multiple priorities to be mapped to one2466 * COS. */2467#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f82468/* [R 1] RX FIFO for receiving data from MAC is empty. */2469#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c2470/* [R 1] TLLH FIFO is empty. */2471#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x183382472/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for2473 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 162474 * indicates the validity of the data in the buffer. Bit 17 indicates that2475 * the sequence ID is valid and it is waiting for the TX timestamp value.2476 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)2477 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.2478 */2479#define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e02480/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2481 * MCP. This location returns the lower 32 bits of timestamp value.2482 */2483#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d82484/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2485 * MCP. This location returns the upper 32 bits of timestamp value.2486 */2487#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc2488/* [RW 11] Mask register for the various parameters used in determining PTP2489 * packet presence. Set each bit to 1 to mask out the particular parameter.2490 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of2491 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP2492 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC2493 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of2494 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable2495 * MAC DA 2. The reset default is set to mask out all parameters.2496 */2497#define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f02498/* [RW 14] Mask register for the rules used in detecting PTP packets. Set2499 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .2500 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP2501 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;2502 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC2503 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype2504 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset2505 * default is to mask out all of the rules.2506 */2507#define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f42508/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for2509 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 162510 * indicates the validity of the data in the buffer. Bit 17 indicates that2511 * the sequence ID is valid and it is waiting for the TX timestamp value.2512 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)2513 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.2514 */2515#define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec2516/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2517 * MCP. This location returns the lower 32 bits of timestamp value.2518 */2519#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e42520/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for2521 * MCP. This location returns the upper 32 bits of timestamp value.2522 */2523#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e82524/* [RW 11] Mask register for the various parameters used in determining PTP2525 * packet presence. Set each bit to 1 to mask out the particular parameter.2526 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of2527 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP2528 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC2529 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of2530 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable2531 * MAC DA 2. The reset default is set to mask out all parameters.2532 */2533#define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f82534/* [RW 14] Mask register for the rules used in detecting PTP packets. Set2535 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .2536 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP2537 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;2538 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC2539 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype2540 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset2541 * default is to mask out all of the rules.2542 */2543#define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc2544/* [RW 32] Specify which of the credit registers the client is to be mapped2545 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are2546 * for client 0; bits [35:32] are for client 8. For clients that are not2547 * subject to WFQ credit blocking - their specifications here are not used.2548 * This is a new register (with 2_) added in E3 B0 to accommodate the 92549 * input clients to ETS arbiter. The reset default is set for management and2550 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to2551 * use credit registers 0-5 respectively (0x543210876). Note that credit2552 * registers can not be shared between clients. Note also that there are2553 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only2554 * credit registers 0-5 are valid. This register should be configured2555 * appropriately before enabling WFQ. */2556#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e82557/* [RW 4] Specify which of the credit registers the client is to be mapped2558 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are2559 * for client 0; bits [35:32] are for client 8. For clients that are not2560 * subject to WFQ credit blocking - their specifications here are not used.2561 * This is a new register (with 2_) added in E3 B0 to accommodate the 92562 * input clients to ETS arbiter. The reset default is set for management and2563 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to2564 * use credit registers 0-5 respectively (0x543210876). Note that credit2565 * registers can not be shared between clients. Note also that there are2566 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only2567 * credit registers 0-5 are valid. This register should be configured2568 * appropriately before enabling WFQ. */2569#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec2570/* [RW 9] Specify whether the client competes directly in the strict2571 * priority arbiter. The bits are mapped according to client ID (client IDs2572 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic2573 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS12574 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.2575 * Default value is set to enable strict priorities for all clients. */2576#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x182342577/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The2578 * bits are mapped according to client ID (client IDs are defined in2579 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;2580 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS22581 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is2582 * 0 for not using WFQ credit blocking. */2583#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x182382584#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x182582585#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c2586#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x182602587#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x182642588#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x182682589#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f42590/* [RW 32] Specify the weight (in bytes) to be added to credit register 02591 * when it is time to increment. */2592#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x182442593#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x182482594#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c2595#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x182502596#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x182542597#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f02598/* [RW 12] Specify the number of strict priority arbitration slots between2599 two round-robin arbitration slots to avoid starvation. A value of 0 means2600 no strict priority cycles - the strict priority with anti-starvation2601 arbiter becomes a round-robin arbiter. */2602#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x182402603/* [RW 32] Specify the client number to be assigned to each priority of the2604 strict priority arbiter. This register specifies bits 31:0 of the 36-bit2605 value. Priority 0 is the highest priority. Bits [3:0] are for priority 02606 client; bits [35-32] are for priority 8 client. The clients are assigned2607 the following IDs: 0-management; 1-debug traffic from this port; 2-debug2608 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;2609 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is2610 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to2611 accommodate the 9 input clients to ETS arbiter. Note that this register2612 is the same as the one for port 0, except that port 1 only has COS 0-22613 traffic. There is no traffic for COS 3-5 of port 1. */2614#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e02615/* [RW 4] Specify the client number to be assigned to each priority of the2616 strict priority arbiter. This register specifies bits 35:32 of the 36-bit2617 value. Priority 0 is the highest priority. Bits [3:0] are for priority 02618 client; bits [35-32] are for priority 8 client. The clients are assigned2619 the following IDs: 0-management; 1-debug traffic from this port; 2-debug2620 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;2621 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is2622 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to2623 accommodate the 9 input clients to ETS arbiter. Note that this register2624 is the same as the one for port 0, except that port 1 only has COS 0-22625 traffic. There is no traffic for COS 3-5 of port 1. */2626#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e42627/* [R 1] TX FIFO for transmitting data to MAC is empty. */2628#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x185942629/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP2630 * packets to BRB LB interface to forward the packet to the host. All2631 * packets from MCP are forwarded to the network when this bit is cleared -2632 * regardless of the configured destination in tx_mng_destination register.2633 */2634#define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f82635/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets2636 forwarded to the host. */2637#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b82638/* [RW 32] Specify the upper bound that credit register 0 is allowed to2639 * reach. */2640/* [RW 1] Pause enable for port0. This register may get 1 only when2641 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same2642 port */2643#define NIG_REG_PAUSE_ENABLE_0 0x160c02644#define NIG_REG_PAUSE_ENABLE_1 0x160c42645/* [RW 1] Input enable for RX PBF LP IF */2646#define NIG_REG_PBF_LB_IN_EN 0x100b42647/* [RW 1] Value of this register will be transmitted to port swap when2648 ~nig_registers_strap_override.strap_override =1 */2649#define NIG_REG_PORT_SWAP 0x103942650/* [RW 1] PPP enable for port0. This register may get 1 only when2651 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the2652 * same port */2653#define NIG_REG_PPP_ENABLE_0 0x160b02654#define NIG_REG_PPP_ENABLE_1 0x160b42655/* [RW 1] output enable for RX parser descriptor IF */2656#define NIG_REG_PRS_EOP_OUT_EN 0x101042657/* [RW 1] Input enable for RX parser request IF */2658#define NIG_REG_PRS_REQ_IN_EN 0x100b82659/* [RW 5] control to serdes - CL45 DEVAD */2660#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x103702661/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */2662#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c2663/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */2664#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x103742665/* [R 1] status from serdes0 that inputs to interrupt logic of link status */2666#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x105782667/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure2668 for port0 */2669#define NIG_REG_STAT0_BRB_DISCARD 0x105f02670/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure2671 for port0 */2672#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f82673/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that2674 between 1024 and 1522 bytes for port0 */2675#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x107502676/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that2677 between 1523 bytes and above for port0 */2678#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x107602679/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure2680 for port1 */2681#define NIG_REG_STAT1_BRB_DISCARD 0x106282682/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that2683 between 1024 and 1522 bytes for port1 */2684#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a02685/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that2686 between 1523 bytes and above for port1 */2687#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b02688/* [WB_R 64] Rx statistics : User octets received for LP */2689#define NIG_REG_STAT2_BRB_OCTET 0x107e02690#define NIG_REG_STATUS_INTERRUPT_PORT0 0x103282691#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c2692/* [RW 1] port swap mux selection. If this register equal to 0 then port2693 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then2694 ort swap is equal to ~nig_registers_port_swap.port_swap */2695#define NIG_REG_STRAP_OVERRIDE 0x103982696/* [WB 64] Addresses for TimeSync related registers in the timesync2697 * generator sub-module.2698 */2699#define NIG_REG_TIMESYNC_GEN_REG 0x188002700/* [RW 1] output enable for RX_XCM0 IF */2701#define NIG_REG_XCM0_OUT_EN 0x100f02702/* [RW 1] output enable for RX_XCM1 IF */2703#define NIG_REG_XCM1_OUT_EN 0x100f42704/* [RW 1] control to xgxs - remote PHY in-band MDIO */2705#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x103482706/* [RW 5] control to xgxs - CL45 DEVAD */2707#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c2708/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */2709#define NIG_REG_XGXS0_CTRL_MD_ST 0x103382710/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */2711#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x103402712/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */2713#define NIG_REG_XGXS0_STATUS_LINK10G 0x106802714/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */2715#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x106842716/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */2717#define NIG_REG_XGXS_LANE_SEL_P0 0x102e82718/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */2719#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e02720#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)2721#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)2722#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)2723#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)2724#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 182725/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */2726#define PBF_REG_COS0_UPPER_BOUND 0x15c05c2727/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter2728 * of port 0. */2729#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc2730/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter2731 * of port 1. */2732#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e42733/* [RW 31] The weight of COS0 in the ETS command arbiter. */2734#define PBF_REG_COS0_WEIGHT 0x15c0542735/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */2736#define PBF_REG_COS0_WEIGHT_P0 0x15c2a82737/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */2738#define PBF_REG_COS0_WEIGHT_P1 0x15c2c02739/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */2740#define PBF_REG_COS1_UPPER_BOUND 0x15c0602741/* [RW 31] The weight of COS1 in the ETS command arbiter. */2742#define PBF_REG_COS1_WEIGHT 0x15c0582743/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */2744#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac2745/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */2746#define PBF_REG_COS1_WEIGHT_P1 0x15c2c42747/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */2748#define PBF_REG_COS2_WEIGHT_P0 0x15c2b02749/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */2750#define PBF_REG_COS2_WEIGHT_P1 0x15c2c82751/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */2752#define PBF_REG_COS3_WEIGHT_P0 0x15c2b42753/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */2754#define PBF_REG_COS4_WEIGHT_P0 0x15c2b82755/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */2756#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc2757/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte2758 * lines. */2759#define PBF_REG_CREDIT_LB_Q 0x1403382760/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte2761 * lines. */2762#define PBF_REG_CREDIT_Q0 0x14033c2763/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte2764 * lines. */2765#define PBF_REG_CREDIT_Q1 0x1403402766/* [RW 1] Disable processing further tasks from port 0 (after ending the2767 current task in process). */2768#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c2769/* [RW 1] Disable processing further tasks from port 1 (after ending the2770 current task in process). */2771#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x1400602772/* [RW 1] Disable processing further tasks from port 4 (after ending the2773 current task in process). */2774#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c2775#define PBF_REG_DISABLE_PF 0x1402e82776#define PBF_REG_DISABLE_VF 0x1402ec2777/* [RW 18] For port 0: For each client that is subject to WFQ (the2778 * corresponding bit is 1); indicates to which of the credit registers this2779 * client is mapped. For clients which are not credit blocked; their mapping2780 * is dont care. */2781#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c2882782/* [RW 9] For port 1: For each client that is subject to WFQ (the2783 * corresponding bit is 1); indicates to which of the credit registers this2784 * client is mapped. For clients which are not credit blocked; their mapping2785 * is dont care. */2786#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c2787/* [RW 6] For port 0: Bit per client to indicate if the client competes in2788 * the strict priority arbiter directly (corresponding bit = 1); or first2789 * goes to the RR arbiter (corresponding bit = 0); and then competes in the2790 * lowest priority in the strict-priority arbiter. */2791#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c2782792/* [RW 3] For port 1: Bit per client to indicate if the client competes in2793 * the strict priority arbiter directly (corresponding bit = 1); or first2794 * goes to the RR arbiter (corresponding bit = 0); and then competes in the2795 * lowest priority in the strict-priority arbiter. */2796#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c2797/* [RW 6] For port 0: Bit per client to indicate if the client is subject to2798 * WFQ credit blocking (corresponding bit = 1). */2799#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c2802800/* [RW 3] For port 0: Bit per client to indicate if the client is subject to2801 * WFQ credit blocking (corresponding bit = 1). */2802#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c2842803/* [RW 16] For port 0: The number of strict priority arbitration slots2804 * between 2 RR arbitration slots. A value of 0 means no strict priority2805 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR2806 * arbiter. */2807#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a02808/* [RW 16] For port 1: The number of strict priority arbitration slots2809 * between 2 RR arbitration slots. A value of 0 means no strict priority2810 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR2811 * arbiter. */2812#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a42813/* [RW 18] For port 0: Indicates which client is connected to each priority2814 * in the strict-priority arbiter. Priority 0 is the highest priority, and2815 * priority 5 is the lowest; to which the RR output is connected to (this is2816 * not configurable). */2817#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c2702818/* [RW 9] For port 1: Indicates which client is connected to each priority2819 * in the strict-priority arbiter. Priority 0 is the highest priority, and2820 * priority 5 is the lowest; to which the RR output is connected to (this is2821 * not configurable). */2822#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c2742823/* [RW 1] Indicates that ETS is performed between the COSes in the command2824 * arbiter. If reset strict priority w/ anti-starvation will be performed2825 * w/o WFQ. */2826#define PBF_REG_ETS_ENABLED 0x15c0502827/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic2828 * Ethernet header. */2829#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a82830/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */2831#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b82832/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest2833 * priority in the command arbiter. */2834#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c2835#define PBF_REG_IF_ENABLE_REG 0x1400442836/* [RW 1] Init bit. When set the initial credits are copied to the credit2837 registers (except the port credits). Should be set and then reset after2838 the configuration of the block has ended. */2839#define PBF_REG_INIT 0x1400002840/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte2841 * lines. */2842#define PBF_REG_INIT_CRD_LB_Q 0x15c2482843/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte2844 * lines. */2845#define PBF_REG_INIT_CRD_Q0 0x15c2302846/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte2847 * lines. */2848#define PBF_REG_INIT_CRD_Q1 0x15c2342849/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is2850 copied to the credit register. Should be set and then reset after the2851 configuration of the port has ended. */2852#define PBF_REG_INIT_P0 0x1400042853/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is2854 copied to the credit register. Should be set and then reset after the2855 configuration of the port has ended. */2856#define PBF_REG_INIT_P1 0x1400082857/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is2858 copied to the credit register. Should be set and then reset after the2859 configuration of the port has ended. */2860#define PBF_REG_INIT_P4 0x14000c2861/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for2862 * the LB queue. Reset upon init. */2863#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x1403542864/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for2865 * queue 0. Reset upon init. */2866#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x1403582867/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for2868 * queue 1. Reset upon init. */2869#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c2870/* [RW 1] Enable for mac interface 0. */2871#define PBF_REG_MAC_IF0_ENABLE 0x1400302872/* [RW 1] Enable for mac interface 1. */2873#define PBF_REG_MAC_IF1_ENABLE 0x1400342874/* [RW 1] Enable for the loopback interface. */2875#define PBF_REG_MAC_LB_ENABLE 0x1400402876/* [RW 6] Bit-map indicating which headers must appear in the packet */2877#define PBF_REG_MUST_HAVE_HDRS 0x15c0c42878/* [RW 16] The number of strict priority arbitration slots between 2 RR2879 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the2880 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */2881#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c0642882/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause2883 not suppoterd. */2884#define PBF_REG_P0_ARB_THRSH 0x1400e42885/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */2886#define PBF_REG_P0_CREDIT 0x1402002887/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte2888 lines. */2889#define PBF_REG_P0_INIT_CRD 0x1400d02890/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for2891 * port 0. Reset upon init. */2892#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x1403082893/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */2894#define PBF_REG_P0_PAUSE_ENABLE 0x1400142895/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */2896#define PBF_REG_P0_TASK_CNT 0x1402042897/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines2898 * freed from the task queue of port 0. Reset upon init. */2899#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f02900/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */2901#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc2902/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port2903 * buffers in 16 byte lines. */2904#define PBF_REG_P1_CREDIT 0x1402082905/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port2906 * buffers in 16 byte lines. */2907#define PBF_REG_P1_INIT_CRD 0x1400d42908/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for2909 * port 1. Reset upon init. */2910#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c2911/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */2912#define PBF_REG_P1_TASK_CNT 0x14020c2913/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines2914 * freed from the task queue of port 1. Reset upon init. */2915#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f42916/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */2917#define PBF_REG_P1_TQ_OCCUPANCY 0x1403002918/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */2919#define PBF_REG_P4_CREDIT 0x1402102920/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte2921 lines. */2922#define PBF_REG_P4_INIT_CRD 0x1400e02923/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for2924 * port 4. Reset upon init. */2925#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x1403102926/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */2927#define PBF_REG_P4_TASK_CNT 0x1402142928/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines2929 * freed from the task queue of port 4. Reset upon init. */2930#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f82931/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */2932#define PBF_REG_P4_TQ_OCCUPANCY 0x1403042933/* [RW 5] Interrupt mask register #0 read/write */2934#define PBF_REG_PBF_INT_MASK 0x1401d42935/* [R 5] Interrupt register #0 read */2936#define PBF_REG_PBF_INT_STS 0x1401c82937/* [RW 20] Parity mask register #0 read/write */2938#define PBF_REG_PBF_PRTY_MASK 0x1401e42939/* [R 28] Parity register #0 read */2940#define PBF_REG_PBF_PRTY_STS 0x1401d82941/* [RC 20] Parity register #0 read clear */2942#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc2943/* [RW 16] The Ethernet type value for L2 tag 0 */2944#define PBF_REG_TAG_ETHERTYPE_0 0x15c0902945/* [RW 4] The length of the info field for L2 tag 0. The length is between2946 * 2B and 14B; in 2B granularity */2947#define PBF_REG_TAG_LEN_0 0x15c09c2948/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task2949 * queue. Reset upon init. */2950#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c2951/* [R 32] Cyclic counter for number of 8 byte lines freed from the task2952 * queue 0. Reset upon init. */2953#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x1403902954/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.2955 * Reset upon init. */2956#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x1403942957/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB2958 * queue. */2959#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a82960/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */2961#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac2962/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */2963#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b02964/* [RW 16] One of 8 values that should be compared to type in Ethernet2965 * parsing. If there is a match; the field after Ethernet is the first VLAN.2966 * Reset value is 0x8100 which is the standard VLAN type. Note that when2967 * checking second VLAN; type is compared only to 0x8100.2968 */2969#define PBF_REG_VLAN_TYPE_0 0x15c06c2970/* [RW 2] Interrupt mask register #0 read/write */2971#define PB_REG_PB_INT_MASK 0x282972/* [R 2] Interrupt register #0 read */2973#define PB_REG_PB_INT_STS 0x1c2974/* [RW 4] Parity mask register #0 read/write */2975#define PB_REG_PB_PRTY_MASK 0x382976/* [R 4] Parity register #0 read */2977#define PB_REG_PB_PRTY_STS 0x2c2978/* [RC 4] Parity register #0 read clear */2979#define PB_REG_PB_PRTY_STS_CLR 0x302980#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)2981#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)2982#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)2983#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)2984#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)2985#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)2986#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)2987#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)2988#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)2989/* [R 8] Config space A attention dirty bits. Each bit indicates that the2990 * corresponding PF generates config space A attention. Set by PXP. Reset by2991 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits2992 * from both paths. */2993#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x90102994/* [R 8] Config space B attention dirty bits. Each bit indicates that the2995 * corresponding PF generates config space B attention. Set by PXP. Reset by2996 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits2997 * from both paths. */2998#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x90142999/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 13000 * - enable. */3001#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x91943002/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;3003 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */3004#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c3005/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 13006 * - enable. */3007#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c3008/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */3009#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x91003010/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */3011#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x91083012/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */3013#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x91103014/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */3015#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac3016/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates3017 * that the FLR register of the corresponding PF was set. Set by PXP. Reset3018 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits3019 * from both paths. */3020#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x90283021/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 13022 * to a bit in this register in order to clear the corresponding bit in3023 * flr_request_pf_7_0 register. Note: register contains bits from both3024 * paths. */3025#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x94183026/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit3027 * indicates that the FLR register of the corresponding VF was set. Set by3028 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */3029#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x90243030/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit3031 * indicates that the FLR register of the corresponding VF was set. Set by3032 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */3033#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x90183034/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit3035 * indicates that the FLR register of the corresponding VF was set. Set by3036 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */3037#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c3038/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit3039 * indicates that the FLR register of the corresponding VF was set. Set by3040 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */3041#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x90203042/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit3043 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target3044 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW3045 * arrived with a correctable error. Bit 3 - Configuration RW arrived with3046 * an uncorrectable error. Bit 4 - Completion with Configuration Request3047 * Retry Status. Bit 5 - Expansion ROM access received with a write request.3048 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and3049 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;3050 * and pcie_rx_last not asserted. */3051#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x90683052#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c3053#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x94303054#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x94343055#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x94383056/* [W 7] Writing 1 to each bit in this register clears a corresponding error3057 * details register and enables logging new error details. Bit 0 - clears3058 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears3059 * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS3060 * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_323061 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -3062 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears3063 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 63064 * - clears TCPL_IN_TWO_RCBS_DETAILS. */3065#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c3066 3067/* [R 9] Interrupt register #0 read */3068#define PGLUE_B_REG_PGLUE_B_INT_STS 0x92983069/* [RC 9] Interrupt register #0 read clear */3070#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c3071/* [RW 2] Parity mask register #0 read/write */3072#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b43073/* [R 2] Parity register #0 read */3074#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a83075/* [RC 2] Parity register #0 read clear */3076#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac3077/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -3078 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion3079 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -3080 * completer abort. 3 - Illegal value for this field. [12] valid - indicates3081 * if there was a completion error since the last time this register was3082 * cleared. */3083#define PGLUE_B_REG_RX_ERR_DETAILS 0x90803084/* [R 18] Details of first ATS Translation Completion request received with3085 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -3086 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -3087 * unsupported request. 2 - completer abort. 3 - Illegal value for this3088 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a3089 * completion error since the last time this register was cleared. */3090#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x90843091/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to3092 * a bit in this register in order to clear the corresponding bit in3093 * shadow_bme_pf_7_0 register. MCP should never use this unless a3094 * work-around is needed. Note: register contains bits from both paths. */3095#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x94583096/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the3097 * VF enable register of the corresponding PF is written to 0 and was3098 * previously 1. Set by PXP. Reset by MCP writing 1 to3099 * sr_iov_disabled_request_clr. Note: register contains bits from both3100 * paths. */3101#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x90303102/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read3103 * completion did not return yet. 1 - tag is unused. Same functionality as3104 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */3105#define PGLUE_B_REG_TAGS_63_32 0x92443106/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 13107 * - enable. */3108#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x91703109/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */3110#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c43111/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */3112#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc3113/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */3114#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d43115/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */3116#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a03117/* [R 32] Address [31:0] of first read request not submitted due to error */3118#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x90983119/* [R 32] Address [63:32] of first read request not submitted due to error */3120#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c3121/* [R 31] Details of first read request not submitted due to error. [4:0]3122 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.3123 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -3124 * VFID. */3125#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a03126/* [R 26] Details of first read request not submitted due to error. [15:0]3127 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -3128 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;3129 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent3130 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -3131 * indicates if there was a request not submitted due to error since the3132 * last time this register was cleared. */3133#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a43134/* [R 32] Address [31:0] of first write request not submitted due to error */3135#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x90883136/* [R 32] Address [63:32] of first write request not submitted due to error */3137#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c3138/* [R 31] Details of first write request not submitted due to error. [4:0]3139 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]3140 * - VFID. */3141#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x90903142/* [R 26] Details of first write request not submitted due to error. [15:0]3143 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -3144 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;3145 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent3146 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -3147 * indicates if there was a request not submitted due to error since the3148 * last time this register was cleared. */3149#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x90943150/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;3151 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any3152 * value (Byte resolution address). */3153#define PGLUE_B_REG_USDM_INB_INT_A_0 0x91283154#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c3155#define PGLUE_B_REG_USDM_INB_INT_A_2 0x91303156#define PGLUE_B_REG_USDM_INB_INT_A_3 0x91343157#define PGLUE_B_REG_USDM_INB_INT_A_4 0x91383158#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c3159#define PGLUE_B_REG_USDM_INB_INT_A_6 0x91403160/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 13161 * - enable. */3162#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c3163/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 13164 * - enable. */3165#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x91803166/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 13167 * - enable. */3168#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x91843169/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */3170#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d83171/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */3172#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e03173/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */3174#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e83175/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */3176#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a43177/* [R 26] Details of first target VF request accessing VF GRC space that3178 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.3179 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a3180 * request accessing VF GRC space that failed permission check since the3181 * last time this register was cleared. Permission checks are: function3182 * permission; R/W permission; address range permission. */3183#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x92343184/* [R 31] Details of first target VF request with length violation (too many3185 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).3186 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]3187 * valid - indicates if there was a request with length violation since the3188 * last time this register was cleared. Length violations: length of more3189 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and3190 * length is more than 1 DW. */3191#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x92303192/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates3193 * that there was a completion with uncorrectable error for the3194 * corresponding PF. Set by PXP. Reset by MCP writing 1 to3195 * was_error_pf_7_0_clr. */3196#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c3197/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 13198 * to a bit in this register in order to clear the corresponding bit in3199 * flr_request_pf_7_0 register. */3200#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x94703201/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit3202 * indicates that there was a completion with uncorrectable error for the3203 * corresponding VF. Set by PXP. Reset by MCP writing 1 to3204 * was_error_vf_127_96_clr. */3205#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x90783206/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP3207 * writes 1 to a bit in this register in order to clear the corresponding3208 * bit in was_error_vf_127_96 register. */3209#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x94743210/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit3211 * indicates that there was a completion with uncorrectable error for the3212 * corresponding VF. Set by PXP. Reset by MCP writing 1 to3213 * was_error_vf_31_0_clr. */3214#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c3215/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes3216 * 1 to a bit in this register in order to clear the corresponding bit in3217 * was_error_vf_31_0 register. */3218#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x94783219/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit3220 * indicates that there was a completion with uncorrectable error for the3221 * corresponding VF. Set by PXP. Reset by MCP writing 1 to3222 * was_error_vf_63_32_clr. */3223#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x90703224/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes3225 * 1 to a bit in this register in order to clear the corresponding bit in3226 * was_error_vf_63_32 register. */3227#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c3228/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit3229 * indicates that there was a completion with uncorrectable error for the3230 * corresponding VF. Set by PXP. Reset by MCP writing 1 to3231 * was_error_vf_95_64_clr. */3232#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x90743233/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes3234 * 1 to a bit in this register in order to clear the corresponding bit in3235 * was_error_vf_95_64 register. */3236#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x94803237/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 13238 * - enable. */3239#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x91883240/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */3241#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec3242/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */3243#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f43244/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */3245#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc3246/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */3247#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a83248#define PRS_REG_A_PRSU_20 0x401343249/* [R 8] debug only: CFC load request current credit. Transaction based. */3250#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x401643251/* [R 8] debug only: CFC search request current credit. Transaction based. */3252#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x401683253/* [RW 6] The initial credit for the search message to the CFC interface.3254 Credit is transaction based. */3255#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c3256/* [RW 24] CID for port 0 if no match */3257#define PRS_REG_CID_PORT_0 0x400fc3258/* [RW 32] The CM header for flush message where 'load existed' bit in CFC3259 load response is reset and packet type is 0. Used in packet start message3260 to TCM. */3261#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc3262#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e03263#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e43264#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e83265#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec3266#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f03267/* [RW 32] The CM header for flush message where 'load existed' bit in CFC3268 load response is set and packet type is 0. Used in packet start message3269 to TCM. */3270#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc3271#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c03272#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c43273#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c83274#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc3275#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d03276/* [RW 32] The CM header for a match and packet type 1 for loopback port.3277 Used in packet start message to TCM. */3278#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c3279#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a03280#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a43281#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a83282/* [RW 32] The CM header for a match and packet type 0. Used in packet start3283 message to TCM. */3284#define PRS_REG_CM_HDR_TYPE_0 0x400783285#define PRS_REG_CM_HDR_TYPE_1 0x4007c3286#define PRS_REG_CM_HDR_TYPE_2 0x400803287#define PRS_REG_CM_HDR_TYPE_3 0x400843288#define PRS_REG_CM_HDR_TYPE_4 0x400883289/* [RW 32] The CM header in case there was not a match on the connection */3290#define PRS_REG_CM_NO_MATCH_HDR 0x400b83291/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */3292#define PRS_REG_E1HOV_MODE 0x401c83293/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet3294 start message to TCM. */3295#define PRS_REG_EVENT_ID_1 0x400543296#define PRS_REG_EVENT_ID_2 0x400583297#define PRS_REG_EVENT_ID_3 0x4005c3298/* [RW 16] The Ethernet type value for FCoE */3299#define PRS_REG_FCOE_TYPE 0x401d03300/* [RW 8] Context region for flush packet with packet type 0. Used in CFC3301 load request message. */3302#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x400043303#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x400083304#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c3305#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x400103306#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x400143307#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x400183308#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c3309#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x400203310/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic3311 * Ethernet header. */3312#define PRS_REG_HDRS_AFTER_BASIC 0x402383313/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic3314 * Ethernet header for port 0 packets. */3315#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x402703316#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x402903317/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */3318#define PRS_REG_HDRS_AFTER_TAG_0 0x402483319/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for3320 * port 0 packets */3321#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x402803322#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a03323/* [RW 4] The increment value to send in the CFC load request message */3324#define PRS_REG_INC_VALUE 0x400483325/* [RW 6] Bit-map indicating which headers must appear in the packet */3326#define PRS_REG_MUST_HAVE_HDRS 0x402543327/* [RW 6] Bit-map indicating which headers must appear in the packet for3328 * port 0 packets */3329#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c3330#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac3331#define PRS_REG_NIC_MODE 0x401383332/* [RW 8] The 8-bit event ID for cases where there is no match on the3333 connection. Used in packet start message to TCM. */3334#define PRS_REG_NO_MATCH_EVENT_ID 0x400703335/* [ST 24] The number of input CFC flush packets */3336#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x401283337/* [ST 32] The number of cycles the Parser halted its operation since it3338 could not allocate the next serial number */3339#define PRS_REG_NUM_OF_DEAD_CYCLES 0x401303340/* [ST 24] The number of input packets */3341#define PRS_REG_NUM_OF_PACKETS 0x401243342/* [ST 24] The number of input transparent flush packets */3343#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c3344/* [RW 8] Context region for received Ethernet packet with a match and3345 packet type 0. Used in CFC load request message */3346#define PRS_REG_PACKET_REGIONS_TYPE_0 0x400283347#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c3348#define PRS_REG_PACKET_REGIONS_TYPE_2 0x400303349#define PRS_REG_PACKET_REGIONS_TYPE_3 0x400343350#define PRS_REG_PACKET_REGIONS_TYPE_4 0x400383351#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c3352#define PRS_REG_PACKET_REGIONS_TYPE_6 0x400403353#define PRS_REG_PACKET_REGIONS_TYPE_7 0x400443354/* [R 2] debug only: Number of pending requests for CAC on port 0. */3355#define PRS_REG_PENDING_BRB_CAC0_RQ 0x401743356/* [R 2] debug only: Number of pending requests for header parsing. */3357#define PRS_REG_PENDING_BRB_PRS_RQ 0x401703358/* [R 1] Interrupt register #0 read */3359#define PRS_REG_PRS_INT_STS 0x401883360/* [RW 8] Parity mask register #0 read/write */3361#define PRS_REG_PRS_PRTY_MASK 0x401a43362/* [R 8] Parity register #0 read */3363#define PRS_REG_PRS_PRTY_STS 0x401983364/* [RC 8] Parity register #0 read clear */3365#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c3366/* [RW 8] Context region for pure acknowledge packets. Used in CFC load3367 request message */3368#define PRS_REG_PURE_REGIONS 0x400243369/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this3370 serail number was released by SDM but cannot be used because a previous3371 serial number was not released. */3372#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x401543373/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this3374 serail number was released by SDM but cannot be used because a previous3375 serial number was not released. */3376#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x401583377/* [R 4] debug only: SRC current credit. Transaction based. */3378#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c3379/* [RW 16] The Ethernet type value for L2 tag 0 */3380#define PRS_REG_TAG_ETHERTYPE_0 0x401d43381/* [RW 4] The length of the info field for L2 tag 0. The length is between3382 * 2B and 14B; in 2B granularity */3383#define PRS_REG_TAG_LEN_0 0x4022c3384/* [R 8] debug only: TCM current credit. Cycle based. */3385#define PRS_REG_TCM_CURRENT_CREDIT 0x401603386/* [R 8] debug only: TSDM current credit. Transaction based. */3387#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c3388/* [RW 16] One of 8 values that should be compared to type in Ethernet3389 * parsing. If there is a match; the field after Ethernet is the first VLAN.3390 * Reset value is 0x8100 which is the standard VLAN type. Note that when3391 * checking second VLAN; type is compared only to 0x8100.3392 */3393#define PRS_REG_VLAN_TYPE_0 0x401a83394#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)3395#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)3396#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)3397#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)3398#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)3399#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)3400#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)3401/* [R 6] Debug only: Number of used entries in the data FIFO */3402#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c3403/* [R 7] Debug only: Number of used entries in the header FIFO */3404#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x1204783405#define PXP2_REG_PGL_ADDR_88_F0 0x1205343406/* [R 32] GRC address for configuration access to PCIE config address 0x88.3407 * any write to this PCIE address will cause a GRC write access to the3408 * address that's in t this register */3409#define PXP2_REG_PGL_ADDR_88_F1 0x1205443410#define PXP2_REG_PGL_ADDR_8C_F0 0x1205383411/* [R 32] GRC address for configuration access to PCIE config address 0x8c.3412 * any write to this PCIE address will cause a GRC write access to the3413 * address that's in t this register */3414#define PXP2_REG_PGL_ADDR_8C_F1 0x1205483415#define PXP2_REG_PGL_ADDR_90_F0 0x12053c3416/* [R 32] GRC address for configuration access to PCIE config address 0x90.3417 * any write to this PCIE address will cause a GRC write access to the3418 * address that's in t this register */3419#define PXP2_REG_PGL_ADDR_90_F1 0x12054c3420#define PXP2_REG_PGL_ADDR_94_F0 0x1205403421/* [R 32] GRC address for configuration access to PCIE config address 0x94.3422 * any write to this PCIE address will cause a GRC write access to the3423 * address that's in t this register */3424#define PXP2_REG_PGL_ADDR_94_F1 0x1205503425#define PXP2_REG_PGL_CONTROL0 0x1204903426#define PXP2_REG_PGL_CONTROL1 0x1205143427#define PXP2_REG_PGL_DEBUG 0x1205203428/* [RW 32] third dword data of expansion rom request. this register is3429 special. reading from it provides a vector outstanding read requests. if3430 a bit is zero it means that a read request on the corresponding tag did3431 not finish yet (not all completions have arrived for it) */3432#define PXP2_REG_PGL_EXP_ROM2 0x1208083433/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;3434 its[15:0]-address */3435#define PXP2_REG_PGL_INT_CSDM_0 0x1204f43436#define PXP2_REG_PGL_INT_CSDM_1 0x1204f83437#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc3438#define PXP2_REG_PGL_INT_CSDM_3 0x1205003439#define PXP2_REG_PGL_INT_CSDM_4 0x1205043440#define PXP2_REG_PGL_INT_CSDM_5 0x1205083441#define PXP2_REG_PGL_INT_CSDM_6 0x12050c3442#define PXP2_REG_PGL_INT_CSDM_7 0x1205103443/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;3444 its[15:0]-address */3445#define PXP2_REG_PGL_INT_TSDM_0 0x1204943446#define PXP2_REG_PGL_INT_TSDM_1 0x1204983447#define PXP2_REG_PGL_INT_TSDM_2 0x12049c3448#define PXP2_REG_PGL_INT_TSDM_3 0x1204a03449#define PXP2_REG_PGL_INT_TSDM_4 0x1204a43450#define PXP2_REG_PGL_INT_TSDM_5 0x1204a83451#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac3452#define PXP2_REG_PGL_INT_TSDM_7 0x1204b03453/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;3454 its[15:0]-address */3455#define PXP2_REG_PGL_INT_USDM_0 0x1204b43456#define PXP2_REG_PGL_INT_USDM_1 0x1204b83457#define PXP2_REG_PGL_INT_USDM_2 0x1204bc3458#define PXP2_REG_PGL_INT_USDM_3 0x1204c03459#define PXP2_REG_PGL_INT_USDM_4 0x1204c43460#define PXP2_REG_PGL_INT_USDM_5 0x1204c83461#define PXP2_REG_PGL_INT_USDM_6 0x1204cc3462#define PXP2_REG_PGL_INT_USDM_7 0x1204d03463/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;3464 its[15:0]-address */3465#define PXP2_REG_PGL_INT_XSDM_0 0x1204d43466#define PXP2_REG_PGL_INT_XSDM_1 0x1204d83467#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc3468#define PXP2_REG_PGL_INT_XSDM_3 0x1204e03469#define PXP2_REG_PGL_INT_XSDM_4 0x1204e43470#define PXP2_REG_PGL_INT_XSDM_5 0x1204e83471#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec3472#define PXP2_REG_PGL_INT_XSDM_7 0x1204f03473/* [RW 3] this field allows one function to pretend being another function3474 when accessing any BAR mapped resource within the device. the value of3475 the field is the number of the function that will be accessed3476 effectively. after software write to this bit it must read it in order to3477 know that the new value is updated */3478#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x1206743479#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x1206783480#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c3481#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x1206803482#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x1206843483#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x1206883484#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c3485#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x1206903486/* [R 1] this bit indicates that a read request was blocked because of3487 bus_master_en was deasserted */3488#define PXP2_REG_PGL_READ_BLOCKED 0x1205683489#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a83490/* [R 18] debug only */3491#define PXP2_REG_PGL_TXW_CDTS 0x12052c3492/* [R 1] this bit indicates that a write request was blocked because of3493 bus_master_en was deasserted */3494#define PXP2_REG_PGL_WRITE_BLOCKED 0x1205643495#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c03496#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e43497#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e83498#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c43499#define PXP2_REG_PSWRQ_BW_ADD28 0x1202283500#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c83501#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d43502#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d83503#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc3504#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e03505#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c3506#define PXP2_REG_PSWRQ_BW_L1 0x1202b03507#define PXP2_REG_PSWRQ_BW_L10 0x1202d43508#define PXP2_REG_PSWRQ_BW_L11 0x1202d83509#define PXP2_REG_PSWRQ_BW_L2 0x1202b43510#define PXP2_REG_PSWRQ_BW_L28 0x1203183511#define PXP2_REG_PSWRQ_BW_L3 0x1202b83512#define PXP2_REG_PSWRQ_BW_L6 0x1202c43513#define PXP2_REG_PSWRQ_BW_L7 0x1202c83514#define PXP2_REG_PSWRQ_BW_L8 0x1202cc3515#define PXP2_REG_PSWRQ_BW_L9 0x1202d03516#define PXP2_REG_PSWRQ_BW_RD 0x1203243517#define PXP2_REG_PSWRQ_BW_UB1 0x1202383518#define PXP2_REG_PSWRQ_BW_UB10 0x12025c3519#define PXP2_REG_PSWRQ_BW_UB11 0x1202603520#define PXP2_REG_PSWRQ_BW_UB2 0x12023c3521#define PXP2_REG_PSWRQ_BW_UB28 0x1202a03522#define PXP2_REG_PSWRQ_BW_UB3 0x1202403523#define PXP2_REG_PSWRQ_BW_UB6 0x12024c3524#define PXP2_REG_PSWRQ_BW_UB7 0x1202503525#define PXP2_REG_PSWRQ_BW_UB8 0x1202543526#define PXP2_REG_PSWRQ_BW_UB9 0x1202583527#define PXP2_REG_PSWRQ_BW_WR 0x1203283528#define PXP2_REG_PSWRQ_CDU0_L2P 0x1200003529#define PXP2_REG_PSWRQ_QM0_L2P 0x1200383530#define PXP2_REG_PSWRQ_SRC0_L2P 0x1200543531#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c3532#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e03533/* [RW 32] Interrupt mask register #0 read/write */3534#define PXP2_REG_PXP2_INT_MASK_0 0x1205783535/* [R 32] Interrupt register #0 read */3536#define PXP2_REG_PXP2_INT_STS_0 0x12056c3537#define PXP2_REG_PXP2_INT_STS_1 0x1206083538/* [RC 32] Interrupt register #0 read clear */3539#define PXP2_REG_PXP2_INT_STS_CLR_0 0x1205703540/* [RW 32] Parity mask register #0 read/write */3541#define PXP2_REG_PXP2_PRTY_MASK_0 0x1205883542#define PXP2_REG_PXP2_PRTY_MASK_1 0x1205983543/* [R 32] Parity register #0 read */3544#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c3545#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c3546/* [RC 32] Parity register #0 read clear */3547#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x1205803548#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x1205903549/* [R 1] Debug only: The 'almost full' indication from each fifo (gives3550 indication about backpressure) */3551#define PXP2_REG_RD_ALMOST_FULL_0 0x1204243552/* [R 8] Debug only: The blocks counter - number of unused block ids */3553#define PXP2_REG_RD_BLK_CNT 0x1204183554/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.3555 Must be bigger than 6. Normally should not be changed. */3556#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c3557/* [RW 2] CDU byte swapping mode configuration for master read requests */3558#define PXP2_REG_RD_CDURD_SWAP_MODE 0x1204043559/* [RW 1] When '1'; inputs to the PSWRD block are ignored */3560#define PXP2_REG_RD_DISABLE_INPUTS 0x1203743561/* [R 1] PSWRD internal memories initialization is done */3562#define PXP2_REG_RD_INIT_DONE 0x1203703563/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3564 allocated for vq10 */3565#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a03566/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3567 allocated for vq11 */3568#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a43569/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3570 allocated for vq17 */3571#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc3572/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3573 allocated for vq18 */3574#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c03575/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3576 allocated for vq19 */3577#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c43578/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3579 allocated for vq22 */3580#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d03581/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3582 allocated for vq25 */3583#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc3584/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3585 allocated for vq6 */3586#define PXP2_REG_RD_MAX_BLKS_VQ6 0x1203903587/* [RW 8] The maximum number of blocks in Tetris Buffer that can be3588 allocated for vq9 */3589#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c3590/* [RW 2] PBF byte swapping mode configuration for master read requests */3591#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f43592/* [R 1] Debug only: Indication if delivery ports are idle */3593#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c3594#define PXP2_REG_RD_PORT_IS_IDLE_1 0x1204203595/* [RW 2] QM byte swapping mode configuration for master read requests */3596#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f83597/* [R 7] Debug only: The SR counter - number of unused sub request ids */3598#define PXP2_REG_RD_SR_CNT 0x1204143599/* [RW 2] SRC byte swapping mode configuration for master read requests */3600#define PXP2_REG_RD_SRC_SWAP_MODE 0x1204003601/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must3602 be bigger than 1. Normally should not be changed. */3603#define PXP2_REG_RD_SR_NUM_CFG 0x1204083604/* [RW 1] Signals the PSWRD block to start initializing internal memories */3605#define PXP2_REG_RD_START_INIT 0x12036c3606/* [RW 2] TM byte swapping mode configuration for master read requests */3607#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc3608/* [RW 10] Bandwidth addition to VQ0 write requests */3609#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc3610/* [RW 10] Bandwidth addition to VQ12 read requests */3611#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec3612/* [RW 10] Bandwidth addition to VQ13 read requests */3613#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f03614/* [RW 10] Bandwidth addition to VQ14 read requests */3615#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f43616/* [RW 10] Bandwidth addition to VQ15 read requests */3617#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f83618/* [RW 10] Bandwidth addition to VQ16 read requests */3619#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc3620/* [RW 10] Bandwidth addition to VQ17 read requests */3621#define PXP2_REG_RQ_BW_RD_ADD17 0x1202003622/* [RW 10] Bandwidth addition to VQ18 read requests */3623#define PXP2_REG_RQ_BW_RD_ADD18 0x1202043624/* [RW 10] Bandwidth addition to VQ19 read requests */3625#define PXP2_REG_RQ_BW_RD_ADD19 0x1202083626/* [RW 10] Bandwidth addition to VQ20 read requests */3627#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c3628/* [RW 10] Bandwidth addition to VQ22 read requests */3629#define PXP2_REG_RQ_BW_RD_ADD22 0x1202103630/* [RW 10] Bandwidth addition to VQ23 read requests */3631#define PXP2_REG_RQ_BW_RD_ADD23 0x1202143632/* [RW 10] Bandwidth addition to VQ24 read requests */3633#define PXP2_REG_RQ_BW_RD_ADD24 0x1202183634/* [RW 10] Bandwidth addition to VQ25 read requests */3635#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c3636/* [RW 10] Bandwidth addition to VQ26 read requests */3637#define PXP2_REG_RQ_BW_RD_ADD26 0x1202203638/* [RW 10] Bandwidth addition to VQ27 read requests */3639#define PXP2_REG_RQ_BW_RD_ADD27 0x1202243640/* [RW 10] Bandwidth addition to VQ4 read requests */3641#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc3642/* [RW 10] Bandwidth addition to VQ5 read requests */3643#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d03644/* [RW 10] Bandwidth Typical L for VQ0 Read requests */3645#define PXP2_REG_RQ_BW_RD_L0 0x1202ac3646/* [RW 10] Bandwidth Typical L for VQ12 Read requests */3647#define PXP2_REG_RQ_BW_RD_L12 0x1202dc3648/* [RW 10] Bandwidth Typical L for VQ13 Read requests */3649#define PXP2_REG_RQ_BW_RD_L13 0x1202e03650/* [RW 10] Bandwidth Typical L for VQ14 Read requests */3651#define PXP2_REG_RQ_BW_RD_L14 0x1202e43652/* [RW 10] Bandwidth Typical L for VQ15 Read requests */3653#define PXP2_REG_RQ_BW_RD_L15 0x1202e83654/* [RW 10] Bandwidth Typical L for VQ16 Read requests */3655#define PXP2_REG_RQ_BW_RD_L16 0x1202ec3656/* [RW 10] Bandwidth Typical L for VQ17 Read requests */3657#define PXP2_REG_RQ_BW_RD_L17 0x1202f03658/* [RW 10] Bandwidth Typical L for VQ18 Read requests */3659#define PXP2_REG_RQ_BW_RD_L18 0x1202f43660/* [RW 10] Bandwidth Typical L for VQ19 Read requests */3661#define PXP2_REG_RQ_BW_RD_L19 0x1202f83662/* [RW 10] Bandwidth Typical L for VQ20 Read requests */3663#define PXP2_REG_RQ_BW_RD_L20 0x1202fc3664/* [RW 10] Bandwidth Typical L for VQ22 Read requests */3665#define PXP2_REG_RQ_BW_RD_L22 0x1203003666/* [RW 10] Bandwidth Typical L for VQ23 Read requests */3667#define PXP2_REG_RQ_BW_RD_L23 0x1203043668/* [RW 10] Bandwidth Typical L for VQ24 Read requests */3669#define PXP2_REG_RQ_BW_RD_L24 0x1203083670/* [RW 10] Bandwidth Typical L for VQ25 Read requests */3671#define PXP2_REG_RQ_BW_RD_L25 0x12030c3672/* [RW 10] Bandwidth Typical L for VQ26 Read requests */3673#define PXP2_REG_RQ_BW_RD_L26 0x1203103674/* [RW 10] Bandwidth Typical L for VQ27 Read requests */3675#define PXP2_REG_RQ_BW_RD_L27 0x1203143676/* [RW 10] Bandwidth Typical L for VQ4 Read requests */3677#define PXP2_REG_RQ_BW_RD_L4 0x1202bc3678/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */3679#define PXP2_REG_RQ_BW_RD_L5 0x1202c03680/* [RW 7] Bandwidth upper bound for VQ0 read requests */3681#define PXP2_REG_RQ_BW_RD_UBOUND0 0x1202343682/* [RW 7] Bandwidth upper bound for VQ12 read requests */3683#define PXP2_REG_RQ_BW_RD_UBOUND12 0x1202643684/* [RW 7] Bandwidth upper bound for VQ13 read requests */3685#define PXP2_REG_RQ_BW_RD_UBOUND13 0x1202683686/* [RW 7] Bandwidth upper bound for VQ14 read requests */3687#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c3688/* [RW 7] Bandwidth upper bound for VQ15 read requests */3689#define PXP2_REG_RQ_BW_RD_UBOUND15 0x1202703690/* [RW 7] Bandwidth upper bound for VQ16 read requests */3691#define PXP2_REG_RQ_BW_RD_UBOUND16 0x1202743692/* [RW 7] Bandwidth upper bound for VQ17 read requests */3693#define PXP2_REG_RQ_BW_RD_UBOUND17 0x1202783694/* [RW 7] Bandwidth upper bound for VQ18 read requests */3695#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c3696/* [RW 7] Bandwidth upper bound for VQ19 read requests */3697#define PXP2_REG_RQ_BW_RD_UBOUND19 0x1202803698/* [RW 7] Bandwidth upper bound for VQ20 read requests */3699#define PXP2_REG_RQ_BW_RD_UBOUND20 0x1202843700/* [RW 7] Bandwidth upper bound for VQ22 read requests */3701#define PXP2_REG_RQ_BW_RD_UBOUND22 0x1202883702/* [RW 7] Bandwidth upper bound for VQ23 read requests */3703#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c3704/* [RW 7] Bandwidth upper bound for VQ24 read requests */3705#define PXP2_REG_RQ_BW_RD_UBOUND24 0x1202903706/* [RW 7] Bandwidth upper bound for VQ25 read requests */3707#define PXP2_REG_RQ_BW_RD_UBOUND25 0x1202943708/* [RW 7] Bandwidth upper bound for VQ26 read requests */3709#define PXP2_REG_RQ_BW_RD_UBOUND26 0x1202983710/* [RW 7] Bandwidth upper bound for VQ27 read requests */3711#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c3712/* [RW 7] Bandwidth upper bound for VQ4 read requests */3713#define PXP2_REG_RQ_BW_RD_UBOUND4 0x1202443714/* [RW 7] Bandwidth upper bound for VQ5 read requests */3715#define PXP2_REG_RQ_BW_RD_UBOUND5 0x1202483716/* [RW 10] Bandwidth addition to VQ29 write requests */3717#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c3718/* [RW 10] Bandwidth addition to VQ30 write requests */3719#define PXP2_REG_RQ_BW_WR_ADD30 0x1202303720/* [RW 10] Bandwidth Typical L for VQ29 Write requests */3721#define PXP2_REG_RQ_BW_WR_L29 0x12031c3722/* [RW 10] Bandwidth Typical L for VQ30 Write requests */3723#define PXP2_REG_RQ_BW_WR_L30 0x1203203724/* [RW 7] Bandwidth upper bound for VQ29 */3725#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a43726/* [RW 7] Bandwidth upper bound for VQ30 */3727#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a83728/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */3729#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x1200083730/* [RW 2] Endian mode for cdu */3731#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a03732#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c3733#define PXP2_REG_RQ_CDU_LAST_ILT 0x1206203734/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;3735 -128k */3736#define PXP2_REG_RQ_CDU_P_SIZE 0x1200183737/* [R 1] 1' indicates that the requester has finished its internal3738 configuration */3739#define PXP2_REG_RQ_CFG_DONE 0x1201b43740/* [RW 2] Endian mode for debug */3741#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a43742/* [RW 1] When '1'; requests will enter input buffers but wont get out3743 towards the glue */3744#define PXP2_REG_RQ_DISABLE_INPUTS 0x1203303745/* [RW 4] Determines alignment of write SRs when a request is split into3746 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B3747 * aligned. 4 - 512B aligned. */3748#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b03749/* [RW 4] Determines alignment of read SRs when a request is split into3750 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B3751 * aligned. 4 - 512B aligned. */3752#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c3753/* [RW 1] when set the new alignment method (E2) will be applied; when reset3754 * the original alignment method (E1 E1H) will be applied */3755#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x1209303756/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will3757 be asserted */3758#define PXP2_REG_RQ_ELT_DISABLE 0x12066c3759/* [RW 2] Endian mode for hc */3760#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a83761/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back3762 compatibility needs; Note that different registers are used per mode */3763#define PXP2_REG_RQ_ILT_MODE 0x1205b43764/* [WB 53] Onchip address table */3765#define PXP2_REG_RQ_ONCHIP_AT 0x1220003766/* [WB 53] Onchip address table - B0 */3767#define PXP2_REG_RQ_ONCHIP_AT_B0 0x1280003768/* [RW 13] Pending read limiter threshold; in Dwords */3769#define PXP2_REG_RQ_PDR_LIMIT 0x12033c3770/* [RW 2] Endian mode for qm */3771#define PXP2_REG_RQ_QM_ENDIAN_M 0x1201943772#define PXP2_REG_RQ_QM_FIRST_ILT 0x1206343773#define PXP2_REG_RQ_QM_LAST_ILT 0x1206383774/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;3775 -128k */3776#define PXP2_REG_RQ_QM_P_SIZE 0x1200503777/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */3778#define PXP2_REG_RQ_RBC_DONE 0x1201b03779/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;3780 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */3781#define PXP2_REG_RQ_RD_MBS0 0x1201603782/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;3783 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */3784#define PXP2_REG_RQ_RD_MBS1 0x1201683785/* [RW 2] Endian mode for src */3786#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c3787#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c3788#define PXP2_REG_RQ_SRC_LAST_ILT 0x1206403789/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;3790 -128k */3791#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c3792/* [RW 2] Endian mode for tm */3793#define PXP2_REG_RQ_TM_ENDIAN_M 0x1201983794#define PXP2_REG_RQ_TM_FIRST_ILT 0x1206443795#define PXP2_REG_RQ_TM_LAST_ILT 0x1206483796/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;3797 -128k */3798#define PXP2_REG_RQ_TM_P_SIZE 0x1200343799/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */3800#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c3801/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */3802#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x1200943803/* [R 8] Number of entries occupied by vq 0 in pswrq memory */3804#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x1208103805/* [R 8] Number of entries occupied by vq 10 in pswrq memory */3806#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x1208183807/* [R 8] Number of entries occupied by vq 11 in pswrq memory */3808#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x1208203809/* [R 8] Number of entries occupied by vq 12 in pswrq memory */3810#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x1208283811/* [R 8] Number of entries occupied by vq 13 in pswrq memory */3812#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x1208303813/* [R 8] Number of entries occupied by vq 14 in pswrq memory */3814#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x1208383815/* [R 8] Number of entries occupied by vq 15 in pswrq memory */3816#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x1208403817/* [R 8] Number of entries occupied by vq 16 in pswrq memory */3818#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x1208483819/* [R 8] Number of entries occupied by vq 17 in pswrq memory */3820#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x1208503821/* [R 8] Number of entries occupied by vq 18 in pswrq memory */3822#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x1208583823/* [R 8] Number of entries occupied by vq 19 in pswrq memory */3824#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x1208603825/* [R 8] Number of entries occupied by vq 1 in pswrq memory */3826#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x1208683827/* [R 8] Number of entries occupied by vq 20 in pswrq memory */3828#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x1208703829/* [R 8] Number of entries occupied by vq 21 in pswrq memory */3830#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x1208783831/* [R 8] Number of entries occupied by vq 22 in pswrq memory */3832#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x1208803833/* [R 8] Number of entries occupied by vq 23 in pswrq memory */3834#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x1208883835/* [R 8] Number of entries occupied by vq 24 in pswrq memory */3836#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x1208903837/* [R 8] Number of entries occupied by vq 25 in pswrq memory */3838#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x1208983839/* [R 8] Number of entries occupied by vq 26 in pswrq memory */3840#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a03841/* [R 8] Number of entries occupied by vq 27 in pswrq memory */3842#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a83843/* [R 8] Number of entries occupied by vq 28 in pswrq memory */3844#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b03845/* [R 8] Number of entries occupied by vq 29 in pswrq memory */3846#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b83847/* [R 8] Number of entries occupied by vq 2 in pswrq memory */3848#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c03849/* [R 8] Number of entries occupied by vq 30 in pswrq memory */3850#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c83851/* [R 8] Number of entries occupied by vq 31 in pswrq memory */3852#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d03853/* [R 8] Number of entries occupied by vq 3 in pswrq memory */3854#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d83855/* [R 8] Number of entries occupied by vq 4 in pswrq memory */3856#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e03857/* [R 8] Number of entries occupied by vq 5 in pswrq memory */3858#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e83859/* [R 8] Number of entries occupied by vq 6 in pswrq memory */3860#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f03861/* [R 8] Number of entries occupied by vq 7 in pswrq memory */3862#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f83863/* [R 8] Number of entries occupied by vq 8 in pswrq memory */3864#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x1209003865/* [R 8] Number of entries occupied by vq 9 in pswrq memory */3866#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x1209083867/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;3868 001:256B; 010: 512B; */3869#define PXP2_REG_RQ_WR_MBS0 0x12015c3870/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;3871 001:256B; 010: 512B; */3872#define PXP2_REG_RQ_WR_MBS1 0x1201643873/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3874 buffer reaches this number has_payload will be asserted */3875#define PXP2_REG_WR_CDU_MPS 0x1205f03876/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3877 buffer reaches this number has_payload will be asserted */3878#define PXP2_REG_WR_CSDM_MPS 0x1205d03879/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3880 buffer reaches this number has_payload will be asserted */3881#define PXP2_REG_WR_DBG_MPS 0x1205e83882/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3883 buffer reaches this number has_payload will be asserted */3884#define PXP2_REG_WR_DMAE_MPS 0x1205ec3885/* [RW 10] if Number of entries in dmae fifo will be higher than this3886 threshold then has_payload indication will be asserted; the default value3887 should be equal to > write MBS size! */3888#define PXP2_REG_WR_DMAE_TH 0x1203683889/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3890 buffer reaches this number has_payload will be asserted */3891#define PXP2_REG_WR_HC_MPS 0x1205c83892/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3893 buffer reaches this number has_payload will be asserted */3894#define PXP2_REG_WR_QM_MPS 0x1205dc3895/* [RW 1] 0 - working in A0 mode; - working in B0 mode */3896#define PXP2_REG_WR_REV_MODE 0x1206703897/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3898 buffer reaches this number has_payload will be asserted */3899#define PXP2_REG_WR_SRC_MPS 0x1205e43900/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3901 buffer reaches this number has_payload will be asserted */3902#define PXP2_REG_WR_TM_MPS 0x1205e03903/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3904 buffer reaches this number has_payload will be asserted */3905#define PXP2_REG_WR_TSDM_MPS 0x1205d43906/* [RW 10] if Number of entries in usdmdp fifo will be higher than this3907 threshold then has_payload indication will be asserted; the default value3908 should be equal to > write MBS size! */3909#define PXP2_REG_WR_USDMDP_TH 0x1203483910/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3911 buffer reaches this number has_payload will be asserted */3912#define PXP2_REG_WR_USDM_MPS 0x1205cc3913/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the3914 buffer reaches this number has_payload will be asserted */3915#define PXP2_REG_WR_XSDM_MPS 0x1205d83916/* [R 1] debug only: Indication if PSWHST arbiter is idle */3917#define PXP_REG_HST_ARB_IS_IDLE 0x1030043918/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means3919 this client is waiting for the arbiter. */3920#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x1030083921/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue3922 block. Should be used for close the gates. */3923#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a43924/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit3925 should update according to 'hst_discard_doorbells' register when the state3926 machine is idle */3927#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a03928/* [RW 1] When 1; new internal writes arriving to the block are discarded.3929 Should be used for close the gates. */3930#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a83931/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'3932 means this PSWHST is discarding inputs from this client. Each bit should3933 update according to 'hst_discard_internal_writes' register when the state3934 machine is idle. */3935#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c3936/* [WB 160] Used for initialization of the inbound interrupts memory */3937#define PXP_REG_HST_INBOUND_INT 0x1038003938/* [RW 7] Indirect access to the permission table. The fields are : {Valid;3939 * VFID[5:0]}3940 */3941#define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x1034003942/* [RW 32] Interrupt mask register #0 read/write */3943#define PXP_REG_PXP_INT_MASK_0 0x1030743944#define PXP_REG_PXP_INT_MASK_1 0x1030843945/* [R 32] Interrupt register #0 read */3946#define PXP_REG_PXP_INT_STS_0 0x1030683947#define PXP_REG_PXP_INT_STS_1 0x1030783948/* [RC 32] Interrupt register #0 read clear */3949#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c3950#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c3951/* [RW 27] Parity mask register #0 read/write */3952#define PXP_REG_PXP_PRTY_MASK 0x1030943953/* [R 26] Parity register #0 read */3954#define PXP_REG_PXP_PRTY_STS 0x1030883955/* [RC 27] Parity register #0 read clear */3956#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c3957/* [RW 4] The activity counter initial increment value sent in the load3958 request */3959#define QM_REG_ACTCTRINITVAL_0 0x1680403960#define QM_REG_ACTCTRINITVAL_1 0x1680443961#define QM_REG_ACTCTRINITVAL_2 0x1680483962#define QM_REG_ACTCTRINITVAL_3 0x16804c3963/* [RW 32] The base logical address (in bytes) of each physical queue. The3964 index I represents the physical queue number. The 12 lsbs are ignore and3965 considered zero so practically there are only 20 bits in this register;3966 queues 63-0 */3967#define QM_REG_BASEADDR 0x1689003968/* [RW 32] The base logical address (in bytes) of each physical queue. The3969 index I represents the physical queue number. The 12 lsbs are ignore and3970 considered zero so practically there are only 20 bits in this register;3971 queues 127-64 */3972#define QM_REG_BASEADDR_EXT_A 0x16e1003973/* [RW 16] The byte credit cost for each task. This value is for both ports */3974#define QM_REG_BYTECRDCOST 0x1682343975/* [RW 16] The initial byte credit value for both ports. */3976#define QM_REG_BYTECRDINITVAL 0x1682383977/* [RW 32] A bit per physical queue. If the bit is cleared then the physical3978 queue uses port 0 else it uses port 1; queues 31-0 */3979#define QM_REG_BYTECRDPORT_LSB 0x1682283980/* [RW 32] A bit per physical queue. If the bit is cleared then the physical3981 queue uses port 0 else it uses port 1; queues 95-64 */3982#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e5203983/* [RW 32] A bit per physical queue. If the bit is cleared then the physical3984 queue uses port 0 else it uses port 1; queues 63-32 */3985#define QM_REG_BYTECRDPORT_MSB 0x1682243986/* [RW 32] A bit per physical queue. If the bit is cleared then the physical3987 queue uses port 0 else it uses port 1; queues 127-96 */3988#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c3989/* [RW 16] The byte credit value that if above the QM is considered almost3990 full */3991#define QM_REG_BYTECREDITAFULLTHR 0x1680943992/* [RW 4] The initial credit for interface */3993#define QM_REG_CMINITCRD_0 0x1680cc3994#define QM_REG_BYTECRDCMDQ_0 0x16e6e83995#define QM_REG_CMINITCRD_1 0x1680d03996#define QM_REG_CMINITCRD_2 0x1680d43997#define QM_REG_CMINITCRD_3 0x1680d83998#define QM_REG_CMINITCRD_4 0x1680dc3999#define QM_REG_CMINITCRD_5 0x1680e04000#define QM_REG_CMINITCRD_6 0x1680e44001#define QM_REG_CMINITCRD_7 0x1680e84002/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface4003 is masked */4004#define QM_REG_CMINTEN 0x1680ec4005/* [RW 12] A bit vector which indicates which one of the queues are tied to4006 interface 0 */4007#define QM_REG_CMINTVOQMASK_0 0x1681f44008#define QM_REG_CMINTVOQMASK_1 0x1681f84009#define QM_REG_CMINTVOQMASK_2 0x1681fc4010#define QM_REG_CMINTVOQMASK_3 0x1682004011#define QM_REG_CMINTVOQMASK_4 0x1682044012#define QM_REG_CMINTVOQMASK_5 0x1682084013#define QM_REG_CMINTVOQMASK_6 0x16820c4014#define QM_REG_CMINTVOQMASK_7 0x1682104015/* [RW 20] The number of connections divided by 16 which dictates the size4016 of each queue which belongs to even function number. */4017#define QM_REG_CONNNUM_0 0x1680204018/* [R 6] Keep the fill level of the fifo from write client 4 */4019#define QM_REG_CQM_WRC_FIFOLVL 0x1680184020/* [RW 8] The context regions sent in the CFC load request */4021#define QM_REG_CTXREG_0 0x1680304022#define QM_REG_CTXREG_1 0x1680344023#define QM_REG_CTXREG_2 0x1680384024#define QM_REG_CTXREG_3 0x16803c4025/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for4026 bypass enable */4027#define QM_REG_ENBYPVOQMASK 0x16823c4028/* [RW 32] A bit mask per each physical queue. If a bit is set then the4029 physical queue uses the byte credit; queues 31-0 */4030#define QM_REG_ENBYTECRD_LSB 0x1682204031/* [RW 32] A bit mask per each physical queue. If a bit is set then the4032 physical queue uses the byte credit; queues 95-64 */4033#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e5184034/* [RW 32] A bit mask per each physical queue. If a bit is set then the4035 physical queue uses the byte credit; queues 63-32 */4036#define QM_REG_ENBYTECRD_MSB 0x16821c4037/* [RW 32] A bit mask per each physical queue. If a bit is set then the4038 physical queue uses the byte credit; queues 127-96 */4039#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e5144040/* [RW 4] If cleared then the secondary interface will not be served by the4041 RR arbiter */4042#define QM_REG_ENSEC 0x1680f04043/* [RW 32] NA */4044#define QM_REG_FUNCNUMSEL_LSB 0x1682304045/* [RW 32] NA */4046#define QM_REG_FUNCNUMSEL_MSB 0x16822c4047/* [RW 32] A mask register to mask the Almost empty signals which will not4048 be use for the almost empty indication to the HW block; queues 31:0 */4049#define QM_REG_HWAEMPTYMASK_LSB 0x1682184050/* [RW 32] A mask register to mask the Almost empty signals which will not4051 be use for the almost empty indication to the HW block; queues 95-64 */4052#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e5104053/* [RW 32] A mask register to mask the Almost empty signals which will not4054 be use for the almost empty indication to the HW block; queues 63:32 */4055#define QM_REG_HWAEMPTYMASK_MSB 0x1682144056/* [RW 32] A mask register to mask the Almost empty signals which will not4057 be use for the almost empty indication to the HW block; queues 127-96 */4058#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c4059/* [RW 4] The number of outstanding request to CFC */4060#define QM_REG_OUTLDREQ 0x1688044061/* [RC 1] A flag to indicate that overflow error occurred in one of the4062 queues. */4063#define QM_REG_OVFERROR 0x16805c4064/* [RC 7] the Q where the overflow occurs */4065#define QM_REG_OVFQNUM 0x1680584066/* [R 16] Pause state for physical queues 15-0 */4067#define QM_REG_PAUSESTATE0 0x1684104068/* [R 16] Pause state for physical queues 31-16 */4069#define QM_REG_PAUSESTATE1 0x1684144070/* [R 16] Pause state for physical queues 47-32 */4071#define QM_REG_PAUSESTATE2 0x16e6844072/* [R 16] Pause state for physical queues 63-48 */4073#define QM_REG_PAUSESTATE3 0x16e6884074/* [R 16] Pause state for physical queues 79-64 */4075#define QM_REG_PAUSESTATE4 0x16e68c4076/* [R 16] Pause state for physical queues 95-80 */4077#define QM_REG_PAUSESTATE5 0x16e6904078/* [R 16] Pause state for physical queues 111-96 */4079#define QM_REG_PAUSESTATE6 0x16e6944080/* [R 16] Pause state for physical queues 127-112 */4081#define QM_REG_PAUSESTATE7 0x16e6984082/* [RW 2] The PCI attributes field used in the PCI request. */4083#define QM_REG_PCIREQAT 0x1680544084#define QM_REG_PF_EN 0x16e70c4085/* [R 24] The number of tasks stored in the QM for the PF. only even4086 * functions are valid in E2 (odd I registers will be hard wired to 0) */4087#define QM_REG_PF_USG_CNT_0 0x16e0404088/* [R 16] NOT USED */4089#define QM_REG_PORT0BYTECRD 0x1683004090/* [R 16] The byte credit of port 1 */4091#define QM_REG_PORT1BYTECRD 0x1683044092/* [RW 3] pci function number of queues 15-0 */4093#define QM_REG_PQ2PCIFUNC_0 0x16e6bc4094#define QM_REG_PQ2PCIFUNC_1 0x16e6c04095#define QM_REG_PQ2PCIFUNC_2 0x16e6c44096#define QM_REG_PQ2PCIFUNC_3 0x16e6c84097#define QM_REG_PQ2PCIFUNC_4 0x16e6cc4098#define QM_REG_PQ2PCIFUNC_5 0x16e6d04099#define QM_REG_PQ2PCIFUNC_6 0x16e6d44100#define QM_REG_PQ2PCIFUNC_7 0x16e6d84101/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:4102 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read4103 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */4104#define QM_REG_PTRTBL 0x168a004105/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:4106 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read4107 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */4108#define QM_REG_PTRTBL_EXT_A 0x16e2004109/* [RW 2] Interrupt mask register #0 read/write */4110#define QM_REG_QM_INT_MASK 0x1684444111/* [R 2] Interrupt register #0 read */4112#define QM_REG_QM_INT_STS 0x1684384113/* [RW 12] Parity mask register #0 read/write */4114#define QM_REG_QM_PRTY_MASK 0x1684544115/* [R 12] Parity register #0 read */4116#define QM_REG_QM_PRTY_STS 0x1684484117/* [RC 12] Parity register #0 read clear */4118#define QM_REG_QM_PRTY_STS_CLR 0x16844c4119/* [R 32] Current queues in pipeline: Queues from 32 to 63 */4120#define QM_REG_QSTATUS_HIGH 0x16802c4121/* [R 32] Current queues in pipeline: Queues from 96 to 127 */4122#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e4084123/* [R 32] Current queues in pipeline: Queues from 0 to 31 */4124#define QM_REG_QSTATUS_LOW 0x1680284125/* [R 32] Current queues in pipeline: Queues from 64 to 95 */4126#define QM_REG_QSTATUS_LOW_EXT_A 0x16e4044127/* [R 24] The number of tasks queued for each queue; queues 63-0 */4128#define QM_REG_QTASKCTR_0 0x1683084129/* [R 24] The number of tasks queued for each queue; queues 127-64 */4130#define QM_REG_QTASKCTR_EXT_A_0 0x16e5844131/* [RW 4] Queue tied to VOQ */4132#define QM_REG_QVOQIDX_0 0x1680f44133#define QM_REG_QVOQIDX_10 0x16811c4134#define QM_REG_QVOQIDX_100 0x16e49c4135#define QM_REG_QVOQIDX_101 0x16e4a04136#define QM_REG_QVOQIDX_102 0x16e4a44137#define QM_REG_QVOQIDX_103 0x16e4a84138#define QM_REG_QVOQIDX_104 0x16e4ac4139#define QM_REG_QVOQIDX_105 0x16e4b04140#define QM_REG_QVOQIDX_106 0x16e4b44141#define QM_REG_QVOQIDX_107 0x16e4b84142#define QM_REG_QVOQIDX_108 0x16e4bc4143#define QM_REG_QVOQIDX_109 0x16e4c04144#define QM_REG_QVOQIDX_11 0x1681204145#define QM_REG_QVOQIDX_110 0x16e4c44146#define QM_REG_QVOQIDX_111 0x16e4c84147#define QM_REG_QVOQIDX_112 0x16e4cc4148#define QM_REG_QVOQIDX_113 0x16e4d04149#define QM_REG_QVOQIDX_114 0x16e4d44150#define QM_REG_QVOQIDX_115 0x16e4d84151#define QM_REG_QVOQIDX_116 0x16e4dc4152#define QM_REG_QVOQIDX_117 0x16e4e04153#define QM_REG_QVOQIDX_118 0x16e4e44154#define QM_REG_QVOQIDX_119 0x16e4e84155#define QM_REG_QVOQIDX_12 0x1681244156#define QM_REG_QVOQIDX_120 0x16e4ec4157#define QM_REG_QVOQIDX_121 0x16e4f04158#define QM_REG_QVOQIDX_122 0x16e4f44159#define QM_REG_QVOQIDX_123 0x16e4f84160#define QM_REG_QVOQIDX_124 0x16e4fc4161#define QM_REG_QVOQIDX_125 0x16e5004162#define QM_REG_QVOQIDX_126 0x16e5044163#define QM_REG_QVOQIDX_127 0x16e5084164#define QM_REG_QVOQIDX_13 0x1681284165#define QM_REG_QVOQIDX_14 0x16812c4166#define QM_REG_QVOQIDX_15 0x1681304167#define QM_REG_QVOQIDX_16 0x1681344168#define QM_REG_QVOQIDX_17 0x1681384169#define QM_REG_QVOQIDX_21 0x1681484170#define QM_REG_QVOQIDX_22 0x16814c4171#define QM_REG_QVOQIDX_23 0x1681504172#define QM_REG_QVOQIDX_24 0x1681544173#define QM_REG_QVOQIDX_25 0x1681584174#define QM_REG_QVOQIDX_26 0x16815c4175#define QM_REG_QVOQIDX_27 0x1681604176#define QM_REG_QVOQIDX_28 0x1681644177#define QM_REG_QVOQIDX_29 0x1681684178#define QM_REG_QVOQIDX_30 0x16816c4179#define QM_REG_QVOQIDX_31 0x1681704180#define QM_REG_QVOQIDX_32 0x1681744181#define QM_REG_QVOQIDX_33 0x1681784182#define QM_REG_QVOQIDX_34 0x16817c4183#define QM_REG_QVOQIDX_35 0x1681804184#define QM_REG_QVOQIDX_36 0x1681844185#define QM_REG_QVOQIDX_37 0x1681884186#define QM_REG_QVOQIDX_38 0x16818c4187#define QM_REG_QVOQIDX_39 0x1681904188#define QM_REG_QVOQIDX_40 0x1681944189#define QM_REG_QVOQIDX_41 0x1681984190#define QM_REG_QVOQIDX_42 0x16819c4191#define QM_REG_QVOQIDX_43 0x1681a04192#define QM_REG_QVOQIDX_44 0x1681a44193#define QM_REG_QVOQIDX_45 0x1681a84194#define QM_REG_QVOQIDX_46 0x1681ac4195#define QM_REG_QVOQIDX_47 0x1681b04196#define QM_REG_QVOQIDX_48 0x1681b44197#define QM_REG_QVOQIDX_49 0x1681b84198#define QM_REG_QVOQIDX_5 0x1681084199#define QM_REG_QVOQIDX_50 0x1681bc4200#define QM_REG_QVOQIDX_51 0x1681c04201#define QM_REG_QVOQIDX_52 0x1681c44202#define QM_REG_QVOQIDX_53 0x1681c84203#define QM_REG_QVOQIDX_54 0x1681cc4204#define QM_REG_QVOQIDX_55 0x1681d04205#define QM_REG_QVOQIDX_56 0x1681d44206#define QM_REG_QVOQIDX_57 0x1681d84207#define QM_REG_QVOQIDX_58 0x1681dc4208#define QM_REG_QVOQIDX_59 0x1681e04209#define QM_REG_QVOQIDX_6 0x16810c4210#define QM_REG_QVOQIDX_60 0x1681e44211#define QM_REG_QVOQIDX_61 0x1681e84212#define QM_REG_QVOQIDX_62 0x1681ec4213#define QM_REG_QVOQIDX_63 0x1681f04214#define QM_REG_QVOQIDX_64 0x16e40c4215#define QM_REG_QVOQIDX_65 0x16e4104216#define QM_REG_QVOQIDX_69 0x16e4204217#define QM_REG_QVOQIDX_7 0x1681104218#define QM_REG_QVOQIDX_70 0x16e4244219#define QM_REG_QVOQIDX_71 0x16e4284220#define QM_REG_QVOQIDX_72 0x16e42c4221#define QM_REG_QVOQIDX_73 0x16e4304222#define QM_REG_QVOQIDX_74 0x16e4344223#define QM_REG_QVOQIDX_75 0x16e4384224#define QM_REG_QVOQIDX_76 0x16e43c4225#define QM_REG_QVOQIDX_77 0x16e4404226#define QM_REG_QVOQIDX_78 0x16e4444227#define QM_REG_QVOQIDX_79 0x16e4484228#define QM_REG_QVOQIDX_8 0x1681144229#define QM_REG_QVOQIDX_80 0x16e44c4230#define QM_REG_QVOQIDX_81 0x16e4504231#define QM_REG_QVOQIDX_85 0x16e4604232#define QM_REG_QVOQIDX_86 0x16e4644233#define QM_REG_QVOQIDX_87 0x16e4684234#define QM_REG_QVOQIDX_88 0x16e46c4235#define QM_REG_QVOQIDX_89 0x16e4704236#define QM_REG_QVOQIDX_9 0x1681184237#define QM_REG_QVOQIDX_90 0x16e4744238#define QM_REG_QVOQIDX_91 0x16e4784239#define QM_REG_QVOQIDX_92 0x16e47c4240#define QM_REG_QVOQIDX_93 0x16e4804241#define QM_REG_QVOQIDX_94 0x16e4844242#define QM_REG_QVOQIDX_95 0x16e4884243#define QM_REG_QVOQIDX_96 0x16e48c4244#define QM_REG_QVOQIDX_97 0x16e4904245#define QM_REG_QVOQIDX_98 0x16e4944246#define QM_REG_QVOQIDX_99 0x16e4984247/* [RW 1] Initialization bit command */4248#define QM_REG_SOFT_RESET 0x1684284249/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */4250#define QM_REG_TASKCRDCOST_0 0x16809c4251#define QM_REG_TASKCRDCOST_1 0x1680a04252#define QM_REG_TASKCRDCOST_2 0x1680a44253#define QM_REG_TASKCRDCOST_4 0x1680ac4254#define QM_REG_TASKCRDCOST_5 0x1680b04255/* [R 6] Keep the fill level of the fifo from write client 3 */4256#define QM_REG_TQM_WRC_FIFOLVL 0x1680104257/* [R 6] Keep the fill level of the fifo from write client 2 */4258#define QM_REG_UQM_WRC_FIFOLVL 0x1680084259/* [RC 32] Credit update error register */4260#define QM_REG_VOQCRDERRREG 0x1684084261/* [R 16] The credit value for each VOQ */4262#define QM_REG_VOQCREDIT_0 0x1682d04263#define QM_REG_VOQCREDIT_1 0x1682d44264#define QM_REG_VOQCREDIT_4 0x1682e04265/* [RW 16] The credit value that if above the QM is considered almost full */4266#define QM_REG_VOQCREDITAFULLTHR 0x1680904267/* [RW 16] The init and maximum credit for each VoQ */4268#define QM_REG_VOQINITCREDIT_0 0x1680604269#define QM_REG_VOQINITCREDIT_1 0x1680644270#define QM_REG_VOQINITCREDIT_2 0x1680684271#define QM_REG_VOQINITCREDIT_4 0x1680704272#define QM_REG_VOQINITCREDIT_5 0x1680744273/* [RW 1] The port of which VOQ belongs */4274#define QM_REG_VOQPORT_0 0x1682a04275#define QM_REG_VOQPORT_1 0x1682a44276#define QM_REG_VOQPORT_2 0x1682a84277/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4278#define QM_REG_VOQQMASK_0_LSB 0x1682404279/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4280#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e5244281/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4282#define QM_REG_VOQQMASK_0_MSB 0x1682444283/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4284#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e5284285/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4286#define QM_REG_VOQQMASK_10_LSB 0x1682904287/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4288#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e5744289/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4290#define QM_REG_VOQQMASK_10_MSB 0x1682944291/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4292#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e5784293/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4294#define QM_REG_VOQQMASK_11_LSB 0x1682984295/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4296#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c4297/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4298#define QM_REG_VOQQMASK_11_MSB 0x16829c4299/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4300#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e5804301/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4302#define QM_REG_VOQQMASK_1_LSB 0x1682484303/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4304#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c4305/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4306#define QM_REG_VOQQMASK_1_MSB 0x16824c4307/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4308#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e5304309/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4310#define QM_REG_VOQQMASK_2_LSB 0x1682504311/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4312#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e5344313/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4314#define QM_REG_VOQQMASK_2_MSB 0x1682544315/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4316#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e5384317/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4318#define QM_REG_VOQQMASK_3_LSB 0x1682584319/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4320#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c4321/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4322#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e5404323/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4324#define QM_REG_VOQQMASK_4_LSB 0x1682604325/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4326#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e5444327/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4328#define QM_REG_VOQQMASK_4_MSB 0x1682644329/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4330#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e5484331/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4332#define QM_REG_VOQQMASK_5_LSB 0x1682684333/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4334#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c4335/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4336#define QM_REG_VOQQMASK_5_MSB 0x16826c4337/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4338#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e5504339/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4340#define QM_REG_VOQQMASK_6_LSB 0x1682704341/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4342#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e5544343/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4344#define QM_REG_VOQQMASK_6_MSB 0x1682744345/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4346#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e5584347/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4348#define QM_REG_VOQQMASK_7_LSB 0x1682784349/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4350#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c4351/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4352#define QM_REG_VOQQMASK_7_MSB 0x16827c4353/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4354#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e5604355/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4356#define QM_REG_VOQQMASK_8_LSB 0x1682804357/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4358#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e5644359/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */4360#define QM_REG_VOQQMASK_8_MSB 0x1682844361/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4362#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e5684363/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */4364#define QM_REG_VOQQMASK_9_LSB 0x1682884365/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */4366#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c4367/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */4368#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e5704369/* [RW 32] Wrr weights */4370#define QM_REG_WRRWEIGHTS_0 0x16880c4371#define QM_REG_WRRWEIGHTS_1 0x1688104372#define QM_REG_WRRWEIGHTS_10 0x1688144373#define QM_REG_WRRWEIGHTS_11 0x1688184374#define QM_REG_WRRWEIGHTS_12 0x16881c4375#define QM_REG_WRRWEIGHTS_13 0x1688204376#define QM_REG_WRRWEIGHTS_14 0x1688244377#define QM_REG_WRRWEIGHTS_15 0x1688284378#define QM_REG_WRRWEIGHTS_16 0x16e0004379#define QM_REG_WRRWEIGHTS_17 0x16e0044380#define QM_REG_WRRWEIGHTS_18 0x16e0084381#define QM_REG_WRRWEIGHTS_19 0x16e00c4382#define QM_REG_WRRWEIGHTS_2 0x16882c4383#define QM_REG_WRRWEIGHTS_20 0x16e0104384#define QM_REG_WRRWEIGHTS_21 0x16e0144385#define QM_REG_WRRWEIGHTS_22 0x16e0184386#define QM_REG_WRRWEIGHTS_23 0x16e01c4387#define QM_REG_WRRWEIGHTS_24 0x16e0204388#define QM_REG_WRRWEIGHTS_25 0x16e0244389#define QM_REG_WRRWEIGHTS_26 0x16e0284390#define QM_REG_WRRWEIGHTS_27 0x16e02c4391#define QM_REG_WRRWEIGHTS_28 0x16e0304392#define QM_REG_WRRWEIGHTS_29 0x16e0344393#define QM_REG_WRRWEIGHTS_3 0x1688304394#define QM_REG_WRRWEIGHTS_30 0x16e0384395#define QM_REG_WRRWEIGHTS_31 0x16e03c4396#define QM_REG_WRRWEIGHTS_4 0x1688344397#define QM_REG_WRRWEIGHTS_5 0x1688384398#define QM_REG_WRRWEIGHTS_6 0x16883c4399#define QM_REG_WRRWEIGHTS_7 0x1688404400#define QM_REG_WRRWEIGHTS_8 0x1688444401#define QM_REG_WRRWEIGHTS_9 0x1688484402/* [R 6] Keep the fill level of the fifo from write client 1 */4403#define QM_REG_XQM_WRC_FIFOLVL 0x1680004404/* [W 1] reset to parity interrupt */4405#define SEM_FAST_REG_PARITY_RST 0x188404406#define SRC_REG_COUNTFREE0 0x405004407/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two4408 ports. If set the searcher support 8 functions. */4409#define SRC_REG_E1HMF_ENABLE 0x404cc4410#define SRC_REG_FIRSTFREE0 0x405104411#define SRC_REG_KEYRSS0_0 0x404084412#define SRC_REG_KEYRSS0_7 0x404244413#define SRC_REG_KEYRSS1_9 0x404544414#define SRC_REG_KEYSEARCH_0 0x404584415#define SRC_REG_KEYSEARCH_1 0x4045c4416#define SRC_REG_KEYSEARCH_2 0x404604417#define SRC_REG_KEYSEARCH_3 0x404644418#define SRC_REG_KEYSEARCH_4 0x404684419#define SRC_REG_KEYSEARCH_5 0x4046c4420#define SRC_REG_KEYSEARCH_6 0x404704421#define SRC_REG_KEYSEARCH_7 0x404744422#define SRC_REG_KEYSEARCH_8 0x404784423#define SRC_REG_KEYSEARCH_9 0x4047c4424#define SRC_REG_LASTFREE0 0x405304425#define SRC_REG_NUMBER_HASH_BITS0 0x404004426/* [RW 1] Reset internal state machines. */4427#define SRC_REG_SOFT_RST 0x4049c4428/* [R 3] Interrupt register #0 read */4429#define SRC_REG_SRC_INT_STS 0x404ac4430/* [RW 3] Parity mask register #0 read/write */4431#define SRC_REG_SRC_PRTY_MASK 0x404c84432/* [R 3] Parity register #0 read */4433#define SRC_REG_SRC_PRTY_STS 0x404bc4434/* [RC 3] Parity register #0 read clear */4435#define SRC_REG_SRC_PRTY_STS_CLR 0x404c04436/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */4437#define TCM_REG_CAM_OCCUP 0x5017c4438/* [RW 1] CDU AG read Interface enable. If 0 - the request input is4439 disregarded; valid output is deasserted; all other signals are treated as4440 usual; if 1 - normal activity. */4441#define TCM_REG_CDU_AG_RD_IFEN 0x500344442/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input4443 are disregarded; all other signals are treated as usual; if 1 - normal4444 activity. */4445#define TCM_REG_CDU_AG_WR_IFEN 0x500304446/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is4447 disregarded; valid output is deasserted; all other signals are treated as4448 usual; if 1 - normal activity. */4449#define TCM_REG_CDU_SM_RD_IFEN 0x5003c4450/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid4451 input is disregarded; all other signals are treated as usual; if 1 -4452 normal activity. */4453#define TCM_REG_CDU_SM_WR_IFEN 0x500384454/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes4455 the initial credit value; read returns the current value of the credit4456 counter. Must be initialized to 1 at start-up. */4457#define TCM_REG_CFC_INIT_CRD 0x502044458/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for4459 weight 8 (the most prioritised); 1 stands for weight 1(least4460 prioritised); 2 stands for weight 2; tc. */4461#define TCM_REG_CP_WEIGHT 0x500c04462/* [RW 1] Input csem Interface enable. If 0 - the valid input is4463 disregarded; acknowledge output is deasserted; all other signals are4464 treated as usual; if 1 - normal activity. */4465#define TCM_REG_CSEM_IFEN 0x5002c4466/* [RC 1] Message length mismatch (relative to last indication) at the In#94467 interface. */4468#define TCM_REG_CSEM_LENGTH_MIS 0x501744469/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for4470 weight 8 (the most prioritised); 1 stands for weight 1(least4471 prioritised); 2 stands for weight 2; tc. */4472#define TCM_REG_CSEM_WEIGHT 0x500bc4473/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */4474#define TCM_REG_ERR_EVNT_ID 0x500a04475/* [RW 28] The CM erroneous header for QM and Timers formatting. */4476#define TCM_REG_ERR_TCM_HDR 0x5009c4477/* [RW 8] The Event ID for Timers expiration. */4478#define TCM_REG_EXPR_EVNT_ID 0x500a44479/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write4480 writes the initial credit value; read returns the current value of the4481 credit counter. Must be initialized to 64 at start-up. */4482#define TCM_REG_FIC0_INIT_CRD 0x5020c4483/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write4484 writes the initial credit value; read returns the current value of the4485 credit counter. Must be initialized to 64 at start-up. */4486#define TCM_REG_FIC1_INIT_CRD 0x502104487/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 14488 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;4489 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and4490 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */4491#define TCM_REG_GR_ARB_TYPE 0x501144492/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the4493 highest priority is 3. It is supposed that the Store channel is the4494 complement of the other 3 groups. */4495#define TCM_REG_GR_LD0_PR 0x5011c4496/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the4497 highest priority is 3. It is supposed that the Store channel is the4498 complement of the other 3 groups. */4499#define TCM_REG_GR_LD1_PR 0x501204500/* [RW 4] The number of double REG-pairs; loaded from the STORM context and4501 sent to STORM; for a specific connection type. The double REG-pairs are4502 used to align to STORM context row size of 128 bits. The offset of these4503 data in the STORM context is always 0. Index _i stands for the connection4504 type (one of 16). */4505#define TCM_REG_N_SM_CTX_LD_0 0x500504506#define TCM_REG_N_SM_CTX_LD_1 0x500544507#define TCM_REG_N_SM_CTX_LD_2 0x500584508#define TCM_REG_N_SM_CTX_LD_3 0x5005c4509#define TCM_REG_N_SM_CTX_LD_4 0x500604510#define TCM_REG_N_SM_CTX_LD_5 0x500644511/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;4512 acknowledge output is deasserted; all other signals are treated as usual;4513 if 1 - normal activity. */4514#define TCM_REG_PBF_IFEN 0x500244515/* [RC 1] Message length mismatch (relative to last indication) at the In#74516 interface. */4517#define TCM_REG_PBF_LENGTH_MIS 0x5016c4518/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for4519 weight 8 (the most prioritised); 1 stands for weight 1(least4520 prioritised); 2 stands for weight 2; tc. */4521#define TCM_REG_PBF_WEIGHT 0x500b44522#define TCM_REG_PHYS_QNUM0_0 0x500e04523#define TCM_REG_PHYS_QNUM0_1 0x500e44524#define TCM_REG_PHYS_QNUM1_0 0x500e84525#define TCM_REG_PHYS_QNUM1_1 0x500ec4526#define TCM_REG_PHYS_QNUM2_0 0x500f04527#define TCM_REG_PHYS_QNUM2_1 0x500f44528#define TCM_REG_PHYS_QNUM3_0 0x500f84529#define TCM_REG_PHYS_QNUM3_1 0x500fc4530/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;4531 acknowledge output is deasserted; all other signals are treated as usual;4532 if 1 - normal activity. */4533#define TCM_REG_PRS_IFEN 0x500204534/* [RC 1] Message length mismatch (relative to last indication) at the In#64535 interface. */4536#define TCM_REG_PRS_LENGTH_MIS 0x501684537/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for4538 weight 8 (the most prioritised); 1 stands for weight 1(least4539 prioritised); 2 stands for weight 2; tc. */4540#define TCM_REG_PRS_WEIGHT 0x500b04541/* [RW 8] The Event ID for Timers formatting in case of stop done. */4542#define TCM_REG_STOP_EVNT_ID 0x500a84543/* [RC 1] Message length mismatch (relative to last indication) at the STORM4544 interface. */4545#define TCM_REG_STORM_LENGTH_MIS 0x501604546/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is4547 disregarded; acknowledge output is deasserted; all other signals are4548 treated as usual; if 1 - normal activity. */4549#define TCM_REG_STORM_TCM_IFEN 0x500104550/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for4551 weight 8 (the most prioritised); 1 stands for weight 1(least4552 prioritised); 2 stands for weight 2; tc. */4553#define TCM_REG_STORM_WEIGHT 0x500ac4554/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;4555 acknowledge output is deasserted; all other signals are treated as usual;4556 if 1 - normal activity. */4557#define TCM_REG_TCM_CFC_IFEN 0x500404558/* [RW 11] Interrupt mask register #0 read/write */4559#define TCM_REG_TCM_INT_MASK 0x501dc4560/* [R 11] Interrupt register #0 read */4561#define TCM_REG_TCM_INT_STS 0x501d04562/* [RW 27] Parity mask register #0 read/write */4563#define TCM_REG_TCM_PRTY_MASK 0x501ec4564/* [R 27] Parity register #0 read */4565#define TCM_REG_TCM_PRTY_STS 0x501e04566/* [RC 27] Parity register #0 read clear */4567#define TCM_REG_TCM_PRTY_STS_CLR 0x501e44568/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS4569 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).4570 Is used to determine the number of the AG context REG-pairs written back;4571 when the input message Reg1WbFlg isn't set. */4572#define TCM_REG_TCM_REG0_SZ 0x500d84573/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is4574 disregarded; valid is deasserted; all other signals are treated as usual;4575 if 1 - normal activity. */4576#define TCM_REG_TCM_STORM0_IFEN 0x500044577/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is4578 disregarded; valid is deasserted; all other signals are treated as usual;4579 if 1 - normal activity. */4580#define TCM_REG_TCM_STORM1_IFEN 0x500084581/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is4582 disregarded; valid is deasserted; all other signals are treated as usual;4583 if 1 - normal activity. */4584#define TCM_REG_TCM_TQM_IFEN 0x5000c4585/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */4586#define TCM_REG_TCM_TQM_USE_Q 0x500d44587/* [RW 28] The CM header for Timers expiration command. */4588#define TCM_REG_TM_TCM_HDR 0x500984589/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is4590 disregarded; acknowledge output is deasserted; all other signals are4591 treated as usual; if 1 - normal activity. */4592#define TCM_REG_TM_TCM_IFEN 0x5001c4593/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for4594 weight 8 (the most prioritised); 1 stands for weight 1(least4595 prioritised); 2 stands for weight 2; tc. */4596#define TCM_REG_TM_WEIGHT 0x500d04597/* [RW 6] QM output initial credit. Max credit available - 32.Write writes4598 the initial credit value; read returns the current value of the credit4599 counter. Must be initialized to 32 at start-up. */4600#define TCM_REG_TQM_INIT_CRD 0x5021c4601/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 04602 stands for weight 8 (the most prioritised); 1 stands for weight 1(least4603 prioritised); 2 stands for weight 2; tc. */4604#define TCM_REG_TQM_P_WEIGHT 0x500c84605/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 04606 stands for weight 8 (the most prioritised); 1 stands for weight 1(least4607 prioritised); 2 stands for weight 2; tc. */4608#define TCM_REG_TQM_S_WEIGHT 0x500cc4609/* [RW 28] The CM header value for QM request (primary). */4610#define TCM_REG_TQM_TCM_HDR_P 0x500904611/* [RW 28] The CM header value for QM request (secondary). */4612#define TCM_REG_TQM_TCM_HDR_S 0x500944613/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;4614 acknowledge output is deasserted; all other signals are treated as usual;4615 if 1 - normal activity. */4616#define TCM_REG_TQM_TCM_IFEN 0x500144617/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;4618 acknowledge output is deasserted; all other signals are treated as usual;4619 if 1 - normal activity. */4620#define TCM_REG_TSDM_IFEN 0x500184621/* [RC 1] Message length mismatch (relative to last indication) at the SDM4622 interface. */4623#define TCM_REG_TSDM_LENGTH_MIS 0x501644624/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for4625 weight 8 (the most prioritised); 1 stands for weight 1(least4626 prioritised); 2 stands for weight 2; tc. */4627#define TCM_REG_TSDM_WEIGHT 0x500c44628/* [RW 1] Input usem Interface enable. If 0 - the valid input is4629 disregarded; acknowledge output is deasserted; all other signals are4630 treated as usual; if 1 - normal activity. */4631#define TCM_REG_USEM_IFEN 0x500284632/* [RC 1] Message length mismatch (relative to last indication) at the In#84633 interface. */4634#define TCM_REG_USEM_LENGTH_MIS 0x501704635/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for4636 weight 8 (the most prioritised); 1 stands for weight 1(least4637 prioritised); 2 stands for weight 2; tc. */4638#define TCM_REG_USEM_WEIGHT 0x500b84639/* [RW 21] Indirect access to the descriptor table of the XX protection4640 mechanism. The fields are: [5:0] - length of the message; 15:6] - message4641 pointer; 20:16] - next pointer. */4642#define TCM_REG_XX_DESCR_TABLE 0x502804643#define TCM_REG_XX_DESCR_TABLE_SIZE 294644/* [R 6] Use to read the value of XX protection Free counter. */4645#define TCM_REG_XX_FREE 0x501784646/* [RW 6] Initial value for the credit counter; responsible for fulfilling4647 of the Input Stage XX protection buffer by the XX protection pending4648 messages. Max credit available - 127.Write writes the initial credit4649 value; read returns the current value of the credit counter. Must be4650 initialized to 19 at start-up. */4651#define TCM_REG_XX_INIT_CRD 0x502204652/* [RW 6] Maximum link list size (messages locked) per connection in the XX4653 protection. */4654#define TCM_REG_XX_MAX_LL_SZ 0x500444655/* [RW 6] The maximum number of pending messages; which may be stored in XX4656 protection. ~tcm_registers_xx_free.xx_free is read on read. */4657#define TCM_REG_XX_MSG_NUM 0x502244658/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */4659#define TCM_REG_XX_OVFL_EVNT_ID 0x500484660/* [RW 16] Indirect access to the XX table of the XX protection mechanism.4661 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -4662 header pointer. */4663#define TCM_REG_XX_TABLE 0x502404664/* [RW 4] Load value for cfc ac credit cnt. */4665#define TM_REG_CFC_AC_CRDCNT_VAL 0x1642084666/* [RW 4] Load value for cfc cld credit cnt. */4667#define TM_REG_CFC_CLD_CRDCNT_VAL 0x1642104668/* [RW 8] Client0 context region. */4669#define TM_REG_CL0_CONT_REGION 0x1640304670/* [RW 8] Client1 context region. */4671#define TM_REG_CL1_CONT_REGION 0x1640344672/* [RW 8] Client2 context region. */4673#define TM_REG_CL2_CONT_REGION 0x1640384674/* [RW 2] Client in High priority client number. */4675#define TM_REG_CLIN_PRIOR0_CLIENT 0x1640244676/* [RW 4] Load value for clout0 cred cnt. */4677#define TM_REG_CLOUT_CRDCNT0_VAL 0x1642204678/* [RW 4] Load value for clout1 cred cnt. */4679#define TM_REG_CLOUT_CRDCNT1_VAL 0x1642284680/* [RW 4] Load value for clout2 cred cnt. */4681#define TM_REG_CLOUT_CRDCNT2_VAL 0x1642304682/* [RW 1] Enable client0 input. */4683#define TM_REG_EN_CL0_INPUT 0x1640084684/* [RW 1] Enable client1 input. */4685#define TM_REG_EN_CL1_INPUT 0x16400c4686/* [RW 1] Enable client2 input. */4687#define TM_REG_EN_CL2_INPUT 0x1640104688#define TM_REG_EN_LINEAR0_TIMER 0x1640144689/* [RW 1] Enable real time counter. */4690#define TM_REG_EN_REAL_TIME_CNT 0x1640d84691/* [RW 1] Enable for Timers state machines. */4692#define TM_REG_EN_TIMERS 0x1640004693/* [RW 4] Load value for expiration credit cnt. CFC max number of4694 outstanding load requests for timers (expiration) context loading. */4695#define TM_REG_EXP_CRDCNT_VAL 0x1642384696/* [RW 32] Linear0 logic address. */4697#define TM_REG_LIN0_LOGIC_ADDR 0x1642404698/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */4699#define TM_REG_LIN0_MAX_ACTIVE_CID 0x1640484700/* [ST 16] Linear0 Number of scans counter. */4701#define TM_REG_LIN0_NUM_SCANS 0x1640a04702/* [WB 64] Linear0 phy address. */4703#define TM_REG_LIN0_PHY_ADDR 0x1642704704/* [RW 1] Linear0 physical address valid. */4705#define TM_REG_LIN0_PHY_ADDR_VALID 0x1642484706#define TM_REG_LIN0_SCAN_ON 0x1640d04707/* [RW 24] Linear0 array scan timeout. */4708#define TM_REG_LIN0_SCAN_TIME 0x16403c4709#define TM_REG_LIN0_VNIC_UC 0x1641284710/* [RW 32] Linear1 logic address. */4711#define TM_REG_LIN1_LOGIC_ADDR 0x1642504712/* [WB 64] Linear1 phy address. */4713#define TM_REG_LIN1_PHY_ADDR 0x1642804714/* [RW 1] Linear1 physical address valid. */4715#define TM_REG_LIN1_PHY_ADDR_VALID 0x1642584716/* [RW 6] Linear timer set_clear fifo threshold. */4717#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x1640704718/* [RW 2] Load value for pci arbiter credit cnt. */4719#define TM_REG_PCIARB_CRDCNT_VAL 0x1642604720/* [RW 20] The amount of hardware cycles for each timer tick. */4721#define TM_REG_TIMER_TICK_SIZE 0x16401c4722/* [RW 8] Timers Context region. */4723#define TM_REG_TM_CONTEXT_REGION 0x1640444724/* [RW 1] Interrupt mask register #0 read/write */4725#define TM_REG_TM_INT_MASK 0x1640fc4726/* [R 1] Interrupt register #0 read */4727#define TM_REG_TM_INT_STS 0x1640f04728/* [RW 7] Parity mask register #0 read/write */4729#define TM_REG_TM_PRTY_MASK 0x16410c4730/* [R 7] Parity register #0 read */4731#define TM_REG_TM_PRTY_STS 0x1641004732/* [RC 7] Parity register #0 read clear */4733#define TM_REG_TM_PRTY_STS_CLR 0x1641044734/* [RW 8] The event id for aggregated interrupt 0 */4735#define TSDM_REG_AGG_INT_EVENT_0 0x420384736#define TSDM_REG_AGG_INT_EVENT_1 0x4203c4737#define TSDM_REG_AGG_INT_EVENT_2 0x420404738#define TSDM_REG_AGG_INT_EVENT_3 0x420444739#define TSDM_REG_AGG_INT_EVENT_4 0x420484740/* [RW 1] The T bit for aggregated interrupt 0 */4741#define TSDM_REG_AGG_INT_T_0 0x420b84742#define TSDM_REG_AGG_INT_T_1 0x420bc4743/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */4744#define TSDM_REG_CFC_RSP_START_ADDR 0x420084745/* [RW 16] The maximum value of the completion counter #0 */4746#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c4747/* [RW 16] The maximum value of the completion counter #1 */4748#define TSDM_REG_CMP_COUNTER_MAX1 0x420204749/* [RW 16] The maximum value of the completion counter #2 */4750#define TSDM_REG_CMP_COUNTER_MAX2 0x420244751/* [RW 16] The maximum value of the completion counter #3 */4752#define TSDM_REG_CMP_COUNTER_MAX3 0x420284753/* [RW 13] The start address in the internal RAM for the completion4754 counters. */4755#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c4756#define TSDM_REG_ENABLE_IN1 0x422384757#define TSDM_REG_ENABLE_IN2 0x4223c4758#define TSDM_REG_ENABLE_OUT1 0x422404759#define TSDM_REG_ENABLE_OUT2 0x422444760/* [RW 4] The initial number of messages that can be sent to the pxp control4761 interface without receiving any ACK. */4762#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc4763/* [ST 32] The number of ACK after placement messages received */4764#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c4765/* [ST 32] The number of packet end messages received from the parser */4766#define TSDM_REG_NUM_OF_PKT_END_MSG 0x422744767/* [ST 32] The number of requests received from the pxp async if */4768#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x422784769/* [ST 32] The number of commands received in queue 0 */4770#define TSDM_REG_NUM_OF_Q0_CMD 0x422484771/* [ST 32] The number of commands received in queue 10 */4772#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c4773/* [ST 32] The number of commands received in queue 11 */4774#define TSDM_REG_NUM_OF_Q11_CMD 0x422704775/* [ST 32] The number of commands received in queue 1 */4776#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c4777/* [ST 32] The number of commands received in queue 3 */4778#define TSDM_REG_NUM_OF_Q3_CMD 0x422504779/* [ST 32] The number of commands received in queue 4 */4780#define TSDM_REG_NUM_OF_Q4_CMD 0x422544781/* [ST 32] The number of commands received in queue 5 */4782#define TSDM_REG_NUM_OF_Q5_CMD 0x422584783/* [ST 32] The number of commands received in queue 6 */4784#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c4785/* [ST 32] The number of commands received in queue 7 */4786#define TSDM_REG_NUM_OF_Q7_CMD 0x422604787/* [ST 32] The number of commands received in queue 8 */4788#define TSDM_REG_NUM_OF_Q8_CMD 0x422644789/* [ST 32] The number of commands received in queue 9 */4790#define TSDM_REG_NUM_OF_Q9_CMD 0x422684791/* [RW 13] The start address in the internal RAM for the packet end message */4792#define TSDM_REG_PCK_END_MSG_START_ADDR 0x420144793/* [RW 13] The start address in the internal RAM for queue counters */4794#define TSDM_REG_Q_COUNTER_START_ADDR 0x420104795/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */4796#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x425484797/* [R 1] parser fifo empty in sdm_sync block */4798#define TSDM_REG_SYNC_PARSER_EMPTY 0x425504799/* [R 1] parser serial fifo empty in sdm_sync block */4800#define TSDM_REG_SYNC_SYNC_EMPTY 0x425584801/* [RW 32] Tick for timer counter. Applicable only when4802 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */4803#define TSDM_REG_TIMER_TICK 0x420004804/* [RW 32] Interrupt mask register #0 read/write */4805#define TSDM_REG_TSDM_INT_MASK_0 0x4229c4806#define TSDM_REG_TSDM_INT_MASK_1 0x422ac4807/* [R 32] Interrupt register #0 read */4808#define TSDM_REG_TSDM_INT_STS_0 0x422904809#define TSDM_REG_TSDM_INT_STS_1 0x422a04810/* [RW 11] Parity mask register #0 read/write */4811#define TSDM_REG_TSDM_PRTY_MASK 0x422bc4812/* [R 11] Parity register #0 read */4813#define TSDM_REG_TSDM_PRTY_STS 0x422b04814/* [RC 11] Parity register #0 read clear */4815#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b44816/* [RW 5] The number of time_slots in the arbitration cycle */4817#define TSEM_REG_ARB_CYCLE_SIZE 0x1800344818/* [RW 3] The source that is associated with arbitration element 0. Source4819 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-4820 sleeping thread with priority 1; 4- sleeping thread with priority 2 */4821#define TSEM_REG_ARB_ELEMENT0 0x1800204822/* [RW 3] The source that is associated with arbitration element 1. Source4823 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-4824 sleeping thread with priority 1; 4- sleeping thread with priority 2.4825 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */4826#define TSEM_REG_ARB_ELEMENT1 0x1800244827/* [RW 3] The source that is associated with arbitration element 2. Source4828 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-4829 sleeping thread with priority 1; 4- sleeping thread with priority 2.4830 Could not be equal to register ~tsem_registers_arb_element0.arb_element04831 and ~tsem_registers_arb_element1.arb_element1 */4832#define TSEM_REG_ARB_ELEMENT2 0x1800284833/* [RW 3] The source that is associated with arbitration element 3. Source4834 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-4835 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could4836 not be equal to register ~tsem_registers_arb_element0.arb_element0 and4837 ~tsem_registers_arb_element1.arb_element1 and4838 ~tsem_registers_arb_element2.arb_element2 */4839#define TSEM_REG_ARB_ELEMENT3 0x18002c4840/* [RW 3] The source that is associated with arbitration element 4. Source4841 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-4842 sleeping thread with priority 1; 4- sleeping thread with priority 2.4843 Could not be equal to register ~tsem_registers_arb_element0.arb_element04844 and ~tsem_registers_arb_element1.arb_element1 and4845 ~tsem_registers_arb_element2.arb_element2 and4846 ~tsem_registers_arb_element3.arb_element3 */4847#define TSEM_REG_ARB_ELEMENT4 0x1800304848#define TSEM_REG_ENABLE_IN 0x1800a44849#define TSEM_REG_ENABLE_OUT 0x1800a84850/* [RW 32] This address space contains all registers and memories that are4851 placed in SEM_FAST block. The SEM_FAST registers are described in4852 appendix B. In order to access the sem_fast registers the base address4853 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */4854#define TSEM_REG_FAST_MEMORY 0x1a00004855/* [RW 1] Disables input messages from FIC0 May be updated during run_time4856 by the microcode */4857#define TSEM_REG_FIC0_DISABLE 0x1802244858/* [RW 1] Disables input messages from FIC1 May be updated during run_time4859 by the microcode */4860#define TSEM_REG_FIC1_DISABLE 0x1802344861/* [RW 15] Interrupt table Read and write access to it is not possible in4862 the middle of the work */4863#define TSEM_REG_INT_TABLE 0x1804004864/* [ST 24] Statistics register. The number of messages that entered through4865 FIC0 */4866#define TSEM_REG_MSG_NUM_FIC0 0x1800004867/* [ST 24] Statistics register. The number of messages that entered through4868 FIC1 */4869#define TSEM_REG_MSG_NUM_FIC1 0x1800044870/* [ST 24] Statistics register. The number of messages that were sent to4871 FOC0 */4872#define TSEM_REG_MSG_NUM_FOC0 0x1800084873/* [ST 24] Statistics register. The number of messages that were sent to4874 FOC1 */4875#define TSEM_REG_MSG_NUM_FOC1 0x18000c4876/* [ST 24] Statistics register. The number of messages that were sent to4877 FOC2 */4878#define TSEM_REG_MSG_NUM_FOC2 0x1800104879/* [ST 24] Statistics register. The number of messages that were sent to4880 FOC3 */4881#define TSEM_REG_MSG_NUM_FOC3 0x1800144882/* [RW 1] Disables input messages from the passive buffer May be updated4883 during run_time by the microcode */4884#define TSEM_REG_PAS_DISABLE 0x18024c4885/* [WB 128] Debug only. Passive buffer memory */4886#define TSEM_REG_PASSIVE_BUFFER 0x1810004887/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */4888#define TSEM_REG_PRAM 0x1c00004889/* [R 8] Valid sleeping threads indication have bit per thread */4890#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c4891/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */4892#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a04893/* [RW 8] List of free threads . There is a bit per thread. */4894#define TSEM_REG_THREADS_LIST 0x1802e44895/* [RC 32] Parity register #0 read clear */4896#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x1801184897#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x1801284898/* [RW 3] The arbitration scheme of time_slot 0 */4899#define TSEM_REG_TS_0_AS 0x1800384900/* [RW 3] The arbitration scheme of time_slot 10 */4901#define TSEM_REG_TS_10_AS 0x1800604902/* [RW 3] The arbitration scheme of time_slot 11 */4903#define TSEM_REG_TS_11_AS 0x1800644904/* [RW 3] The arbitration scheme of time_slot 12 */4905#define TSEM_REG_TS_12_AS 0x1800684906/* [RW 3] The arbitration scheme of time_slot 13 */4907#define TSEM_REG_TS_13_AS 0x18006c4908/* [RW 3] The arbitration scheme of time_slot 14 */4909#define TSEM_REG_TS_14_AS 0x1800704910/* [RW 3] The arbitration scheme of time_slot 15 */4911#define TSEM_REG_TS_15_AS 0x1800744912/* [RW 3] The arbitration scheme of time_slot 16 */4913#define TSEM_REG_TS_16_AS 0x1800784914/* [RW 3] The arbitration scheme of time_slot 17 */4915#define TSEM_REG_TS_17_AS 0x18007c4916/* [RW 3] The arbitration scheme of time_slot 18 */4917#define TSEM_REG_TS_18_AS 0x1800804918/* [RW 3] The arbitration scheme of time_slot 1 */4919#define TSEM_REG_TS_1_AS 0x18003c4920/* [RW 3] The arbitration scheme of time_slot 2 */4921#define TSEM_REG_TS_2_AS 0x1800404922/* [RW 3] The arbitration scheme of time_slot 3 */4923#define TSEM_REG_TS_3_AS 0x1800444924/* [RW 3] The arbitration scheme of time_slot 4 */4925#define TSEM_REG_TS_4_AS 0x1800484926/* [RW 3] The arbitration scheme of time_slot 5 */4927#define TSEM_REG_TS_5_AS 0x18004c4928/* [RW 3] The arbitration scheme of time_slot 6 */4929#define TSEM_REG_TS_6_AS 0x1800504930/* [RW 3] The arbitration scheme of time_slot 7 */4931#define TSEM_REG_TS_7_AS 0x1800544932/* [RW 3] The arbitration scheme of time_slot 8 */4933#define TSEM_REG_TS_8_AS 0x1800584934/* [RW 3] The arbitration scheme of time_slot 9 */4935#define TSEM_REG_TS_9_AS 0x18005c4936/* [RW 32] Interrupt mask register #0 read/write */4937#define TSEM_REG_TSEM_INT_MASK_0 0x1801004938#define TSEM_REG_TSEM_INT_MASK_1 0x1801104939/* [R 32] Interrupt register #0 read */4940#define TSEM_REG_TSEM_INT_STS_0 0x1800f44941#define TSEM_REG_TSEM_INT_STS_1 0x1801044942/* [RW 32] Parity mask register #0 read/write */4943#define TSEM_REG_TSEM_PRTY_MASK_0 0x1801204944#define TSEM_REG_TSEM_PRTY_MASK_1 0x1801304945/* [R 32] Parity register #0 read */4946#define TSEM_REG_TSEM_PRTY_STS_0 0x1801144947#define TSEM_REG_TSEM_PRTY_STS_1 0x1801244948/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 644949 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */4950#define TSEM_REG_VFPF_ERR_NUM 0x1803804951/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits4952 * [10:8] of the address should be the offset within the accessed LCID4953 * context; the bits [7:0] are the accessed LCID.Example: to write to REG104954 * LCID100. The RBC address should be 12'ha64. */4955#define UCM_REG_AG_CTX 0xe20004956/* [R 5] Used to read the XX protection CAM occupancy counter. */4957#define UCM_REG_CAM_OCCUP 0xe01704958/* [RW 1] CDU AG read Interface enable. If 0 - the request input is4959 disregarded; valid output is deasserted; all other signals are treated as4960 usual; if 1 - normal activity. */4961#define UCM_REG_CDU_AG_RD_IFEN 0xe00384962/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input4963 are disregarded; all other signals are treated as usual; if 1 - normal4964 activity. */4965#define UCM_REG_CDU_AG_WR_IFEN 0xe00344966/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is4967 disregarded; valid output is deasserted; all other signals are treated as4968 usual; if 1 - normal activity. */4969#define UCM_REG_CDU_SM_RD_IFEN 0xe00404970/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid4971 input is disregarded; all other signals are treated as usual; if 1 -4972 normal activity. */4973#define UCM_REG_CDU_SM_WR_IFEN 0xe003c4974/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes4975 the initial credit value; read returns the current value of the credit4976 counter. Must be initialized to 1 at start-up. */4977#define UCM_REG_CFC_INIT_CRD 0xe02044978/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for4979 weight 8 (the most prioritised); 1 stands for weight 1(least4980 prioritised); 2 stands for weight 2; tc. */4981#define UCM_REG_CP_WEIGHT 0xe00c44982/* [RW 1] Input csem Interface enable. If 0 - the valid input is4983 disregarded; acknowledge output is deasserted; all other signals are4984 treated as usual; if 1 - normal activity. */4985#define UCM_REG_CSEM_IFEN 0xe00284986/* [RC 1] Set when the message length mismatch (relative to last indication)4987 at the csem interface is detected. */4988#define UCM_REG_CSEM_LENGTH_MIS 0xe01604989/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for4990 weight 8 (the most prioritised); 1 stands for weight 1(least4991 prioritised); 2 stands for weight 2; tc. */4992#define UCM_REG_CSEM_WEIGHT 0xe00b84993/* [RW 1] Input dorq Interface enable. If 0 - the valid input is4994 disregarded; acknowledge output is deasserted; all other signals are4995 treated as usual; if 1 - normal activity. */4996#define UCM_REG_DORQ_IFEN 0xe00304997/* [RC 1] Set when the message length mismatch (relative to last indication)4998 at the dorq interface is detected. */4999#define UCM_REG_DORQ_LENGTH_MIS 0xe01685000/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for5001 weight 8 (the most prioritised); 1 stands for weight 1(least5002 prioritised); 2 stands for weight 2; tc. */5003#define UCM_REG_DORQ_WEIGHT 0xe00c05004/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */5005#define UCM_REG_ERR_EVNT_ID 0xe00a45006/* [RW 28] The CM erroneous header for QM and Timers formatting. */5007#define UCM_REG_ERR_UCM_HDR 0xe00a05008/* [RW 8] The Event ID for Timers expiration. */5009#define UCM_REG_EXPR_EVNT_ID 0xe00a85010/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write5011 writes the initial credit value; read returns the current value of the5012 credit counter. Must be initialized to 64 at start-up. */5013#define UCM_REG_FIC0_INIT_CRD 0xe020c5014/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write5015 writes the initial credit value; read returns the current value of the5016 credit counter. Must be initialized to 64 at start-up. */5017#define UCM_REG_FIC1_INIT_CRD 0xe02105018/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 15019 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;5020 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and5021 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */5022#define UCM_REG_GR_ARB_TYPE 0xe01445023/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the5024 highest priority is 3. It is supposed that the Store channel group is5025 complement to the others. */5026#define UCM_REG_GR_LD0_PR 0xe014c5027/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the5028 highest priority is 3. It is supposed that the Store channel group is5029 complement to the others. */5030#define UCM_REG_GR_LD1_PR 0xe01505031/* [RW 2] The queue index for invalidate counter flag decision. */5032#define UCM_REG_INV_CFLG_Q 0xe00e45033/* [RW 5] The number of double REG-pairs; loaded from the STORM context and5034 sent to STORM; for a specific connection type. the double REG-pairs are5035 used in order to align to STORM context row size of 128 bits. The offset5036 of these data in the STORM context is always 0. Index _i stands for the5037 connection type (one of 16). */5038#define UCM_REG_N_SM_CTX_LD_0 0xe00545039#define UCM_REG_N_SM_CTX_LD_1 0xe00585040#define UCM_REG_N_SM_CTX_LD_2 0xe005c5041#define UCM_REG_N_SM_CTX_LD_3 0xe00605042#define UCM_REG_N_SM_CTX_LD_4 0xe00645043#define UCM_REG_N_SM_CTX_LD_5 0xe00685044#define UCM_REG_PHYS_QNUM0_0 0xe01105045#define UCM_REG_PHYS_QNUM0_1 0xe01145046#define UCM_REG_PHYS_QNUM1_0 0xe01185047#define UCM_REG_PHYS_QNUM1_1 0xe011c5048#define UCM_REG_PHYS_QNUM2_0 0xe01205049#define UCM_REG_PHYS_QNUM2_1 0xe01245050#define UCM_REG_PHYS_QNUM3_0 0xe01285051#define UCM_REG_PHYS_QNUM3_1 0xe012c5052/* [RW 8] The Event ID for Timers formatting in case of stop done. */5053#define UCM_REG_STOP_EVNT_ID 0xe00ac5054/* [RC 1] Set when the message length mismatch (relative to last indication)5055 at the STORM interface is detected. */5056#define UCM_REG_STORM_LENGTH_MIS 0xe01545057/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is5058 disregarded; acknowledge output is deasserted; all other signals are5059 treated as usual; if 1 - normal activity. */5060#define UCM_REG_STORM_UCM_IFEN 0xe00105061/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for5062 weight 8 (the most prioritised); 1 stands for weight 1(least5063 prioritised); 2 stands for weight 2; tc. */5064#define UCM_REG_STORM_WEIGHT 0xe00b05065/* [RW 4] Timers output initial credit. Max credit available - 15.Write5066 writes the initial credit value; read returns the current value of the5067 credit counter. Must be initialized to 4 at start-up. */5068#define UCM_REG_TM_INIT_CRD 0xe021c5069/* [RW 28] The CM header for Timers expiration command. */5070#define UCM_REG_TM_UCM_HDR 0xe009c5071/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is5072 disregarded; acknowledge output is deasserted; all other signals are5073 treated as usual; if 1 - normal activity. */5074#define UCM_REG_TM_UCM_IFEN 0xe001c5075/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for5076 weight 8 (the most prioritised); 1 stands for weight 1(least5077 prioritised); 2 stands for weight 2; tc. */5078#define UCM_REG_TM_WEIGHT 0xe00d45079/* [RW 1] Input tsem Interface enable. If 0 - the valid input is5080 disregarded; acknowledge output is deasserted; all other signals are5081 treated as usual; if 1 - normal activity. */5082#define UCM_REG_TSEM_IFEN 0xe00245083/* [RC 1] Set when the message length mismatch (relative to last indication)5084 at the tsem interface is detected. */5085#define UCM_REG_TSEM_LENGTH_MIS 0xe015c5086/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for5087 weight 8 (the most prioritised); 1 stands for weight 1(least5088 prioritised); 2 stands for weight 2; tc. */5089#define UCM_REG_TSEM_WEIGHT 0xe00b45090/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;5091 acknowledge output is deasserted; all other signals are treated as usual;5092 if 1 - normal activity. */5093#define UCM_REG_UCM_CFC_IFEN 0xe00445094/* [RW 11] Interrupt mask register #0 read/write */5095#define UCM_REG_UCM_INT_MASK 0xe01d45096/* [R 11] Interrupt register #0 read */5097#define UCM_REG_UCM_INT_STS 0xe01c85098/* [RW 27] Parity mask register #0 read/write */5099#define UCM_REG_UCM_PRTY_MASK 0xe01e45100/* [R 27] Parity register #0 read */5101#define UCM_REG_UCM_PRTY_STS 0xe01d85102/* [RC 27] Parity register #0 read clear */5103#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc5104/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS5105 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).5106 Is used to determine the number of the AG context REG-pairs written back;5107 when the Reg1WbFlg isn't set. */5108#define UCM_REG_UCM_REG0_SZ 0xe00dc5109/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is5110 disregarded; valid is deasserted; all other signals are treated as usual;5111 if 1 - normal activity. */5112#define UCM_REG_UCM_STORM0_IFEN 0xe00045113/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is5114 disregarded; valid is deasserted; all other signals are treated as usual;5115 if 1 - normal activity. */5116#define UCM_REG_UCM_STORM1_IFEN 0xe00085117/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is5118 disregarded; acknowledge output is deasserted; all other signals are5119 treated as usual; if 1 - normal activity. */5120#define UCM_REG_UCM_TM_IFEN 0xe00205121/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is5122 disregarded; valid is deasserted; all other signals are treated as usual;5123 if 1 - normal activity. */5124#define UCM_REG_UCM_UQM_IFEN 0xe000c5125/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */5126#define UCM_REG_UCM_UQM_USE_Q 0xe00d85127/* [RW 6] QM output initial credit. Max credit available - 32.Write writes5128 the initial credit value; read returns the current value of the credit5129 counter. Must be initialized to 32 at start-up. */5130#define UCM_REG_UQM_INIT_CRD 0xe02205131/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 05132 stands for weight 8 (the most prioritised); 1 stands for weight 1(least5133 prioritised); 2 stands for weight 2; tc. */5134#define UCM_REG_UQM_P_WEIGHT 0xe00cc5135/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 05136 stands for weight 8 (the most prioritised); 1 stands for weight 1(least5137 prioritised); 2 stands for weight 2; tc. */5138#define UCM_REG_UQM_S_WEIGHT 0xe00d05139/* [RW 28] The CM header value for QM request (primary). */5140#define UCM_REG_UQM_UCM_HDR_P 0xe00945141/* [RW 28] The CM header value for QM request (secondary). */5142#define UCM_REG_UQM_UCM_HDR_S 0xe00985143/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;5144 acknowledge output is deasserted; all other signals are treated as usual;5145 if 1 - normal activity. */5146#define UCM_REG_UQM_UCM_IFEN 0xe00145147/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;5148 acknowledge output is deasserted; all other signals are treated as usual;5149 if 1 - normal activity. */5150#define UCM_REG_USDM_IFEN 0xe00185151/* [RC 1] Set when the message length mismatch (relative to last indication)5152 at the SDM interface is detected. */5153#define UCM_REG_USDM_LENGTH_MIS 0xe01585154/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for5155 weight 8 (the most prioritised); 1 stands for weight 1(least5156 prioritised); 2 stands for weight 2; tc. */5157#define UCM_REG_USDM_WEIGHT 0xe00c85158/* [RW 1] Input xsem Interface enable. If 0 - the valid input is5159 disregarded; acknowledge output is deasserted; all other signals are5160 treated as usual; if 1 - normal activity. */5161#define UCM_REG_XSEM_IFEN 0xe002c5162/* [RC 1] Set when the message length mismatch (relative to last indication)5163 at the xsem interface isdetected. */5164#define UCM_REG_XSEM_LENGTH_MIS 0xe01645165/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for5166 weight 8 (the most prioritised); 1 stands for weight 1(least5167 prioritised); 2 stands for weight 2; tc. */5168#define UCM_REG_XSEM_WEIGHT 0xe00bc5169/* [RW 20] Indirect access to the descriptor table of the XX protection5170 mechanism. The fields are:[5:0] - message length; 14:6] - message5171 pointer; 19:15] - next pointer. */5172#define UCM_REG_XX_DESCR_TABLE 0xe02805173#define UCM_REG_XX_DESCR_TABLE_SIZE 275174/* [R 6] Use to read the XX protection Free counter. */5175#define UCM_REG_XX_FREE 0xe016c5176/* [RW 6] Initial value for the credit counter; responsible for fulfilling5177 of the Input Stage XX protection buffer by the XX protection pending5178 messages. Write writes the initial credit value; read returns the current5179 value of the credit counter. Must be initialized to 12 at start-up. */5180#define UCM_REG_XX_INIT_CRD 0xe02245181/* [RW 6] The maximum number of pending messages; which may be stored in XX5182 protection. ~ucm_registers_xx_free.xx_free read on read. */5183#define UCM_REG_XX_MSG_NUM 0xe02285184/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */5185#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c5186/* [RW 16] Indirect access to the XX table of the XX protection mechanism.5187 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -5188 header pointer. */5189#define UCM_REG_XX_TABLE 0xe03005190#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)5191#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)5192#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)5193#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)5194#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)5195#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)5196#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)5197#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)5198#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)5199#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)5200#define UMAC_REG_COMMAND_CONFIG 0x85201/* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE5202 * state from LPI state when it receives packet for transmission. The5203 * decrement unit is 1 micro-second. */5204#define UMAC_REG_EEE_WAKE_TIMER 0x6c5205/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers5206 * to bit 17 of the MAC address etc. */5207#define UMAC_REG_MAC_ADDR0 0xc5208/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 15209 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */5210#define UMAC_REG_MAC_ADDR1 0x105211/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive5212 * logic to check frames. */5213#define UMAC_REG_MAXFR 0x145214#define UMAC_REG_UMAC_EEE_CTRL 0x645215#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)5216/* [RW 8] The event id for aggregated interrupt 0 */5217#define USDM_REG_AGG_INT_EVENT_0 0xc40385218#define USDM_REG_AGG_INT_EVENT_1 0xc403c5219#define USDM_REG_AGG_INT_EVENT_2 0xc40405220#define USDM_REG_AGG_INT_EVENT_4 0xc40485221#define USDM_REG_AGG_INT_EVENT_5 0xc404c5222#define USDM_REG_AGG_INT_EVENT_6 0xc40505223/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)5224 or auto-mask-mode (1) */5225#define USDM_REG_AGG_INT_MODE_0 0xc41b85226#define USDM_REG_AGG_INT_MODE_1 0xc41bc5227#define USDM_REG_AGG_INT_MODE_4 0xc41c85228#define USDM_REG_AGG_INT_MODE_5 0xc41cc5229#define USDM_REG_AGG_INT_MODE_6 0xc41d05230/* [RW 1] The T bit for aggregated interrupt 5 */5231#define USDM_REG_AGG_INT_T_5 0xc40cc5232#define USDM_REG_AGG_INT_T_6 0xc40d05233/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */5234#define USDM_REG_CFC_RSP_START_ADDR 0xc40085235/* [RW 16] The maximum value of the completion counter #0 */5236#define USDM_REG_CMP_COUNTER_MAX0 0xc401c5237/* [RW 16] The maximum value of the completion counter #1 */5238#define USDM_REG_CMP_COUNTER_MAX1 0xc40205239/* [RW 16] The maximum value of the completion counter #2 */5240#define USDM_REG_CMP_COUNTER_MAX2 0xc40245241/* [RW 16] The maximum value of the completion counter #3 */5242#define USDM_REG_CMP_COUNTER_MAX3 0xc40285243/* [RW 13] The start address in the internal RAM for the completion5244 counters. */5245#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c5246#define USDM_REG_ENABLE_IN1 0xc42385247#define USDM_REG_ENABLE_IN2 0xc423c5248#define USDM_REG_ENABLE_OUT1 0xc42405249#define USDM_REG_ENABLE_OUT2 0xc42445250/* [RW 4] The initial number of messages that can be sent to the pxp control5251 interface without receiving any ACK. */5252#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c05253/* [ST 32] The number of ACK after placement messages received */5254#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc42805255/* [ST 32] The number of packet end messages received from the parser */5256#define USDM_REG_NUM_OF_PKT_END_MSG 0xc42785257/* [ST 32] The number of requests received from the pxp async if */5258#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c5259/* [ST 32] The number of commands received in queue 0 */5260#define USDM_REG_NUM_OF_Q0_CMD 0xc42485261/* [ST 32] The number of commands received in queue 10 */5262#define USDM_REG_NUM_OF_Q10_CMD 0xc42705263/* [ST 32] The number of commands received in queue 11 */5264#define USDM_REG_NUM_OF_Q11_CMD 0xc42745265/* [ST 32] The number of commands received in queue 1 */5266#define USDM_REG_NUM_OF_Q1_CMD 0xc424c5267/* [ST 32] The number of commands received in queue 2 */5268#define USDM_REG_NUM_OF_Q2_CMD 0xc42505269/* [ST 32] The number of commands received in queue 3 */5270#define USDM_REG_NUM_OF_Q3_CMD 0xc42545271/* [ST 32] The number of commands received in queue 4 */5272#define USDM_REG_NUM_OF_Q4_CMD 0xc42585273/* [ST 32] The number of commands received in queue 5 */5274#define USDM_REG_NUM_OF_Q5_CMD 0xc425c5275/* [ST 32] The number of commands received in queue 6 */5276#define USDM_REG_NUM_OF_Q6_CMD 0xc42605277/* [ST 32] The number of commands received in queue 7 */5278#define USDM_REG_NUM_OF_Q7_CMD 0xc42645279/* [ST 32] The number of commands received in queue 8 */5280#define USDM_REG_NUM_OF_Q8_CMD 0xc42685281/* [ST 32] The number of commands received in queue 9 */5282#define USDM_REG_NUM_OF_Q9_CMD 0xc426c5283/* [RW 13] The start address in the internal RAM for the packet end message */5284#define USDM_REG_PCK_END_MSG_START_ADDR 0xc40145285/* [RW 13] The start address in the internal RAM for queue counters */5286#define USDM_REG_Q_COUNTER_START_ADDR 0xc40105287/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */5288#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc45505289/* [R 1] parser fifo empty in sdm_sync block */5290#define USDM_REG_SYNC_PARSER_EMPTY 0xc45585291/* [R 1] parser serial fifo empty in sdm_sync block */5292#define USDM_REG_SYNC_SYNC_EMPTY 0xc45605293/* [RW 32] Tick for timer counter. Applicable only when5294 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */5295#define USDM_REG_TIMER_TICK 0xc40005296/* [RW 32] Interrupt mask register #0 read/write */5297#define USDM_REG_USDM_INT_MASK_0 0xc42a05298#define USDM_REG_USDM_INT_MASK_1 0xc42b05299/* [R 32] Interrupt register #0 read */5300#define USDM_REG_USDM_INT_STS_0 0xc42945301#define USDM_REG_USDM_INT_STS_1 0xc42a45302/* [RW 11] Parity mask register #0 read/write */5303#define USDM_REG_USDM_PRTY_MASK 0xc42c05304/* [R 11] Parity register #0 read */5305#define USDM_REG_USDM_PRTY_STS 0xc42b45306/* [RC 11] Parity register #0 read clear */5307#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b85308/* [RW 5] The number of time_slots in the arbitration cycle */5309#define USEM_REG_ARB_CYCLE_SIZE 0x3000345310/* [RW 3] The source that is associated with arbitration element 0. Source5311 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5312 sleeping thread with priority 1; 4- sleeping thread with priority 2 */5313#define USEM_REG_ARB_ELEMENT0 0x3000205314/* [RW 3] The source that is associated with arbitration element 1. Source5315 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5316 sleeping thread with priority 1; 4- sleeping thread with priority 2.5317 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */5318#define USEM_REG_ARB_ELEMENT1 0x3000245319/* [RW 3] The source that is associated with arbitration element 2. Source5320 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5321 sleeping thread with priority 1; 4- sleeping thread with priority 2.5322 Could not be equal to register ~usem_registers_arb_element0.arb_element05323 and ~usem_registers_arb_element1.arb_element1 */5324#define USEM_REG_ARB_ELEMENT2 0x3000285325/* [RW 3] The source that is associated with arbitration element 3. Source5326 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5327 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could5328 not be equal to register ~usem_registers_arb_element0.arb_element0 and5329 ~usem_registers_arb_element1.arb_element1 and5330 ~usem_registers_arb_element2.arb_element2 */5331#define USEM_REG_ARB_ELEMENT3 0x30002c5332/* [RW 3] The source that is associated with arbitration element 4. Source5333 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5334 sleeping thread with priority 1; 4- sleeping thread with priority 2.5335 Could not be equal to register ~usem_registers_arb_element0.arb_element05336 and ~usem_registers_arb_element1.arb_element1 and5337 ~usem_registers_arb_element2.arb_element2 and5338 ~usem_registers_arb_element3.arb_element3 */5339#define USEM_REG_ARB_ELEMENT4 0x3000305340#define USEM_REG_ENABLE_IN 0x3000a45341#define USEM_REG_ENABLE_OUT 0x3000a85342/* [RW 32] This address space contains all registers and memories that are5343 placed in SEM_FAST block. The SEM_FAST registers are described in5344 appendix B. In order to access the sem_fast registers the base address5345 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */5346#define USEM_REG_FAST_MEMORY 0x3200005347/* [RW 1] Disables input messages from FIC0 May be updated during run_time5348 by the microcode */5349#define USEM_REG_FIC0_DISABLE 0x3002245350/* [RW 1] Disables input messages from FIC1 May be updated during run_time5351 by the microcode */5352#define USEM_REG_FIC1_DISABLE 0x3002345353/* [RW 15] Interrupt table Read and write access to it is not possible in5354 the middle of the work */5355#define USEM_REG_INT_TABLE 0x3004005356/* [ST 24] Statistics register. The number of messages that entered through5357 FIC0 */5358#define USEM_REG_MSG_NUM_FIC0 0x3000005359/* [ST 24] Statistics register. The number of messages that entered through5360 FIC1 */5361#define USEM_REG_MSG_NUM_FIC1 0x3000045362/* [ST 24] Statistics register. The number of messages that were sent to5363 FOC0 */5364#define USEM_REG_MSG_NUM_FOC0 0x3000085365/* [ST 24] Statistics register. The number of messages that were sent to5366 FOC1 */5367#define USEM_REG_MSG_NUM_FOC1 0x30000c5368/* [ST 24] Statistics register. The number of messages that were sent to5369 FOC2 */5370#define USEM_REG_MSG_NUM_FOC2 0x3000105371/* [ST 24] Statistics register. The number of messages that were sent to5372 FOC3 */5373#define USEM_REG_MSG_NUM_FOC3 0x3000145374/* [RW 1] Disables input messages from the passive buffer May be updated5375 during run_time by the microcode */5376#define USEM_REG_PAS_DISABLE 0x30024c5377/* [WB 128] Debug only. Passive buffer memory */5378#define USEM_REG_PASSIVE_BUFFER 0x3020005379/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */5380#define USEM_REG_PRAM 0x3400005381/* [R 16] Valid sleeping threads indication have bit per thread */5382#define USEM_REG_SLEEP_THREADS_VALID 0x30026c5383/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */5384#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a05385/* [RW 16] List of free threads . There is a bit per thread. */5386#define USEM_REG_THREADS_LIST 0x3002e45387/* [RW 3] The arbitration scheme of time_slot 0 */5388#define USEM_REG_TS_0_AS 0x3000385389/* [RW 3] The arbitration scheme of time_slot 10 */5390#define USEM_REG_TS_10_AS 0x3000605391/* [RW 3] The arbitration scheme of time_slot 11 */5392#define USEM_REG_TS_11_AS 0x3000645393/* [RW 3] The arbitration scheme of time_slot 12 */5394#define USEM_REG_TS_12_AS 0x3000685395/* [RW 3] The arbitration scheme of time_slot 13 */5396#define USEM_REG_TS_13_AS 0x30006c5397/* [RW 3] The arbitration scheme of time_slot 14 */5398#define USEM_REG_TS_14_AS 0x3000705399/* [RW 3] The arbitration scheme of time_slot 15 */5400#define USEM_REG_TS_15_AS 0x3000745401/* [RW 3] The arbitration scheme of time_slot 16 */5402#define USEM_REG_TS_16_AS 0x3000785403/* [RW 3] The arbitration scheme of time_slot 17 */5404#define USEM_REG_TS_17_AS 0x30007c5405/* [RW 3] The arbitration scheme of time_slot 18 */5406#define USEM_REG_TS_18_AS 0x3000805407/* [RW 3] The arbitration scheme of time_slot 1 */5408#define USEM_REG_TS_1_AS 0x30003c5409/* [RW 3] The arbitration scheme of time_slot 2 */5410#define USEM_REG_TS_2_AS 0x3000405411/* [RW 3] The arbitration scheme of time_slot 3 */5412#define USEM_REG_TS_3_AS 0x3000445413/* [RW 3] The arbitration scheme of time_slot 4 */5414#define USEM_REG_TS_4_AS 0x3000485415/* [RW 3] The arbitration scheme of time_slot 5 */5416#define USEM_REG_TS_5_AS 0x30004c5417/* [RW 3] The arbitration scheme of time_slot 6 */5418#define USEM_REG_TS_6_AS 0x3000505419/* [RW 3] The arbitration scheme of time_slot 7 */5420#define USEM_REG_TS_7_AS 0x3000545421/* [RW 3] The arbitration scheme of time_slot 8 */5422#define USEM_REG_TS_8_AS 0x3000585423/* [RW 3] The arbitration scheme of time_slot 9 */5424#define USEM_REG_TS_9_AS 0x30005c5425/* [RW 32] Interrupt mask register #0 read/write */5426#define USEM_REG_USEM_INT_MASK_0 0x3001105427#define USEM_REG_USEM_INT_MASK_1 0x3001205428/* [R 32] Interrupt register #0 read */5429#define USEM_REG_USEM_INT_STS_0 0x3001045430#define USEM_REG_USEM_INT_STS_1 0x3001145431/* [RW 32] Parity mask register #0 read/write */5432#define USEM_REG_USEM_PRTY_MASK_0 0x3001305433#define USEM_REG_USEM_PRTY_MASK_1 0x3001405434/* [R 32] Parity register #0 read */5435#define USEM_REG_USEM_PRTY_STS_0 0x3001245436#define USEM_REG_USEM_PRTY_STS_1 0x3001345437/* [RC 32] Parity register #0 read clear */5438#define USEM_REG_USEM_PRTY_STS_CLR_0 0x3001285439#define USEM_REG_USEM_PRTY_STS_CLR_1 0x3001385440/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 645441 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */5442#define USEM_REG_VFPF_ERR_NUM 0x3003805443#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)5444#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)5445#define VFC_REG_MEMORIES_RST 0x1943c5446/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits5447 * [12:8] of the address should be the offset within the accessed LCID5448 * context; the bits [7:0] are the accessed LCID.Example: to write to REG105449 * LCID100. The RBC address should be 13'ha64. */5450#define XCM_REG_AG_CTX 0x280005451/* [RW 2] The queue index for registration on Aux1 counter flag. */5452#define XCM_REG_AUX1_Q 0x201345453/* [RW 2] Per each decision rule the queue index to register to. */5454#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b05455/* [R 5] Used to read the XX protection CAM occupancy counter. */5456#define XCM_REG_CAM_OCCUP 0x202445457/* [RW 1] CDU AG read Interface enable. If 0 - the request input is5458 disregarded; valid output is deasserted; all other signals are treated as5459 usual; if 1 - normal activity. */5460#define XCM_REG_CDU_AG_RD_IFEN 0x200445461/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input5462 are disregarded; all other signals are treated as usual; if 1 - normal5463 activity. */5464#define XCM_REG_CDU_AG_WR_IFEN 0x200405465/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is5466 disregarded; valid output is deasserted; all other signals are treated as5467 usual; if 1 - normal activity. */5468#define XCM_REG_CDU_SM_RD_IFEN 0x2004c5469/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid5470 input is disregarded; all other signals are treated as usual; if 1 -5471 normal activity. */5472#define XCM_REG_CDU_SM_WR_IFEN 0x200485473/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes5474 the initial credit value; read returns the current value of the credit5475 counter. Must be initialized to 1 at start-up. */5476#define XCM_REG_CFC_INIT_CRD 0x204045477/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for5478 weight 8 (the most prioritised); 1 stands for weight 1(least5479 prioritised); 2 stands for weight 2; tc. */5480#define XCM_REG_CP_WEIGHT 0x200dc5481/* [RW 1] Input csem Interface enable. If 0 - the valid input is5482 disregarded; acknowledge output is deasserted; all other signals are5483 treated as usual; if 1 - normal activity. */5484#define XCM_REG_CSEM_IFEN 0x200285485/* [RC 1] Set at message length mismatch (relative to last indication) at5486 the csem interface. */5487#define XCM_REG_CSEM_LENGTH_MIS 0x202285488/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for5489 weight 8 (the most prioritised); 1 stands for weight 1(least5490 prioritised); 2 stands for weight 2; tc. */5491#define XCM_REG_CSEM_WEIGHT 0x200c45492/* [RW 1] Input dorq Interface enable. If 0 - the valid input is5493 disregarded; acknowledge output is deasserted; all other signals are5494 treated as usual; if 1 - normal activity. */5495#define XCM_REG_DORQ_IFEN 0x200305496/* [RC 1] Set at message length mismatch (relative to last indication) at5497 the dorq interface. */5498#define XCM_REG_DORQ_LENGTH_MIS 0x202305499/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for5500 weight 8 (the most prioritised); 1 stands for weight 1(least5501 prioritised); 2 stands for weight 2; tc. */5502#define XCM_REG_DORQ_WEIGHT 0x200cc5503/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */5504#define XCM_REG_ERR_EVNT_ID 0x200b05505/* [RW 28] The CM erroneous header for QM and Timers formatting. */5506#define XCM_REG_ERR_XCM_HDR 0x200ac5507/* [RW 8] The Event ID for Timers expiration. */5508#define XCM_REG_EXPR_EVNT_ID 0x200b45509/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write5510 writes the initial credit value; read returns the current value of the5511 credit counter. Must be initialized to 64 at start-up. */5512#define XCM_REG_FIC0_INIT_CRD 0x2040c5513/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write5514 writes the initial credit value; read returns the current value of the5515 credit counter. Must be initialized to 64 at start-up. */5516#define XCM_REG_FIC1_INIT_CRD 0x204105517#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x201185518#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c5519#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x201085520#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c5521/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 15522 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;5523 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and5524 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */5525#define XCM_REG_GR_ARB_TYPE 0x2020c5526/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the5527 highest priority is 3. It is supposed that the Channel group is the5528 complement of the other 3 groups. */5529#define XCM_REG_GR_LD0_PR 0x202145530/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the5531 highest priority is 3. It is supposed that the Channel group is the5532 complement of the other 3 groups. */5533#define XCM_REG_GR_LD1_PR 0x202185534/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is5535 disregarded; acknowledge output is deasserted; all other signals are5536 treated as usual; if 1 - normal activity. */5537#define XCM_REG_NIG0_IFEN 0x200385538/* [RC 1] Set at message length mismatch (relative to last indication) at5539 the nig0 interface. */5540#define XCM_REG_NIG0_LENGTH_MIS 0x202385541/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for5542 weight 8 (the most prioritised); 1 stands for weight 1(least5543 prioritised); 2 stands for weight 2; tc. */5544#define XCM_REG_NIG0_WEIGHT 0x200d45545/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is5546 disregarded; acknowledge output is deasserted; all other signals are5547 treated as usual; if 1 - normal activity. */5548#define XCM_REG_NIG1_IFEN 0x2003c5549/* [RC 1] Set at message length mismatch (relative to last indication) at5550 the nig1 interface. */5551#define XCM_REG_NIG1_LENGTH_MIS 0x2023c5552/* [RW 5] The number of double REG-pairs; loaded from the STORM context and5553 sent to STORM; for a specific connection type. The double REG-pairs are5554 used in order to align to STORM context row size of 128 bits. The offset5555 of these data in the STORM context is always 0. Index _i stands for the5556 connection type (one of 16). */5557#define XCM_REG_N_SM_CTX_LD_0 0x200605558#define XCM_REG_N_SM_CTX_LD_1 0x200645559#define XCM_REG_N_SM_CTX_LD_2 0x200685560#define XCM_REG_N_SM_CTX_LD_3 0x2006c5561#define XCM_REG_N_SM_CTX_LD_4 0x200705562#define XCM_REG_N_SM_CTX_LD_5 0x200745563/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;5564 acknowledge output is deasserted; all other signals are treated as usual;5565 if 1 - normal activity. */5566#define XCM_REG_PBF_IFEN 0x200345567/* [RC 1] Set at message length mismatch (relative to last indication) at5568 the pbf interface. */5569#define XCM_REG_PBF_LENGTH_MIS 0x202345570/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for5571 weight 8 (the most prioritised); 1 stands for weight 1(least5572 prioritised); 2 stands for weight 2; tc. */5573#define XCM_REG_PBF_WEIGHT 0x200d05574#define XCM_REG_PHYS_QNUM3_0 0x201005575#define XCM_REG_PHYS_QNUM3_1 0x201045576/* [RW 8] The Event ID for Timers formatting in case of stop done. */5577#define XCM_REG_STOP_EVNT_ID 0x200b85578/* [RC 1] Set at message length mismatch (relative to last indication) at5579 the STORM interface. */5580#define XCM_REG_STORM_LENGTH_MIS 0x2021c5581/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for5582 weight 8 (the most prioritised); 1 stands for weight 1(least5583 prioritised); 2 stands for weight 2; tc. */5584#define XCM_REG_STORM_WEIGHT 0x200bc5585/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is5586 disregarded; acknowledge output is deasserted; all other signals are5587 treated as usual; if 1 - normal activity. */5588#define XCM_REG_STORM_XCM_IFEN 0x200105589/* [RW 4] Timers output initial credit. Max credit available - 15.Write5590 writes the initial credit value; read returns the current value of the5591 credit counter. Must be initialized to 4 at start-up. */5592#define XCM_REG_TM_INIT_CRD 0x2041c5593/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for5594 weight 8 (the most prioritised); 1 stands for weight 1(least5595 prioritised); 2 stands for weight 2; tc. */5596#define XCM_REG_TM_WEIGHT 0x200ec5597/* [RW 28] The CM header for Timers expiration command. */5598#define XCM_REG_TM_XCM_HDR 0x200a85599/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is5600 disregarded; acknowledge output is deasserted; all other signals are5601 treated as usual; if 1 - normal activity. */5602#define XCM_REG_TM_XCM_IFEN 0x2001c5603/* [RW 1] Input tsem Interface enable. If 0 - the valid input is5604 disregarded; acknowledge output is deasserted; all other signals are5605 treated as usual; if 1 - normal activity. */5606#define XCM_REG_TSEM_IFEN 0x200245607/* [RC 1] Set at message length mismatch (relative to last indication) at5608 the tsem interface. */5609#define XCM_REG_TSEM_LENGTH_MIS 0x202245610/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for5611 weight 8 (the most prioritised); 1 stands for weight 1(least5612 prioritised); 2 stands for weight 2; tc. */5613#define XCM_REG_TSEM_WEIGHT 0x200c05614/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */5615#define XCM_REG_UNA_GT_NXT_Q 0x201205616/* [RW 1] Input usem Interface enable. If 0 - the valid input is5617 disregarded; acknowledge output is deasserted; all other signals are5618 treated as usual; if 1 - normal activity. */5619#define XCM_REG_USEM_IFEN 0x2002c5620/* [RC 1] Message length mismatch (relative to last indication) at the usem5621 interface. */5622#define XCM_REG_USEM_LENGTH_MIS 0x2022c5623/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for5624 weight 8 (the most prioritised); 1 stands for weight 1(least5625 prioritised); 2 stands for weight 2; tc. */5626#define XCM_REG_USEM_WEIGHT 0x200c85627#define XCM_REG_WU_DA_CNT_CMD00 0x201d45628#define XCM_REG_WU_DA_CNT_CMD01 0x201d85629#define XCM_REG_WU_DA_CNT_CMD10 0x201dc5630#define XCM_REG_WU_DA_CNT_CMD11 0x201e05631#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e45632#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e85633#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec5634#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f05635#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c45636#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c85637#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc5638#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d05639/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;5640 acknowledge output is deasserted; all other signals are treated as usual;5641 if 1 - normal activity. */5642#define XCM_REG_XCM_CFC_IFEN 0x200505643/* [RW 14] Interrupt mask register #0 read/write */5644#define XCM_REG_XCM_INT_MASK 0x202b45645/* [R 14] Interrupt register #0 read */5646#define XCM_REG_XCM_INT_STS 0x202a85647/* [RW 30] Parity mask register #0 read/write */5648#define XCM_REG_XCM_PRTY_MASK 0x202c45649/* [R 30] Parity register #0 read */5650#define XCM_REG_XCM_PRTY_STS 0x202b85651/* [RC 30] Parity register #0 read clear */5652#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc5653 5654/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS5655 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).5656 Is used to determine the number of the AG context REG-pairs written back;5657 when the Reg1WbFlg isn't set. */5658#define XCM_REG_XCM_REG0_SZ 0x200f45659/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is5660 disregarded; valid is deasserted; all other signals are treated as usual;5661 if 1 - normal activity. */5662#define XCM_REG_XCM_STORM0_IFEN 0x200045663/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is5664 disregarded; valid is deasserted; all other signals are treated as usual;5665 if 1 - normal activity. */5666#define XCM_REG_XCM_STORM1_IFEN 0x200085667/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is5668 disregarded; acknowledge output is deasserted; all other signals are5669 treated as usual; if 1 - normal activity. */5670#define XCM_REG_XCM_TM_IFEN 0x200205671/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is5672 disregarded; valid is deasserted; all other signals are treated as usual;5673 if 1 - normal activity. */5674#define XCM_REG_XCM_XQM_IFEN 0x2000c5675/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */5676#define XCM_REG_XCM_XQM_USE_Q 0x200f05677/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */5678#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc5679/* [RW 6] QM output initial credit. Max credit available - 32.Write writes5680 the initial credit value; read returns the current value of the credit5681 counter. Must be initialized to 32 at start-up. */5682#define XCM_REG_XQM_INIT_CRD 0x204205683/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 05684 stands for weight 8 (the most prioritised); 1 stands for weight 1(least5685 prioritised); 2 stands for weight 2; tc. */5686#define XCM_REG_XQM_P_WEIGHT 0x200e45687/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 05688 stands for weight 8 (the most prioritised); 1 stands for weight 1(least5689 prioritised); 2 stands for weight 2; tc. */5690#define XCM_REG_XQM_S_WEIGHT 0x200e85691/* [RW 28] The CM header value for QM request (primary). */5692#define XCM_REG_XQM_XCM_HDR_P 0x200a05693/* [RW 28] The CM header value for QM request (secondary). */5694#define XCM_REG_XQM_XCM_HDR_S 0x200a45695/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;5696 acknowledge output is deasserted; all other signals are treated as usual;5697 if 1 - normal activity. */5698#define XCM_REG_XQM_XCM_IFEN 0x200145699/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;5700 acknowledge output is deasserted; all other signals are treated as usual;5701 if 1 - normal activity. */5702#define XCM_REG_XSDM_IFEN 0x200185703/* [RC 1] Set at message length mismatch (relative to last indication) at5704 the SDM interface. */5705#define XCM_REG_XSDM_LENGTH_MIS 0x202205706/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for5707 weight 8 (the most prioritised); 1 stands for weight 1(least5708 prioritised); 2 stands for weight 2; tc. */5709#define XCM_REG_XSDM_WEIGHT 0x200e05710/* [RW 17] Indirect access to the descriptor table of the XX protection5711 mechanism. The fields are: [5:0] - message length; 11:6] - message5712 pointer; 16:12] - next pointer. */5713#define XCM_REG_XX_DESCR_TABLE 0x204805714#define XCM_REG_XX_DESCR_TABLE_SIZE 325715/* [R 6] Used to read the XX protection Free counter. */5716#define XCM_REG_XX_FREE 0x202405717/* [RW 6] Initial value for the credit counter; responsible for fulfilling5718 of the Input Stage XX protection buffer by the XX protection pending5719 messages. Max credit available - 3.Write writes the initial credit value;5720 read returns the current value of the credit counter. Must be initialized5721 to 2 at start-up. */5722#define XCM_REG_XX_INIT_CRD 0x204245723/* [RW 6] The maximum number of pending messages; which may be stored in XX5724 protection. ~xcm_registers_xx_free.xx_free read on read. */5725#define XCM_REG_XX_MSG_NUM 0x204285726/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */5727#define XCM_REG_XX_OVFL_EVNT_ID 0x200585728#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)5729#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)5730#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)5731#define XMAC_CTRL_REG_RX_EN (0x1<<1)5732#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)5733#define XMAC_CTRL_REG_TX_EN (0x1<<0)5734#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7)5735#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)5736#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)5737#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)5738#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)5739#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)5740#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)5741#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)5742#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x605743#define XMAC_REG_CTRL 05744/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC5745 * packets transmitted by the MAC */5746#define XMAC_REG_CTRL_SA_HI 0x2c5747/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC5748 * packets transmitted by the MAC */5749#define XMAC_REG_CTRL_SA_LO 0x285750#define XMAC_REG_EEE_CTRL 0xd85751#define XMAC_REG_EEE_TIMERS_HI 0xe45752#define XMAC_REG_PAUSE_CTRL 0x685753#define XMAC_REG_PFC_CTRL 0x705754#define XMAC_REG_PFC_CTRL_HI 0x745755#define XMAC_REG_RX_LSS_CTRL 0x505756#define XMAC_REG_RX_LSS_STATUS 0x585757/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &5758 * CRC in strip mode */5759#define XMAC_REG_RX_MAX_SIZE 0x405760#define XMAC_REG_TX_CTRL 0x205761#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0)5762#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1)5763/* [RW 16] Indirect access to the XX table of the XX protection mechanism.5764 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -5765 header pointer. */5766#define XCM_REG_XX_TABLE 0x205005767/* [RW 8] The event id for aggregated interrupt 0 */5768#define XSDM_REG_AGG_INT_EVENT_0 0x1660385769#define XSDM_REG_AGG_INT_EVENT_1 0x16603c5770#define XSDM_REG_AGG_INT_EVENT_10 0x1660605771#define XSDM_REG_AGG_INT_EVENT_11 0x1660645772#define XSDM_REG_AGG_INT_EVENT_12 0x1660685773#define XSDM_REG_AGG_INT_EVENT_13 0x16606c5774#define XSDM_REG_AGG_INT_EVENT_14 0x1660705775#define XSDM_REG_AGG_INT_EVENT_2 0x1660405776#define XSDM_REG_AGG_INT_EVENT_3 0x1660445777#define XSDM_REG_AGG_INT_EVENT_4 0x1660485778#define XSDM_REG_AGG_INT_EVENT_5 0x16604c5779#define XSDM_REG_AGG_INT_EVENT_6 0x1660505780#define XSDM_REG_AGG_INT_EVENT_7 0x1660545781#define XSDM_REG_AGG_INT_EVENT_8 0x1660585782#define XSDM_REG_AGG_INT_EVENT_9 0x16605c5783/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)5784 or auto-mask-mode (1) */5785#define XSDM_REG_AGG_INT_MODE_0 0x1661b85786#define XSDM_REG_AGG_INT_MODE_1 0x1661bc5787/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */5788#define XSDM_REG_CFC_RSP_START_ADDR 0x1660085789/* [RW 16] The maximum value of the completion counter #0 */5790#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c5791/* [RW 16] The maximum value of the completion counter #1 */5792#define XSDM_REG_CMP_COUNTER_MAX1 0x1660205793/* [RW 16] The maximum value of the completion counter #2 */5794#define XSDM_REG_CMP_COUNTER_MAX2 0x1660245795/* [RW 16] The maximum value of the completion counter #3 */5796#define XSDM_REG_CMP_COUNTER_MAX3 0x1660285797/* [RW 13] The start address in the internal RAM for the completion5798 counters. */5799#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c5800#define XSDM_REG_ENABLE_IN1 0x1662385801#define XSDM_REG_ENABLE_IN2 0x16623c5802#define XSDM_REG_ENABLE_OUT1 0x1662405803#define XSDM_REG_ENABLE_OUT2 0x1662445804/* [RW 4] The initial number of messages that can be sent to the pxp control5805 interface without receiving any ACK. */5806#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc5807/* [ST 32] The number of ACK after placement messages received */5808#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c5809/* [ST 32] The number of packet end messages received from the parser */5810#define XSDM_REG_NUM_OF_PKT_END_MSG 0x1662745811/* [ST 32] The number of requests received from the pxp async if */5812#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x1662785813/* [ST 32] The number of commands received in queue 0 */5814#define XSDM_REG_NUM_OF_Q0_CMD 0x1662485815/* [ST 32] The number of commands received in queue 10 */5816#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c5817/* [ST 32] The number of commands received in queue 11 */5818#define XSDM_REG_NUM_OF_Q11_CMD 0x1662705819/* [ST 32] The number of commands received in queue 1 */5820#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c5821/* [ST 32] The number of commands received in queue 3 */5822#define XSDM_REG_NUM_OF_Q3_CMD 0x1662505823/* [ST 32] The number of commands received in queue 4 */5824#define XSDM_REG_NUM_OF_Q4_CMD 0x1662545825/* [ST 32] The number of commands received in queue 5 */5826#define XSDM_REG_NUM_OF_Q5_CMD 0x1662585827/* [ST 32] The number of commands received in queue 6 */5828#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c5829/* [ST 32] The number of commands received in queue 7 */5830#define XSDM_REG_NUM_OF_Q7_CMD 0x1662605831/* [ST 32] The number of commands received in queue 8 */5832#define XSDM_REG_NUM_OF_Q8_CMD 0x1662645833/* [ST 32] The number of commands received in queue 9 */5834#define XSDM_REG_NUM_OF_Q9_CMD 0x1662685835/* [RW 13] The start address in the internal RAM for queue counters */5836#define XSDM_REG_Q_COUNTER_START_ADDR 0x1660105837/* [W 17] Generate an operation after completion; bit-16 is5838 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and5839 * bits 4:0 are the T124Param[4:0] */5840#define XSDM_REG_OPERATION_GEN 0x1664c45841/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */5842#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x1665485843/* [R 1] parser fifo empty in sdm_sync block */5844#define XSDM_REG_SYNC_PARSER_EMPTY 0x1665505845/* [R 1] parser serial fifo empty in sdm_sync block */5846#define XSDM_REG_SYNC_SYNC_EMPTY 0x1665585847/* [RW 32] Tick for timer counter. Applicable only when5848 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */5849#define XSDM_REG_TIMER_TICK 0x1660005850/* [RW 32] Interrupt mask register #0 read/write */5851#define XSDM_REG_XSDM_INT_MASK_0 0x16629c5852#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac5853/* [R 32] Interrupt register #0 read */5854#define XSDM_REG_XSDM_INT_STS_0 0x1662905855#define XSDM_REG_XSDM_INT_STS_1 0x1662a05856/* [RW 11] Parity mask register #0 read/write */5857#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc5858/* [R 11] Parity register #0 read */5859#define XSDM_REG_XSDM_PRTY_STS 0x1662b05860/* [RC 11] Parity register #0 read clear */5861#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b45862/* [RW 5] The number of time_slots in the arbitration cycle */5863#define XSEM_REG_ARB_CYCLE_SIZE 0x2800345864/* [RW 3] The source that is associated with arbitration element 0. Source5865 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5866 sleeping thread with priority 1; 4- sleeping thread with priority 2 */5867#define XSEM_REG_ARB_ELEMENT0 0x2800205868/* [RW 3] The source that is associated with arbitration element 1. Source5869 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5870 sleeping thread with priority 1; 4- sleeping thread with priority 2.5871 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */5872#define XSEM_REG_ARB_ELEMENT1 0x2800245873/* [RW 3] The source that is associated with arbitration element 2. Source5874 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5875 sleeping thread with priority 1; 4- sleeping thread with priority 2.5876 Could not be equal to register ~xsem_registers_arb_element0.arb_element05877 and ~xsem_registers_arb_element1.arb_element1 */5878#define XSEM_REG_ARB_ELEMENT2 0x2800285879/* [RW 3] The source that is associated with arbitration element 3. Source5880 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5881 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could5882 not be equal to register ~xsem_registers_arb_element0.arb_element0 and5883 ~xsem_registers_arb_element1.arb_element1 and5884 ~xsem_registers_arb_element2.arb_element2 */5885#define XSEM_REG_ARB_ELEMENT3 0x28002c5886/* [RW 3] The source that is associated with arbitration element 4. Source5887 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-5888 sleeping thread with priority 1; 4- sleeping thread with priority 2.5889 Could not be equal to register ~xsem_registers_arb_element0.arb_element05890 and ~xsem_registers_arb_element1.arb_element1 and5891 ~xsem_registers_arb_element2.arb_element2 and5892 ~xsem_registers_arb_element3.arb_element3 */5893#define XSEM_REG_ARB_ELEMENT4 0x2800305894#define XSEM_REG_ENABLE_IN 0x2800a45895#define XSEM_REG_ENABLE_OUT 0x2800a85896/* [RW 32] This address space contains all registers and memories that are5897 placed in SEM_FAST block. The SEM_FAST registers are described in5898 appendix B. In order to access the sem_fast registers the base address5899 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */5900#define XSEM_REG_FAST_MEMORY 0x2a00005901/* [RW 1] Disables input messages from FIC0 May be updated during run_time5902 by the microcode */5903#define XSEM_REG_FIC0_DISABLE 0x2802245904/* [RW 1] Disables input messages from FIC1 May be updated during run_time5905 by the microcode */5906#define XSEM_REG_FIC1_DISABLE 0x2802345907/* [RW 15] Interrupt table Read and write access to it is not possible in5908 the middle of the work */5909#define XSEM_REG_INT_TABLE 0x2804005910/* [ST 24] Statistics register. The number of messages that entered through5911 FIC0 */5912#define XSEM_REG_MSG_NUM_FIC0 0x2800005913/* [ST 24] Statistics register. The number of messages that entered through5914 FIC1 */5915#define XSEM_REG_MSG_NUM_FIC1 0x2800045916/* [ST 24] Statistics register. The number of messages that were sent to5917 FOC0 */5918#define XSEM_REG_MSG_NUM_FOC0 0x2800085919/* [ST 24] Statistics register. The number of messages that were sent to5920 FOC1 */5921#define XSEM_REG_MSG_NUM_FOC1 0x28000c5922/* [ST 24] Statistics register. The number of messages that were sent to5923 FOC2 */5924#define XSEM_REG_MSG_NUM_FOC2 0x2800105925/* [ST 24] Statistics register. The number of messages that were sent to5926 FOC3 */5927#define XSEM_REG_MSG_NUM_FOC3 0x2800145928/* [RW 1] Disables input messages from the passive buffer May be updated5929 during run_time by the microcode */5930#define XSEM_REG_PAS_DISABLE 0x28024c5931/* [WB 128] Debug only. Passive buffer memory */5932#define XSEM_REG_PASSIVE_BUFFER 0x2820005933/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */5934#define XSEM_REG_PRAM 0x2c00005935/* [R 16] Valid sleeping threads indication have bit per thread */5936#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c5937/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */5938#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a05939/* [RW 16] List of free threads . There is a bit per thread. */5940#define XSEM_REG_THREADS_LIST 0x2802e45941/* [RW 3] The arbitration scheme of time_slot 0 */5942#define XSEM_REG_TS_0_AS 0x2800385943/* [RW 3] The arbitration scheme of time_slot 10 */5944#define XSEM_REG_TS_10_AS 0x2800605945/* [RW 3] The arbitration scheme of time_slot 11 */5946#define XSEM_REG_TS_11_AS 0x2800645947/* [RW 3] The arbitration scheme of time_slot 12 */5948#define XSEM_REG_TS_12_AS 0x2800685949/* [RW 3] The arbitration scheme of time_slot 13 */5950#define XSEM_REG_TS_13_AS 0x28006c5951/* [RW 3] The arbitration scheme of time_slot 14 */5952#define XSEM_REG_TS_14_AS 0x2800705953/* [RW 3] The arbitration scheme of time_slot 15 */5954#define XSEM_REG_TS_15_AS 0x2800745955/* [RW 3] The arbitration scheme of time_slot 16 */5956#define XSEM_REG_TS_16_AS 0x2800785957/* [RW 3] The arbitration scheme of time_slot 17 */5958#define XSEM_REG_TS_17_AS 0x28007c5959/* [RW 3] The arbitration scheme of time_slot 18 */5960#define XSEM_REG_TS_18_AS 0x2800805961/* [RW 3] The arbitration scheme of time_slot 1 */5962#define XSEM_REG_TS_1_AS 0x28003c5963/* [RW 3] The arbitration scheme of time_slot 2 */5964#define XSEM_REG_TS_2_AS 0x2800405965/* [RW 3] The arbitration scheme of time_slot 3 */5966#define XSEM_REG_TS_3_AS 0x2800445967/* [RW 3] The arbitration scheme of time_slot 4 */5968#define XSEM_REG_TS_4_AS 0x2800485969/* [RW 3] The arbitration scheme of time_slot 5 */5970#define XSEM_REG_TS_5_AS 0x28004c5971/* [RW 3] The arbitration scheme of time_slot 6 */5972#define XSEM_REG_TS_6_AS 0x2800505973/* [RW 3] The arbitration scheme of time_slot 7 */5974#define XSEM_REG_TS_7_AS 0x2800545975/* [RW 3] The arbitration scheme of time_slot 8 */5976#define XSEM_REG_TS_8_AS 0x2800585977/* [RW 3] The arbitration scheme of time_slot 9 */5978#define XSEM_REG_TS_9_AS 0x28005c5979/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 645980 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */5981#define XSEM_REG_VFPF_ERR_NUM 0x2803805982/* [RW 32] Interrupt mask register #0 read/write */5983#define XSEM_REG_XSEM_INT_MASK_0 0x2801105984#define XSEM_REG_XSEM_INT_MASK_1 0x2801205985/* [R 32] Interrupt register #0 read */5986#define XSEM_REG_XSEM_INT_STS_0 0x2801045987#define XSEM_REG_XSEM_INT_STS_1 0x2801145988/* [RW 32] Parity mask register #0 read/write */5989#define XSEM_REG_XSEM_PRTY_MASK_0 0x2801305990#define XSEM_REG_XSEM_PRTY_MASK_1 0x2801405991/* [R 32] Parity register #0 read */5992#define XSEM_REG_XSEM_PRTY_STS_0 0x2801245993#define XSEM_REG_XSEM_PRTY_STS_1 0x2801345994/* [RC 32] Parity register #0 read clear */5995#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x2801285996#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x2801385997#define MCPR_ACCESS_LOCK_LOCK (1L<<31)5998#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)5999#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)6000#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)6001#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)6002#define MCPR_NVM_COMMAND_DOIT (1L<<4)6003#define MCPR_NVM_COMMAND_DONE (1L<<3)6004#define MCPR_NVM_COMMAND_FIRST (1L<<7)6005#define MCPR_NVM_COMMAND_LAST (1L<<8)6006#define MCPR_NVM_COMMAND_WR (1L<<5)6007#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)6008#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)6009#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)6010#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)6011#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)6012#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)6013#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)6014#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)6015#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)6016#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)6017#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)6018#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)6019#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)6020#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)6021#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)6022#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)6023#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)6024#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)6025#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)6026#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)6027#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)6028#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)6029#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)6030#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)6031#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)6032#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)6033#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)6034#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)6035#define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)6036#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)6037#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)6038#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)6039#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)6040#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)6041#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)6042#define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)6043#define EMAC_LED_1000MB_OVERRIDE (1L<<1)6044#define EMAC_LED_100MB_OVERRIDE (1L<<2)6045#define EMAC_LED_10MB_OVERRIDE (1L<<3)6046#define EMAC_LED_2500MB_OVERRIDE (1L<<12)6047#define EMAC_LED_OVERRIDE (1L<<0)6048#define EMAC_LED_TRAFFIC (1L<<6)6049#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)6050#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)6051#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)6052#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)6053#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)6054#define EMAC_MDIO_COMM_DATA (0xffffL<<0)6055#define EMAC_MDIO_COMM_START_BUSY (1L<<29)6056#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)6057#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)6058#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)6059#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 166060#define EMAC_MDIO_STATUS_10MB (1L<<1)6061#define EMAC_MODE_25G_MODE (1L<<5)6062#define EMAC_MODE_HALF_DUPLEX (1L<<1)6063#define EMAC_MODE_PORT_GMII (2L<<2)6064#define EMAC_MODE_PORT_MII (1L<<2)6065#define EMAC_MODE_PORT_MII_10M (3L<<2)6066#define EMAC_MODE_RESET (1L<<0)6067#define EMAC_REG_EMAC_LED 0xc6068#define EMAC_REG_EMAC_MAC_MATCH 0x106069#define EMAC_REG_EMAC_MDIO_COMM 0xac6070#define EMAC_REG_EMAC_MDIO_MODE 0xb46071#define EMAC_REG_EMAC_MDIO_STATUS 0xb06072#define EMAC_REG_EMAC_MODE 0x06073#define EMAC_REG_EMAC_RX_MODE 0xc86074#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c6075#define EMAC_REG_EMAC_RX_STAT_AC 0x1806076#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f46077#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 236078#define EMAC_REG_EMAC_TX_MODE 0xbc6079#define EMAC_REG_EMAC_TX_STAT_AC 0x2806080#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 226081#define EMAC_REG_RX_PFC_MODE 0x3206082#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)6083#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)6084#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)6085#define EMAC_REG_RX_PFC_PARAM 0x3246086#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 06087#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 166088#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x3286089#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)6090#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x3306091#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)6092#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c6093#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)6094#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x3346095#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)6096#define EMAC_RX_MODE_FLOW_EN (1L<<2)6097#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)6098#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)6099#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)6100#define EMAC_RX_MODE_RESET (1L<<0)6101#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)6102#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)6103#define EMAC_TX_MODE_FLOW_EN (1L<<4)6104#define EMAC_TX_MODE_RESET (1L<<0)6105#define MISC_REGISTERS_GPIO_0 06106#define MISC_REGISTERS_GPIO_1 16107#define MISC_REGISTERS_GPIO_2 26108#define MISC_REGISTERS_GPIO_3 36109#define MISC_REGISTERS_GPIO_CLR_POS 166110#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)6111#define MISC_REGISTERS_GPIO_FLOAT_POS 246112#define MISC_REGISTERS_GPIO_HIGH 16113#define MISC_REGISTERS_GPIO_INPUT_HI_Z 26114#define MISC_REGISTERS_GPIO_INT_CLR_POS 246115#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 06116#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 16117#define MISC_REGISTERS_GPIO_INT_SET_POS 166118#define MISC_REGISTERS_GPIO_LOW 06119#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 16120#define MISC_REGISTERS_GPIO_OUTPUT_LOW 06121#define MISC_REGISTERS_GPIO_PORT_SHIFT 46122#define MISC_REGISTERS_GPIO_SET_POS 86123#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x5886124#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)6125#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)6126#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)6127#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)6128#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)6129#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)6130#define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22)6131#define MISC_REGISTERS_RESET_REG_1_SET 0x5846132#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x5986133#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)6134#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)6135#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)6136#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)6137#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)6138#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)6139#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)6140#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)6141#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)6142#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)6143#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)6144#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)6145#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)6146#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)6147#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)6148#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)6149#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)6150#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)6151#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)6152#define MISC_REGISTERS_RESET_REG_2_SET 0x5946153#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)6154#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)6155#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)6156#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)6157#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a86158#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)6159#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)6160#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)6161#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)6162#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)6163#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)6164#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)6165#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)6166#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)6167#define MISC_REGISTERS_RESET_REG_3_SET 0x5a46168#define MISC_REGISTERS_SPIO_4 46169#define MISC_REGISTERS_SPIO_5 56170#define MISC_REGISTERS_SPIO_7 76171#define MISC_REGISTERS_SPIO_CLR_POS 166172#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)6173#define MISC_REGISTERS_SPIO_FLOAT_POS 246174#define MISC_REGISTERS_SPIO_INPUT_HI_Z 26175#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 166176#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 16177#define MISC_REGISTERS_SPIO_OUTPUT_LOW 06178#define MISC_REGISTERS_SPIO_SET_POS 86179#define MISC_SPIO_CLR_POS 166180#define MISC_SPIO_FLOAT (0xffL<<24)6181#define MISC_SPIO_FLOAT_POS 246182#define MISC_SPIO_INPUT_HI_Z 26183#define MISC_SPIO_INT_OLD_SET_POS 166184#define MISC_SPIO_OUTPUT_HIGH 16185#define MISC_SPIO_OUTPUT_LOW 06186#define MISC_SPIO_SET_POS 86187#define MISC_SPIO_SPIO4 0x106188#define MISC_SPIO_SPIO5 0x206189#define HW_LOCK_MAX_RESOURCE_VALUE 316190#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 136191#define HW_LOCK_RESOURCE_DRV_FLAGS 106192#define HW_LOCK_RESOURCE_GPIO 16193#define HW_LOCK_RESOURCE_MDIO 06194#define HW_LOCK_RESOURCE_NVRAM 126195#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 36196#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 86197#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 96198#define HW_LOCK_RESOURCE_RECOVERY_REG 116199#define HW_LOCK_RESOURCE_RESET 56200#define HW_LOCK_RESOURCE_SPIO 26201#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)6202#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)6203#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)6204#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)6205#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)6206#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)6207#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)6208#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)6209#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)6210#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)6211#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)6212#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)6213#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)6214#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)6215#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)6216#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)6217#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)6218#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)6219#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)6220#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)6221#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)6222#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)6223#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1U<<31)6224#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)6225#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)6226#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)6227#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)6228#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)6229#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)6230#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)6231#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)6232#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)6233#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)6234#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)6235#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)6236#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)6237#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)6238#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)6239#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)6240#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)6241#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)6242#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)6243#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)6244#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)6245#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)6246#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)6247#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)6248#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)6249#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)6250#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)6251#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)6252#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)6253#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)6254#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)6255#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)6256#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)6257#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)6258#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)6259#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)6260#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)6261#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)6262#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)6263#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)6264#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)6265#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)6266 6267#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)6268#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)6269 6270#define RESERVED_GENERAL_ATTENTION_BIT_0 06271 6272#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe06273#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe000006274 6275#define RESERVED_GENERAL_ATTENTION_BIT_6 66276#define RESERVED_GENERAL_ATTENTION_BIT_7 76277#define RESERVED_GENERAL_ATTENTION_BIT_8 86278#define RESERVED_GENERAL_ATTENTION_BIT_9 96279#define RESERVED_GENERAL_ATTENTION_BIT_10 106280#define RESERVED_GENERAL_ATTENTION_BIT_11 116281#define RESERVED_GENERAL_ATTENTION_BIT_12 126282#define RESERVED_GENERAL_ATTENTION_BIT_13 136283#define RESERVED_GENERAL_ATTENTION_BIT_14 146284#define RESERVED_GENERAL_ATTENTION_BIT_15 156285#define RESERVED_GENERAL_ATTENTION_BIT_16 166286#define RESERVED_GENERAL_ATTENTION_BIT_17 176287#define RESERVED_GENERAL_ATTENTION_BIT_18 186288#define RESERVED_GENERAL_ATTENTION_BIT_19 196289#define RESERVED_GENERAL_ATTENTION_BIT_20 206290#define RESERVED_GENERAL_ATTENTION_BIT_21 216291 6292/* storm asserts attention bits */6293#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_76294#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_86295#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_96296#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_106297 6298/* mcp error attention bit */6299#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_116300 6301/*E1H NIG status sync attention mapped to group 4-7*/6302#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_126303#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_136304#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_146305#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_156306#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_166307#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_176308#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_186309#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_196310 6311 6312#define LATCHED_ATTN_RBCR 236313#define LATCHED_ATTN_RBCT 246314#define LATCHED_ATTN_RBCN 256315#define LATCHED_ATTN_RBCU 266316#define LATCHED_ATTN_RBCP 276317#define LATCHED_ATTN_TIMEOUT_GRC 286318#define LATCHED_ATTN_RSVD_GRC 296319#define LATCHED_ATTN_ROM_PARITY_MCP 306320#define LATCHED_ATTN_UM_RX_PARITY_MCP 316321#define LATCHED_ATTN_UM_TX_PARITY_MCP 326322#define LATCHED_ATTN_SCPAD_PARITY_MCP 336323 6324#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)6325#define GENERAL_ATTEN_OFFSET(atten_name)\6326 (1UL << ((94 + atten_name) % 32))6327/*6328 * This file defines GRC base address for every block.6329 * This file is included by chipsim, asm microcode and cpp microcode.6330 * These values are used in Design.xml on regBase attribute6331 * Use the base with the generated offsets of specific registers.6332 */6333 6334#define GRCBASE_PXPCS 0x0000006335#define GRCBASE_PCICONFIG 0x0020006336#define GRCBASE_PCIREG 0x0024006337#define GRCBASE_EMAC0 0x0080006338#define GRCBASE_EMAC1 0x0084006339#define GRCBASE_DBU 0x0088006340#define GRCBASE_MISC 0x00A0006341#define GRCBASE_DBG 0x00C0006342#define GRCBASE_NIG 0x0100006343#define GRCBASE_XCM 0x0200006344#define GRCBASE_PRS 0x0400006345#define GRCBASE_SRCH 0x0404006346#define GRCBASE_TSDM 0x0420006347#define GRCBASE_TCM 0x0500006348#define GRCBASE_BRB1 0x0600006349#define GRCBASE_MCP 0x0800006350#define GRCBASE_UPB 0x0C10006351#define GRCBASE_CSDM 0x0C20006352#define GRCBASE_USDM 0x0C40006353#define GRCBASE_CCM 0x0D00006354#define GRCBASE_UCM 0x0E00006355#define GRCBASE_CDU 0x1010006356#define GRCBASE_DMAE 0x1020006357#define GRCBASE_PXP 0x1030006358#define GRCBASE_CFC 0x1040006359#define GRCBASE_HC 0x1080006360#define GRCBASE_PXP2 0x1200006361#define GRCBASE_PBF 0x1400006362#define GRCBASE_UMAC0 0x1600006363#define GRCBASE_UMAC1 0x1604006364#define GRCBASE_XPB 0x1610006365#define GRCBASE_MSTAT0 0x1620006366#define GRCBASE_MSTAT1 0x1628006367#define GRCBASE_XMAC0 0x1630006368#define GRCBASE_XMAC1 0x1638006369#define GRCBASE_TIMERS 0x1640006370#define GRCBASE_XSDM 0x1660006371#define GRCBASE_QM 0x1680006372#define GRCBASE_DQ 0x1700006373#define GRCBASE_TSEM 0x1800006374#define GRCBASE_CSEM 0x2000006375#define GRCBASE_XSEM 0x2800006376#define GRCBASE_USEM 0x3000006377#define GRCBASE_MISC_AEU GRCBASE_MISC6378 6379 6380/* offset of configuration space in the pci core register */6381#define PCICFG_OFFSET 0x20006382#define PCICFG_VENDOR_ID_OFFSET 0x006383#define PCICFG_DEVICE_ID_OFFSET 0x026384#define PCICFG_COMMAND_OFFSET 0x046385#define PCICFG_COMMAND_IO_SPACE (1<<0)6386#define PCICFG_COMMAND_MEM_SPACE (1<<1)6387#define PCICFG_COMMAND_BUS_MASTER (1<<2)6388#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)6389#define PCICFG_COMMAND_MWI_CYCLES (1<<4)6390#define PCICFG_COMMAND_VGA_SNOOP (1<<5)6391#define PCICFG_COMMAND_PERR_ENA (1<<6)6392#define PCICFG_COMMAND_STEPPING (1<<7)6393#define PCICFG_COMMAND_SERR_ENA (1<<8)6394#define PCICFG_COMMAND_FAST_B2B (1<<9)6395#define PCICFG_COMMAND_INT_DISABLE (1<<10)6396#define PCICFG_COMMAND_RESERVED (0x1f<<11)6397#define PCICFG_STATUS_OFFSET 0x066398#define PCICFG_REVISION_ID_OFFSET 0x086399#define PCICFG_REVESION_ID_MASK 0xff6400#define PCICFG_REVESION_ID_ERROR_VAL 0xff6401#define PCICFG_CACHE_LINE_SIZE 0x0c6402#define PCICFG_LATENCY_TIMER 0x0d6403#define PCICFG_BAR_1_LOW 0x106404#define PCICFG_BAR_1_HIGH 0x146405#define PCICFG_BAR_2_LOW 0x186406#define PCICFG_BAR_2_HIGH 0x1c6407#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c6408#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e6409#define PCICFG_INT_LINE 0x3c6410#define PCICFG_INT_PIN 0x3d6411#define PCICFG_PM_CAPABILITY 0x486412#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)6413#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)6414#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)6415#define PCICFG_PM_CAPABILITY_DSI (1<<21)6416#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)6417#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)6418#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)6419#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)6420#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)6421#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)6422#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)6423#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)6424#define PCICFG_PM_CSR_OFFSET 0x4c6425#define PCICFG_PM_CSR_STATE (0x3<<0)6426#define PCICFG_PM_CSR_PME_ENABLE (1<<8)6427#define PCICFG_PM_CSR_PME_STATUS (1<<15)6428#define PCICFG_MSI_CAP_ID_OFFSET 0x586429#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)6430#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)6431#define PCICFG_MSI_CONTROL_MENA (0x7<<20)6432#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)6433#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)6434#define PCICFG_GRC_ADDRESS 0x786435#define PCICFG_GRC_DATA 0x806436#define PCICFG_ME_REGISTER 0x986437#define PCICFG_MSIX_CAP_ID_OFFSET 0xa06438#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)6439#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)6440#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)6441#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)6442 6443#define PCICFG_DEVICE_CONTROL 0xb46444#define PCICFG_DEVICE_STATUS 0xb66445#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)6446#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)6447#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)6448#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)6449#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)6450#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)6451#define PCICFG_LINK_CONTROL 0xbc6452 6453 6454#define BAR_USTRORM_INTMEM 0x4000006455#define BAR_CSTRORM_INTMEM 0x4100006456#define BAR_XSTRORM_INTMEM 0x4200006457#define BAR_TSTRORM_INTMEM 0x4300006458 6459/* for accessing the IGU in case of status block ACK */6460#define BAR_IGU_INTMEM 0x4400006461 6462#define BAR_DOORBELL_OFFSET 0x8000006463 6464#define BAR_ME_REGISTER 0x4500006465 6466/* config_2 offset */6467#define GRC_CONFIG_2_SIZE_REG 0x4086468#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)6469#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)6470#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)6471#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)6472#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)6473#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)6474#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)6475#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)6476#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)6477#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)6478#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)6479#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)6480#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)6481#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)6482#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)6483#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)6484#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)6485#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)6486#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)6487#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)6488#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)6489#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)6490#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)6491#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)6492#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)6493#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)6494#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)6495#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)6496#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)6497#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)6498#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)6499#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)6500#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)6501#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)6502#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)6503#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)6504#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)6505#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)6506#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)6507#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)6508 6509/* config_3 offset */6510#define GRC_CONFIG_3_SIZE_REG 0x40c6511#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)6512#define PCI_CONFIG_3_FORCE_PME (1L<<24)6513#define PCI_CONFIG_3_PME_STATUS (1L<<25)6514#define PCI_CONFIG_3_PME_ENABLE (1L<<26)6515#define PCI_CONFIG_3_PM_STATE (0x3L<<27)6516#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)6517#define PCI_CONFIG_3_PCI_POWER (1L<<31)6518 6519#define GRC_BAR2_CONFIG 0x4e06520#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)6521#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)6522#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)6523#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)6524#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)6525#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)6526#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)6527#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)6528#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)6529#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)6530#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)6531#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)6532#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)6533#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)6534#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)6535#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)6536#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)6537#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)6538 6539#define PCI_PM_DATA_A 0x4106540#define PCI_PM_DATA_B 0x4146541#define PCI_ID_VAL1 0x4346542#define PCI_ID_VAL2 0x4386543#define PCI_ID_VAL3 0x43c6544 6545#define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C6546#define GRC_CONFIG_REG_PF_INIT_VF 0x6246547#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xf6548/* First VF_NUM for PF is encoded in this register.6549 * The number of VFs assigned to a PF is assumed to be a multiple of 8.6550 * Software should program these bits based on Total Number of VFs \6551 * programmed for each PF.6552 * Since registers from 0x000-0x7ff are split across functions, each PF will6553 * have the same location for the same 4 bits6554 */6555 6556#define PXPCS_TL_CONTROL_5 0x8146557#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/6558#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/6559#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/6560#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/6561#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/6562#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/6563#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/6564#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/6565#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/6566#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/6567#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/6568#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/6569#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/6570#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/6571#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/6572#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/6573#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/6574#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/6575#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/6576#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/6577#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/6578#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/6579#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/6580#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/6581#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/6582#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/6583#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/6584#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/6585#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/6586#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/6587 6588 6589#define PXPCS_TL_FUNC345_STAT 0x8546590#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */6591#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\6592 (1 << 28) /* Unsupported Request Error Status in function4, if \6593 set, generate pcie_err_attn output when this error is seen. WC */6594#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\6595 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \6596 generate pcie_err_attn output when this error is seen.. WC */6597#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\6598 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \6599 generate pcie_err_attn output when this error is seen.. WC */6600#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\6601 (1 << 25) /* Receiver Overflow Status Status in function 4, if \6602 set, generate pcie_err_attn output when this error is seen.. WC \6603 */6604#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\6605 (1 << 24) /* Unexpected Completion Status Status in function 4, \6606 if set, generate pcie_err_attn output when this error is seen. WC \6607 */6608#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\6609 (1 << 23) /* Receive UR Statusin function 4. If set, generate \6610 pcie_err_attn output when this error is seen. WC */6611#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\6612 (1 << 22) /* Completer Timeout Status Status in function 4, if \6613 set, generate pcie_err_attn output when this error is seen. WC */6614#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\6615 (1 << 21) /* Flow Control Protocol Error Status Status in \6616 function 4, if set, generate pcie_err_attn output when this error \6617 is seen. WC */6618#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\6619 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \6620 generate pcie_err_attn output when this error is seen.. WC */6621#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */6622#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\6623 (1 << 18) /* Unsupported Request Error Status in function3, if \6624 set, generate pcie_err_attn output when this error is seen. WC */6625#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\6626 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \6627 generate pcie_err_attn output when this error is seen.. WC */6628#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\6629 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \6630 generate pcie_err_attn output when this error is seen.. WC */6631#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\6632 (1 << 15) /* Receiver Overflow Status Status in function 3, if \6633 set, generate pcie_err_attn output when this error is seen.. WC \6634 */6635#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\6636 (1 << 14) /* Unexpected Completion Status Status in function 3, \6637 if set, generate pcie_err_attn output when this error is seen. WC \6638 */6639#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\6640 (1 << 13) /* Receive UR Statusin function 3. If set, generate \6641 pcie_err_attn output when this error is seen. WC */6642#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\6643 (1 << 12) /* Completer Timeout Status Status in function 3, if \6644 set, generate pcie_err_attn output when this error is seen. WC */6645#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\6646 (1 << 11) /* Flow Control Protocol Error Status Status in \6647 function 3, if set, generate pcie_err_attn output when this error \6648 is seen. WC */6649#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\6650 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \6651 generate pcie_err_attn output when this error is seen.. WC */6652#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */6653#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\6654 (1 << 8) /* Unsupported Request Error Status for Function 2, if \6655 set, generate pcie_err_attn output when this error is seen. WC */6656#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\6657 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \6658 generate pcie_err_attn output when this error is seen.. WC */6659#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\6660 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \6661 generate pcie_err_attn output when this error is seen.. WC */6662#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\6663 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \6664 set, generate pcie_err_attn output when this error is seen.. WC \6665 */6666#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\6667 (1 << 4) /* Unexpected Completion Status Status for Function 2, \6668 if set, generate pcie_err_attn output when this error is seen. WC \6669 */6670#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\6671 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \6672 pcie_err_attn output when this error is seen. WC */6673#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\6674 (1 << 2) /* Completer Timeout Status Status for Function 2, if \6675 set, generate pcie_err_attn output when this error is seen. WC */6676#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\6677 (1 << 1) /* Flow Control Protocol Error Status Status for \6678 Function 2, if set, generate pcie_err_attn output when this error \6679 is seen. WC */6680#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\6681 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \6682 generate pcie_err_attn output when this error is seen.. WC */6683 6684 6685#define PXPCS_TL_FUNC678_STAT 0x85C6686#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */6687#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\6688 (1 << 28) /* Unsupported Request Error Status in function7, if \6689 set, generate pcie_err_attn output when this error is seen. WC */6690#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\6691 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \6692 generate pcie_err_attn output when this error is seen.. WC */6693#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\6694 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \6695 generate pcie_err_attn output when this error is seen.. WC */6696#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\6697 (1 << 25) /* Receiver Overflow Status Status in function 7, if \6698 set, generate pcie_err_attn output when this error is seen.. WC \6699 */6700#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\6701 (1 << 24) /* Unexpected Completion Status Status in function 7, \6702 if set, generate pcie_err_attn output when this error is seen. WC \6703 */6704#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\6705 (1 << 23) /* Receive UR Statusin function 7. If set, generate \6706 pcie_err_attn output when this error is seen. WC */6707#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\6708 (1 << 22) /* Completer Timeout Status Status in function 7, if \6709 set, generate pcie_err_attn output when this error is seen. WC */6710#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\6711 (1 << 21) /* Flow Control Protocol Error Status Status in \6712 function 7, if set, generate pcie_err_attn output when this error \6713 is seen. WC */6714#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\6715 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \6716 generate pcie_err_attn output when this error is seen.. WC */6717#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */6718#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\6719 (1 << 18) /* Unsupported Request Error Status in function6, if \6720 set, generate pcie_err_attn output when this error is seen. WC */6721#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\6722 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \6723 generate pcie_err_attn output when this error is seen.. WC */6724#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\6725 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \6726 generate pcie_err_attn output when this error is seen.. WC */6727#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\6728 (1 << 15) /* Receiver Overflow Status Status in function 6, if \6729 set, generate pcie_err_attn output when this error is seen.. WC \6730 */6731#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\6732 (1 << 14) /* Unexpected Completion Status Status in function 6, \6733 if set, generate pcie_err_attn output when this error is seen. WC \6734 */6735#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\6736 (1 << 13) /* Receive UR Statusin function 6. If set, generate \6737 pcie_err_attn output when this error is seen. WC */6738#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\6739 (1 << 12) /* Completer Timeout Status Status in function 6, if \6740 set, generate pcie_err_attn output when this error is seen. WC */6741#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\6742 (1 << 11) /* Flow Control Protocol Error Status Status in \6743 function 6, if set, generate pcie_err_attn output when this error \6744 is seen. WC */6745#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\6746 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \6747 generate pcie_err_attn output when this error is seen.. WC */6748#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */6749#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\6750 (1 << 8) /* Unsupported Request Error Status for Function 5, if \6751 set, generate pcie_err_attn output when this error is seen. WC */6752#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\6753 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \6754 generate pcie_err_attn output when this error is seen.. WC */6755#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\6756 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \6757 generate pcie_err_attn output when this error is seen.. WC */6758#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\6759 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \6760 set, generate pcie_err_attn output when this error is seen.. WC \6761 */6762#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\6763 (1 << 4) /* Unexpected Completion Status Status for Function 5, \6764 if set, generate pcie_err_attn output when this error is seen. WC \6765 */6766#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\6767 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \6768 pcie_err_attn output when this error is seen. WC */6769#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\6770 (1 << 2) /* Completer Timeout Status Status for Function 5, if \6771 set, generate pcie_err_attn output when this error is seen. WC */6772#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\6773 (1 << 1) /* Flow Control Protocol Error Status Status for \6774 Function 5, if set, generate pcie_err_attn output when this error \6775 is seen. WC */6776#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\6777 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \6778 generate pcie_err_attn output when this error is seen.. WC */6779 6780 6781#define BAR_USTRORM_INTMEM 0x4000006782#define BAR_CSTRORM_INTMEM 0x4100006783#define BAR_XSTRORM_INTMEM 0x4200006784#define BAR_TSTRORM_INTMEM 0x4300006785 6786/* for accessing the IGU in case of status block ACK */6787#define BAR_IGU_INTMEM 0x4400006788 6789#define BAR_DOORBELL_OFFSET 0x8000006790 6791#define BAR_ME_REGISTER 0x4500006792#define ME_REG_PF_NUM_SHIFT 06793#define ME_REG_PF_NUM\6794 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */6795#define ME_REG_VF_VALID (1<<8)6796#define ME_REG_VF_NUM_SHIFT 96797#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)6798#define ME_REG_VF_ERR (0x1<<3)6799#define ME_REG_ABS_PF_NUM_SHIFT 166800#define ME_REG_ABS_PF_NUM\6801 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */6802 6803 6804#define PXP_VF_ADDR_IGU_START 06805#define PXP_VF_ADDR_IGU_SIZE 0x30006806#define PXP_VF_ADDR_IGU_END\6807 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)6808 6809#define PXP_VF_ADDR_USDM_QUEUES_START 0x30006810#define PXP_VF_ADDR_USDM_QUEUES_SIZE\6811 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)6812#define PXP_VF_ADDR_USDM_QUEUES_END\6813 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)6814 6815#define PXP_VF_ADDR_CSDM_GLOBAL_START 0x76006816#define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)6817#define PXP_VF_ADDR_CSDM_GLOBAL_END\6818 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)6819 6820#define PXP_VF_ADDR_DB_START 0x7c006821#define PXP_VF_ADDR_DB_SIZE 0x2006822#define PXP_VF_ADDR_DB_END\6823 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)6824 6825#define MDIO_REG_BANK_CL73_IEEEB0 0x06826#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x06827#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x02006828#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x10006829#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x80006830 6831#define MDIO_REG_BANK_CL73_IEEEB1 0x106832#define MDIO_CL73_IEEEB1_AN_ADV1 0x006833#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x04006834#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x08006835#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C006836#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C006837#define MDIO_CL73_IEEEB1_AN_ADV2 0x016838#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x00006839#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x00206840#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x00406841#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x00806842#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x036843#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x04006844#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x08006845#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C006846#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C006847#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x046848 6849#define MDIO_REG_BANK_RX0 0x80b06850#define MDIO_RX0_RX_STATUS 0x106851#define MDIO_RX0_RX_STATUS_SIGDET 0x80006852#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x10006853#define MDIO_RX0_RX_EQ_BOOST 0x1c6854#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x76855#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x106856 6857#define MDIO_REG_BANK_RX1 0x80c06858#define MDIO_RX1_RX_EQ_BOOST 0x1c6859#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x76860#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x106861 6862#define MDIO_REG_BANK_RX2 0x80d06863#define MDIO_RX2_RX_EQ_BOOST 0x1c6864#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x76865#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x106866 6867#define MDIO_REG_BANK_RX3 0x80e06868#define MDIO_RX3_RX_EQ_BOOST 0x1c6869#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x76870#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x106871 6872#define MDIO_REG_BANK_RX_ALL 0x80f06873#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c6874#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x76875#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x106876 6877#define MDIO_REG_BANK_TX0 0x80606878#define MDIO_TX0_TX_DRIVER 0x176879#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf0006880#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 126881#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f006882#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 86883#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f06884#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 46885#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e6886#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 16887#define MDIO_TX0_TX_DRIVER_ICBUF1T 16888 6889#define MDIO_REG_BANK_TX1 0x80706890#define MDIO_TX1_TX_DRIVER 0x176891#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf0006892#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 126893#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f006894#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 86895#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f06896#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 46897#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e6898#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 16899#define MDIO_TX0_TX_DRIVER_ICBUF1T 16900 6901#define MDIO_REG_BANK_TX2 0x80806902#define MDIO_TX2_TX_DRIVER 0x176903#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf0006904#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 126905#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f006906#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 86907#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f06908#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 46909#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e6910#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 16911#define MDIO_TX0_TX_DRIVER_ICBUF1T 16912 6913#define MDIO_REG_BANK_TX3 0x80906914#define MDIO_TX3_TX_DRIVER 0x176915#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf0006916#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 126917#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f006918#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 86919#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f06920#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 46921#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e6922#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 16923#define MDIO_TX0_TX_DRIVER_ICBUF1T 16924 6925#define MDIO_REG_BANK_XGXS_BLOCK0 0x80006926#define MDIO_BLOCK0_XGXS_CONTROL 0x106927 6928#define MDIO_REG_BANK_XGXS_BLOCK1 0x80106929#define MDIO_BLOCK1_LANE_CTRL0 0x156930#define MDIO_BLOCK1_LANE_CTRL1 0x166931#define MDIO_BLOCK1_LANE_CTRL2 0x176932#define MDIO_BLOCK1_LANE_PRBS 0x196933 6934#define MDIO_REG_BANK_XGXS_BLOCK2 0x81006935#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x106936#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x80006937#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x40006938#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x116939#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x80006940#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x146941#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x00016942#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x00106943#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x156944 6945#define MDIO_REG_BANK_GP_STATUS 0x81206946#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B6947#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x00016948#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x00026949#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x00046950#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x00086951#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x00106952#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x00206953#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x00406954#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x00806955#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f006956#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x00006957#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x01006958#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x02006959#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x03006960#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x04006961#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x05006962#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x06006963#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x07006964#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x08006965#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x09006966#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A006967#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B006968#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C006969#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D006970#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E006971#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F006972#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B006973#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E006974#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F006975#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x39006976 6977 6978#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x81306979#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x106980#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x80006981#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x116982#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x16983#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x136984#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)6985 6986#define MDIO_REG_BANK_SERDES_DIGITAL 0x83006987#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x106988#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x00016989#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x00026990#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x00046991#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x00086992#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x00106993#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x00206994#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x116995#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x00016996#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x00406997#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x146998#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x00016999#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x00027000#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x00047001#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x00187002#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 37003#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x00187004#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x00107005#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x00087006#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x00007007#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x157008#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x00027009#define MDIO_SERDES_DIGITAL_MISC1 0x187010#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE0007011#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x00007012#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x20007013#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x40007014#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x60007015#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x80007016#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x00107017#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f7018#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x00007019#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x00017020#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x00027021#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x00037022#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x00047023#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x00057024#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x00067025#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x00077026#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x00087027#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x00097028 7029#define MDIO_REG_BANK_OVER_1G 0x83207030#define MDIO_OVER_1G_DIGCTL_3_4 0x147031#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe07032#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 57033#define MDIO_OVER_1G_UP1 0x197034#define MDIO_OVER_1G_UP1_2_5G 0x00017035#define MDIO_OVER_1G_UP1_5G 0x00027036#define MDIO_OVER_1G_UP1_6G 0x00047037#define MDIO_OVER_1G_UP1_10G 0x00107038#define MDIO_OVER_1G_UP1_10GH 0x00087039#define MDIO_OVER_1G_UP1_12G 0x00207040#define MDIO_OVER_1G_UP1_12_5G 0x00407041#define MDIO_OVER_1G_UP1_13G 0x00807042#define MDIO_OVER_1G_UP1_15G 0x01007043#define MDIO_OVER_1G_UP1_16G 0x02007044#define MDIO_OVER_1G_UP2 0x1A7045#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x00077046#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x00387047#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C07048#define MDIO_OVER_1G_UP3 0x1B7049#define MDIO_OVER_1G_UP3_HIGIG2 0x00017050#define MDIO_OVER_1G_LP_UP1 0x1C7051#define MDIO_OVER_1G_LP_UP2 0x1D7052#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff7053#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x07807054#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 77055#define MDIO_OVER_1G_LP_UP3 0x1E7056 7057#define MDIO_REG_BANK_REMOTE_PHY 0x83307058#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x107059#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x00107060#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x06007061 7062#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x83507063#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x107064#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x00017065#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x00027066 7067#define MDIO_REG_BANK_CL73_USERB0 0x83707068#define MDIO_CL73_USERB0_CL73_UCTRL 0x107069#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x00027070#define MDIO_CL73_USERB0_CL73_USTAT1 0x117071#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x01007072#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x04007073#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x127074#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x80007075#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x40007076#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x20007077#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x147078#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x00017079 7080#define MDIO_REG_BANK_AER_BLOCK 0xFFD07081#define MDIO_AER_BLOCK_AER_REG 0x1E7082 7083#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE07084#define MDIO_COMBO_IEEE0_MII_CONTROL 0x107085#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x20407086#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x00007087#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x20007088#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x00407089#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x01007090#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x02007091#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x10007092#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x40007093#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x80007094#define MDIO_COMBO_IEEE0_MII_STATUS 0x117095#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x00047096#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x00207097#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x147098#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x00207099#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x00407100#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x01807101#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x00007102#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x00807103#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x01007104#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x01807105#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x80007106#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x157107#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x80007108#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x40007109#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x01807110#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x00007111#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x01807112#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x00407113#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x00207114/*WhenthelinkpartnerisinSGMIImode(bit0=1),then7115bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.7116Theotherbitsarereservedandshouldbezero*/7117#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x00017118 7119 7120#define MDIO_PMA_DEVAD 0x17121/*ieee*/7122#define MDIO_PMA_REG_CTRL 0x07123#define MDIO_PMA_REG_STATUS 0x17124#define MDIO_PMA_REG_10G_CTRL2 0x77125#define MDIO_PMA_REG_TX_DISABLE 0x00097126#define MDIO_PMA_REG_RX_SD 0xa7127/*bcm*/7128#define MDIO_PMA_REG_BCM_CTRL 0x00967129#define MDIO_PMA_REG_FEC_CTRL 0x00ab7130#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc8007131#define MDIO_PMA_REG_DIGITAL_CTRL 0xc8087132#define MDIO_PMA_REG_DIGITAL_STATUS 0xc8097133#define MDIO_PMA_REG_TX_POWER_DOWN 0xca027134#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca097135#define MDIO_PMA_REG_MISC_CTRL 0xca0a7136#define MDIO_PMA_REG_GEN_CTRL 0xca107137#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x01887138#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a7139#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca127140#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca137141#define MDIO_PMA_REG_ROM_VER1 0xca197142#define MDIO_PMA_REG_ROM_VER2 0xca1a7143#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b7144#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d7145#define MDIO_PMA_REG_PLL_CTRL 0xca1e7146#define MDIO_PMA_REG_MISC_CTRL0 0xca237147#define MDIO_PMA_REG_LRM_MODE 0xca3f7148#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca467149#define MDIO_PMA_REG_MISC_CTRL1 0xca857150 7151#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x80007152#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c7153#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x00007154#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x00047155#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x00087156#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c7157#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x80027158#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x80037159#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc8207160#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff7161#define MDIO_PMA_REG_8726_TX_CTRL1 0xca017162#define MDIO_PMA_REG_8726_TX_CTRL2 0xca057163 7164#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x80057165#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x80077166#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff7167#define MDIO_PMA_REG_8727_TX_CTRL1 0xca027168#define MDIO_PMA_REG_8727_TX_CTRL2 0xca057169#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc8087170#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e7171#define MDIO_PMA_REG_8727_PCS_GP 0xc8427172#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e47173 7174#define MDIO_AN_REG_8727_MISC_CTRL 0x83097175 7176#define MDIO_PMA_REG_8073_CHIP_REV 0xc8017177#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc8207178#define MDIO_PMA_REG_8073_XAUI_WA 0xc8417179#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd087180 7181#define MDIO_PMA_REG_7101_RESET 0xc0007182#define MDIO_PMA_REG_7107_LED_CNTL 0xc0077183#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc0097184#define MDIO_PMA_REG_7101_VER1 0xc0267185#define MDIO_PMA_REG_7101_VER2 0xc0277186 7187#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa8117188#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c7189#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f7190#define MDIO_PMA_REG_8481_LED3_MASK 0xa8327191#define MDIO_PMA_REG_8481_LED3_BLINK 0xa8347192#define MDIO_PMA_REG_8481_LED5_MASK 0xa8387193#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa8357194#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b7195#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x8007196#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 117197 7198 7199#define MDIO_WIS_DEVAD 0x27200/*bcm*/7201#define MDIO_WIS_REG_LASI_CNTL 0x90027202#define MDIO_WIS_REG_LASI_STATUS 0x90057203 7204#define MDIO_PCS_DEVAD 0x37205#define MDIO_PCS_REG_STATUS 0x00207206#define MDIO_PCS_REG_LASI_STATUS 0x90057207#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD0007208#define MDIO_PCS_REG_7101_SPI_MUX 0xD0087209#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A7210#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)7211#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A7212#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)7213#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)7214#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)7215#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE0287216 7217 7218#define MDIO_XS_DEVAD 0x47219#define MDIO_XS_PLL_SEQUENCER 0x80007220#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a7221 7222#define MDIO_XS_8706_REG_BANK_RX0 0x80bc7223#define MDIO_XS_8706_REG_BANK_RX1 0x80cc7224#define MDIO_XS_8706_REG_BANK_RX2 0x80dc7225#define MDIO_XS_8706_REG_BANK_RX3 0x80ec7226#define MDIO_XS_8706_REG_BANK_RXA 0x80fc7227 7228#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA7229 7230#define MDIO_AN_DEVAD 0x77231/*ieee*/7232#define MDIO_AN_REG_CTRL 0x00007233#define MDIO_AN_REG_STATUS 0x00017234#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x00207235#define MDIO_AN_REG_ADV_PAUSE 0x00107236#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x04007237#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x08007238#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C007239#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C007240#define MDIO_AN_REG_ADV 0x00117241#define MDIO_AN_REG_ADV2 0x00127242#define MDIO_AN_REG_LP_AUTO_NEG 0x00137243#define MDIO_AN_REG_LP_AUTO_NEG2 0x00147244#define MDIO_AN_REG_MASTER_STATUS 0x00217245#define MDIO_AN_REG_EEE_ADV 0x003c7246#define MDIO_AN_REG_LP_EEE_ADV 0x003d7247/*bcm*/7248#define MDIO_AN_REG_LINK_STATUS 0x83047249#define MDIO_AN_REG_CL37_CL73 0x83707250#define MDIO_AN_REG_CL37_AN 0xffe07251#define MDIO_AN_REG_CL37_FC_LD 0xffe47252#define MDIO_AN_REG_CL37_FC_LP 0xffe57253#define MDIO_AN_REG_1000T_STATUS 0xffea7254 7255#define MDIO_AN_REG_8073_2_5G 0x83297256#define MDIO_AN_REG_8073_BAM 0x83507257 7258#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x00207259#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe07260#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x407261#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe17262#define MDIO_AN_REG_848xx_ID_MSB 0xffe27263#define BCM84858_PHY_ID 0x600d7264#define MDIO_AN_REG_848xx_ID_LSB 0xffe37265#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe47266#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe67267#define MDIO_AN_REG_8481_1000T_CTRL 0xffe97268#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff07269#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x00087270#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff57271#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff77272#define MDIO_AN_REG_8481_AUX_CTRL 0xfff87273#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc7274 7275/* BCM84823 only */7276#define MDIO_CTL_DEVAD 0x1e7277#define MDIO_CTL_REG_84823_MEDIA 0x401a7278#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x00187279 /* These pins configure the BCM84823 interface to MAC after reset. */7280#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x00087281#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x00107282 /* These pins configure the BCM84823 interface to Line after reset. */7283#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x00607284#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x00207285#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x00407286 /* When this pin is active high during reset, 10GBASE-T core is power7287 * down, When it is active low the 10GBASE-T is power up7288 */7289#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x00807290#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x01007291#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x00007292#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x01007293#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x10007294#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x40057295#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x00807296#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b7297#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f7298#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e37299#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec7300#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x00807301/* BCM84858 only */7302#define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT 0x80007303 7304/* BCM84833 only */7305#define MDIO_84833_TOP_CFG_FW_REV 0x400f7306#define MDIO_84833_TOP_CFG_FW_EEE 0x10b17307#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f817308#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a7309#define MDIO_84833_SUPER_ISOLATE 0x80007310/* These are mailbox register set used by 84833/84858. */7311#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x40057312#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x40067313#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x40077314#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x40087315#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x40097316#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x40377317#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x40387318#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x40397319#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a7320#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b7321#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c7322#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)7323#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)7324#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)7325#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)7326#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)7327#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)7328#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)7329 7330/* Mailbox command set used by 84833/84858 */7331#define PHY848xx_CMD_SET_PAIR_SWAP 0x80017332#define PHY848xx_CMD_GET_EEE_MODE 0x80087333#define PHY848xx_CMD_SET_EEE_MODE 0x80097334/* Mailbox status set used by 84833 only */7335#define PHY84833_STATUS_CMD_RECEIVED 0x00017336#define PHY84833_STATUS_CMD_IN_PROGRESS 0x00027337#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x00047338#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x00087339#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x00107340#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x00207341#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x00407342#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x00807343#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a57344/* Mailbox Process */7345#define PHY84833_MB_PROCESS1 17346#define PHY84833_MB_PROCESS2 27347#define PHY84833_MB_PROCESS3 37348 7349/* Mailbox status set used by 84858 only */7350#define PHY84858_STATUS_CMD_RECEIVED 0x00017351#define PHY84858_STATUS_CMD_IN_PROGRESS 0x00027352#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x00047353#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x00087354#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb7355 7356 7357/* Warpcore clause 45 addressing */7358#define MDIO_WC_DEVAD 0x37359#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x07360#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x77361#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x107362#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x117363#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x127364#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x40007365#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x80007366#define MDIO_WC_REG_PCS_STATUS2 0x00217367#define MDIO_WC_REG_PMD_KR_CONTROL 0x00967368#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x80007369#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e7370#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x80107371#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x80157372#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x80167373#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x80177374#define MDIO_WC_REG_TX0_ANA_CTRL0 0x80617375#define MDIO_WC_REG_TX1_ANA_CTRL0 0x80717376#define MDIO_WC_REG_TX2_ANA_CTRL0 0x80817377#define MDIO_WC_REG_TX3_ANA_CTRL0 0x80917378#define MDIO_WC_REG_TX0_TX_DRIVER 0x80677379#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x017380#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e7381#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x047382#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f07383#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x087384#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f007385#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c7386#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x70007387#define MDIO_WC_REG_TX1_TX_DRIVER 0x80777388#define MDIO_WC_REG_TX2_TX_DRIVER 0x80877389#define MDIO_WC_REG_TX3_TX_DRIVER 0x80977390#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b97391#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d97392#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba7393#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca7394#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da7395#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea7396#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa7397#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x81047398#define MDIO_WC_REG_XGXS_STATUS3 0x81297399#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x81307400#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x81317401#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x81417402#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x81427403#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B7404#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x81697405#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d07406#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d17407#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d27408#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d37409#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d47410#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x10007411#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x01007412#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x00107413#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x17414#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE7415#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F07416#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F27417#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x07418#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x07419#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x17420#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x27421#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x37422#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x47423#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x47424#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x87425#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc7426#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE7427#define MDIO_WC_REG_DSC_SMC 0x82137428#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e7429#define MDIO_WC_REG_TX_FIR_TAP 0x82e27430#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x007431#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f7432#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x047433#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f07434#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a7435#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c007436#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x80007437#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e27438#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e37439#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e67440#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e77441#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e87442#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec7443#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x83007444#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x83017445#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x83027446#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x83047447#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x83087448#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x83097449#define MDIO_WC_REG_DIGITAL3_UP1 0x83297450#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c7451#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c7452#define MDIO_WC_REG_DIGITAL4_MISC5 0x833e7453#define MDIO_WC_REG_DIGITAL5_MISC6 0x83457454#define MDIO_WC_REG_DIGITAL5_MISC7 0x83497455#define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d7456#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e7457#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x83507458#define MDIO_WC_REG_CL49_USERB0_CTRL 0x83687459#define MDIO_WC_REG_CL73_USERB0_CTRL 0x83707460#define MDIO_WC_REG_CL73_USERB0_USTAT 0x83717461#define MDIO_WC_REG_CL73_BAM_CTRL1 0x83727462#define MDIO_WC_REG_CL73_BAM_CTRL2 0x83737463#define MDIO_WC_REG_CL73_BAM_CTRL3 0x83747464#define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b7465#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x83907466#define MDIO_WC_REG_TX66_CONTROL 0x83b07467#define MDIO_WC_REG_RX66_CONTROL 0x83c07468#define MDIO_WC_REG_RX66_SCW0 0x83c27469#define MDIO_WC_REG_RX66_SCW1 0x83c37470#define MDIO_WC_REG_RX66_SCW2 0x83c47471#define MDIO_WC_REG_RX66_SCW3 0x83c57472#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c67473#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c77474#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c87475#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c97476#define MDIO_WC_REG_FX100_CTRL1 0x84007477#define MDIO_WC_REG_FX100_CTRL3 0x84027478#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x84367479#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x84377480#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x84387481#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x84397482#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a7483#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b7484#define MDIO_WC_REG_ETA_CL73_OUI1 0x84537485#define MDIO_WC_REG_ETA_CL73_OUI2 0x84547486#define MDIO_WC_REG_ETA_CL73_OUI3 0x84557487#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x84567488#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x84577489#define MDIO_WC_REG_MICROBLK_CMD 0xffc27490#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc57491#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc7492 7493#define MDIO_WC_REG_AERBLK_AER 0xffde7494#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe07495#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe17496 7497#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A7498#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 07499#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 47500 7501#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x81417502 7503#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f7504 7505/* 54618se */7506#define MDIO_REG_GPHY_PHYID_LSB 0x37507#define MDIO_REG_GPHY_ID_54618SE 0x5cd57508#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd7509#define MDIO_REG_GPHY_CL45_DATA_REG 0xe7510#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e7511#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x157512#define MDIO_REG_GPHY_EXP_ACCESS 0x177513#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd007514#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x407515#define MDIO_REG_GPHY_AUX_STATUS 0x197516#define MDIO_REG_INTR_STATUS 0x1a7517#define MDIO_REG_INTR_MASK 0x1b7518#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)7519#define MDIO_REG_GPHY_SHADOW 0x1c7520#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)7521#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)7522#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)7523#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)7524#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)7525 7526#define IGU_FUNC_BASE 0x04007527 7528#define IGU_ADDR_MSIX 0x00007529#define IGU_ADDR_INT_ACK 0x02007530#define IGU_ADDR_PROD_UPD 0x02017531#define IGU_ADDR_ATTN_BITS_UPD 0x02027532#define IGU_ADDR_ATTN_BITS_SET 0x02037533#define IGU_ADDR_ATTN_BITS_CLR 0x02047534#define IGU_ADDR_COALESCE_NOW 0x02057535#define IGU_ADDR_SIMD_MASK 0x02067536#define IGU_ADDR_SIMD_NOMASK 0x02077537#define IGU_ADDR_MSI_CTL 0x02107538#define IGU_ADDR_MSI_ADDR_LO 0x02117539#define IGU_ADDR_MSI_ADDR_HI 0x02127540#define IGU_ADDR_MSI_DATA 0x02137541 7542#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 07543#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 17544#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 27545#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 37546 7547#define COMMAND_REG_INT_ACK 0x07548#define COMMAND_REG_PROD_UPD 0x47549#define COMMAND_REG_ATTN_BITS_UPD 0x87550#define COMMAND_REG_ATTN_BITS_SET 0xc7551#define COMMAND_REG_ATTN_BITS_CLR 0x107552#define COMMAND_REG_COALESCE_NOW 0x147553#define COMMAND_REG_SIMD_MASK 0x187554#define COMMAND_REG_SIMD_NOMASK 0x1c7555 7556 7557#define IGU_MEM_BASE 0x00007558 7559#define IGU_MEM_MSIX_BASE 0x00007560#define IGU_MEM_MSIX_UPPER 0x007f7561#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff7562 7563#define IGU_MEM_PBA_MSIX_BASE 0x02007564#define IGU_MEM_PBA_MSIX_UPPER 0x02007565 7566#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x02017567#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff7568 7569#define IGU_CMD_INT_ACK_BASE 0x04007570#define IGU_CMD_INT_ACK_UPPER\7571 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)7572#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff7573 7574#define IGU_CMD_E2_PROD_UPD_BASE 0x05007575#define IGU_CMD_E2_PROD_UPD_UPPER\7576 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)7577#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f7578 7579#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a07580#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a17581#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a27582 7583#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a37584#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a47585#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a57586#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a67587 7588#define IGU_REG_RESERVED_UPPER 0x05ff7589/* Fields of IGU PF CONFIGURATION REGISTER */7590#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */7591#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */7592#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */7593#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */7594#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */7595#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */7596 7597/* Fields of IGU VF CONFIGURATION REGISTER */7598#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */7599#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */7600#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */7601#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */7602#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */7603 7604 7605#define IGU_BC_DSB_NUM_SEGS 57606#define IGU_BC_NDSB_NUM_SEGS 27607#define IGU_NORM_DSB_NUM_SEGS 27608#define IGU_NORM_NDSB_NUM_SEGS 17609#define IGU_BC_BASE_DSB_PROD 1287610#define IGU_NORM_BASE_DSB_PROD 1367611 7612 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \7613 [5:2] = 0; [1:0] = PF number) */7614#define IGU_FID_ENCODE_IS_PF (0x1<<6)7615#define IGU_FID_ENCODE_IS_PF_SHIFT 67616#define IGU_FID_VF_NUM_MASK (0x3f)7617#define IGU_FID_PF_NUM_MASK (0x7)7618 7619#define IGU_REG_MAPPING_MEMORY_VALID (1<<0)7620#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)7621#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 17622#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)7623#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 77624 7625 7626#define CDU_REGION_NUMBER_XCM_AG 27627#define CDU_REGION_NUMBER_UCM_AG 47628 7629 7630/* String-to-compress [31:8] = CID (all 24 bits)7631 * String-to-compress [7:4] = Region7632 * String-to-compress [3:0] = Type7633 */7634#define CDU_VALID_DATA(_cid, _region, _type)\7635 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))7636#define CDU_CRC8(_cid, _region, _type)\7637 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))7638#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\7639 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))7640#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\7641 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))7642#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)7643 7644/* IdleChk registers */7645#define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc7646#define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b87647#define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e07648#define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc7649#define PXP2_REG_RD_CPL_ERR_DETAILS 0x1207787650#define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c7651#define PXP2_REG_RQ_GARB 0x1207487652#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc7653#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c07654#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c47655#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c87656#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc7657#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d07658#define PBF_REG_CREDIT_Q2 0x1403447659#define PBF_REG_CREDIT_Q3 0x1403487660#define PBF_REG_CREDIT_Q4 0x14034c7661#define PBF_REG_CREDIT_Q5 0x1403507662#define PBF_REG_INIT_CRD_Q2 0x15c2387663#define PBF_REG_INIT_CRD_Q3 0x15c23c7664#define PBF_REG_INIT_CRD_Q4 0x15c2407665#define PBF_REG_INIT_CRD_Q5 0x15c2447666#define PBF_REG_TASK_CNT_Q0 0x1403747667#define PBF_REG_TASK_CNT_Q1 0x1403787668#define PBF_REG_TASK_CNT_Q2 0x14037c7669#define PBF_REG_TASK_CNT_Q3 0x1403807670#define PBF_REG_TASK_CNT_Q4 0x1403847671#define PBF_REG_TASK_CNT_Q5 0x1403887672#define PBF_REG_TASK_CNT_LB_Q 0x1403707673#define QM_REG_BYTECRD0 0x16e6fc7674#define QM_REG_BYTECRD1 0x16e7007675#define QM_REG_BYTECRD2 0x16e7047676#define QM_REG_BYTECRD3 0x16e7ac7677#define QM_REG_BYTECRD4 0x16e7b07678#define QM_REG_BYTECRD5 0x16e7b47679#define QM_REG_BYTECRD6 0x16e7b87680#define QM_REG_BYTECRDCMDQ_0 0x16e6e87681#define QM_REG_BYTECRDERRREG 0x16e7087682#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa7147683#define QM_REG_VOQCREDIT_2 0x1682d87684#define QM_REG_VOQCREDIT_3 0x1682dc7685#define QM_REG_VOQCREDIT_5 0x1682e47686#define QM_REG_VOQCREDIT_6 0x1682e87687#define QM_REG_VOQINITCREDIT_3 0x16806c7688#define QM_REG_VOQINITCREDIT_6 0x1680787689#define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc7690#define QM_REG_FWVOQ1TOHWVOQ 0x16e7c07691#define QM_REG_FWVOQ2TOHWVOQ 0x16e7c47692#define QM_REG_FWVOQ3TOHWVOQ 0x16e7c87693#define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc7694#define QM_REG_FWVOQ5TOHWVOQ 0x16e7d07695#define QM_REG_FWVOQ6TOHWVOQ 0x16e7d47696#define QM_REG_FWVOQ7TOHWVOQ 0x16e7d87697#define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec7698#define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f87699#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x105307700#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x105387701#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x105087702#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x104607703#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x104747704#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x104187705#define NIG_REG_EGRESS_DELAY0_EMPTY 0x104207706#define NIG_REG_EGRESS_DELAY1_EMPTY 0x104287707#define NIG_REG_LLH0_FIFO_EMPTY 0x105487708#define NIG_REG_LLH1_FIFO_EMPTY 0x105587709#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a87710#define NIG_REG_P0_TLLH_FIFO_EMPTY 0x183087711#define NIG_REG_P0_HBUF_DSCR_EMPTY 0x183187712#define NIG_REG_P1_HBUF_DSCR_EMPTY 0x183487713#define NIG_REG_P0_RX_MACFIFO_EMPTY 0x185707714#define NIG_REG_P0_TX_MACFIFO_EMPTY 0x185787715#define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c7716#define NIG_REG_EGRESS_DELAY3_EMPTY 0x186307717#define NIG_REG_EGRESS_DELAY4_EMPTY 0x186347718#define NIG_REG_EGRESS_DELAY5_EMPTY 0x186387719 7720/******************************************************************************7721 * Description:7722 * Calculates crc 8 on a word value: polynomial 0-1-2-87723 * Code was translated from Verilog.7724 * Return:7725 *****************************************************************************/7726static inline u8 calc_crc8(u32 data, u8 crc)7727{7728 u8 D[32];7729 u8 NewCRC[8];7730 u8 C[8];7731 u8 crc_res;7732 u8 i;7733 7734 /* split the data into 31 bits */7735 for (i = 0; i < 32; i++) {7736 D[i] = (u8)(data & 1);7737 data = data >> 1;7738 }7739 7740 /* split the crc into 8 bits */7741 for (i = 0; i < 8; i++) {7742 C[i] = crc & 1;7743 crc = crc >> 1;7744 }7745 7746 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^7747 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^7748 C[6] ^ C[7];7749 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^7750 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^7751 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^7752 C[6];7753 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^7754 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^7755 C[0] ^ C[1] ^ C[4] ^ C[5];7756 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^7757 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^7758 C[1] ^ C[2] ^ C[5] ^ C[6];7759 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^7760 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^7761 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];7762 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^7763 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^7764 C[3] ^ C[4] ^ C[7];7765 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^7766 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^7767 C[5];7768 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^7769 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^7770 C[6];7771 7772 crc_res = 0;7773 for (i = 0; i < 8; i++)7774 crc_res |= (NewCRC[i] << i);7775 7776 return crc_res;7777}7778#endif /* BNX2X_REG_H */7779