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1/* Broadcom NetXtreme-C/E network driver.2 *3 * Copyright (c) 2014-2016 Broadcom Corporation4 * Copyright (c) 2016-2018 Broadcom Limited5 *6 * This program is free software; you can redistribute it and/or modify7 * it under the terms of the GNU General Public License as published by8 * the Free Software Foundation.9 */10 11#ifndef BNXT_H12#define BNXT_H13 14#define DRV_MODULE_NAME		"bnxt_en"15 16/* DO NOT CHANGE DRV_VER_* defines17 * FIXME: Delete them18 */19#define DRV_VER_MAJ	120#define DRV_VER_MIN	1021#define DRV_VER_UPD	322 23#include <linux/ethtool.h>24#include <linux/interrupt.h>25#include <linux/rhashtable.h>26#include <linux/crash_dump.h>27#include <linux/auxiliary_bus.h>28#include <net/devlink.h>29#include <net/dst_metadata.h>30#include <net/xdp.h>31#include <linux/dim.h>32#include <linux/io-64-nonatomic-lo-hi.h>33#ifdef CONFIG_TEE_BNXT_FW34#include <linux/firmware/broadcom/tee_bnxt_fw.h>35#endif36 37extern struct list_head bnxt_block_cb_list;38 39struct page_pool;40 41struct tx_bd {42	__le32 tx_bd_len_flags_type;43	#define TX_BD_TYPE					(0x3f << 0)44	 #define TX_BD_TYPE_SHORT_TX_BD				 (0x00 << 0)45	 #define TX_BD_TYPE_LONG_TX_BD				 (0x10 << 0)46	#define TX_BD_FLAGS_PACKET_END				(1 << 6)47	#define TX_BD_FLAGS_NO_CMPL				(1 << 7)48	#define TX_BD_FLAGS_BD_CNT				(0x1f << 8)49	 #define TX_BD_FLAGS_BD_CNT_SHIFT			 850	#define TX_BD_FLAGS_LHINT				(3 << 13)51	 #define TX_BD_FLAGS_LHINT_SHIFT			 1352	 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER		 (0 << 13)53	 #define TX_BD_FLAGS_LHINT_512_TO_1023			 (1 << 13)54	 #define TX_BD_FLAGS_LHINT_1024_TO_2047			 (2 << 13)55	 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER		 (3 << 13)56	#define TX_BD_FLAGS_COAL_NOW				(1 << 15)57	#define TX_BD_LEN					(0xffff << 16)58	 #define TX_BD_LEN_SHIFT				 1659 60	u32 tx_bd_opaque;61	__le64 tx_bd_haddr;62} __packed;63 64#define TX_OPAQUE_IDX_MASK	0x0000ffff65#define TX_OPAQUE_BDS_MASK	0x00ff000066#define TX_OPAQUE_BDS_SHIFT	1667#define TX_OPAQUE_RING_MASK	0xff00000068#define TX_OPAQUE_RING_SHIFT	2469 70#define SET_TX_OPAQUE(bp, txr, idx, bds)				\71	(((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) |			\72	 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))73 74#define TX_OPAQUE_IDX(opq)	((opq) & TX_OPAQUE_IDX_MASK)75#define TX_OPAQUE_RING(opq)	(((opq) & TX_OPAQUE_RING_MASK) >>	\76				 TX_OPAQUE_RING_SHIFT)77#define TX_OPAQUE_BDS(opq)	(((opq) & TX_OPAQUE_BDS_MASK) >>	\78				 TX_OPAQUE_BDS_SHIFT)79#define TX_OPAQUE_PROD(bp, opq)	((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\80				 (bp)->tx_ring_mask)81 82struct tx_bd_ext {83	__le32 tx_bd_hsize_lflags;84	#define TX_BD_FLAGS_TCP_UDP_CHKSUM			(1 << 0)85	#define TX_BD_FLAGS_IP_CKSUM				(1 << 1)86	#define TX_BD_FLAGS_NO_CRC				(1 << 2)87	#define TX_BD_FLAGS_STAMP				(1 << 3)88	#define TX_BD_FLAGS_T_IP_CHKSUM				(1 << 4)89	#define TX_BD_FLAGS_LSO					(1 << 5)90	#define TX_BD_FLAGS_IPID_FMT				(1 << 6)91	#define TX_BD_FLAGS_T_IPID				(1 << 7)92	#define TX_BD_HSIZE					(0xff << 16)93	 #define TX_BD_HSIZE_SHIFT				 1694 95	__le32 tx_bd_mss;96	__le32 tx_bd_cfa_action;97	#define TX_BD_CFA_ACTION				(0xffff << 16)98	 #define TX_BD_CFA_ACTION_SHIFT				 1699 100	__le32 tx_bd_cfa_meta;101	#define TX_BD_CFA_META_MASK                             0xfffffff102	#define TX_BD_CFA_META_VID_MASK                         0xfff103	#define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)104	 #define TX_BD_CFA_META_PRI_SHIFT                        12105	#define TX_BD_CFA_META_TPID_MASK                        (3 << 16)106	 #define TX_BD_CFA_META_TPID_SHIFT                       16107	#define TX_BD_CFA_META_KEY                              (0xf << 28)108	 #define TX_BD_CFA_META_KEY_SHIFT			 28109	#define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)110};111 112#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))113 114struct rx_bd {115	__le32 rx_bd_len_flags_type;116	#define RX_BD_TYPE					(0x3f << 0)117	 #define RX_BD_TYPE_RX_PACKET_BD			 0x4118	 #define RX_BD_TYPE_RX_BUFFER_BD			 0x5119	 #define RX_BD_TYPE_RX_AGG_BD				 0x6120	 #define RX_BD_TYPE_16B_BD_SIZE				 (0 << 4)121	 #define RX_BD_TYPE_32B_BD_SIZE				 (1 << 4)122	 #define RX_BD_TYPE_48B_BD_SIZE				 (2 << 4)123	 #define RX_BD_TYPE_64B_BD_SIZE				 (3 << 4)124	#define RX_BD_FLAGS_SOP					(1 << 6)125	#define RX_BD_FLAGS_EOP					(1 << 7)126	#define RX_BD_FLAGS_BUFFERS				(3 << 8)127	 #define RX_BD_FLAGS_1_BUFFER_PACKET			 (0 << 8)128	 #define RX_BD_FLAGS_2_BUFFER_PACKET			 (1 << 8)129	 #define RX_BD_FLAGS_3_BUFFER_PACKET			 (2 << 8)130	 #define RX_BD_FLAGS_4_BUFFER_PACKET			 (3 << 8)131	#define RX_BD_LEN					(0xffff << 16)132	 #define RX_BD_LEN_SHIFT				 16133 134	u32 rx_bd_opaque;135	__le64 rx_bd_haddr;136};137 138struct tx_cmp {139	__le32 tx_cmp_flags_type;140	#define CMP_TYPE					(0x3f << 0)141	 #define CMP_TYPE_TX_L2_CMP				 0142	 #define CMP_TYPE_TX_L2_COAL_CMP			 2143	 #define CMP_TYPE_TX_L2_PKT_TS_CMP			 4144	 #define CMP_TYPE_RX_L2_CMP				 17145	 #define CMP_TYPE_RX_AGG_CMP				 18146	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19147	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21148	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22149	 #define CMP_TYPE_RX_L2_V3_CMP				 23150	 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP		 25151	 #define CMP_TYPE_STATUS_CMP				 32152	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34153	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36154	 #define CMP_TYPE_ERROR_STATUS				 48155	 #define CMPL_BASE_TYPE_STAT_EJECT			 0x1aUL156	 #define CMPL_BASE_TYPE_HWRM_DONE			 0x20UL157	 #define CMPL_BASE_TYPE_HWRM_FWD_REQ			 0x22UL158	 #define CMPL_BASE_TYPE_HWRM_FWD_RESP			 0x24UL159	 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT		 0x2eUL160 161	#define TX_CMP_FLAGS_ERROR				(1 << 6)162	#define TX_CMP_FLAGS_PUSH				(1 << 7)163 164	u32 tx_cmp_opaque;165	__le32 tx_cmp_errors_v;166	#define TX_CMP_V					(1 << 0)167	#define TX_CMP_ERRORS_BUFFER_ERROR			(7 << 1)168	 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR		 0169	 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT		 2170	 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG	 4171	 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS		 5172	 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT			 (1 << 4)173	 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN			 (1 << 5)174	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 << 6)175	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 << 7)176 177	__le32 sq_cons_idx;178	#define TX_CMP_SQ_CONS_IDX_MASK				0x00ffffff179};180 181#define TX_CMP_SQ_CONS_IDX(txcmp)					\182	(le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)183 184struct tx_ts_cmp {185	__le32 tx_ts_cmp_flags_type;186	#define TX_TS_CMP_FLAGS_ERROR				(1 << 6)187	#define TX_TS_CMP_FLAGS_TS_TYPE				(1 << 7)188	 #define TX_TS_CMP_FLAGS_TS_TYPE_PM			 (0 << 7)189	 #define TX_TS_CMP_FLAGS_TS_TYPE_PA			 (1 << 7)190	#define TX_TS_CMP_FLAGS_TS_FALLBACK			(1 << 8)191	#define TX_TS_CMP_TS_SUB_NS				(0xf << 12)192	#define TX_TS_CMP_TS_NS_MID				(0xffff << 16)193	#define TX_TS_CMP_TS_NS_MID_SFT				16194	u32 tx_ts_cmp_opaque;195	__le32 tx_ts_cmp_errors_v;196	#define TX_TS_CMP_V					(1 << 0)197	#define TX_TS_CMP_TS_INVALID_ERR			(1 << 10)198	__le32 tx_ts_cmp_ts_ns_lo;199};200 201#define BNXT_GET_TX_TS_48B_NS(tscmp)					\202	(le32_to_cpu((tscmp)->tx_ts_cmp_ts_ns_lo) |			\203	 ((u64)(le32_to_cpu((tscmp)->tx_ts_cmp_flags_type) &		\204	  TX_TS_CMP_TS_NS_MID) << TX_TS_CMP_TS_NS_MID_SFT))205 206#define BNXT_TX_TS_ERR(tscmp)						\207	(((tscmp)->tx_ts_cmp_flags_type & cpu_to_le32(TX_TS_CMP_FLAGS_ERROR)) &&\208	 ((tscmp)->tx_ts_cmp_errors_v & cpu_to_le32(TX_TS_CMP_TS_INVALID_ERR)))209 210struct rx_cmp {211	__le32 rx_cmp_len_flags_type;212	#define RX_CMP_CMP_TYPE					(0x3f << 0)213	#define RX_CMP_FLAGS_ERROR				(1 << 6)214	#define RX_CMP_FLAGS_PLACEMENT				(7 << 7)215	#define RX_CMP_FLAGS_RSS_VALID				(1 << 10)216	#define RX_CMP_FLAGS_PKT_METADATA_PRESENT		(1 << 11)217	 #define RX_CMP_FLAGS_ITYPES_SHIFT			 12218	 #define RX_CMP_FLAGS_ITYPES_MASK			 0xf000219	 #define RX_CMP_FLAGS_ITYPE_UNKNOWN			 (0 << 12)220	 #define RX_CMP_FLAGS_ITYPE_IP				 (1 << 12)221	 #define RX_CMP_FLAGS_ITYPE_TCP				 (2 << 12)222	 #define RX_CMP_FLAGS_ITYPE_UDP				 (3 << 12)223	 #define RX_CMP_FLAGS_ITYPE_FCOE			 (4 << 12)224	 #define RX_CMP_FLAGS_ITYPE_ROCE			 (5 << 12)225	 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS			 (8 << 12)226	 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS			 (9 << 12)227	#define RX_CMP_LEN					(0xffff << 16)228	 #define RX_CMP_LEN_SHIFT				 16229 230	u32 rx_cmp_opaque;231	__le32 rx_cmp_misc_v1;232	#define RX_CMP_V1					(1 << 0)233	#define RX_CMP_AGG_BUFS					(0x1f << 1)234	 #define RX_CMP_AGG_BUFS_SHIFT				 1235	#define RX_CMP_RSS_HASH_TYPE				(0x7f << 9)236	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9237	#define RX_CMP_V3_RSS_EXT_OP_LEGACY			(0xf << 12)238	 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT		 12239	#define RX_CMP_V3_RSS_EXT_OP_NEW			(0xf << 8)240	 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT			 8241	#define RX_CMP_PAYLOAD_OFFSET				(0xff << 16)242	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16243	#define RX_CMP_SUB_NS_TS				(0xf << 16)244	 #define RX_CMP_SUB_NS_TS_SHIFT				 16245	#define RX_CMP_METADATA1				(0xf << 28)246	 #define RX_CMP_METADATA1_SHIFT				 28247	#define RX_CMP_METADATA1_TPID_SEL			(0x7 << 28)248	#define RX_CMP_METADATA1_TPID_8021Q			(0x1 << 28)249	#define RX_CMP_METADATA1_TPID_8021AD			(0x0 << 28)250	#define RX_CMP_METADATA1_VALID				(0x8 << 28)251 252	__le32 rx_cmp_rss_hash;253};254 255#define BNXT_PTP_RX_TS_VALID(flags)				\256	(((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)257 258#define BNXT_ALL_RX_TS_VALID(flags)				\259	!((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)260 261#define RX_CMP_HASH_VALID(rxcmp)				\262	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))263 264#define RSS_PROFILE_ID_MASK	0x1f265 266#define RX_CMP_HASH_TYPE(rxcmp)					\267	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\268	  RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)269 270#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp)				\271	((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\272	 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)273 274#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp)				\275	((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\276	 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)277 278#define RX_CMP_V3_HASH_TYPE(bp, rxcmp)				\279	(((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ?		\280	  RX_CMP_V3_HASH_TYPE_NEW(rxcmp) :			\281	  RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))282 283#define EXT_OP_INNER_4		0x0284#define EXT_OP_OUTER_4		0x2285#define EXT_OP_INNFL_3		0x8286#define EXT_OP_OUTFL_3		0xa287 288#define RX_CMP_VLAN_VALID(rxcmp)				\289	((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))290 291#define RX_CMP_VLAN_TPID_SEL(rxcmp)				\292	(le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)293 294struct rx_cmp_ext {295	__le32 rx_cmp_flags2;296	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1297	#define RX_CMP_FLAGS2_L4_CS_CALC			(0x1 << 1)298	#define RX_CMP_FLAGS2_T_IP_CS_CALC			(0x1 << 2)299	#define RX_CMP_FLAGS2_T_L4_CS_CALC			(0x1 << 3)300	#define RX_CMP_FLAGS2_META_FORMAT_VLAN			(0x1 << 4)301	__le32 rx_cmp_meta_data;302	#define RX_CMP_FLAGS2_METADATA_TCI_MASK			0xffff303	#define RX_CMP_FLAGS2_METADATA_VID_MASK			0xfff304	#define RX_CMP_FLAGS2_METADATA_TPID_MASK		0xffff0000305	 #define RX_CMP_FLAGS2_METADATA_TPID_SFT		 16306	__le32 rx_cmp_cfa_code_errors_v2;307	#define RX_CMP_V					(1 << 0)308	#define RX_CMPL_ERRORS_MASK				(0x7fff << 1)309	 #define RX_CMPL_ERRORS_SFT				 1310	#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK		(0x7 << 1)311	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER		 (0x0 << 1)312	 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT	 (0x1 << 1)313	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)314	 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT		 (0x3 << 1)315	#define RX_CMPL_ERRORS_IP_CS_ERROR			(0x1 << 4)316	#define RX_CMPL_ERRORS_L4_CS_ERROR			(0x1 << 5)317	#define RX_CMPL_ERRORS_T_IP_CS_ERROR			(0x1 << 6)318	#define RX_CMPL_ERRORS_T_L4_CS_ERROR			(0x1 << 7)319	#define RX_CMPL_ERRORS_CRC_ERROR			(0x1 << 8)320	#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK			(0x7 << 9)321	 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR		 (0x0 << 9)322	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	 (0x1 << 9)323	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	 (0x2 << 9)324	 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	 (0x3 << 9)325	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	 (0x4 << 9)326	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	 (0x5 << 9)327	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL	 (0x6 << 9)328	#define RX_CMPL_ERRORS_PKT_ERROR_MASK			(0xf << 12)329	 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR		 (0x0 << 12)330	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION	 (0x1 << 12)331	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN	 (0x2 << 12)332	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL		 (0x3 << 12)333	 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR	 (0x4 << 12)334	 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	 (0x5 << 12)335	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN	 (0x6 << 12)336	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)337	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN	 (0x8 << 12)338 339	#define RX_CMPL_CFA_CODE_MASK				(0xffff << 16)340	 #define RX_CMPL_CFA_CODE_SFT				 16341	#define RX_CMPL_METADATA0_TCI_MASK			(0xffff << 16)342	#define RX_CMPL_METADATA0_VID_MASK			(0x0fff << 16)343	 #define RX_CMPL_METADATA0_SFT				 16344 345	__le32 rx_cmp_timestamp;346};347 348#define RX_CMP_L2_ERRORS						\349	cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)350 351#define RX_CMP_L4_CS_BITS						\352	(cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))353 354#define RX_CMP_L4_CS_ERR_BITS						\355	(cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))356 357#define RX_CMP_L4_CS_OK(rxcmp1)						\358	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\359	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))360 361#define RX_CMP_ENCAP(rxcmp1)						\362	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\363	     RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)364 365#define RX_CMP_CFA_CODE(rxcmpl1)					\366	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\367	  RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)368 369#define RX_CMP_METADATA0_TCI(rxcmp1)					\370	((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) &		\371	  RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)372 373struct rx_agg_cmp {374	__le32 rx_agg_cmp_len_flags_type;375	#define RX_AGG_CMP_TYPE					(0x3f << 0)376	#define RX_AGG_CMP_LEN					(0xffff << 16)377	 #define RX_AGG_CMP_LEN_SHIFT				 16378	u32 rx_agg_cmp_opaque;379	__le32 rx_agg_cmp_v;380	#define RX_AGG_CMP_V					(1 << 0)381	#define RX_AGG_CMP_AGG_ID				(0xffff << 16)382	 #define RX_AGG_CMP_AGG_ID_SHIFT			 16383	__le32 rx_agg_cmp_unused;384};385 386#define TPA_AGG_AGG_ID(rx_agg)				\387	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\388	 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)389 390struct rx_tpa_start_cmp {391	__le32 rx_tpa_start_cmp_len_flags_type;392	#define RX_TPA_START_CMP_TYPE				(0x3f << 0)393	#define RX_TPA_START_CMP_FLAGS				(0x3ff << 6)394	 #define RX_TPA_START_CMP_FLAGS_SHIFT			 6395	#define RX_TPA_START_CMP_FLAGS_ERROR			(0x1 << 6)396	#define RX_TPA_START_CMP_FLAGS_PLACEMENT		(0x7 << 7)397	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT		 7398	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)399	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)400	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)401	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS	 (0x6 << 7)402	#define RX_TPA_START_CMP_FLAGS_RSS_VALID		(0x1 << 10)403	#define RX_TPA_START_CMP_FLAGS_TIMESTAMP		(0x1 << 11)404	#define RX_TPA_START_CMP_FLAGS_ITYPES			(0xf << 12)405	 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT		 12406	 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP		 (0x2 << 12)407	#define RX_TPA_START_CMP_LEN				(0xffff << 16)408	 #define RX_TPA_START_CMP_LEN_SHIFT			 16409 410	u32 rx_tpa_start_cmp_opaque;411	__le32 rx_tpa_start_cmp_misc_v1;412	#define RX_TPA_START_CMP_V1				(0x1 << 0)413	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f << 9)414	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9415	#define RX_TPA_START_CMP_V3_RSS_HASH_TYPE		(0x1ff << 7)416	 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT	 7417	#define RX_TPA_START_CMP_AGG_ID				(0x7f << 25)418	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25419	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff << 16)420	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16421	#define RX_TPA_START_CMP_METADATA1			(0xf << 28)422	 #define RX_TPA_START_CMP_METADATA1_SHIFT		 28423	#define RX_TPA_START_METADATA1_TPID_SEL			(0x7 << 28)424	#define RX_TPA_START_METADATA1_TPID_8021Q		(0x1 << 28)425	#define RX_TPA_START_METADATA1_TPID_8021AD		(0x0 << 28)426	#define RX_TPA_START_METADATA1_VALID			(0x8 << 28)427 428	__le32 rx_tpa_start_cmp_rss_hash;429};430 431#define TPA_START_HASH_VALID(rx_tpa_start)				\432	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\433	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))434 435#define TPA_START_HASH_TYPE(rx_tpa_start)				\436	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\437	   RX_TPA_START_CMP_RSS_HASH_TYPE) >>				\438	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)439 440#define TPA_START_V3_HASH_TYPE(rx_tpa_start)				\441	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\442	   RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >>			\443	  RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)444 445#define TPA_START_AGG_ID(rx_tpa_start)					\446	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\447	 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)448 449#define TPA_START_AGG_ID_P5(rx_tpa_start)				\450	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\451	 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)452 453#define TPA_START_ERROR(rx_tpa_start)					\454	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\455	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))456 457#define TPA_START_VLAN_VALID(rx_tpa_start)				\458	((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 &			\459	 cpu_to_le32(RX_TPA_START_METADATA1_VALID))460 461#define TPA_START_VLAN_TPID_SEL(rx_tpa_start)				\462	(le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\463	 RX_TPA_START_METADATA1_TPID_SEL)464 465struct rx_tpa_start_cmp_ext {466	__le32 rx_tpa_start_cmp_flags2;467	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 << 0)468	#define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC		(0x1 << 1)469	#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC		(0x1 << 2)470	#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC		(0x1 << 3)471	#define RX_TPA_START_CMP_FLAGS2_IP_TYPE			(0x1 << 8)472	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 << 9)473	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 << 10)474	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10475	#define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE		(0x1 << 10)476	#define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO		(0x1 << 11)477	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff << 16)478	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16479 480	__le32 rx_tpa_start_cmp_metadata;481	__le32 rx_tpa_start_cmp_cfa_code_v2;482	#define RX_TPA_START_CMP_V2				(0x1 << 0)483	#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK	(0x7 << 1)484	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT	 1485	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)486	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)487	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)488	#define RX_TPA_START_CMP_CFA_CODE			(0xffff << 16)489	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16490	#define RX_TPA_START_CMP_METADATA0_TCI_MASK		(0xffff << 16)491	#define RX_TPA_START_CMP_METADATA0_VID_MASK		(0x0fff << 16)492	 #define RX_TPA_START_CMP_METADATA0_SFT			 16493	__le32 rx_tpa_start_cmp_hdr_info;494};495 496#define TPA_START_CFA_CODE(rx_tpa_start)				\497	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\498	 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)499 500#define TPA_START_IS_IPV6(rx_tpa_start)				\501	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\502	    cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))503 504#define TPA_START_ERROR_CODE(rx_tpa_start)				\505	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\506	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>			\507	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)508 509#define TPA_START_METADATA0_TCI(rx_tpa_start)				\510	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\511	  RX_TPA_START_CMP_METADATA0_TCI_MASK) >>			\512	 RX_TPA_START_CMP_METADATA0_SFT)513 514struct rx_tpa_end_cmp {515	__le32 rx_tpa_end_cmp_len_flags_type;516	#define RX_TPA_END_CMP_TYPE				(0x3f << 0)517	#define RX_TPA_END_CMP_FLAGS				(0x3ff << 6)518	 #define RX_TPA_END_CMP_FLAGS_SHIFT			 6519	#define RX_TPA_END_CMP_FLAGS_PLACEMENT			(0x7 << 7)520	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT		 7521	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)522	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)523	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)524	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS		 (0x6 << 7)525	#define RX_TPA_END_CMP_FLAGS_RSS_VALID			(0x1 << 10)526	#define RX_TPA_END_CMP_FLAGS_ITYPES			(0xf << 12)527	 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT		 12528	 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP			 (0x2 << 12)529	#define RX_TPA_END_CMP_LEN				(0xffff << 16)530	 #define RX_TPA_END_CMP_LEN_SHIFT			 16531 532	u32 rx_tpa_end_cmp_opaque;533	__le32 rx_tpa_end_cmp_misc_v1;534	#define RX_TPA_END_CMP_V1				(0x1 << 0)535	#define RX_TPA_END_CMP_AGG_BUFS				(0x3f << 1)536	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT			 1537	#define RX_TPA_END_CMP_TPA_SEGS				(0xff << 8)538	 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT			 8539	#define RX_TPA_END_CMP_PAYLOAD_OFFSET			(0xff << 16)540	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT		 16541	#define RX_TPA_END_CMP_AGG_ID				(0x7f << 25)542	 #define RX_TPA_END_CMP_AGG_ID_SHIFT			 25543	#define RX_TPA_END_CMP_AGG_ID_P5			(0xffff << 16)544	 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5			 16545 546	__le32 rx_tpa_end_cmp_tsdelta;547	#define RX_TPA_END_GRO_TS				(0x1 << 31)548};549 550#define TPA_END_AGG_ID(rx_tpa_end)					\551	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\552	 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)553 554#define TPA_END_AGG_ID_P5(rx_tpa_end)					\555	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\556	 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)557 558#define TPA_END_PAYLOAD_OFF(rx_tpa_end)					\559	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\560	 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)561 562#define TPA_END_AGG_BUFS(rx_tpa_end)					\563	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\564	 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)565 566#define TPA_END_TPA_SEGS(rx_tpa_end)					\567	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\568	 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)569 570#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO				\571	cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &		\572		    RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)573 574#define TPA_END_GRO(rx_tpa_end)						\575	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\576	 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)577 578#define TPA_END_GRO_TS(rx_tpa_end)					\579	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\580	    cpu_to_le32(RX_TPA_END_GRO_TS)))581 582struct rx_tpa_end_cmp_ext {583	__le32 rx_tpa_end_cmp_dup_acks;584	#define RX_TPA_END_CMP_TPA_DUP_ACKS			(0xf << 0)585	#define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5		(0xff << 16)586	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5		 16587	#define RX_TPA_END_CMP_AGG_BUFS_P5			(0xff << 24)588	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5		 24589 590	__le32 rx_tpa_end_cmp_seg_len;591	#define RX_TPA_END_CMP_TPA_SEG_LEN			(0xffff << 0)592 593	__le32 rx_tpa_end_cmp_errors_v2;594	#define RX_TPA_END_CMP_V2				(0x1 << 0)595	#define RX_TPA_END_CMP_ERRORS				(0x3 << 1)596	#define RX_TPA_END_CMP_ERRORS_P5			(0x7 << 1)597	#define RX_TPA_END_CMPL_ERRORS_SHIFT			 1598	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)599	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)600	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT	 (0x3 << 1)601	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR	 (0x4 << 1)602	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)603 604	u32 rx_tpa_end_cmp_start_opaque;605};606 607#define TPA_END_ERRORS(rx_tpa_end_ext)					\608	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\609	 cpu_to_le32(RX_TPA_END_CMP_ERRORS))610 611#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)				\612	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\613	 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>				\614	RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)615 616#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)				\617	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\618	 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)619 620#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)				\621	(((data1) &							\622	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\623	 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)624 625#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)			\626	(((data1) &							\627	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\628	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)629 630#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)			\631	((data2) &							\632	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)633 634#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)				\635	!!((data1) &							\636	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)637 638#define EVENT_DATA1_RECOVERY_ENABLED(data1)				\639	!!((data1) &							\640	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)641 642#define BNXT_EVENT_ERROR_REPORT_TYPE(data1)				\643	(((data1) &							\644	  ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\645	 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)646 647#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2)				\648	(((data2) &							\649	  ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\650	 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)651 652struct nqe_cn {653	__le16	type;654	#define NQ_CN_TYPE_MASK           0x3fUL655	#define NQ_CN_TYPE_SFT            0656	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL657	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION658	#define NQ_CN_TOGGLE_MASK         0xc0UL659	#define NQ_CN_TOGGLE_SFT          6660	__le16	reserved16;661	__le32	cq_handle_low;662	__le32	v;663	#define NQ_CN_V     0x1UL664	__le32	cq_handle_high;665};666 667#define BNXT_NQ_HDL_IDX_MASK	0x00ffffff668#define BNXT_NQ_HDL_TYPE_MASK	0xff000000669#define BNXT_NQ_HDL_TYPE_SHIFT	24670#define BNXT_NQ_HDL_TYPE_RX	0x00671#define BNXT_NQ_HDL_TYPE_TX	0x01672 673#define BNXT_NQ_HDL_IDX(hdl)	((hdl) & BNXT_NQ_HDL_IDX_MASK)674#define BNXT_NQ_HDL_TYPE(hdl)	(((hdl) & BNXT_NQ_HDL_TYPE_MASK) >>	\675				 BNXT_NQ_HDL_TYPE_SHIFT)676 677#define BNXT_SET_NQ_HDL(cpr)						\678	(((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)679 680#define NQE_CN_TYPE(type)	((type) & NQ_CN_TYPE_MASK)681#define NQE_CN_TOGGLE(type)	(((type) & NQ_CN_TOGGLE_MASK) >>	\682				 NQ_CN_TOGGLE_SFT)683 684#define DB_IDX_MASK						0xffffff685#define DB_IDX_VALID						(0x1 << 26)686#define DB_IRQ_DIS						(0x1 << 27)687#define DB_KEY_TX						(0x0 << 28)688#define DB_KEY_RX						(0x1 << 28)689#define DB_KEY_CP						(0x2 << 28)690#define DB_KEY_ST						(0x3 << 28)691#define DB_KEY_TX_PUSH						(0x4 << 28)692#define DB_LONG_TX_PUSH						(0x2 << 24)693 694#define BNXT_MIN_ROCE_CP_RINGS	2695#define BNXT_MIN_ROCE_STAT_CTXS	1696 697/* 64-bit doorbell */698#define DBR_INDEX_MASK					0x0000000000ffffffULL699#define DBR_EPOCH_MASK					0x01000000UL700#define DBR_EPOCH_SFT					24701#define DBR_TOGGLE_MASK					0x06000000UL702#define DBR_TOGGLE_SFT					25703#define DBR_XID_MASK					0x000fffff00000000ULL704#define DBR_XID_SFT					32705#define DBR_PATH_L2					(0x1ULL << 56)706#define DBR_VALID					(0x1ULL << 58)707#define DBR_TYPE_SQ					(0x0ULL << 60)708#define DBR_TYPE_RQ					(0x1ULL << 60)709#define DBR_TYPE_SRQ					(0x2ULL << 60)710#define DBR_TYPE_SRQ_ARM				(0x3ULL << 60)711#define DBR_TYPE_CQ					(0x4ULL << 60)712#define DBR_TYPE_CQ_ARMSE				(0x5ULL << 60)713#define DBR_TYPE_CQ_ARMALL				(0x6ULL << 60)714#define DBR_TYPE_CQ_ARMENA				(0x7ULL << 60)715#define DBR_TYPE_SRQ_ARMENA				(0x8ULL << 60)716#define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL << 60)717#define DBR_TYPE_NQ					(0xaULL << 60)718#define DBR_TYPE_NQ_ARM					(0xbULL << 60)719#define DBR_TYPE_NQ_MASK				(0xeULL << 60)720#define DBR_TYPE_NULL					(0xfULL << 60)721 722#define DB_PF_OFFSET_P5					0x10000723#define DB_VF_OFFSET_P5					0x4000724 725#define INVALID_HW_RING_ID	((u16)-1)726 727/* The hardware supports certain page sizes.  Use the supported page sizes728 * to allocate the rings.729 */730#if (PAGE_SHIFT < 12)731#define BNXT_PAGE_SHIFT	12732#elif (PAGE_SHIFT <= 13)733#define BNXT_PAGE_SHIFT	PAGE_SHIFT734#elif (PAGE_SHIFT < 16)735#define BNXT_PAGE_SHIFT	13736#else737#define BNXT_PAGE_SHIFT	16738#endif739 740#define BNXT_PAGE_SIZE	(1 << BNXT_PAGE_SHIFT)741 742/* The RXBD length is 16-bit so we can only support page sizes < 64K */743#if (PAGE_SHIFT > 15)744#define BNXT_RX_PAGE_SHIFT 15745#else746#define BNXT_RX_PAGE_SHIFT PAGE_SHIFT747#endif748 749#define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)750 751#define BNXT_MAX_MTU		9500752 753/* First RX buffer page in XDP multi-buf mode754 *755 * +-------------------------------------------------------------------------+756 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size              | skb_shared_info|757 * | (bp->rx_dma_offset) |                                  |                |758 * +-------------------------------------------------------------------------+759 */760#define BNXT_MAX_PAGE_MODE_MTU_SBUF \761	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\762	 XDP_PACKET_HEADROOM)763#define BNXT_MAX_PAGE_MODE_MTU	\764	(BNXT_MAX_PAGE_MODE_MTU_SBUF - \765	 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))766 767#define BNXT_MIN_PKT_SIZE	52768 769#define BNXT_DEFAULT_RX_RING_SIZE	511770#define BNXT_DEFAULT_TX_RING_SIZE	511771 772#define MAX_TPA		64773#define MAX_TPA_P5	256774#define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)775#define MAX_TPA_SEGS_P5	0x3f776 777#if (BNXT_PAGE_SHIFT == 16)778#define MAX_RX_PAGES_AGG_ENA	1779#define MAX_RX_PAGES	4780#define MAX_RX_AGG_PAGES	4781#define MAX_TX_PAGES	1782#define MAX_CP_PAGES	16783#else784#define MAX_RX_PAGES_AGG_ENA	8785#define MAX_RX_PAGES	32786#define MAX_RX_AGG_PAGES	32787#define MAX_TX_PAGES	8788#define MAX_CP_PAGES	128789#endif790 791#define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))792#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))793#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))794 795#define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)796#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)797 798#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)799 800#define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)801#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)802 803#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)804 805#define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)806#define BNXT_MAX_RX_DESC_CNT_JUM_ENA	(RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)807#define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)808#define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)809 810/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1.  We need one extra811 * BD because the first TX BD is always a long BD.812 */813#define BNXT_MIN_TX_DESC_CNT		(MAX_SKB_FRAGS + 2)814 815#define RX_RING(bp, x)	(((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))816#define RX_AGG_RING(bp, x)	(((x) & (bp)->rx_agg_ring_mask) >>	\817				 (BNXT_PAGE_SHIFT - 4))818#define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))819 820#define TX_RING(bp, x)	(((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))821#define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))822 823#define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))824#define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))825 826#define TX_CMP_VALID(txcmp, raw_cons)					\827	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\828	 !((raw_cons) & bp->cp_bit))829 830#define RX_CMP_VALID(rxcmp1, raw_cons)					\831	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\832	 !((raw_cons) & bp->cp_bit))833 834#define RX_AGG_CMP_VALID(agg, raw_cons)				\835	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\836	 !((raw_cons) & bp->cp_bit))837 838#define NQ_CMP_VALID(nqcmp, raw_cons)				\839	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))840 841#define TX_CMP_TYPE(txcmp)					\842	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)843 844#define RX_CMP_TYPE(rxcmp)					\845	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)846 847#define RING_RX(bp, idx)	((idx) & (bp)->rx_ring_mask)848#define NEXT_RX(idx)		((idx) + 1)849 850#define RING_RX_AGG(bp, idx)	((idx) & (bp)->rx_agg_ring_mask)851#define NEXT_RX_AGG(idx)	((idx) + 1)852 853#define RING_TX(bp, idx)	((idx) & (bp)->tx_ring_mask)854#define NEXT_TX(idx)		((idx) + 1)855 856#define ADV_RAW_CMP(idx, n)	((idx) + (n))857#define NEXT_RAW_CMP(idx)	ADV_RAW_CMP(idx, 1)858#define RING_CMP(idx)		((idx) & bp->cp_ring_mask)859#define NEXT_CMP(idx)		RING_CMP(ADV_RAW_CMP(idx, 1))860 861#define DFLT_HWRM_CMD_TIMEOUT		500862 863#define BNXT_RX_EVENT		1864#define BNXT_AGG_EVENT		2865#define BNXT_TX_EVENT		4866#define BNXT_REDIRECT_EVENT	8867#define BNXT_TX_CMP_EVENT	0x10868 869struct bnxt_sw_tx_bd {870	union {871		struct sk_buff		*skb;872		struct xdp_frame	*xdpf;873	};874	DEFINE_DMA_UNMAP_ADDR(mapping);875	DEFINE_DMA_UNMAP_LEN(len);876	struct page		*page;877	u8			is_ts_pkt;878	u8			is_push;879	u8			action;880	unsigned short		nr_frags;881	union {882		u16			rx_prod;883		u16			txts_prod;884	};885};886 887struct bnxt_sw_rx_bd {888	void			*data;889	u8			*data_ptr;890	dma_addr_t		mapping;891};892 893struct bnxt_sw_rx_agg_bd {894	struct page		*page;895	unsigned int		offset;896	dma_addr_t		mapping;897};898 899struct bnxt_ring_mem_info {900	int			nr_pages;901	int			page_size;902	u16			flags;903#define BNXT_RMEM_VALID_PTE_FLAG	1904#define BNXT_RMEM_RING_PTE_FLAG		2905#define BNXT_RMEM_USE_FULL_PAGE_FLAG	4906 907	u16			depth;908	struct bnxt_ctx_mem_type	*ctx_mem;909 910	void			**pg_arr;911	dma_addr_t		*dma_arr;912 913	__le64			*pg_tbl;914	dma_addr_t		pg_tbl_map;915 916	int			vmem_size;917	void			**vmem;918};919 920struct bnxt_ring_struct {921	struct bnxt_ring_mem_info	ring_mem;922 923	u16			fw_ring_id; /* Ring id filled by Chimp FW */924	union {925		u16		grp_idx;926		u16		map_idx; /* Used by cmpl rings */927	};928	u32			handle;929	u8			queue_id;930};931 932struct tx_push_bd {933	__le32			doorbell;934	__le32			tx_bd_len_flags_type;935	u32			tx_bd_opaque;936	struct tx_bd_ext	txbd2;937};938 939struct tx_push_buffer {940	struct tx_push_bd	push_bd;941	u32			data[25];942};943 944struct bnxt_db_info {945	void __iomem		*doorbell;946	union {947		u64		db_key64;948		u32		db_key32;949	};950	u32			db_ring_mask;951	u32			db_epoch_mask;952	u8			db_epoch_shift;953};954 955#define DB_EPOCH(db, idx)	(((idx) & (db)->db_epoch_mask) <<	\956				 ((db)->db_epoch_shift))957 958#define DB_TOGGLE(tgl)		((tgl) << DBR_TOGGLE_SFT)959 960#define DB_RING_IDX(db, idx)	(((idx) & (db)->db_ring_mask) |		\961				 DB_EPOCH(db, idx))962 963struct bnxt_tx_ring_info {964	struct bnxt_napi	*bnapi;965	struct bnxt_cp_ring_info	*tx_cpr;966	u16			tx_prod;967	u16			tx_cons;968	u16			tx_hw_cons;969	u16			txq_index;970	u8			tx_napi_idx;971	u8			kick_pending;972	struct bnxt_db_info	tx_db;973 974	struct tx_bd		*tx_desc_ring[MAX_TX_PAGES];975	struct bnxt_sw_tx_bd	*tx_buf_ring;976 977	dma_addr_t		tx_desc_mapping[MAX_TX_PAGES];978 979	struct tx_push_buffer	*tx_push;980	dma_addr_t		tx_push_mapping;981	__le64			data_mapping;982 983#define BNXT_DEV_STATE_CLOSING	0x1984	u32			dev_state;985 986	struct bnxt_ring_struct	tx_ring_struct;987	/* Synchronize simultaneous xdp_xmit on same ring */988	spinlock_t		xdp_tx_lock;989};990 991#define BNXT_LEGACY_COAL_CMPL_PARAMS					\992	(RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |		\993	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |		\994	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |		\995	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |			\996	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |		\997	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \998	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |		\999	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \1000	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)1001 1002#define BNXT_COAL_CMPL_ENABLES						\1003	(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \1004	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \1005	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \1006	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)1007 1008#define BNXT_COAL_CMPL_MIN_TMR_ENABLE					\1009	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN1010 1011#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE			\1012	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT1013 1014struct bnxt_coal_cap {1015	u32			cmpl_params;1016	u32			nq_params;1017	u16			num_cmpl_dma_aggr_max;1018	u16			num_cmpl_dma_aggr_during_int_max;1019	u16			cmpl_aggr_dma_tmr_max;1020	u16			cmpl_aggr_dma_tmr_during_int_max;1021	u16			int_lat_tmr_min_max;1022	u16			int_lat_tmr_max_max;1023	u16			num_cmpl_aggr_int_max;1024	u16			timer_units;1025};1026 1027struct bnxt_coal {1028	u16			coal_ticks;1029	u16			coal_ticks_irq;1030	u16			coal_bufs;1031	u16			coal_bufs_irq;1032			/* RING_IDLE enabled when coal ticks < idle_thresh  */1033	u16			idle_thresh;1034	u8			bufs_per_record;1035	u8			budget;1036	u16			flags;1037};1038 1039struct bnxt_tpa_info {1040	void			*data;1041	u8			*data_ptr;1042	dma_addr_t		mapping;1043	u16			len;1044	unsigned short		gso_type;1045	u32			flags2;1046	u32			metadata;1047	enum pkt_hash_types	hash_type;1048	u32			rss_hash;1049	u32			hdr_info;1050 1051#define BNXT_TPA_L4_SIZE(hdr_info)	\1052	(((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)1053 1054#define BNXT_TPA_INNER_L3_OFF(hdr_info)	\1055	(((hdr_info) >> 18) & 0x1ff)1056 1057#define BNXT_TPA_INNER_L2_OFF(hdr_info)	\1058	(((hdr_info) >> 9) & 0x1ff)1059 1060#define BNXT_TPA_OUTER_L3_OFF(hdr_info)	\1061	((hdr_info) & 0x1ff)1062 1063	u16			cfa_code; /* cfa_code in TPA start compl */1064	u8			agg_count;1065	u8			vlan_valid:1;1066	u8			cfa_code_valid:1;1067	struct rx_agg_cmp	*agg_arr;1068};1069 1070#define BNXT_AGG_IDX_BMAP_SIZE	(MAX_TPA_P5 / BITS_PER_LONG)1071 1072struct bnxt_tpa_idx_map {1073	u16		agg_id_tbl[1024];1074	unsigned long	agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];1075};1076 1077struct bnxt_rx_ring_info {1078	struct bnxt_napi	*bnapi;1079	struct bnxt_cp_ring_info	*rx_cpr;1080	u16			rx_prod;1081	u16			rx_agg_prod;1082	u16			rx_sw_agg_prod;1083	u16			rx_next_cons;1084	struct bnxt_db_info	rx_db;1085	struct bnxt_db_info	rx_agg_db;1086 1087	struct bpf_prog		*xdp_prog;1088 1089	struct rx_bd		*rx_desc_ring[MAX_RX_PAGES];1090	struct bnxt_sw_rx_bd	*rx_buf_ring;1091 1092	struct rx_bd		*rx_agg_desc_ring[MAX_RX_AGG_PAGES];1093	struct bnxt_sw_rx_agg_bd	*rx_agg_ring;1094 1095	unsigned long		*rx_agg_bmap;1096	u16			rx_agg_bmap_size;1097 1098	dma_addr_t		rx_desc_mapping[MAX_RX_PAGES];1099	dma_addr_t		rx_agg_desc_mapping[MAX_RX_AGG_PAGES];1100 1101	struct bnxt_tpa_info	*rx_tpa;1102	struct bnxt_tpa_idx_map *rx_tpa_idx_map;1103 1104	struct bnxt_ring_struct	rx_ring_struct;1105	struct bnxt_ring_struct	rx_agg_ring_struct;1106	struct xdp_rxq_info	xdp_rxq;1107	struct page_pool	*page_pool;1108};1109 1110struct bnxt_rx_sw_stats {1111	u64			rx_l4_csum_errors;1112	u64			rx_resets;1113	u64			rx_buf_errors;1114	u64			rx_oom_discards;1115	u64			rx_netpoll_discards;1116};1117 1118struct bnxt_tx_sw_stats {1119	u64			tx_resets;1120};1121 1122struct bnxt_cmn_sw_stats {1123	u64			missed_irqs;1124};1125 1126struct bnxt_sw_stats {1127	struct bnxt_rx_sw_stats rx;1128	struct bnxt_tx_sw_stats tx;1129	struct bnxt_cmn_sw_stats cmn;1130};1131 1132struct bnxt_total_ring_err_stats {1133	u64			rx_total_l4_csum_errors;1134	u64			rx_total_resets;1135	u64			rx_total_buf_errors;1136	u64			rx_total_oom_discards;1137	u64			rx_total_netpoll_discards;1138	u64			rx_total_ring_discards;1139	u64			tx_total_resets;1140	u64			tx_total_ring_discards;1141	u64			total_missed_irqs;1142};1143 1144struct bnxt_stats_mem {1145	u64		*sw_stats;1146	u64		*hw_masks;1147	void		*hw_stats;1148	dma_addr_t	hw_stats_map;1149	int		len;1150};1151 1152struct bnxt_cp_ring_info {1153	struct bnxt_napi	*bnapi;1154	u32			cp_raw_cons;1155	struct bnxt_db_info	cp_db;1156 1157	u8			had_work_done:1;1158	u8			has_more_work:1;1159	u8			had_nqe_notify:1;1160	u8			toggle;1161 1162	u8			cp_ring_type;1163	u8			cp_idx;1164 1165	u32			last_cp_raw_cons;1166 1167	struct bnxt_coal	rx_ring_coal;1168	u64			rx_packets;1169	u64			rx_bytes;1170	u64			event_ctr;1171 1172	struct dim		dim;1173 1174	union {1175		struct tx_cmp	**cp_desc_ring;1176		struct nqe_cn	**nq_desc_ring;1177	};1178 1179	dma_addr_t		*cp_desc_mapping;1180 1181	struct bnxt_stats_mem	stats;1182	u32			hw_stats_ctx_id;1183 1184	struct bnxt_sw_stats	*sw_stats;1185 1186	struct bnxt_ring_struct	cp_ring_struct;1187 1188	int			cp_ring_count;1189	struct bnxt_cp_ring_info *cp_ring_arr;1190};1191 1192#define BNXT_MAX_QUEUE		81193#define BNXT_MAX_TXR_PER_NAPI	BNXT_MAX_QUEUE1194 1195#define bnxt_for_each_napi_tx(iter, bnapi, txr)		\1196	for (iter = 0, txr = (bnapi)->tx_ring[0]; txr;	\1197	     txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ?	\1198	     (bnapi)->tx_ring[++iter] : NULL)1199 1200struct bnxt_napi {1201	struct napi_struct	napi;1202	struct bnxt		*bp;1203 1204	int			index;1205	struct bnxt_cp_ring_info	cp_ring;1206	struct bnxt_rx_ring_info	*rx_ring;1207	struct bnxt_tx_ring_info	*tx_ring[BNXT_MAX_TXR_PER_NAPI];1208 1209	void			(*tx_int)(struct bnxt *, struct bnxt_napi *,1210					  int budget);1211	u8			events;1212	u8			tx_fault:1;1213 1214	u32			flags;1215#define BNXT_NAPI_FLAG_XDP	0x11216 1217	bool			in_reset;1218};1219 1220/* "TxRx", 2 hypens, plus maximum integer */1221#define BNXT_IRQ_NAME_EXTRA	171222 1223struct bnxt_irq {1224	irq_handler_t	handler;1225	unsigned int	vector;1226	u8		requested:1;1227	u8		have_cpumask:1;1228	char		name[IFNAMSIZ + BNXT_IRQ_NAME_EXTRA];1229	cpumask_var_t	cpu_mask;1230};1231 1232#define HWRM_RING_ALLOC_TX	0x11233#define HWRM_RING_ALLOC_RX	0x21234#define HWRM_RING_ALLOC_AGG	0x41235#define HWRM_RING_ALLOC_CMPL	0x81236#define HWRM_RING_ALLOC_NQ	0x101237 1238#define INVALID_STATS_CTX_ID	-11239 1240struct bnxt_ring_grp_info {1241	u16	fw_stats_ctx;1242	u16	fw_grp_id;1243	u16	rx_fw_ring_id;1244	u16	agg_fw_ring_id;1245	u16	cp_fw_ring_id;1246};1247 1248#define BNXT_VNIC_DEFAULT	01249#define BNXT_VNIC_NTUPLE	11250 1251struct bnxt_vnic_info {1252	u16		fw_vnic_id; /* returned by Chimp during alloc */1253#define BNXT_MAX_CTX_PER_VNIC	81254	u16		fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];1255	u16		fw_l2_ctx_id;1256	u16		mru;1257#define BNXT_MAX_UC_ADDRS	41258	struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];1259				/* index 0 always dev_addr */1260	u16		uc_filter_count;1261	u8		*uc_list;1262 1263	u16		*fw_grp_ids;1264	dma_addr_t	rss_table_dma_addr;1265	__le16		*rss_table;1266	dma_addr_t	rss_hash_key_dma_addr;1267	u64		*rss_hash_key;1268	int		rss_table_size;1269#define BNXT_RSS_TABLE_ENTRIES_P5	641270#define BNXT_RSS_TABLE_SIZE_P5		(BNXT_RSS_TABLE_ENTRIES_P5 * 4)1271#define BNXT_RSS_TABLE_MAX_TBL_P5	81272#define BNXT_MAX_RSS_TABLE_SIZE_P5				\1273	(BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)1274#define BNXT_MAX_RSS_TABLE_ENTRIES_P5				\1275	(BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)1276 1277	u32		rx_mask;1278 1279	u8		*mc_list;1280	int		mc_list_size;1281	int		mc_list_count;1282	dma_addr_t	mc_list_mapping;1283#define BNXT_MAX_MC_ADDRS	161284 1285	u32		flags;1286#define BNXT_VNIC_RSS_FLAG	11287#define BNXT_VNIC_RFS_FLAG	21288#define BNXT_VNIC_MCAST_FLAG	41289#define BNXT_VNIC_UCAST_FLAG	81290#define BNXT_VNIC_RFS_NEW_RSS_FLAG	0x101291#define BNXT_VNIC_NTUPLE_FLAG		0x201292#define BNXT_VNIC_RSSCTX_FLAG		0x401293	struct ethtool_rxfh_context *rss_ctx;1294	u32		vnic_id;1295};1296 1297struct bnxt_rss_ctx {1298	struct bnxt_vnic_info vnic;1299	u8	index;1300};1301 1302#define BNXT_MAX_ETH_RSS_CTX	321303#define BNXT_VNIC_ID_INVALID	0xffffffff1304 1305struct bnxt_hw_rings {1306	int tx;1307	int rx;1308	int grp;1309	int cp;1310	int cp_p5;1311	int stat;1312	int vnic;1313	int rss_ctx;1314};1315 1316struct bnxt_hw_resc {1317	u16	min_rsscos_ctxs;1318	u16	max_rsscos_ctxs;1319	u16	resv_rsscos_ctxs;1320	u16	min_cp_rings;1321	u16	max_cp_rings;1322	u16	resv_cp_rings;1323	u16	min_tx_rings;1324	u16	max_tx_rings;1325	u16	resv_tx_rings;1326	u16	max_tx_sch_inputs;1327	u16	min_rx_rings;1328	u16	max_rx_rings;1329	u16	resv_rx_rings;1330	u16	min_hw_ring_grps;1331	u16	max_hw_ring_grps;1332	u16	resv_hw_ring_grps;1333	u16	min_l2_ctxs;1334	u16	max_l2_ctxs;1335	u16	min_vnics;1336	u16	max_vnics;1337	u16	resv_vnics;1338	u16	min_stat_ctxs;1339	u16	max_stat_ctxs;1340	u16	resv_stat_ctxs;1341	u16	max_nqs;1342	u16	max_irqs;1343	u16	resv_irqs;1344	u32	max_encap_records;1345	u32	max_decap_records;1346	u32	max_tx_em_flows;1347	u32	max_tx_wm_flows;1348	u32	max_rx_em_flows;1349	u32	max_rx_wm_flows;1350};1351 1352#if defined(CONFIG_BNXT_SRIOV)1353struct bnxt_vf_info {1354	u16	fw_fid;1355	u8	mac_addr[ETH_ALEN];	/* PF assigned MAC Address */1356	u8	vf_mac_addr[ETH_ALEN];	/* VF assigned MAC address, only1357					 * stored by PF.1358					 */1359	u16	vlan;1360	u16	func_qcfg_flags;1361	u32	flags;1362#define BNXT_VF_SPOOFCHK	0x21363#define BNXT_VF_LINK_FORCED	0x41364#define BNXT_VF_LINK_UP		0x81365#define BNXT_VF_TRUST		0x101366	u32	min_tx_rate;1367	u32	max_tx_rate;1368	void	*hwrm_cmd_req_addr;1369	dma_addr_t	hwrm_cmd_req_dma_addr;1370};1371#endif1372 1373struct bnxt_pf_info {1374#define BNXT_FIRST_PF_FID	11375#define BNXT_FIRST_VF_FID	1281376	u16	fw_fid;1377	u16	port_id;1378	u8	mac_addr[ETH_ALEN];1379	u32	first_vf_id;1380	u16	active_vfs;1381	u16	registered_vfs;1382	u16	max_vfs;1383	unsigned long	*vf_event_bmap;1384	u16	hwrm_cmd_req_pages;1385	u8	vf_resv_strategy;1386#define BNXT_VF_RESV_STRATEGY_MAXIMAL	01387#define BNXT_VF_RESV_STRATEGY_MINIMAL	11388#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC	21389	void			*hwrm_cmd_req_addr[4];1390	dma_addr_t		hwrm_cmd_req_dma_addr[4];1391	struct bnxt_vf_info	*vf;1392};1393 1394struct bnxt_filter_base {1395	struct hlist_node	hash;1396	struct list_head	list;1397	__le64			filter_id;1398	u8			type;1399#define BNXT_FLTR_TYPE_NTUPLE	11400#define BNXT_FLTR_TYPE_L2	21401	u8			flags;1402#define BNXT_ACT_DROP		11403#define BNXT_ACT_RING_DST	21404#define BNXT_ACT_FUNC_DST	41405#define BNXT_ACT_NO_AGING	81406#define BNXT_ACT_RSS_CTX	0x101407	u16			sw_id;1408	u16			rxq;1409	u16			fw_vnic_id;1410	u16			vf_idx;1411	unsigned long		state;1412#define BNXT_FLTR_VALID		01413#define BNXT_FLTR_INSERTED	11414#define BNXT_FLTR_FW_DELETED	21415 1416	struct rcu_head         rcu;1417};1418 1419struct bnxt_flow_masks {1420	struct flow_dissector_key_ports ports;1421	struct flow_dissector_key_addrs addrs;1422};1423 1424extern const struct bnxt_flow_masks BNXT_FLOW_MASK_NONE;1425extern const struct bnxt_flow_masks BNXT_FLOW_IPV6_MASK_ALL;1426extern const struct bnxt_flow_masks BNXT_FLOW_IPV4_MASK_ALL;1427 1428struct bnxt_ntuple_filter {1429	/* base filter must be the first member */1430	struct bnxt_filter_base	base;1431	struct flow_keys	fkeys;1432	struct bnxt_flow_masks	fmasks;1433	struct bnxt_l2_filter	*l2_fltr;1434	u32			flow_id;1435};1436 1437struct bnxt_l2_key {1438	union {1439		struct {1440			u8	dst_mac_addr[ETH_ALEN];1441			u16	vlan;1442		};1443		u32	filter_key;1444	};1445};1446 1447struct bnxt_ipv4_tuple {1448	struct flow_dissector_key_ipv4_addrs v4addrs;1449	struct flow_dissector_key_ports ports;1450};1451 1452struct bnxt_ipv6_tuple {1453	struct flow_dissector_key_ipv6_addrs v6addrs;1454	struct flow_dissector_key_ports ports;1455};1456 1457#define BNXT_L2_KEY_SIZE	(sizeof(struct bnxt_l2_key) / 4)1458 1459struct bnxt_l2_filter {1460	/* base filter must be the first member */1461	struct bnxt_filter_base	base;1462	struct bnxt_l2_key	l2_key;1463	atomic_t		refcnt;1464};1465 1466/* Compat version of hwrm_port_phy_qcfg_output capped at 96 bytes.  The1467 * first 95 bytes are identical to hwrm_port_phy_qcfg_output in bnxt_hsi.h.1468 * The last valid byte in the compat version is different.1469 */1470struct hwrm_port_phy_qcfg_output_compat {1471	__le16	error_code;1472	__le16	req_type;1473	__le16	seq_id;1474	__le16	resp_len;1475	u8	link;1476	u8	active_fec_signal_mode;1477	__le16	link_speed;1478	u8	duplex_cfg;1479	u8	pause;1480	__le16	support_speeds;1481	__le16	force_link_speed;1482	u8	auto_mode;1483	u8	auto_pause;1484	__le16	auto_link_speed;1485	__le16	auto_link_speed_mask;1486	u8	wirespeed;1487	u8	lpbk;1488	u8	force_pause;1489	u8	module_status;1490	__le32	preemphasis;1491	u8	phy_maj;1492	u8	phy_min;1493	u8	phy_bld;1494	u8	phy_type;1495	u8	media_type;1496	u8	xcvr_pkg_type;1497	u8	eee_config_phy_addr;1498	u8	parallel_detect;1499	__le16	link_partner_adv_speeds;1500	u8	link_partner_adv_auto_mode;1501	u8	link_partner_adv_pause;1502	__le16	adv_eee_link_speed_mask;1503	__le16	link_partner_adv_eee_link_speed_mask;1504	__le32	xcvr_identifier_type_tx_lpi_timer;1505	__le16	fec_cfg;1506	u8	duplex_state;1507	u8	option_flags;1508	char	phy_vendor_name[16];1509	char	phy_vendor_partnumber[16];1510	__le16	support_pam4_speeds;1511	__le16	force_pam4_link_speed;1512	__le16	auto_pam4_link_speed_mask;1513	u8	link_partner_pam4_adv_speeds;1514	u8	valid;1515};1516 1517struct bnxt_link_info {1518	u8			phy_type;1519	u8			media_type;1520	u8			transceiver;1521	u8			phy_addr;1522	u8			phy_link_status;1523#define BNXT_LINK_NO_LINK	PORT_PHY_QCFG_RESP_LINK_NO_LINK1524#define BNXT_LINK_SIGNAL	PORT_PHY_QCFG_RESP_LINK_SIGNAL1525#define BNXT_LINK_LINK		PORT_PHY_QCFG_RESP_LINK_LINK1526	u8			wire_speed;1527	u8			phy_state;1528#define BNXT_PHY_STATE_ENABLED		01529#define BNXT_PHY_STATE_DISABLED		11530 1531	u8			link_state;1532#define BNXT_LINK_STATE_UNKNOWN	01533#define BNXT_LINK_STATE_DOWN	11534#define BNXT_LINK_STATE_UP	21535#define BNXT_LINK_IS_UP(bp)	((bp)->link_info.link_state == BNXT_LINK_STATE_UP)1536	u8			active_lanes;1537	u8			duplex;1538#define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF1539#define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL1540	u8			pause;1541#define BNXT_LINK_PAUSE_TX	PORT_PHY_QCFG_RESP_PAUSE_TX1542#define BNXT_LINK_PAUSE_RX	PORT_PHY_QCFG_RESP_PAUSE_RX1543#define BNXT_LINK_PAUSE_BOTH	(PORT_PHY_QCFG_RESP_PAUSE_RX | \1544				 PORT_PHY_QCFG_RESP_PAUSE_TX)1545	u8			lp_pause;1546	u8			auto_pause_setting;1547	u8			force_pause_setting;1548	u8			duplex_setting;1549	u8			auto_mode;1550#define BNXT_AUTO_MODE(mode)	((mode) > BNXT_LINK_AUTO_NONE && \1551				 (mode) <= BNXT_LINK_AUTO_MSK)1552#define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE1553#define BNXT_LINK_AUTO_ALLSPDS	PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS1554#define BNXT_LINK_AUTO_ONESPD	PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED1555#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW1556#define BNXT_LINK_AUTO_MSK	PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK1557#define PHY_VER_LEN		31558	u8			phy_ver[PHY_VER_LEN];1559	u16			link_speed;1560#define BNXT_LINK_SPEED_100MB	PORT_PHY_QCFG_RESP_LINK_SPEED_100MB1561#define BNXT_LINK_SPEED_1GB	PORT_PHY_QCFG_RESP_LINK_SPEED_1GB1562#define BNXT_LINK_SPEED_2GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2GB1563#define BNXT_LINK_SPEED_2_5GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB1564#define BNXT_LINK_SPEED_10GB	PORT_PHY_QCFG_RESP_LINK_SPEED_10GB1565#define BNXT_LINK_SPEED_20GB	PORT_PHY_QCFG_RESP_LINK_SPEED_20GB1566#define BNXT_LINK_SPEED_25GB	PORT_PHY_QCFG_RESP_LINK_SPEED_25GB1567#define BNXT_LINK_SPEED_40GB	PORT_PHY_QCFG_RESP_LINK_SPEED_40GB1568#define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB1569#define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB1570#define BNXT_LINK_SPEED_200GB	PORT_PHY_QCFG_RESP_LINK_SPEED_200GB1571#define BNXT_LINK_SPEED_400GB	PORT_PHY_QCFG_RESP_LINK_SPEED_400GB1572	u16			support_speeds;1573	u16			support_pam4_speeds;1574	u16			support_speeds2;1575 1576	u16			auto_link_speeds;	/* fw adv setting */1577#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB1578#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB1579#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB1580#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB1581#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB1582#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB1583#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB1584#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB1585#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB1586#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB1587	u16			auto_pam4_link_speeds;1588#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G1589#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G1590#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G1591	u16			auto_link_speeds2;1592#define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB1593#define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB1594#define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB1595#define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB1596#define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB1597#define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB1598#define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4	\1599	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_561600#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4	\1601	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_561602#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4	\1603	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_561604#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4	\1605	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_561606#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112	\1607	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_1121608#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112	\1609	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_1121610#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112	\1611	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_1121612 1613	u16			support_auto_speeds;1614	u16			support_pam4_auto_speeds;1615	u16			support_auto_speeds2;1616 1617	u16			lp_auto_link_speeds;1618	u16			lp_auto_pam4_link_speeds;1619	u16			force_link_speed;1620	u16			force_pam4_link_speed;1621	u16			force_link_speed2;1622#define BNXT_LINK_SPEED_50GB_PAM4	\1623	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_561624#define BNXT_LINK_SPEED_100GB_PAM4	\1625	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_561626#define BNXT_LINK_SPEED_200GB_PAM4	\1627	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_561628#define BNXT_LINK_SPEED_400GB_PAM4	\1629	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_561630#define BNXT_LINK_SPEED_100GB_PAM4_112	\1631	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_1121632#define BNXT_LINK_SPEED_200GB_PAM4_112	\1633	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_1121634#define BNXT_LINK_SPEED_400GB_PAM4_112	\1635	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_1121636 1637	u32			preemphasis;1638	u8			module_status;1639	u8			active_fec_sig_mode;1640	u16			fec_cfg;1641#define BNXT_FEC_NONE		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED1642#define BNXT_FEC_AUTONEG_CAP	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED1643#define BNXT_FEC_AUTONEG	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED1644#define BNXT_FEC_ENC_BASE_R_CAP	\1645	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED1646#define BNXT_FEC_ENC_BASE_R	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED1647#define BNXT_FEC_ENC_RS_CAP	\1648	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED1649#define BNXT_FEC_ENC_LLRS_CAP	\1650	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |	\1651	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)1652#define BNXT_FEC_ENC_RS		\1653	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |	\1654	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |	\1655	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)1656#define BNXT_FEC_ENC_LLRS	\1657	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |	\1658	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)1659 1660	/* copy of requested setting from ethtool cmd */1661	u8			autoneg;1662#define BNXT_AUTONEG_SPEED		11663#define BNXT_AUTONEG_FLOW_CTRL		21664	u8			req_signal_mode;1665#define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ1666#define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM41667#define BNXT_SIG_MODE_PAM4_112	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_1121668#define BNXT_SIG_MODE_MAX	(PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)1669	u8			req_duplex;1670	u8			req_flow_ctrl;1671	u16			req_link_speed;1672	u16			advertising;	/* user adv setting */1673	u16			advertising_pam4;1674	bool			force_link_chng;1675 1676	bool			phy_retry;1677	unsigned long		phy_retry_expires;1678 1679	/* a copy of phy_qcfg output used to report link1680	 * info to VF1681	 */1682	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;1683};1684 1685#define BNXT_FEC_RS544_ON					\1686	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |		\1687	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)1688 1689#define BNXT_FEC_RS544_OFF					\1690	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |	\1691	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)1692 1693#define BNXT_FEC_RS272_ON					\1694	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |		\1695	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)1696 1697#define BNXT_FEC_RS272_OFF					\1698	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |	\1699	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)1700 1701#define BNXT_PAM4_SUPPORTED(link_info)				\1702	((link_info)->support_pam4_speeds)1703 1704#define BNXT_FEC_RS_ON(link_info)				\1705	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\1706	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\1707	 (BNXT_PAM4_SUPPORTED(link_info) ?			\1708	  (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))1709 1710#define BNXT_FEC_LLRS_ON					\1711	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\1712	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\1713	 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)1714 1715#define BNXT_FEC_RS_OFF(link_info)				\1716	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |		\1717	 (BNXT_PAM4_SUPPORTED(link_info) ?			\1718	  (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))1719 1720#define BNXT_FEC_BASE_R_ON(link_info)				\1721	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |		\1722	 BNXT_FEC_RS_OFF(link_info))1723 1724#define BNXT_FEC_ALL_OFF(link_info)				\1725	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\1726	 BNXT_FEC_RS_OFF(link_info))1727 1728struct bnxt_queue_info {1729	u8	queue_id;1730	u8	queue_profile;1731};1732 1733#define BNXT_MAX_LED			41734 1735struct bnxt_led_info {1736	u8	led_id;1737	u8	led_type;1738	u8	led_group_id;1739	u8	unused;1740	__le16	led_state_caps;1741#define BNXT_LED_ALT_BLINK_CAP(x)	((x) &	\1742	cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))1743 1744	__le16	led_color_caps;1745};1746 1747#define BNXT_MAX_TEST	81748 1749struct bnxt_test_info {1750	u8 offline_mask;1751	u16 timeout;1752	char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];1753};1754 1755#define CHIMP_REG_VIEW_ADDR				\1756	((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)1757 1758#define BNXT_GRCPF_REG_CHIMP_COMM		0x01759#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x1001760#define BNXT_GRCPF_REG_WINDOW_BASE_OUT		0x4001761 1762#define BNXT_GRC_REG_STATUS_P5			0x5201763 1764#define BNXT_GRCPF_REG_KONG_COMM		0xA001765#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER	0xB001766 1767#define BNXT_GRC_REG_CHIP_NUM			0x481768#define BNXT_GRC_REG_BASE			0x2600001769 1770#define BNXT_TS_REG_TIMESYNC_TS0_LOWER		0x640180c1771#define BNXT_TS_REG_TIMESYNC_TS0_UPPER		0x64018101772 1773#define BNXT_GRC_BASE_MASK			0xfffff0001774#define BNXT_GRC_OFFSET_MASK			0x00000ffc1775 1776struct bnxt_tc_flow_stats {1777	u64		packets;1778	u64		bytes;1779};1780 1781#ifdef CONFIG_BNXT_FLOWER_OFFLOAD1782struct bnxt_flower_indr_block_cb_priv {1783	struct net_device *tunnel_netdev;1784	struct bnxt *bp;1785	struct list_head list;1786};1787#endif1788 1789struct bnxt_tc_info {1790	bool				enabled;1791 1792	/* hash table to store TC offloaded flows */1793	struct rhashtable		flow_table;1794	struct rhashtable_params	flow_ht_params;1795 1796	/* hash table to store L2 keys of TC flows */1797	struct rhashtable		l2_table;1798	struct rhashtable_params	l2_ht_params;1799	/* hash table to store L2 keys for TC tunnel decap */1800	struct rhashtable		decap_l2_table;1801	struct rhashtable_params	decap_l2_ht_params;1802	/* hash table to store tunnel decap entries */1803	struct rhashtable		decap_table;1804	struct rhashtable_params	decap_ht_params;1805	/* hash table to store tunnel encap entries */1806	struct rhashtable		encap_table;1807	struct rhashtable_params	encap_ht_params;1808 1809	/* lock to atomically add/del an l2 node when a flow is1810	 * added or deleted.1811	 */1812	struct mutex			lock;1813 1814	/* Fields used for batching stats query */1815	struct rhashtable_iter		iter;1816#define BNXT_FLOW_STATS_BATCH_MAX	101817	struct bnxt_tc_stats_batch {1818		void			  *flow_node;1819		struct bnxt_tc_flow_stats hw_stats;1820	} stats_batch[BNXT_FLOW_STATS_BATCH_MAX];1821 1822	/* Stat counter mask (width) */1823	u64				bytes_mask;1824	u64				packets_mask;1825};1826 1827struct bnxt_vf_rep_stats {1828	u64			packets;1829	u64			bytes;1830	u64			dropped;1831};1832 1833struct bnxt_vf_rep {1834	struct bnxt			*bp;1835	struct net_device		*dev;1836	struct metadata_dst		*dst;1837	u16				vf_idx;1838	u16				tx_cfa_action;1839	u16				rx_cfa_code;1840 1841	struct bnxt_vf_rep_stats	rx_stats;1842	struct bnxt_vf_rep_stats	tx_stats;1843};1844 1845#define PTU_PTE_VALID             0x1UL1846#define PTU_PTE_LAST              0x2UL1847#define PTU_PTE_NEXT_TO_LAST      0x4UL1848 1849#define MAX_CTX_PAGES	(BNXT_PAGE_SIZE / 8)1850#define MAX_CTX_TOTAL_PAGES	(MAX_CTX_PAGES * MAX_CTX_PAGES)1851 1852struct bnxt_ctx_pg_info {1853	u32		entries;1854	u32		nr_pages;1855	void		*ctx_pg_arr[MAX_CTX_PAGES];1856	dma_addr_t	ctx_dma_arr[MAX_CTX_PAGES];1857	struct bnxt_ring_mem_info ring_mem;1858	struct bnxt_ctx_pg_info **ctx_pg_tbl;1859};1860 1861#define BNXT_MAX_TQM_SP_RINGS		11862#define BNXT_MAX_TQM_FP_RINGS		81863#define BNXT_MAX_TQM_RINGS		\1864	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)1865 1866#define BNXT_BACKING_STORE_CFG_LEGACY_LEN	2561867 1868#define BNXT_SET_CTX_PAGE_ATTR(attr)					\1869do {									\1870	if (BNXT_PAGE_SIZE == 0x2000)					\1871		attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K;	\1872	else if (BNXT_PAGE_SIZE == 0x10000)				\1873		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K;	\1874	else								\1875		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;	\1876} while (0)1877 1878struct bnxt_ctx_mem_type {1879	u16	type;1880	u16	entry_size;1881	u32	flags;1882#define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID1883	u32	instance_bmap;1884	u8	init_value;1885	u8	entry_multiple;1886	u16	init_offset;1887#define	BNXT_CTX_INIT_INVALID_OFFSET	0xffff1888	u32	max_entries;1889	u32	min_entries;1890	u8	last:1;1891	u8	split_entry_cnt;1892#define BNXT_MAX_SPLIT_ENTRY	41893	union {1894		struct {1895			u32	qp_l2_entries;1896			u32	qp_qp1_entries;1897			u32	qp_fast_qpmd_entries;1898		};1899		u32	srq_l2_entries;1900		u32	cq_l2_entries;1901		u32	vnic_entries;1902		struct {1903			u32	mrav_av_entries;1904			u32	mrav_num_entries_units;1905		};1906		u32	split[BNXT_MAX_SPLIT_ENTRY];1907	};1908	struct bnxt_ctx_pg_info	*pg_info;1909};1910 1911#define BNXT_CTX_MRAV_AV_SPLIT_ENTRY	01912 1913#define BNXT_CTX_QP	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP1914#define BNXT_CTX_SRQ	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ1915#define BNXT_CTX_CQ	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ1916#define BNXT_CTX_VNIC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC1917#define BNXT_CTX_STAT	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT1918#define BNXT_CTX_STQM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING1919#define BNXT_CTX_FTQM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING1920#define BNXT_CTX_MRAV	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV1921#define BNXT_CTX_TIM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM1922#define BNXT_CTX_TKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC1923#define BNXT_CTX_RKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC1924#define BNXT_CTX_MTQM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING1925#define BNXT_CTX_SQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW1926#define BNXT_CTX_RQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW1927#define BNXT_CTX_SRQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW1928#define BNXT_CTX_CQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW1929#define BNXT_CTX_QTKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC1930#define BNXT_CTX_QRKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC1931#define BNXT_CTX_TBLSC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE1932#define BNXT_CTX_XPAR	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION1933 1934#define BNXT_CTX_MAX	(BNXT_CTX_TIM + 1)1935#define BNXT_CTX_L2_MAX	(BNXT_CTX_FTQM + 1)1936#define BNXT_CTX_V2_MAX	(BNXT_CTX_XPAR + 1)1937#define BNXT_CTX_INV	((u16)-1)1938 1939struct bnxt_ctx_mem_info {1940	u8	tqm_fp_rings_count;1941 1942	u32	flags;1943	#define BNXT_CTX_FLAG_INITED	0x011944	struct bnxt_ctx_mem_type	ctx_arr[BNXT_CTX_V2_MAX];1945};1946 1947enum bnxt_health_severity {1948	SEVERITY_NORMAL = 0,1949	SEVERITY_WARNING,1950	SEVERITY_RECOVERABLE,1951	SEVERITY_FATAL,1952};1953 1954enum bnxt_health_remedy {1955	REMEDY_DEVLINK_RECOVER,1956	REMEDY_POWER_CYCLE_DEVICE,1957	REMEDY_POWER_CYCLE_HOST,1958	REMEDY_FW_UPDATE,1959	REMEDY_HW_REPLACE,1960};1961 1962struct bnxt_fw_health {1963	u32 flags;1964	u32 polling_dsecs;1965	u32 master_func_wait_dsecs;1966	u32 normal_func_wait_dsecs;1967	u32 post_reset_wait_dsecs;1968	u32 post_reset_max_wait_dsecs;1969	u32 regs[4];1970	u32 mapped_regs[4];1971#define BNXT_FW_HEALTH_REG		01972#define BNXT_FW_HEARTBEAT_REG		11973#define BNXT_FW_RESET_CNT_REG		21974#define BNXT_FW_RESET_INPROG_REG	31975	u32 fw_reset_inprog_reg_mask;1976	u32 last_fw_heartbeat;1977	u32 last_fw_reset_cnt;1978	u8 enabled:1;1979	u8 primary:1;1980	u8 status_reliable:1;1981	u8 resets_reliable:1;1982	u8 tmr_multiplier;1983	u8 tmr_counter;1984	u8 fw_reset_seq_cnt;1985	u32 fw_reset_seq_regs[16];1986	u32 fw_reset_seq_vals[16];1987	u32 fw_reset_seq_delay_msec[16];1988	u32 echo_req_data1;1989	u32 echo_req_data2;1990	struct devlink_health_reporter	*fw_reporter;1991	/* Protects severity and remedy */1992	struct mutex lock;1993	enum bnxt_health_severity severity;1994	enum bnxt_health_remedy remedy;1995	u32 arrests;1996	u32 discoveries;1997	u32 survivals;1998	u32 fatalities;1999	u32 diagnoses;2000};2001 2002#define BNXT_FW_HEALTH_REG_TYPE_MASK	32003#define BNXT_FW_HEALTH_REG_TYPE_CFG	02004#define BNXT_FW_HEALTH_REG_TYPE_GRC	12005#define BNXT_FW_HEALTH_REG_TYPE_BAR0	22006#define BNXT_FW_HEALTH_REG_TYPE_BAR1	32007 2008#define BNXT_FW_HEALTH_REG_TYPE(reg)	((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)2009#define BNXT_FW_HEALTH_REG_OFF(reg)	((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)2010 2011#define BNXT_FW_HEALTH_WIN_BASE		0x30002012#define BNXT_FW_HEALTH_WIN_MAP_OFF	82013 2014#define BNXT_FW_HEALTH_WIN_OFF(reg)	(BNXT_FW_HEALTH_WIN_BASE +	\2015					 ((reg) & BNXT_GRC_OFFSET_MASK))2016 2017#define BNXT_FW_STATUS_HEALTH_MSK	0xffff2018#define BNXT_FW_STATUS_HEALTHY		0x80002019#define BNXT_FW_STATUS_SHUTDOWN		0x1000002020#define BNXT_FW_STATUS_RECOVERING	0x4000002021 2022#define BNXT_FW_IS_HEALTHY(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\2023					 BNXT_FW_STATUS_HEALTHY)2024 2025#define BNXT_FW_IS_BOOTING(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \2026					 BNXT_FW_STATUS_HEALTHY)2027 2028#define BNXT_FW_IS_ERR(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \2029					 BNXT_FW_STATUS_HEALTHY)2030 2031#define BNXT_FW_IS_RECOVERING(sts)	(BNXT_FW_IS_ERR(sts) &&		       \2032					 ((sts) & BNXT_FW_STATUS_RECOVERING))2033 2034#define BNXT_FW_RETRY			52035#define BNXT_FW_IF_RETRY		102036#define BNXT_FW_SLOT_RESET_RETRY	42037 2038struct bnxt_aux_priv {2039	struct auxiliary_device aux_dev;2040	struct bnxt_en_dev *edev;2041	int id;2042};2043 2044enum board_idx {2045	BCM57301,2046	BCM57302,2047	BCM57304,2048	BCM57417_NPAR,2049	BCM58700,2050	BCM57311,2051	BCM57312,2052	BCM57402,2053	BCM57404,2054	BCM57406,2055	BCM57402_NPAR,2056	BCM57407,2057	BCM57412,2058	BCM57414,2059	BCM57416,2060	BCM57417,2061	BCM57412_NPAR,2062	BCM57314,2063	BCM57417_SFP,2064	BCM57416_SFP,2065	BCM57404_NPAR,2066	BCM57406_NPAR,2067	BCM57407_SFP,2068	BCM57407_NPAR,2069	BCM57414_NPAR,2070	BCM57416_NPAR,2071	BCM57452,2072	BCM57454,2073	BCM5745x_NPAR,2074	BCM57508,2075	BCM57504,2076	BCM57502,2077	BCM57508_NPAR,2078	BCM57504_NPAR,2079	BCM57502_NPAR,2080	BCM57608,2081	BCM57604,2082	BCM57602,2083	BCM57601,2084	BCM58802,2085	BCM58804,2086	BCM58808,2087	NETXTREME_E_VF,2088	NETXTREME_C_VF,2089	NETXTREME_S_VF,2090	NETXTREME_C_VF_HV,2091	NETXTREME_E_VF_HV,2092	NETXTREME_E_P5_VF,2093	NETXTREME_E_P5_VF_HV,2094	NETXTREME_E_P7_VF,2095};2096 2097struct bnxt {2098	void __iomem		*bar0;2099	void __iomem		*bar1;2100	void __iomem		*bar2;2101 2102	u32			reg_base;2103	u16			chip_num;2104#define CHIP_NUM_57301		0x16c82105#define CHIP_NUM_57302		0x16c92106#define CHIP_NUM_57304		0x16ca2107#define CHIP_NUM_58700		0x16cd2108#define CHIP_NUM_57402		0x16d02109#define CHIP_NUM_57404		0x16d12110#define CHIP_NUM_57406		0x16d22111#define CHIP_NUM_57407		0x16d52112 2113#define CHIP_NUM_57311		0x16ce2114#define CHIP_NUM_57312		0x16cf2115#define CHIP_NUM_57314		0x16df2116#define CHIP_NUM_57317		0x16e02117#define CHIP_NUM_57412		0x16d62118#define CHIP_NUM_57414		0x16d72119#define CHIP_NUM_57416		0x16d82120#define CHIP_NUM_57417		0x16d92121#define CHIP_NUM_57412L		0x16da2122#define CHIP_NUM_57414L		0x16db2123 2124#define CHIP_NUM_5745X		0xd7302125#define CHIP_NUM_57452		0xc4522126#define CHIP_NUM_57454		0xc4542127 2128#define CHIP_NUM_57508		0x17502129#define CHIP_NUM_57504		0x17512130#define CHIP_NUM_57502		0x17522131 2132#define CHIP_NUM_57608		0x17602133 2134#define CHIP_NUM_58802		0xd8022135#define CHIP_NUM_58804		0xd8042136#define CHIP_NUM_58808		0xd8082137 2138	u8			chip_rev;2139 2140#define BNXT_CHIP_NUM_5730X(chip_num)		\2141	((chip_num) >= CHIP_NUM_57301 &&	\2142	 (chip_num) <= CHIP_NUM_57304)2143 2144#define BNXT_CHIP_NUM_5740X(chip_num)		\2145	(((chip_num) >= CHIP_NUM_57402 &&	\2146	  (chip_num) <= CHIP_NUM_57406) ||	\2147	 (chip_num) == CHIP_NUM_57407)2148 2149#define BNXT_CHIP_NUM_5731X(chip_num)		\2150	((chip_num) == CHIP_NUM_57311 ||	\2151	 (chip_num) == CHIP_NUM_57312 ||	\2152	 (chip_num) == CHIP_NUM_57314 ||	\2153	 (chip_num) == CHIP_NUM_57317)2154 2155#define BNXT_CHIP_NUM_5741X(chip_num)		\2156	((chip_num) >= CHIP_NUM_57412 &&	\2157	 (chip_num) <= CHIP_NUM_57414L)2158 2159#define BNXT_CHIP_NUM_58700(chip_num)		\2160	 ((chip_num) == CHIP_NUM_58700)2161 2162#define BNXT_CHIP_NUM_5745X(chip_num)		\2163	((chip_num) == CHIP_NUM_5745X ||	\2164	 (chip_num) == CHIP_NUM_57452 ||	\2165	 (chip_num) == CHIP_NUM_57454)2166 2167 2168#define BNXT_CHIP_NUM_57X0X(chip_num)		\2169	(BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))2170 2171#define BNXT_CHIP_NUM_57X1X(chip_num)		\2172	(BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))2173 2174#define BNXT_CHIP_NUM_588XX(chip_num)		\2175	((chip_num) == CHIP_NUM_58802 ||	\2176	 (chip_num) == CHIP_NUM_58804 ||        \2177	 (chip_num) == CHIP_NUM_58808)2178 2179#define BNXT_VPD_FLD_LEN	322180	char			board_partno[BNXT_VPD_FLD_LEN];2181	char			board_serialno[BNXT_VPD_FLD_LEN];2182 2183	struct net_device	*dev;2184	struct pci_dev		*pdev;2185 2186	atomic_t		intr_sem;2187 2188	u32			flags;2189	#define BNXT_FLAG_CHIP_P5_PLUS	0x12190	#define BNXT_FLAG_VF		0x22191	#define BNXT_FLAG_LRO		0x42192#ifdef CONFIG_INET2193	#define BNXT_FLAG_GRO		0x82194#else2195	/* Cannot support hardware GRO if CONFIG_INET is not set */2196	#define BNXT_FLAG_GRO		0x02197#endif2198	#define BNXT_FLAG_TPA		(BNXT_FLAG_LRO | BNXT_FLAG_GRO)2199	#define BNXT_FLAG_JUMBO		0x102200	#define BNXT_FLAG_STRIP_VLAN	0x202201	#define BNXT_FLAG_AGG_RINGS	(BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \2202					 BNXT_FLAG_LRO)2203	#define BNXT_FLAG_RFS		0x1002204	#define BNXT_FLAG_SHARED_RINGS	0x2002205	#define BNXT_FLAG_PORT_STATS	0x4002206	#define BNXT_FLAG_WOL_CAP	0x40002207	#define BNXT_FLAG_ROCEV1_CAP	0x80002208	#define BNXT_FLAG_ROCEV2_CAP	0x100002209	#define BNXT_FLAG_ROCE_CAP	(BNXT_FLAG_ROCEV1_CAP |	\2210					 BNXT_FLAG_ROCEV2_CAP)2211	#define BNXT_FLAG_NO_AGG_RINGS	0x200002212	#define BNXT_FLAG_RX_PAGE_MODE	0x400002213	#define BNXT_FLAG_CHIP_P7	0x800002214	#define BNXT_FLAG_MULTI_HOST	0x1000002215	#define BNXT_FLAG_DSN_VALID	0x2000002216	#define BNXT_FLAG_DOUBLE_DB	0x4000002217	#define BNXT_FLAG_UDP_GSO_CAP	0x8000002218	#define BNXT_FLAG_CHIP_NITRO_A0	0x10000002219	#define BNXT_FLAG_DIM		0x20000002220	#define BNXT_FLAG_ROCE_MIRROR_CAP	0x40000002221	#define BNXT_FLAG_TX_COAL_CMPL	0x80000002222	#define BNXT_FLAG_PORT_STATS_EXT	0x100000002223 2224	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |		\2225					    BNXT_FLAG_RFS |		\2226					    BNXT_FLAG_STRIP_VLAN)2227 2228#define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))2229#define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)2230#define BNXT_NPAR(bp)		((bp)->port_partition_type)2231#define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)2232#define BNXT_SINGLE_PF(bp)	(BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))2233#define BNXT_SH_PORT_CFG_OK(bp)	(BNXT_PF(bp) &&				\2234				 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))2235#define BNXT_PHY_CFG_ABLE(bp)	((BNXT_SINGLE_PF(bp) ||			\2236				  BNXT_SH_PORT_CFG_OK(bp)) &&		\2237				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)2238#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)2239#define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)2240#define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &&	\2241				 (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\2242				  (bp)->max_tpa_v2) && !is_kdump_kernel())2243#define BNXT_RX_JUMBO_MODE(bp)	((bp)->flags & BNXT_FLAG_JUMBO)2244 2245#define BNXT_CHIP_P7(bp)			\2246	((bp)->chip_num == CHIP_NUM_57608)2247 2248#define BNXT_CHIP_P5(bp)			\2249	((bp)->chip_num == CHIP_NUM_57508 ||	\2250	 (bp)->chip_num == CHIP_NUM_57504 ||	\2251	 (bp)->chip_num == CHIP_NUM_57502)2252 2253/* Chip class phase 5 */2254#define BNXT_CHIP_P5_PLUS(bp)			\2255	(BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))2256 2257/* Chip class phase 4.x */2258#define BNXT_CHIP_P4(bp)			\2259	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\2260	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\2261	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\2262	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\2263	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))2264 2265/* Chip class phase 3.x */2266#define BNXT_CHIP_P3(bp)			\2267	(BNXT_CHIP_NUM_57X0X((bp)->chip_num) ||	\2268	 BNXT_CHIP_TYPE_NITRO_A0(bp))2269 2270#define BNXT_CHIP_P4_PLUS(bp)			\2271	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))2272 2273#define BNXT_CHIP_P5_AND_MINUS(bp)		\2274	(BNXT_CHIP_P3(bp) || BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))2275 2276	struct bnxt_aux_priv	*aux_priv;2277	struct bnxt_en_dev	*edev;2278 2279	struct bnxt_napi	**bnapi;2280 2281	struct bnxt_rx_ring_info	*rx_ring;2282	struct bnxt_tx_ring_info	*tx_ring;2283	u16			*tx_ring_map;2284 2285	struct sk_buff *	(*gro_func)(struct bnxt_tpa_info *, int, int,2286					    struct sk_buff *);2287 2288	struct sk_buff *	(*rx_skb_func)(struct bnxt *,2289					       struct bnxt_rx_ring_info *,2290					       u16, void *, u8 *, dma_addr_t,2291					       unsigned int);2292 2293	u16			max_tpa_v2;2294	u16			max_tpa;2295	u32			rx_buf_size;2296	u32			rx_buf_use_size;	/* useable size */2297	u16			rx_offset;2298	u16			rx_dma_offset;2299	enum dma_data_direction	rx_dir;2300	u32			rx_ring_size;2301	u32			rx_agg_ring_size;2302	u32			rx_copy_thresh;2303	u32			rx_ring_mask;2304	u32			rx_agg_ring_mask;2305	int			rx_nr_pages;2306	int			rx_agg_nr_pages;2307	int			rx_nr_rings;2308	int			rsscos_nr_ctxs;2309 2310	u32			tx_ring_size;2311	u32			tx_ring_mask;2312	int			tx_nr_pages;2313	int			tx_nr_rings;2314	int			tx_nr_rings_per_tc;2315	int			tx_nr_rings_xdp;2316 2317	int			tx_wake_thresh;2318	int			tx_push_thresh;2319	int			tx_push_size;2320 2321	u32			cp_ring_size;2322	u32			cp_ring_mask;2323	u32			cp_bit;2324	int			cp_nr_pages;2325	int			cp_nr_rings;2326 2327	/* grp_info indexed by completion ring index */2328	struct bnxt_ring_grp_info	*grp_info;2329	struct bnxt_vnic_info	*vnic_info;2330	u32			num_rss_ctx;2331	int			nr_vnics;2332	u32			*rss_indir_tbl;2333	u16			rss_indir_tbl_entries;2334	u32			rss_hash_cfg;2335	u32			rss_hash_delta;2336	u32			rss_cap;2337#define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA	BIT(0)2338#define BNXT_RSS_CAP_UDP_RSS_CAP		BIT(1)2339#define BNXT_RSS_CAP_NEW_RSS_CAP		BIT(2)2340#define BNXT_RSS_CAP_RSS_TCAM			BIT(3)2341#define BNXT_RSS_CAP_AH_V4_RSS_CAP		BIT(4)2342#define BNXT_RSS_CAP_AH_V6_RSS_CAP		BIT(5)2343#define BNXT_RSS_CAP_ESP_V4_RSS_CAP		BIT(6)2344#define BNXT_RSS_CAP_ESP_V6_RSS_CAP		BIT(7)2345#define BNXT_RSS_CAP_MULTI_RSS_CTX		BIT(8)2346 2347	u8			rss_hash_key[HW_HASH_KEY_SIZE];2348	u8			rss_hash_key_valid:1;2349	u8			rss_hash_key_updated:1;2350 2351	u16			max_mtu;2352	u16			tso_max_segs;2353	u8			max_tc;2354	u8			max_lltc;	/* lossless TCs */2355	struct bnxt_queue_info	q_info[BNXT_MAX_QUEUE];2356	u8			tc_to_qidx[BNXT_MAX_QUEUE];2357	u8			q_ids[BNXT_MAX_QUEUE];2358	u8			max_q;2359	u8			num_tc;2360 2361	unsigned int		current_interval;2362#define BNXT_TIMER_INTERVAL	HZ2363 2364	struct timer_list	timer;2365 2366	unsigned long		state;2367#define BNXT_STATE_OPEN		02368#define BNXT_STATE_IN_SP_TASK	12369#define BNXT_STATE_READ_STATS	22370#define BNXT_STATE_FW_RESET_DET 32371#define BNXT_STATE_IN_FW_RESET	42372#define BNXT_STATE_ABORT_ERR	52373#define BNXT_STATE_FW_FATAL_COND	62374#define BNXT_STATE_DRV_REGISTERED	72375#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN	82376#define BNXT_STATE_NAPI_DISABLED	92377#define BNXT_STATE_L2_FILTER_RETRY	102378#define BNXT_STATE_FW_ACTIVATE		112379#define BNXT_STATE_RECOVER		122380#define BNXT_STATE_FW_NON_FATAL_COND	132381#define BNXT_STATE_FW_ACTIVATE_RESET	142382#define BNXT_STATE_HALF_OPEN		15	/* For offline ethtool tests */2383 2384#define BNXT_NO_FW_ACCESS(bp)					\2385	(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||	\2386	 pci_channel_offline((bp)->pdev))2387 2388	struct bnxt_irq	*irq_tbl;2389	int			total_irqs;2390	int			ulp_num_msix_want;2391	u8			mac_addr[ETH_ALEN];2392 2393#ifdef CONFIG_BNXT_DCB2394	struct ieee_pfc		*ieee_pfc;2395	struct ieee_ets		*ieee_ets;2396	u8			dcbx_cap;2397	u8			default_pri;2398	u8			max_dscp_value;2399#endif /* CONFIG_BNXT_DCB */2400 2401	u32			msg_enable;2402 2403	u64			fw_cap;2404	#define BNXT_FW_CAP_SHORT_CMD			BIT_ULL(0)2405	#define BNXT_FW_CAP_LLDP_AGENT			BIT_ULL(1)2406	#define BNXT_FW_CAP_DCBX_AGENT			BIT_ULL(2)2407	#define BNXT_FW_CAP_NEW_RM			BIT_ULL(3)2408	#define BNXT_FW_CAP_IF_CHANGE			BIT_ULL(4)2409	#define BNXT_FW_CAP_KONG_MB_CHNL		BIT_ULL(7)2410	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		BIT_ULL(10)2411	#define BNXT_FW_CAP_TRUSTED_VF			BIT_ULL(11)2412	#define BNXT_FW_CAP_ERROR_RECOVERY		BIT_ULL(13)2413	#define BNXT_FW_CAP_PKG_VER			BIT_ULL(14)2414	#define BNXT_FW_CAP_CFA_ADV_FLOW		BIT_ULL(15)2415	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	BIT_ULL(16)2416	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	BIT_ULL(17)2417	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		BIT_ULL(18)2418	#define BNXT_FW_CAP_TX_TS_CMP			BIT_ULL(19)2419	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		BIT_ULL(20)2420	#define BNXT_FW_CAP_HOT_RESET			BIT_ULL(21)2421	#define BNXT_FW_CAP_PTP_RTC			BIT_ULL(22)2422	#define BNXT_FW_CAP_RX_ALL_PKT_TS		BIT_ULL(23)2423	#define BNXT_FW_CAP_VLAN_RX_STRIP		BIT_ULL(24)2424	#define BNXT_FW_CAP_VLAN_TX_INSERT		BIT_ULL(25)2425	#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED	BIT_ULL(26)2426	#define BNXT_FW_CAP_LIVEPATCH			BIT_ULL(27)2427	#define BNXT_FW_CAP_PTP_PPS			BIT_ULL(28)2428	#define BNXT_FW_CAP_HOT_RESET_IF		BIT_ULL(29)2429	#define BNXT_FW_CAP_RING_MONITOR		BIT_ULL(30)2430	#define BNXT_FW_CAP_DBG_QCAPS			BIT_ULL(31)2431	#define BNXT_FW_CAP_PTP				BIT_ULL(32)2432	#define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED	BIT_ULL(33)2433	#define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP		BIT_ULL(34)2434	#define BNXT_FW_CAP_PRE_RESV_VNICS		BIT_ULL(35)2435	#define BNXT_FW_CAP_BACKING_STORE_V2		BIT_ULL(36)2436	#define BNXT_FW_CAP_VNIC_TUNNEL_TPA		BIT_ULL(37)2437	#define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO	BIT_ULL(38)2438	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3	BIT_ULL(39)2439	#define BNXT_FW_CAP_VNIC_RE_FLUSH		BIT_ULL(40)2440 2441	u32			fw_dbg_cap;2442 2443#define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)2444#define BNXT_PTP_USE_RTC(bp)	(!BNXT_MH(bp) && \2445				 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))2446#define BNXT_SUPPORTS_NTUPLE_VNIC(bp)	\2447	(BNXT_PF(bp) && ((bp)->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3))2448 2449#define BNXT_SUPPORTS_MULTI_RSS_CTX(bp)				\2450	(BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) &&	\2451	 ((bp)->rss_cap & BNXT_RSS_CAP_MULTI_RSS_CTX))2452#define BNXT_SUPPORTS_QUEUE_API(bp)				\2453	(BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) &&	\2454	 ((bp)->fw_cap & BNXT_FW_CAP_VNIC_RE_FLUSH))2455 2456	u32			hwrm_spec_code;2457	u16			hwrm_cmd_seq;2458	u16                     hwrm_cmd_kong_seq;2459	struct dma_pool		*hwrm_dma_pool;2460	struct hlist_head	hwrm_pending_list;2461 2462	struct rtnl_link_stats64	net_stats_prev;2463	struct bnxt_stats_mem	port_stats;2464	struct bnxt_stats_mem	rx_port_stats_ext;2465	struct bnxt_stats_mem	tx_port_stats_ext;2466	u16			fw_rx_stats_ext_size;2467	u16			fw_tx_stats_ext_size;2468	u16			hw_ring_stats_size;2469	u8			pri2cos_idx[8];2470	u8			pri2cos_valid;2471 2472	struct bnxt_total_ring_err_stats ring_err_stats_prev;2473 2474	u16			hwrm_max_req_len;2475	u16			hwrm_max_ext_req_len;2476	unsigned int		hwrm_cmd_timeout;2477	unsigned int		hwrm_cmd_max_timeout;2478	struct mutex		hwrm_cmd_lock;	/* serialize hwrm messages */2479	struct hwrm_ver_get_output	ver_resp;2480#define FW_VER_STR_LEN		322481#define BC_HWRM_STR_LEN		212482#define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)2483	char			fw_ver_str[FW_VER_STR_LEN];2484	char			hwrm_ver_supp[FW_VER_STR_LEN];2485	char			nvm_cfg_ver[FW_VER_STR_LEN];2486	u64			fw_ver_code;2487#define BNXT_FW_VER_CODE(maj, min, bld, rsv)			\2488	((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))2489#define BNXT_FW_MAJ(bp)		((bp)->fw_ver_code >> 48)2490#define BNXT_FW_BLD(bp)		(((bp)->fw_ver_code >> 16) & 0xffff)2491 2492	u16			vxlan_fw_dst_port_id;2493	u16			nge_fw_dst_port_id;2494	u16			vxlan_gpe_fw_dst_port_id;2495	__be16			vxlan_port;2496	__be16			nge_port;2497	__be16			vxlan_gpe_port;2498	u8			port_partition_type;2499	u8			port_count;2500	u16			br_mode;2501 2502	struct bnxt_coal_cap	coal_cap;2503	struct bnxt_coal	rx_coal;2504	struct bnxt_coal	tx_coal;2505 2506	u32			stats_coal_ticks;2507#define BNXT_DEF_STATS_COAL_TICKS	 10000002508#define BNXT_MIN_STATS_COAL_TICKS	  2500002509#define BNXT_MAX_STATS_COAL_TICKS	 10000002510 2511	struct work_struct	sp_task;2512	unsigned long		sp_event;2513#define BNXT_RX_MASK_SP_EVENT		02514#define BNXT_RX_NTP_FLTR_SP_EVENT	12515#define BNXT_LINK_CHNG_SP_EVENT		22516#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT	32517#define BNXT_RESET_TASK_SP_EVENT	62518#define BNXT_RST_RING_SP_EVENT		72519#define BNXT_HWRM_PF_UNLOAD_SP_EVENT	82520#define BNXT_PERIODIC_STATS_SP_EVENT	92521#define BNXT_HWRM_PORT_MODULE_SP_EVENT	102522#define BNXT_RESET_TASK_SILENT_SP_EVENT	112523#define BNXT_LINK_SPEED_CHNG_SP_EVENT	142524#define BNXT_FLOW_STATS_SP_EVENT	152525#define BNXT_UPDATE_PHY_SP_EVENT	162526#define BNXT_RING_COAL_NOW_SP_EVENT	172527#define BNXT_FW_RESET_NOTIFY_SP_EVENT	182528#define BNXT_FW_EXCEPTION_SP_EVENT	192529#define BNXT_LINK_CFG_CHANGE_SP_EVENT	212530#define BNXT_THERMAL_THRESHOLD_SP_EVENT	222531#define BNXT_FW_ECHO_REQUEST_SP_EVENT	232532#define BNXT_RESTART_ULP_SP_EVENT	242533 2534	struct delayed_work	fw_reset_task;2535	int			fw_reset_state;2536#define BNXT_FW_RESET_STATE_POLL_VF	12537#define BNXT_FW_RESET_STATE_RESET_FW	22538#define BNXT_FW_RESET_STATE_ENABLE_DEV	32539#define BNXT_FW_RESET_STATE_POLL_FW	42540#define BNXT_FW_RESET_STATE_OPENING	52541#define BNXT_FW_RESET_STATE_POLL_FW_DOWN	62542 2543	u16			fw_reset_min_dsecs;2544#define BNXT_DFLT_FW_RST_MIN_DSECS	202545	u16			fw_reset_max_dsecs;2546#define BNXT_DFLT_FW_RST_MAX_DSECS	602547	unsigned long		fw_reset_timestamp;2548 2549	struct bnxt_fw_health	*fw_health;2550 2551	struct bnxt_hw_resc	hw_resc;2552	struct bnxt_pf_info	pf;2553	struct bnxt_ctx_mem_info	*ctx;2554#ifdef CONFIG_BNXT_SRIOV2555	int			nr_vfs;2556	struct bnxt_vf_info	vf;2557	wait_queue_head_t	sriov_cfg_wait;2558	bool			sriov_cfg;2559#define BNXT_SRIOV_CFG_WAIT_TMO	msecs_to_jiffies(10000)2560#endif2561 2562#if BITS_PER_LONG == 322563	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */2564	spinlock_t		db_lock;2565#endif2566	int			db_offset;	/* db_offset within db_size */2567	int			db_size;2568 2569#define BNXT_NTP_FLTR_MAX_FLTR	40962570#define BNXT_MAX_FLTR		(BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)2571#define BNXT_NTP_FLTR_HASH_SIZE	5122572#define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)2573	struct hlist_head	ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];2574	spinlock_t		ntp_fltr_lock;	/* for hash table add, del */2575 2576	unsigned long		*ntp_fltr_bmap;2577	int			ntp_fltr_count;2578	int			max_fltr;2579 2580#define BNXT_L2_FLTR_MAX_FLTR	10242581#define BNXT_L2_FLTR_HASH_SIZE	322582#define BNXT_L2_FLTR_HASH_MASK	(BNXT_L2_FLTR_HASH_SIZE - 1)2583	struct hlist_head	l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];2584 2585	u32			hash_seed;2586	u64			toeplitz_prefix;2587 2588	struct list_head	usr_fltr_list;2589 2590	/* To protect link related settings during link changes and2591	 * ethtool settings changes.2592	 */2593	struct mutex		link_lock;2594	struct bnxt_link_info	link_info;2595	struct ethtool_keee	eee;2596	u32			lpi_tmr_lo;2597	u32			lpi_tmr_hi;2598 2599	/* copied from flags and flags2 in hwrm_port_phy_qcaps_output */2600	u32			phy_flags;2601#define BNXT_PHY_FL_EEE_CAP		PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED2602#define BNXT_PHY_FL_EXT_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED2603#define BNXT_PHY_FL_AN_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED2604#define BNXT_PHY_FL_SHARED_PORT_CFG	PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED2605#define BNXT_PHY_FL_PORT_STATS_NO_RESET	PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET2606#define BNXT_PHY_FL_NO_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED2607#define BNXT_PHY_FL_FW_MANAGED_LKDN	PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN2608#define BNXT_PHY_FL_NO_FCS		PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS2609#define BNXT_PHY_FL_NO_PAUSE		(PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)2610#define BNXT_PHY_FL_NO_PFC		(PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)2611#define BNXT_PHY_FL_BANK_SEL		(PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)2612#define BNXT_PHY_FL_SPEEDS2		(PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)2613 2614	u8			num_tests;2615	struct bnxt_test_info	*test_info;2616 2617	u8			wol_filter_id;2618	u8			wol;2619 2620	u8			num_leds;2621	struct bnxt_led_info	leds[BNXT_MAX_LED];2622	u16			dump_flag;2623#define BNXT_DUMP_LIVE		02624#define BNXT_DUMP_CRASH		12625 2626	struct bpf_prog		*xdp_prog;2627 2628	struct bnxt_ptp_cfg	*ptp_cfg;2629	u8			ptp_all_rx_tstamp;2630 2631	/* devlink interface and vf-rep structs */2632	struct devlink		*dl;2633	struct devlink_port	dl_port;2634	enum devlink_eswitch_mode eswitch_mode;2635	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */2636	u16			*cfa_code_map; /* cfa_code -> vf_idx map */2637	u8			dsn[8];2638	struct bnxt_tc_info	*tc_info;2639	struct list_head	tc_indr_block_list;2640	struct dentry		*debugfs_pdev;2641#ifdef CONFIG_BNXT_HWMON2642	struct device		*hwmon_dev;2643	u8			warn_thresh_temp;2644	u8			crit_thresh_temp;2645	u8			fatal_thresh_temp;2646	u8			shutdown_thresh_temp;2647#endif2648	u32			thermal_threshold_type;2649	enum board_idx		board_idx;2650 2651	struct bnxt_ctx_pg_info	*fw_crash_mem;2652	u32			fw_crash_len;2653};2654 2655#define BNXT_NUM_RX_RING_STATS			82656#define BNXT_NUM_TX_RING_STATS			82657#define BNXT_NUM_TPA_RING_STATS			42658#define BNXT_NUM_TPA_RING_STATS_P5		52659#define BNXT_NUM_TPA_RING_STATS_P7		62660 2661#define BNXT_RING_STATS_SIZE_P5					\2662	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\2663	  BNXT_NUM_TPA_RING_STATS_P5) * 8)2664 2665#define BNXT_RING_STATS_SIZE_P7					\2666	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\2667	  BNXT_NUM_TPA_RING_STATS_P7) * 8)2668 2669#define BNXT_GET_RING_STATS64(sw, counter)		\2670	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))2671 2672#define BNXT_GET_RX_PORT_STATS64(sw, counter)		\2673	(*((sw) + offsetof(struct rx_port_stats, counter) / 8))2674 2675#define BNXT_GET_TX_PORT_STATS64(sw, counter)		\2676	(*((sw) + offsetof(struct tx_port_stats, counter) / 8))2677 2678#define BNXT_PORT_STATS_SIZE				\2679	(sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)2680 2681#define BNXT_TX_PORT_STATS_BYTE_OFFSET			\2682	(sizeof(struct rx_port_stats) + 512)2683 2684#define BNXT_RX_STATS_OFFSET(counter)			\2685	(offsetof(struct rx_port_stats, counter) / 8)2686 2687#define BNXT_TX_STATS_OFFSET(counter)			\2688	((offsetof(struct tx_port_stats, counter) +	\2689	  BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)2690 2691#define BNXT_RX_STATS_EXT_OFFSET(counter)		\2692	(offsetof(struct rx_port_stats_ext, counter) / 8)2693 2694#define BNXT_RX_STATS_EXT_NUM_LEGACY                   \2695	BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)2696 2697#define BNXT_TX_STATS_EXT_OFFSET(counter)		\2698	(offsetof(struct tx_port_stats_ext, counter) / 8)2699 2700#define BNXT_HW_FEATURE_VLAN_ALL_RX				\2701	(NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)2702#define BNXT_HW_FEATURE_VLAN_ALL_TX				\2703	(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)2704 2705#define I2C_DEV_ADDR_A0				0xa02706#define I2C_DEV_ADDR_A2				0xa22707#define SFF_DIAG_SUPPORT_OFFSET			0x5c2708#define SFF_MODULE_ID_SFP			0x32709#define SFF_MODULE_ID_QSFP			0xc2710#define SFF_MODULE_ID_QSFP_PLUS			0xd2711#define SFF_MODULE_ID_QSFP28			0x112712#define BNXT_MAX_PHY_I2C_RESP_SIZE		642713 2714static inline u32 bnxt_tx_avail(struct bnxt *bp,2715				const struct bnxt_tx_ring_info *txr)2716{2717	u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);2718 2719	return bp->tx_ring_size - (used & bp->tx_ring_mask);2720}2721 2722static inline void bnxt_writeq(struct bnxt *bp, u64 val,2723			       volatile void __iomem *addr)2724{2725#if BITS_PER_LONG == 322726	spin_lock(&bp->db_lock);2727	lo_hi_writeq(val, addr);2728	spin_unlock(&bp->db_lock);2729#else2730	writeq(val, addr);2731#endif2732}2733 2734static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,2735				       volatile void __iomem *addr)2736{2737#if BITS_PER_LONG == 322738	spin_lock(&bp->db_lock);2739	lo_hi_writeq_relaxed(val, addr);2740	spin_unlock(&bp->db_lock);2741#else2742	writeq_relaxed(val, addr);2743#endif2744}2745 2746/* For TX and RX ring doorbells with no ordering guarantee*/2747static inline void bnxt_db_write_relaxed(struct bnxt *bp,2748					 struct bnxt_db_info *db, u32 idx)2749{2750	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {2751		bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),2752				    db->doorbell);2753	} else {2754		u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);2755 2756		writel_relaxed(db_val, db->doorbell);2757		if (bp->flags & BNXT_FLAG_DOUBLE_DB)2758			writel_relaxed(db_val, db->doorbell);2759	}2760}2761 2762/* For TX and RX ring doorbells */2763static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,2764				 u32 idx)2765{2766	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {2767		bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),2768			    db->doorbell);2769	} else {2770		u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);2771 2772		writel(db_val, db->doorbell);2773		if (bp->flags & BNXT_FLAG_DOUBLE_DB)2774			writel(db_val, db->doorbell);2775	}2776}2777 2778/* Must hold rtnl_lock */2779static inline bool bnxt_sriov_cfg(struct bnxt *bp)2780{2781#if defined(CONFIG_BNXT_SRIOV)2782	return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);2783#else2784	return false;2785#endif2786}2787 2788extern const u16 bnxt_lhint_arr[];2789 2790int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,2791		       u16 prod, gfp_t gfp);2792void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);2793u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);2794void bnxt_set_tpa_flags(struct bnxt *bp);2795void bnxt_set_ring_params(struct bnxt *);2796int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);2797void bnxt_insert_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);2798void bnxt_del_one_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);2799int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,2800			    int bmap_size, bool async_only);2801int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);2802void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);2803struct bnxt_l2_filter *bnxt_alloc_new_l2_filter(struct bnxt *bp,2804						struct bnxt_l2_key *key,2805						u16 flags);2806int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);2807int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);2808int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,2809				     struct bnxt_ntuple_filter *fltr);2810int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,2811				      struct bnxt_ntuple_filter *fltr);2812int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, struct bnxt_vnic_info *vnic,2813			   u32 tpa_flags);2814void bnxt_fill_ipv6_mask(__be32 mask[4]);2815void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp,2816				 struct ethtool_rxfh_context *rss_ctx);2817int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);2818int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic);2819int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic,2820			 unsigned int start_rx_ring_idx,2821			 unsigned int nr_rings);2822int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);2823int bnxt_nq_rings_in_use(struct bnxt *bp);2824int bnxt_hwrm_set_coal(struct bnxt *);2825void bnxt_free_ctx_mem(struct bnxt *bp);2826int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);2827unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);2828unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);2829unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);2830unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);2831int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);2832void bnxt_tx_disable(struct bnxt *bp);2833void bnxt_tx_enable(struct bnxt *bp);2834void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,2835			  u16 curr);2836void bnxt_report_link(struct bnxt *bp);2837int bnxt_update_link(struct bnxt *bp, bool chng_link_state);2838int bnxt_hwrm_set_pause(struct bnxt *);2839int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);2840int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);2841int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);2842int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);2843int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);2844int bnxt_hwrm_func_qcaps(struct bnxt *bp);2845int bnxt_hwrm_fw_set_time(struct bnxt *);2846int bnxt_hwrm_vnic_update(struct bnxt *bp, struct bnxt_vnic_info *vnic,2847			  u8 valid);2848int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);2849int __bnxt_setup_vnic_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);2850void bnxt_del_one_rss_ctx(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx,2851			  bool all);2852int bnxt_open_nic(struct bnxt *, bool, bool);2853int bnxt_half_open_nic(struct bnxt *bp);2854void bnxt_half_close_nic(struct bnxt *bp);2855void bnxt_reenable_sriov(struct bnxt *bp);2856void bnxt_close_nic(struct bnxt *, bool, bool);2857void bnxt_get_ring_err_stats(struct bnxt *bp,2858			     struct bnxt_total_ring_err_stats *stats);2859bool bnxt_rfs_capable(struct bnxt *bp, bool new_rss_ctx);2860int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,2861			 u32 *reg_buf);2862void bnxt_fw_exception(struct bnxt *bp);2863void bnxt_fw_reset(struct bnxt *bp);2864int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,2865		     int tx_xdp);2866int bnxt_fw_init_one(struct bnxt *bp);2867bool bnxt_hwrm_reset_permitted(struct bnxt *bp);2868int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);2869struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,2870				struct bnxt_ntuple_filter *fltr, u32 idx);2871u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,2872			    const struct sk_buff *skb);2873int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,2874			   u32 idx);2875void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr);2876int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);2877int bnxt_restore_pf_fw_resources(struct bnxt *bp);2878int bnxt_get_port_parent_id(struct net_device *dev,2879			    struct netdev_phys_item_id *ppid);2880void bnxt_dim_work(struct work_struct *work);2881int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);2882void bnxt_print_device_info(struct bnxt *bp);2883#endif2884