800 lines · c
1/* Broadcom NetXtreme-C/E network driver.2 *3 * Copyright (c) 2014-2016 Broadcom Corporation4 * Copyright (c) 2016-2017 Broadcom Limited5 *6 * This program is free software; you can redistribute it and/or modify7 * it under the terms of the GNU General Public License as published by8 * the Free Software Foundation.9 */10 11#include <linux/netdevice.h>12#include <linux/types.h>13#include <linux/errno.h>14#include <linux/rtnetlink.h>15#include <linux/interrupt.h>16#include <linux/pci.h>17#include <linux/etherdevice.h>18#include <rdma/ib_verbs.h>19#include "bnxt_hsi.h"20#include "bnxt.h"21#include "bnxt_hwrm.h"22#include "bnxt_dcb.h"23 24#ifdef CONFIG_BNXT_DCB25static int bnxt_queue_to_tc(struct bnxt *bp, u8 queue_id)26{27 int i, j;28 29 for (i = 0; i < bp->max_tc; i++) {30 if (bp->q_info[i].queue_id == queue_id) {31 for (j = 0; j < bp->max_tc; j++) {32 if (bp->tc_to_qidx[j] == i)33 return j;34 }35 }36 }37 return -EINVAL;38}39 40static int bnxt_hwrm_queue_pri2cos_cfg(struct bnxt *bp, struct ieee_ets *ets)41{42 struct hwrm_queue_pri2cos_cfg_input *req;43 u8 *pri2cos;44 int rc, i;45 46 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PRI2COS_CFG);47 if (rc)48 return rc;49 50 req->flags = cpu_to_le32(QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR |51 QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN);52 53 pri2cos = &req->pri0_cos_queue_id;54 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {55 u8 qidx;56 57 req->enables |= cpu_to_le32(58 QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID << i);59 60 qidx = bp->tc_to_qidx[ets->prio_tc[i]];61 pri2cos[i] = bp->q_info[qidx].queue_id;62 }63 return hwrm_req_send(bp, req);64}65 66static int bnxt_hwrm_queue_pri2cos_qcfg(struct bnxt *bp, struct ieee_ets *ets)67{68 struct hwrm_queue_pri2cos_qcfg_output *resp;69 struct hwrm_queue_pri2cos_qcfg_input *req;70 int rc;71 72 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PRI2COS_QCFG);73 if (rc)74 return rc;75 76 req->flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);77 resp = hwrm_req_hold(bp, req);78 rc = hwrm_req_send(bp, req);79 if (!rc) {80 u8 *pri2cos = &resp->pri0_cos_queue_id;81 int i;82 83 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {84 u8 queue_id = pri2cos[i];85 int tc;86 87 tc = bnxt_queue_to_tc(bp, queue_id);88 if (tc >= 0)89 ets->prio_tc[i] = tc;90 }91 }92 hwrm_req_drop(bp, req);93 return rc;94}95 96static int bnxt_hwrm_queue_cos2bw_cfg(struct bnxt *bp, struct ieee_ets *ets,97 u8 max_tc)98{99 struct hwrm_queue_cos2bw_cfg_input *req;100 struct bnxt_cos2bw_cfg cos2bw;101 int rc, i;102 103 rc = hwrm_req_init(bp, req, HWRM_QUEUE_COS2BW_CFG);104 if (rc)105 return rc;106 107 for (i = 0; i < max_tc; i++) {108 u8 qidx = bp->tc_to_qidx[i];109 110 req->enables |= cpu_to_le32(111 QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID <<112 qidx);113 114 memset(&cos2bw, 0, sizeof(cos2bw));115 cos2bw.queue_id = bp->q_info[qidx].queue_id;116 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_STRICT) {117 cos2bw.tsa =118 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP;119 cos2bw.pri_lvl = i;120 } else {121 cos2bw.tsa =122 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS;123 cos2bw.bw_weight = ets->tc_tx_bw[i];124 /* older firmware requires min_bw to be set to the125 * same weight value in percent.126 */127 cos2bw.min_bw =128 cpu_to_le32((ets->tc_tx_bw[i] * 100) |129 BW_VALUE_UNIT_PERCENT1_100);130 }131 if (qidx == 0) {132 req->queue_id0 = cos2bw.queue_id;133 req->queue_id0_min_bw = cos2bw.min_bw;134 req->queue_id0_max_bw = cos2bw.max_bw;135 req->queue_id0_tsa_assign = cos2bw.tsa;136 req->queue_id0_pri_lvl = cos2bw.pri_lvl;137 req->queue_id0_bw_weight = cos2bw.bw_weight;138 } else {139 memcpy(&req->cfg[i - 1], &cos2bw.cfg, sizeof(cos2bw.cfg));140 }141 }142 return hwrm_req_send(bp, req);143}144 145static int bnxt_hwrm_queue_cos2bw_qcfg(struct bnxt *bp, struct ieee_ets *ets)146{147 struct hwrm_queue_cos2bw_qcfg_output *resp;148 struct hwrm_queue_cos2bw_qcfg_input *req;149 struct bnxt_cos2bw_cfg cos2bw;150 int rc, i;151 152 rc = hwrm_req_init(bp, req, HWRM_QUEUE_COS2BW_QCFG);153 if (rc)154 return rc;155 156 resp = hwrm_req_hold(bp, req);157 rc = hwrm_req_send(bp, req);158 if (rc) {159 hwrm_req_drop(bp, req);160 return rc;161 }162 163 for (i = 0; i < bp->max_tc; i++) {164 int tc;165 166 if (i == 0) {167 cos2bw.queue_id = resp->queue_id0;168 cos2bw.min_bw = resp->queue_id0_min_bw;169 cos2bw.max_bw = resp->queue_id0_max_bw;170 cos2bw.tsa = resp->queue_id0_tsa_assign;171 cos2bw.pri_lvl = resp->queue_id0_pri_lvl;172 cos2bw.bw_weight = resp->queue_id0_bw_weight;173 } else {174 memcpy(&cos2bw.cfg, &resp->cfg[i - 1], sizeof(cos2bw.cfg));175 }176 177 tc = bnxt_queue_to_tc(bp, cos2bw.queue_id);178 if (tc < 0)179 continue;180 181 if (cos2bw.tsa ==182 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP) {183 ets->tc_tsa[tc] = IEEE_8021QAZ_TSA_STRICT;184 } else {185 ets->tc_tsa[tc] = IEEE_8021QAZ_TSA_ETS;186 ets->tc_tx_bw[tc] = cos2bw.bw_weight;187 }188 }189 hwrm_req_drop(bp, req);190 return 0;191}192 193static int bnxt_queue_remap(struct bnxt *bp, unsigned int lltc_mask)194{195 unsigned long qmap = 0;196 int max = bp->max_tc;197 int i, j, rc;198 199 /* Assign lossless TCs first */200 for (i = 0, j = 0; i < max; ) {201 if (lltc_mask & (1 << i)) {202 if (BNXT_LLQ(bp->q_info[j].queue_profile)) {203 bp->tc_to_qidx[i] = j;204 __set_bit(j, &qmap);205 i++;206 }207 j++;208 continue;209 }210 i++;211 }212 213 for (i = 0, j = 0; i < max; i++) {214 if (lltc_mask & (1 << i))215 continue;216 j = find_next_zero_bit(&qmap, max, j);217 bp->tc_to_qidx[i] = j;218 __set_bit(j, &qmap);219 j++;220 }221 222 if (netif_running(bp->dev)) {223 bnxt_close_nic(bp, false, false);224 rc = bnxt_open_nic(bp, false, false);225 if (rc) {226 netdev_warn(bp->dev, "failed to open NIC, rc = %d\n", rc);227 return rc;228 }229 }230 if (bp->ieee_ets) {231 int tc = bp->num_tc;232 233 if (!tc)234 tc = 1;235 rc = bnxt_hwrm_queue_cos2bw_cfg(bp, bp->ieee_ets, tc);236 if (rc) {237 netdev_warn(bp->dev, "failed to config BW, rc = %d\n", rc);238 return rc;239 }240 rc = bnxt_hwrm_queue_pri2cos_cfg(bp, bp->ieee_ets);241 if (rc) {242 netdev_warn(bp->dev, "failed to config prio, rc = %d\n", rc);243 return rc;244 }245 }246 return 0;247}248 249static int bnxt_hwrm_queue_pfc_cfg(struct bnxt *bp, struct ieee_pfc *pfc)250{251 struct hwrm_queue_pfcenable_cfg_input *req;252 struct ieee_ets *my_ets = bp->ieee_ets;253 unsigned int tc_mask = 0, pri_mask = 0;254 u8 i, pri, lltc_count = 0;255 bool need_q_remap = false;256 int rc;257 258 if (!my_ets)259 return -EINVAL;260 261 for (i = 0; i < bp->max_tc; i++) {262 for (pri = 0; pri < IEEE_8021QAZ_MAX_TCS; pri++) {263 if ((pfc->pfc_en & (1 << pri)) &&264 (my_ets->prio_tc[pri] == i)) {265 pri_mask |= 1 << pri;266 tc_mask |= 1 << i;267 }268 }269 if (tc_mask & (1 << i))270 lltc_count++;271 }272 if (lltc_count > bp->max_lltc)273 return -EINVAL;274 275 for (i = 0; i < bp->max_tc; i++) {276 if (tc_mask & (1 << i)) {277 u8 qidx = bp->tc_to_qidx[i];278 279 if (!BNXT_LLQ(bp->q_info[qidx].queue_profile)) {280 need_q_remap = true;281 break;282 }283 }284 }285 286 if (need_q_remap)287 bnxt_queue_remap(bp, tc_mask);288 289 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCENABLE_CFG);290 if (rc)291 return rc;292 293 req->flags = cpu_to_le32(pri_mask);294 return hwrm_req_send(bp, req);295}296 297static int bnxt_hwrm_queue_pfc_qcfg(struct bnxt *bp, struct ieee_pfc *pfc)298{299 struct hwrm_queue_pfcenable_qcfg_output *resp;300 struct hwrm_queue_pfcenable_qcfg_input *req;301 u8 pri_mask;302 int rc;303 304 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCENABLE_QCFG);305 if (rc)306 return rc;307 308 resp = hwrm_req_hold(bp, req);309 rc = hwrm_req_send(bp, req);310 if (rc) {311 hwrm_req_drop(bp, req);312 return rc;313 }314 315 pri_mask = le32_to_cpu(resp->flags);316 pfc->pfc_en = pri_mask;317 hwrm_req_drop(bp, req);318 return 0;319}320 321static int bnxt_hwrm_set_dcbx_app(struct bnxt *bp, struct dcb_app *app,322 bool add)323{324 struct hwrm_fw_set_structured_data_input *set;325 struct hwrm_fw_get_structured_data_input *get;326 struct hwrm_struct_data_dcbx_app *fw_app;327 struct hwrm_struct_hdr *data;328 dma_addr_t mapping;329 size_t data_len;330 int rc, n, i;331 332 if (bp->hwrm_spec_code < 0x10601)333 return 0;334 335 rc = hwrm_req_init(bp, get, HWRM_FW_GET_STRUCTURED_DATA);336 if (rc)337 return rc;338 339 hwrm_req_hold(bp, get);340 hwrm_req_alloc_flags(bp, get, GFP_KERNEL | __GFP_ZERO);341 342 n = IEEE_8021QAZ_MAX_TCS;343 data_len = sizeof(*data) + sizeof(*fw_app) * n;344 data = hwrm_req_dma_slice(bp, get, data_len, &mapping);345 if (!data) {346 rc = -ENOMEM;347 goto set_app_exit;348 }349 350 get->dest_data_addr = cpu_to_le64(mapping);351 get->structure_id = cpu_to_le16(STRUCT_HDR_STRUCT_ID_DCBX_APP);352 get->subtype = cpu_to_le16(HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL);353 get->count = 0;354 rc = hwrm_req_send(bp, get);355 if (rc)356 goto set_app_exit;357 358 fw_app = (struct hwrm_struct_data_dcbx_app *)(data + 1);359 360 if (data->struct_id != cpu_to_le16(STRUCT_HDR_STRUCT_ID_DCBX_APP)) {361 rc = -ENODEV;362 goto set_app_exit;363 }364 365 n = data->count;366 for (i = 0; i < n; i++, fw_app++) {367 if (fw_app->protocol_id == cpu_to_be16(app->protocol) &&368 fw_app->protocol_selector == app->selector &&369 fw_app->priority == app->priority) {370 if (add)371 goto set_app_exit;372 else373 break;374 }375 }376 if (add) {377 /* append */378 n++;379 fw_app->protocol_id = cpu_to_be16(app->protocol);380 fw_app->protocol_selector = app->selector;381 fw_app->priority = app->priority;382 fw_app->valid = 1;383 } else {384 size_t len = 0;385 386 /* not found, nothing to delete */387 if (n == i)388 goto set_app_exit;389 390 len = (n - 1 - i) * sizeof(*fw_app);391 if (len)392 memmove(fw_app, fw_app + 1, len);393 n--;394 memset(fw_app + n, 0, sizeof(*fw_app));395 }396 data->count = n;397 data->len = cpu_to_le16(sizeof(*fw_app) * n);398 data->subtype = cpu_to_le16(HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL);399 400 rc = hwrm_req_init(bp, set, HWRM_FW_SET_STRUCTURED_DATA);401 if (rc)402 goto set_app_exit;403 404 set->src_data_addr = cpu_to_le64(mapping);405 set->data_len = cpu_to_le16(sizeof(*data) + sizeof(*fw_app) * n);406 set->hdr_cnt = 1;407 rc = hwrm_req_send(bp, set);408 409set_app_exit:410 hwrm_req_drop(bp, get); /* dropping get request and associated slice */411 return rc;412}413 414static int bnxt_hwrm_queue_dscp_qcaps(struct bnxt *bp)415{416 struct hwrm_queue_dscp_qcaps_output *resp;417 struct hwrm_queue_dscp_qcaps_input *req;418 int rc;419 420 bp->max_dscp_value = 0;421 if (bp->hwrm_spec_code < 0x10800 || BNXT_VF(bp))422 return 0;423 424 rc = hwrm_req_init(bp, req, HWRM_QUEUE_DSCP_QCAPS);425 if (rc)426 return rc;427 428 resp = hwrm_req_hold(bp, req);429 rc = hwrm_req_send_silent(bp, req);430 if (!rc) {431 bp->max_dscp_value = (1 << resp->num_dscp_bits) - 1;432 if (bp->max_dscp_value < 0x3f)433 bp->max_dscp_value = 0;434 }435 hwrm_req_drop(bp, req);436 return rc;437}438 439static int bnxt_hwrm_queue_dscp2pri_cfg(struct bnxt *bp, struct dcb_app *app,440 bool add)441{442 struct hwrm_queue_dscp2pri_cfg_input *req;443 struct bnxt_dscp2pri_entry *dscp2pri;444 dma_addr_t mapping;445 int rc;446 447 if (bp->hwrm_spec_code < 0x10800)448 return 0;449 450 rc = hwrm_req_init(bp, req, HWRM_QUEUE_DSCP2PRI_CFG);451 if (rc)452 return rc;453 454 dscp2pri = hwrm_req_dma_slice(bp, req, sizeof(*dscp2pri), &mapping);455 if (!dscp2pri) {456 hwrm_req_drop(bp, req);457 return -ENOMEM;458 }459 460 req->src_data_addr = cpu_to_le64(mapping);461 dscp2pri->dscp = app->protocol;462 if (add)463 dscp2pri->mask = 0x3f;464 else465 dscp2pri->mask = 0;466 dscp2pri->pri = app->priority;467 req->entry_cnt = cpu_to_le16(1);468 rc = hwrm_req_send(bp, req);469 return rc;470}471 472static int bnxt_ets_validate(struct bnxt *bp, struct ieee_ets *ets, u8 *tc)473{474 int total_ets_bw = 0;475 bool zero = false;476 u8 max_tc = 0;477 int i;478 479 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {480 if (ets->prio_tc[i] > bp->max_tc) {481 netdev_err(bp->dev, "priority to TC mapping exceeds TC count %d\n",482 ets->prio_tc[i]);483 return -EINVAL;484 }485 if (ets->prio_tc[i] > max_tc)486 max_tc = ets->prio_tc[i];487 488 if ((ets->tc_tx_bw[i] || ets->tc_tsa[i]) && i > bp->max_tc)489 return -EINVAL;490 491 switch (ets->tc_tsa[i]) {492 case IEEE_8021QAZ_TSA_STRICT:493 break;494 case IEEE_8021QAZ_TSA_ETS:495 total_ets_bw += ets->tc_tx_bw[i];496 zero = zero || !ets->tc_tx_bw[i];497 break;498 default:499 return -ENOTSUPP;500 }501 }502 if (total_ets_bw > 100) {503 netdev_warn(bp->dev, "rejecting ETS config exceeding available bandwidth\n");504 return -EINVAL;505 }506 if (zero && total_ets_bw == 100) {507 netdev_warn(bp->dev, "rejecting ETS config starving a TC\n");508 return -EINVAL;509 }510 511 if (max_tc >= bp->max_tc)512 *tc = bp->max_tc;513 else514 *tc = max_tc + 1;515 return 0;516}517 518static int bnxt_dcbnl_ieee_getets(struct net_device *dev, struct ieee_ets *ets)519{520 struct bnxt *bp = netdev_priv(dev);521 struct ieee_ets *my_ets = bp->ieee_ets;522 int rc;523 524 ets->ets_cap = bp->max_tc;525 526 if (!my_ets) {527 if (bp->dcbx_cap & DCB_CAP_DCBX_HOST)528 return 0;529 530 my_ets = kzalloc(sizeof(*my_ets), GFP_KERNEL);531 if (!my_ets)532 return -ENOMEM;533 rc = bnxt_hwrm_queue_cos2bw_qcfg(bp, my_ets);534 if (rc)535 goto error;536 rc = bnxt_hwrm_queue_pri2cos_qcfg(bp, my_ets);537 if (rc)538 goto error;539 540 /* cache result */541 bp->ieee_ets = my_ets;542 }543 544 ets->cbs = my_ets->cbs;545 memcpy(ets->tc_tx_bw, my_ets->tc_tx_bw, sizeof(ets->tc_tx_bw));546 memcpy(ets->tc_rx_bw, my_ets->tc_rx_bw, sizeof(ets->tc_rx_bw));547 memcpy(ets->tc_tsa, my_ets->tc_tsa, sizeof(ets->tc_tsa));548 memcpy(ets->prio_tc, my_ets->prio_tc, sizeof(ets->prio_tc));549 return 0;550error:551 kfree(my_ets);552 return rc;553}554 555static int bnxt_dcbnl_ieee_setets(struct net_device *dev, struct ieee_ets *ets)556{557 struct bnxt *bp = netdev_priv(dev);558 struct ieee_ets *my_ets = bp->ieee_ets;559 u8 max_tc = 0;560 int rc, i;561 562 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||563 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))564 return -EINVAL;565 566 rc = bnxt_ets_validate(bp, ets, &max_tc);567 if (!rc) {568 if (!my_ets) {569 my_ets = kzalloc(sizeof(*my_ets), GFP_KERNEL);570 if (!my_ets)571 return -ENOMEM;572 /* initialize PRI2TC mappings to invalid value */573 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)574 my_ets->prio_tc[i] = IEEE_8021QAZ_MAX_TCS;575 bp->ieee_ets = my_ets;576 }577 rc = bnxt_setup_mq_tc(dev, max_tc);578 if (rc)579 return rc;580 rc = bnxt_hwrm_queue_cos2bw_cfg(bp, ets, max_tc);581 if (rc)582 return rc;583 rc = bnxt_hwrm_queue_pri2cos_cfg(bp, ets);584 if (rc)585 return rc;586 memcpy(my_ets, ets, sizeof(*my_ets));587 }588 return rc;589}590 591static int bnxt_dcbnl_ieee_getpfc(struct net_device *dev, struct ieee_pfc *pfc)592{593 struct bnxt *bp = netdev_priv(dev);594 __le64 *stats = bp->port_stats.hw_stats;595 struct ieee_pfc *my_pfc = bp->ieee_pfc;596 long rx_off, tx_off;597 int i, rc;598 599 pfc->pfc_cap = bp->max_lltc;600 601 if (!my_pfc) {602 if (bp->dcbx_cap & DCB_CAP_DCBX_HOST)603 return 0;604 605 my_pfc = kzalloc(sizeof(*my_pfc), GFP_KERNEL);606 if (!my_pfc)607 return 0;608 bp->ieee_pfc = my_pfc;609 rc = bnxt_hwrm_queue_pfc_qcfg(bp, my_pfc);610 if (rc)611 return 0;612 }613 614 pfc->pfc_en = my_pfc->pfc_en;615 pfc->mbc = my_pfc->mbc;616 pfc->delay = my_pfc->delay;617 618 if (!stats)619 return 0;620 621 rx_off = BNXT_RX_STATS_OFFSET(rx_pfc_ena_frames_pri0);622 tx_off = BNXT_TX_STATS_OFFSET(tx_pfc_ena_frames_pri0);623 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++, rx_off++, tx_off++) {624 pfc->requests[i] = le64_to_cpu(*(stats + tx_off));625 pfc->indications[i] = le64_to_cpu(*(stats + rx_off));626 }627 628 return 0;629}630 631static int bnxt_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)632{633 struct bnxt *bp = netdev_priv(dev);634 struct ieee_pfc *my_pfc = bp->ieee_pfc;635 int rc;636 637 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||638 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST) ||639 (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))640 return -EINVAL;641 642 if (!my_pfc) {643 my_pfc = kzalloc(sizeof(*my_pfc), GFP_KERNEL);644 if (!my_pfc)645 return -ENOMEM;646 bp->ieee_pfc = my_pfc;647 }648 rc = bnxt_hwrm_queue_pfc_cfg(bp, pfc);649 if (!rc)650 memcpy(my_pfc, pfc, sizeof(*my_pfc));651 652 return rc;653}654 655static int bnxt_dcbnl_ieee_dscp_app_prep(struct bnxt *bp, struct dcb_app *app)656{657 if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP) {658 if (!bp->max_dscp_value)659 return -ENOTSUPP;660 if (app->protocol > bp->max_dscp_value)661 return -EINVAL;662 }663 return 0;664}665 666static int bnxt_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)667{668 struct bnxt *bp = netdev_priv(dev);669 int rc;670 671 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||672 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))673 return -EINVAL;674 675 rc = bnxt_dcbnl_ieee_dscp_app_prep(bp, app);676 if (rc)677 return rc;678 679 rc = dcb_ieee_setapp(dev, app);680 if (rc)681 return rc;682 683 if ((app->selector == IEEE_8021QAZ_APP_SEL_ETHERTYPE &&684 app->protocol == ETH_P_IBOE) ||685 (app->selector == IEEE_8021QAZ_APP_SEL_DGRAM &&686 app->protocol == ROCE_V2_UDP_DPORT))687 rc = bnxt_hwrm_set_dcbx_app(bp, app, true);688 689 if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP)690 rc = bnxt_hwrm_queue_dscp2pri_cfg(bp, app, true);691 692 return rc;693}694 695static int bnxt_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)696{697 struct bnxt *bp = netdev_priv(dev);698 int rc;699 700 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||701 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))702 return -EINVAL;703 704 rc = bnxt_dcbnl_ieee_dscp_app_prep(bp, app);705 if (rc)706 return rc;707 708 rc = dcb_ieee_delapp(dev, app);709 if (rc)710 return rc;711 if ((app->selector == IEEE_8021QAZ_APP_SEL_ETHERTYPE &&712 app->protocol == ETH_P_IBOE) ||713 (app->selector == IEEE_8021QAZ_APP_SEL_DGRAM &&714 app->protocol == ROCE_V2_UDP_DPORT))715 rc = bnxt_hwrm_set_dcbx_app(bp, app, false);716 717 if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP)718 rc = bnxt_hwrm_queue_dscp2pri_cfg(bp, app, false);719 720 return rc;721}722 723static u8 bnxt_dcbnl_getdcbx(struct net_device *dev)724{725 struct bnxt *bp = netdev_priv(dev);726 727 return bp->dcbx_cap;728}729 730static u8 bnxt_dcbnl_setdcbx(struct net_device *dev, u8 mode)731{732 struct bnxt *bp = netdev_priv(dev);733 734 /* All firmware DCBX settings are set in NVRAM */735 if (bp->dcbx_cap & DCB_CAP_DCBX_LLD_MANAGED)736 return 1;737 738 if (mode & DCB_CAP_DCBX_HOST) {739 if (BNXT_VF(bp) || (bp->fw_cap & BNXT_FW_CAP_LLDP_AGENT))740 return 1;741 742 /* only support IEEE */743 if ((mode & DCB_CAP_DCBX_VER_CEE) ||744 !(mode & DCB_CAP_DCBX_VER_IEEE))745 return 1;746 }747 748 if (mode == bp->dcbx_cap)749 return 0;750 751 bp->dcbx_cap = mode;752 return 0;753}754 755static const struct dcbnl_rtnl_ops dcbnl_ops = {756 .ieee_getets = bnxt_dcbnl_ieee_getets,757 .ieee_setets = bnxt_dcbnl_ieee_setets,758 .ieee_getpfc = bnxt_dcbnl_ieee_getpfc,759 .ieee_setpfc = bnxt_dcbnl_ieee_setpfc,760 .ieee_setapp = bnxt_dcbnl_ieee_setapp,761 .ieee_delapp = bnxt_dcbnl_ieee_delapp,762 .getdcbx = bnxt_dcbnl_getdcbx,763 .setdcbx = bnxt_dcbnl_setdcbx,764};765 766void bnxt_dcb_init(struct bnxt *bp)767{768 bp->dcbx_cap = 0;769 if (bp->hwrm_spec_code < 0x10501)770 return;771 772 bnxt_hwrm_queue_dscp_qcaps(bp);773 bp->dcbx_cap = DCB_CAP_DCBX_VER_IEEE;774 if (BNXT_PF(bp) && !(bp->fw_cap & BNXT_FW_CAP_LLDP_AGENT))775 bp->dcbx_cap |= DCB_CAP_DCBX_HOST;776 else if (bp->fw_cap & BNXT_FW_CAP_DCBX_AGENT)777 bp->dcbx_cap |= DCB_CAP_DCBX_LLD_MANAGED;778 bp->dev->dcbnl_ops = &dcbnl_ops;779}780 781void bnxt_dcb_free(struct bnxt *bp)782{783 kfree(bp->ieee_pfc);784 kfree(bp->ieee_ets);785 bp->ieee_pfc = NULL;786 bp->ieee_ets = NULL;787}788 789#else790 791void bnxt_dcb_init(struct bnxt *bp)792{793}794 795void bnxt_dcb_free(struct bnxt *bp)796{797}798 799#endif800