brintos / linux-shallow public Read only

1/* Broadcom NetXtreme-C/E network driver.2 *3 * Copyright (c) 2014-2016 Broadcom Corporation4 * Copyright (c) 2014-2018 Broadcom Limited5 * Copyright (c) 2018-2024 Broadcom Inc.6 *7 * This program is free software; you can redistribute it and/or modify8 * it under the terms of the GNU General Public License as published by9 * the Free Software Foundation.10 *11 * DO NOT MODIFY!!! This file is automatically generated.12 */13 14#ifndef _BNXT_HSI_H_15#define _BNXT_HSI_H_16 17/* hwrm_cmd_hdr (size:128b/16B) */18struct hwrm_cmd_hdr {19	__le16	req_type;20	__le16	cmpl_ring;21	__le16	seq_id;22	__le16	target_id;23	__le64	resp_addr;24};25 26/* hwrm_resp_hdr (size:64b/8B) */27struct hwrm_resp_hdr {28	__le16	error_code;29	__le16	req_type;30	__le16	seq_id;31	__le16	resp_len;32};33 34#define CMD_DISCR_TLV_ENCAP 0x8000UL35#define CMD_DISCR_LAST     CMD_DISCR_TLV_ENCAP36 37 38#define TLV_TYPE_HWRM_REQUEST                    0x1UL39#define TLV_TYPE_HWRM_RESPONSE                   0x2UL40#define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL41#define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL42#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL43#define TLV_TYPE_QUERY_ROCE_CC_GEN2              0x6UL44#define TLV_TYPE_MODIFY_ROCE_CC_GEN2             0x7UL45#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL46#define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL47#define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL48#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           0x8005UL49#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS      0x8006UL50#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY  0x8007UL51#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      0x8008UL52#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY    0x8009UL53#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS        0x800aUL54#define TLV_TYPE_LAST                           TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS55 56 57/* tlv (size:64b/8B) */58struct tlv {59	__le16	cmd_discr;60	u8	reserved_8b;61	u8	flags;62	#define TLV_FLAGS_MORE         0x1UL63	#define TLV_FLAGS_MORE_LAST      0x0UL64	#define TLV_FLAGS_MORE_NOT_LAST  0x1UL65	#define TLV_FLAGS_REQUIRED     0x2UL66	#define TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)67	#define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)68	#define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES69	__le16	tlv_type;70	__le16	length;71};72 73/* input (size:128b/16B) */74struct input {75	__le16	req_type;76	__le16	cmpl_ring;77	__le16	seq_id;78	__le16	target_id;79	__le64	resp_addr;80};81 82/* output (size:64b/8B) */83struct output {84	__le16	error_code;85	__le16	req_type;86	__le16	seq_id;87	__le16	resp_len;88};89 90/* hwrm_short_input (size:128b/16B) */91struct hwrm_short_input {92	__le16	req_type;93	__le16	signature;94	#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL95	#define SHORT_REQ_SIGNATURE_LAST     SHORT_REQ_SIGNATURE_SHORT_CMD96	__le16	target_id;97	#define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL98	#define SHORT_REQ_TARGET_ID_TOOLS   0xfffdUL99	#define SHORT_REQ_TARGET_ID_LAST   SHORT_REQ_TARGET_ID_TOOLS100	__le16	size;101	__le64	req_addr;102};103 104/* cmd_nums (size:64b/8B) */105struct cmd_nums {106	__le16	req_type;107	#define HWRM_VER_GET                              0x0UL108	#define HWRM_FUNC_ECHO_RESPONSE                   0xbUL109	#define HWRM_ERROR_RECOVERY_QCFG                  0xcUL110	#define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL111	#define HWRM_FUNC_BUF_UNRGTR                      0xeUL112	#define HWRM_FUNC_VF_CFG                          0xfUL113	#define HWRM_RESERVED1                            0x10UL114	#define HWRM_FUNC_RESET                           0x11UL115	#define HWRM_FUNC_GETFID                          0x12UL116	#define HWRM_FUNC_VF_ALLOC                        0x13UL117	#define HWRM_FUNC_VF_FREE                         0x14UL118	#define HWRM_FUNC_QCAPS                           0x15UL119	#define HWRM_FUNC_QCFG                            0x16UL120	#define HWRM_FUNC_CFG                             0x17UL121	#define HWRM_FUNC_QSTATS                          0x18UL122	#define HWRM_FUNC_CLR_STATS                       0x19UL123	#define HWRM_FUNC_DRV_UNRGTR                      0x1aUL124	#define HWRM_FUNC_VF_RESC_FREE                    0x1bUL125	#define HWRM_FUNC_VF_VNIC_IDS_QUERY               0x1cUL126	#define HWRM_FUNC_DRV_RGTR                        0x1dUL127	#define HWRM_FUNC_DRV_QVER                        0x1eUL128	#define HWRM_FUNC_BUF_RGTR                        0x1fUL129	#define HWRM_PORT_PHY_CFG                         0x20UL130	#define HWRM_PORT_MAC_CFG                         0x21UL131	#define HWRM_PORT_TS_QUERY                        0x22UL132	#define HWRM_PORT_QSTATS                          0x23UL133	#define HWRM_PORT_LPBK_QSTATS                     0x24UL134	#define HWRM_PORT_CLR_STATS                       0x25UL135	#define HWRM_PORT_LPBK_CLR_STATS                  0x26UL136	#define HWRM_PORT_PHY_QCFG                        0x27UL137	#define HWRM_PORT_MAC_QCFG                        0x28UL138	#define HWRM_PORT_MAC_PTP_QCFG                    0x29UL139	#define HWRM_PORT_PHY_QCAPS                       0x2aUL140	#define HWRM_PORT_PHY_I2C_WRITE                   0x2bUL141	#define HWRM_PORT_PHY_I2C_READ                    0x2cUL142	#define HWRM_PORT_LED_CFG                         0x2dUL143	#define HWRM_PORT_LED_QCFG                        0x2eUL144	#define HWRM_PORT_LED_QCAPS                       0x2fUL145	#define HWRM_QUEUE_QPORTCFG                       0x30UL146	#define HWRM_QUEUE_QCFG                           0x31UL147	#define HWRM_QUEUE_CFG                            0x32UL148	#define HWRM_FUNC_VLAN_CFG                        0x33UL149	#define HWRM_FUNC_VLAN_QCFG                       0x34UL150	#define HWRM_QUEUE_PFCENABLE_QCFG                 0x35UL151	#define HWRM_QUEUE_PFCENABLE_CFG                  0x36UL152	#define HWRM_QUEUE_PRI2COS_QCFG                   0x37UL153	#define HWRM_QUEUE_PRI2COS_CFG                    0x38UL154	#define HWRM_QUEUE_COS2BW_QCFG                    0x39UL155	#define HWRM_QUEUE_COS2BW_CFG                     0x3aUL156	#define HWRM_QUEUE_DSCP_QCAPS                     0x3bUL157	#define HWRM_QUEUE_DSCP2PRI_QCFG                  0x3cUL158	#define HWRM_QUEUE_DSCP2PRI_CFG                   0x3dUL159	#define HWRM_VNIC_ALLOC                           0x40UL160	#define HWRM_VNIC_FREE                            0x41UL161	#define HWRM_VNIC_CFG                             0x42UL162	#define HWRM_VNIC_QCFG                            0x43UL163	#define HWRM_VNIC_TPA_CFG                         0x44UL164	#define HWRM_VNIC_TPA_QCFG                        0x45UL165	#define HWRM_VNIC_RSS_CFG                         0x46UL166	#define HWRM_VNIC_RSS_QCFG                        0x47UL167	#define HWRM_VNIC_PLCMODES_CFG                    0x48UL168	#define HWRM_VNIC_PLCMODES_QCFG                   0x49UL169	#define HWRM_VNIC_QCAPS                           0x4aUL170	#define HWRM_VNIC_UPDATE                          0x4bUL171	#define HWRM_RING_ALLOC                           0x50UL172	#define HWRM_RING_FREE                            0x51UL173	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        0x52UL174	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     0x53UL175	#define HWRM_RING_AGGINT_QCAPS                    0x54UL176	#define HWRM_RING_SCHQ_ALLOC                      0x55UL177	#define HWRM_RING_SCHQ_CFG                        0x56UL178	#define HWRM_RING_SCHQ_FREE                       0x57UL179	#define HWRM_RING_RESET                           0x5eUL180	#define HWRM_RING_GRP_ALLOC                       0x60UL181	#define HWRM_RING_GRP_FREE                        0x61UL182	#define HWRM_RING_CFG                             0x62UL183	#define HWRM_RING_QCFG                            0x63UL184	#define HWRM_RESERVED5                            0x64UL185	#define HWRM_RESERVED6                            0x65UL186	#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            0x70UL187	#define HWRM_VNIC_RSS_COS_LB_CTX_FREE             0x71UL188	#define HWRM_QUEUE_MPLS_QCAPS                     0x80UL189	#define HWRM_QUEUE_MPLSTC2PRI_QCFG                0x81UL190	#define HWRM_QUEUE_MPLSTC2PRI_CFG                 0x82UL191	#define HWRM_QUEUE_VLANPRI_QCAPS                  0x83UL192	#define HWRM_QUEUE_VLANPRI2PRI_QCFG               0x84UL193	#define HWRM_QUEUE_VLANPRI2PRI_CFG                0x85UL194	#define HWRM_QUEUE_GLOBAL_CFG                     0x86UL195	#define HWRM_QUEUE_GLOBAL_QCFG                    0x87UL196	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG      0x88UL197	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG       0x89UL198	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG      0x8aUL199	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG       0x8bUL200	#define HWRM_QUEUE_QCAPS                          0x8cUL201	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG       0x8dUL202	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG        0x8eUL203	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG       0x8fUL204	#define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL205	#define HWRM_CFA_L2_FILTER_FREE                   0x91UL206	#define HWRM_CFA_L2_FILTER_CFG                    0x92UL207	#define HWRM_CFA_L2_SET_RX_MASK                   0x93UL208	#define HWRM_CFA_VLAN_ANTISPOOF_CFG               0x94UL209	#define HWRM_CFA_TUNNEL_FILTER_ALLOC              0x95UL210	#define HWRM_CFA_TUNNEL_FILTER_FREE               0x96UL211	#define HWRM_CFA_ENCAP_RECORD_ALLOC               0x97UL212	#define HWRM_CFA_ENCAP_RECORD_FREE                0x98UL213	#define HWRM_CFA_NTUPLE_FILTER_ALLOC              0x99UL214	#define HWRM_CFA_NTUPLE_FILTER_FREE               0x9aUL215	#define HWRM_CFA_NTUPLE_FILTER_CFG                0x9bUL216	#define HWRM_CFA_EM_FLOW_ALLOC                    0x9cUL217	#define HWRM_CFA_EM_FLOW_FREE                     0x9dUL218	#define HWRM_CFA_EM_FLOW_CFG                      0x9eUL219	#define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL220	#define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL221	#define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL222	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG        0xa3UL223	#define HWRM_STAT_CTX_ENG_QUERY                   0xafUL224	#define HWRM_STAT_CTX_ALLOC                       0xb0UL225	#define HWRM_STAT_CTX_FREE                        0xb1UL226	#define HWRM_STAT_CTX_QUERY                       0xb2UL227	#define HWRM_STAT_CTX_CLR_STATS                   0xb3UL228	#define HWRM_PORT_QSTATS_EXT                      0xb4UL229	#define HWRM_PORT_PHY_MDIO_WRITE                  0xb5UL230	#define HWRM_PORT_PHY_MDIO_READ                   0xb6UL231	#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            0xb7UL232	#define HWRM_PORT_PHY_MDIO_BUS_RELEASE            0xb8UL233	#define HWRM_PORT_QSTATS_EXT_PFC_WD               0xb9UL234	#define HWRM_RESERVED7                            0xbaUL235	#define HWRM_PORT_TX_FIR_CFG                      0xbbUL236	#define HWRM_PORT_TX_FIR_QCFG                     0xbcUL237	#define HWRM_PORT_ECN_QSTATS                      0xbdUL238	#define HWRM_FW_LIVEPATCH_QUERY                   0xbeUL239	#define HWRM_FW_LIVEPATCH                         0xbfUL240	#define HWRM_FW_RESET                             0xc0UL241	#define HWRM_FW_QSTATUS                           0xc1UL242	#define HWRM_FW_HEALTH_CHECK                      0xc2UL243	#define HWRM_FW_SYNC                              0xc3UL244	#define HWRM_FW_STATE_QCAPS                       0xc4UL245	#define HWRM_FW_STATE_QUIESCE                     0xc5UL246	#define HWRM_FW_STATE_BACKUP                      0xc6UL247	#define HWRM_FW_STATE_RESTORE                     0xc7UL248	#define HWRM_FW_SET_TIME                          0xc8UL249	#define HWRM_FW_GET_TIME                          0xc9UL250	#define HWRM_FW_SET_STRUCTURED_DATA               0xcaUL251	#define HWRM_FW_GET_STRUCTURED_DATA               0xcbUL252	#define HWRM_FW_IPC_MAILBOX                       0xccUL253	#define HWRM_FW_ECN_CFG                           0xcdUL254	#define HWRM_FW_ECN_QCFG                          0xceUL255	#define HWRM_FW_SECURE_CFG                        0xcfUL256	#define HWRM_EXEC_FWD_RESP                        0xd0UL257	#define HWRM_REJECT_FWD_RESP                      0xd1UL258	#define HWRM_FWD_RESP                             0xd2UL259	#define HWRM_FWD_ASYNC_EVENT_CMPL                 0xd3UL260	#define HWRM_OEM_CMD                              0xd4UL261	#define HWRM_PORT_PRBS_TEST                       0xd5UL262	#define HWRM_PORT_SFP_SIDEBAND_CFG                0xd6UL263	#define HWRM_PORT_SFP_SIDEBAND_QCFG               0xd7UL264	#define HWRM_FW_STATE_UNQUIESCE                   0xd8UL265	#define HWRM_PORT_DSC_DUMP                        0xd9UL266	#define HWRM_PORT_EP_TX_QCFG                      0xdaUL267	#define HWRM_PORT_EP_TX_CFG                       0xdbUL268	#define HWRM_PORT_CFG                             0xdcUL269	#define HWRM_PORT_QCFG                            0xddUL270	#define HWRM_PORT_MAC_QCAPS                       0xdfUL271	#define HWRM_TEMP_MONITOR_QUERY                   0xe0UL272	#define HWRM_REG_POWER_QUERY                      0xe1UL273	#define HWRM_CORE_FREQUENCY_QUERY                 0xe2UL274	#define HWRM_REG_POWER_HISTOGRAM                  0xe3UL275	#define HWRM_WOL_FILTER_ALLOC                     0xf0UL276	#define HWRM_WOL_FILTER_FREE                      0xf1UL277	#define HWRM_WOL_FILTER_QCFG                      0xf2UL278	#define HWRM_WOL_REASON_QCFG                      0xf3UL279	#define HWRM_CFA_METER_QCAPS                      0xf4UL280	#define HWRM_CFA_METER_PROFILE_ALLOC              0xf5UL281	#define HWRM_CFA_METER_PROFILE_FREE               0xf6UL282	#define HWRM_CFA_METER_PROFILE_CFG                0xf7UL283	#define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL284	#define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL285	#define HWRM_CFA_METER_INSTANCE_CFG               0xfaUL286	#define HWRM_CFA_VFR_ALLOC                        0xfdUL287	#define HWRM_CFA_VFR_FREE                         0xfeUL288	#define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL289	#define HWRM_CFA_VF_PAIR_FREE                     0x101UL290	#define HWRM_CFA_VF_PAIR_INFO                     0x102UL291	#define HWRM_CFA_FLOW_ALLOC                       0x103UL292	#define HWRM_CFA_FLOW_FREE                        0x104UL293	#define HWRM_CFA_FLOW_FLUSH                       0x105UL294	#define HWRM_CFA_FLOW_STATS                       0x106UL295	#define HWRM_CFA_FLOW_INFO                        0x107UL296	#define HWRM_CFA_DECAP_FILTER_ALLOC               0x108UL297	#define HWRM_CFA_DECAP_FILTER_FREE                0x109UL298	#define HWRM_CFA_VLAN_ANTISPOOF_QCFG              0x10aUL299	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC       0x10bUL300	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE        0x10cUL301	#define HWRM_CFA_PAIR_ALLOC                       0x10dUL302	#define HWRM_CFA_PAIR_FREE                        0x10eUL303	#define HWRM_CFA_PAIR_INFO                        0x10fUL304	#define HWRM_FW_IPC_MSG                           0x110UL305	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        0x111UL306	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       0x112UL307	#define HWRM_CFA_FLOW_AGING_TIMER_RESET           0x113UL308	#define HWRM_CFA_FLOW_AGING_CFG                   0x114UL309	#define HWRM_CFA_FLOW_AGING_QCFG                  0x115UL310	#define HWRM_CFA_FLOW_AGING_QCAPS                 0x116UL311	#define HWRM_CFA_CTX_MEM_RGTR                     0x117UL312	#define HWRM_CFA_CTX_MEM_UNRGTR                   0x118UL313	#define HWRM_CFA_CTX_MEM_QCTX                     0x119UL314	#define HWRM_CFA_CTX_MEM_QCAPS                    0x11aUL315	#define HWRM_CFA_COUNTER_QCAPS                    0x11bUL316	#define HWRM_CFA_COUNTER_CFG                      0x11cUL317	#define HWRM_CFA_COUNTER_QCFG                     0x11dUL318	#define HWRM_CFA_COUNTER_QSTATS                   0x11eUL319	#define HWRM_CFA_TCP_FLAG_PROCESS_QCFG            0x11fUL320	#define HWRM_CFA_EEM_QCAPS                        0x120UL321	#define HWRM_CFA_EEM_CFG                          0x121UL322	#define HWRM_CFA_EEM_QCFG                         0x122UL323	#define HWRM_CFA_EEM_OP                           0x123UL324	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS              0x124UL325	#define HWRM_CFA_TFLIB                            0x125UL326	#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR            0x126UL327	#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR          0x127UL328	#define HWRM_CFA_TLS_FILTER_ALLOC                 0x128UL329	#define HWRM_CFA_TLS_FILTER_FREE                  0x129UL330	#define HWRM_CFA_RELEASE_AFM_FUNC                 0x12aUL331	#define HWRM_ENGINE_CKV_STATUS                    0x12eUL332	#define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL333	#define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL334	#define HWRM_ENGINE_CKV_KEY_ADD                   0x131UL335	#define HWRM_ENGINE_CKV_KEY_DELETE                0x132UL336	#define HWRM_ENGINE_CKV_FLUSH                     0x133UL337	#define HWRM_ENGINE_CKV_RNG_GET                   0x134UL338	#define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL339	#define HWRM_ENGINE_CKV_KEY_LABEL_CFG             0x136UL340	#define HWRM_ENGINE_CKV_KEY_LABEL_QCFG            0x137UL341	#define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL342	#define HWRM_ENGINE_QG_QUERY                      0x13dUL343	#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL344	#define HWRM_ENGINE_QG_METER_PROFILE_QUERY        0x13fUL345	#define HWRM_ENGINE_QG_METER_PROFILE_ALLOC        0x140UL346	#define HWRM_ENGINE_QG_METER_PROFILE_FREE         0x141UL347	#define HWRM_ENGINE_QG_METER_QUERY                0x142UL348	#define HWRM_ENGINE_QG_METER_BIND                 0x143UL349	#define HWRM_ENGINE_QG_METER_UNBIND               0x144UL350	#define HWRM_ENGINE_QG_FUNC_BIND                  0x145UL351	#define HWRM_ENGINE_SG_CONFIG_QUERY               0x146UL352	#define HWRM_ENGINE_SG_QUERY                      0x147UL353	#define HWRM_ENGINE_SG_METER_QUERY                0x148UL354	#define HWRM_ENGINE_SG_METER_CONFIG               0x149UL355	#define HWRM_ENGINE_SG_QG_BIND                    0x14aUL356	#define HWRM_ENGINE_QG_SG_UNBIND                  0x14bUL357	#define HWRM_ENGINE_CONFIG_QUERY                  0x154UL358	#define HWRM_ENGINE_STATS_CONFIG                  0x155UL359	#define HWRM_ENGINE_STATS_CLEAR                   0x156UL360	#define HWRM_ENGINE_STATS_QUERY                   0x157UL361	#define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR  0x158UL362	#define HWRM_ENGINE_RQ_ALLOC                      0x15eUL363	#define HWRM_ENGINE_RQ_FREE                       0x15fUL364	#define HWRM_ENGINE_CQ_ALLOC                      0x160UL365	#define HWRM_ENGINE_CQ_FREE                       0x161UL366	#define HWRM_ENGINE_NQ_ALLOC                      0x162UL367	#define HWRM_ENGINE_NQ_FREE                       0x163UL368	#define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL369	#define HWRM_ENGINE_FUNC_QCFG                     0x165UL370	#define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL371	#define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL372	#define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL373	#define HWRM_FUNC_BACKING_STORE_CFG               0x193UL374	#define HWRM_FUNC_BACKING_STORE_QCFG              0x194UL375	#define HWRM_FUNC_VF_BW_CFG                       0x195UL376	#define HWRM_FUNC_VF_BW_QCFG                      0x196UL377	#define HWRM_FUNC_HOST_PF_IDS_QUERY               0x197UL378	#define HWRM_FUNC_QSTATS_EXT                      0x198UL379	#define HWRM_STAT_EXT_CTX_QUERY                   0x199UL380	#define HWRM_FUNC_SPD_CFG                         0x19aUL381	#define HWRM_FUNC_SPD_QCFG                        0x19bUL382	#define HWRM_FUNC_PTP_PIN_QCFG                    0x19cUL383	#define HWRM_FUNC_PTP_PIN_CFG                     0x19dUL384	#define HWRM_FUNC_PTP_CFG                         0x19eUL385	#define HWRM_FUNC_PTP_TS_QUERY                    0x19fUL386	#define HWRM_FUNC_PTP_EXT_CFG                     0x1a0UL387	#define HWRM_FUNC_PTP_EXT_QCFG                    0x1a1UL388	#define HWRM_FUNC_KEY_CTX_ALLOC                   0x1a2UL389	#define HWRM_FUNC_BACKING_STORE_CFG_V2            0x1a3UL390	#define HWRM_FUNC_BACKING_STORE_QCFG_V2           0x1a4UL391	#define HWRM_FUNC_DBR_PACING_CFG                  0x1a5UL392	#define HWRM_FUNC_DBR_PACING_QCFG                 0x1a6UL393	#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT      0x1a7UL394	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2          0x1a8UL395	#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY         0x1a9UL396	#define HWRM_FUNC_DBR_RECOVERY_COMPLETED          0x1aaUL397	#define HWRM_FUNC_SYNCE_CFG                       0x1abUL398	#define HWRM_FUNC_SYNCE_QCFG                      0x1acUL399	#define HWRM_FUNC_KEY_CTX_FREE                    0x1adUL400	#define HWRM_FUNC_LAG_MODE_CFG                    0x1aeUL401	#define HWRM_FUNC_LAG_MODE_QCFG                   0x1afUL402	#define HWRM_FUNC_LAG_CREATE                      0x1b0UL403	#define HWRM_FUNC_LAG_UPDATE                      0x1b1UL404	#define HWRM_FUNC_LAG_FREE                        0x1b2UL405	#define HWRM_FUNC_LAG_QCFG                        0x1b3UL406	#define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD         0x1c2UL407	#define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE      0x1c3UL408	#define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY       0x1c4UL409	#define HWRM_SELFTEST_QLIST                       0x200UL410	#define HWRM_SELFTEST_EXEC                        0x201UL411	#define HWRM_SELFTEST_IRQ                         0x202UL412	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA        0x203UL413	#define HWRM_PCIE_QSTATS                          0x204UL414	#define HWRM_MFG_FRU_WRITE_CONTROL                0x205UL415	#define HWRM_MFG_TIMERS_QUERY                     0x206UL416	#define HWRM_MFG_OTP_CFG                          0x207UL417	#define HWRM_MFG_OTP_QCFG                         0x208UL418	#define HWRM_MFG_HDMA_TEST                        0x209UL419	#define HWRM_MFG_FRU_EEPROM_WRITE                 0x20aUL420	#define HWRM_MFG_FRU_EEPROM_READ                  0x20bUL421	#define HWRM_MFG_SOC_IMAGE                        0x20cUL422	#define HWRM_MFG_SOC_QSTATUS                      0x20dUL423	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE     0x20eUL424	#define HWRM_MFG_PARAM_CRITICAL_DATA_READ         0x20fUL425	#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH       0x210UL426	#define HWRM_MFG_PRVSN_EXPORT_CSR                 0x211UL427	#define HWRM_MFG_PRVSN_IMPORT_CERT                0x212UL428	#define HWRM_MFG_PRVSN_GET_STATE                  0x213UL429	#define HWRM_MFG_GET_NVM_MEASUREMENT              0x214UL430	#define HWRM_MFG_PSOC_QSTATUS                     0x215UL431	#define HWRM_MFG_SELFTEST_QLIST                   0x216UL432	#define HWRM_MFG_SELFTEST_EXEC                    0x217UL433	#define HWRM_STAT_GENERIC_QSTATS                  0x218UL434	#define HWRM_MFG_PRVSN_EXPORT_CERT                0x219UL435	#define HWRM_STAT_DB_ERROR_QSTATS                 0x21aUL436	#define HWRM_MFG_TESTS                            0x21bUL437	#define HWRM_PORT_POE_CFG                         0x230UL438	#define HWRM_PORT_POE_QCFG                        0x231UL439	#define HWRM_UDCC_QCAPS                           0x258UL440	#define HWRM_UDCC_CFG                             0x259UL441	#define HWRM_UDCC_QCFG                            0x25aUL442	#define HWRM_UDCC_SESSION_CFG                     0x25bUL443	#define HWRM_UDCC_SESSION_QCFG                    0x25cUL444	#define HWRM_UDCC_SESSION_QUERY                   0x25dUL445	#define HWRM_UDCC_COMP_CFG                        0x25eUL446	#define HWRM_UDCC_COMP_QCFG                       0x25fUL447	#define HWRM_UDCC_COMP_QUERY                      0x260UL448	#define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS            0x261UL449	#define HWRM_QUEUE_PFCWD_TIMEOUT_CFG              0x262UL450	#define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG             0x263UL451	#define HWRM_TF                                   0x2bcUL452	#define HWRM_TF_VERSION_GET                       0x2bdUL453	#define HWRM_TF_SESSION_OPEN                      0x2c6UL454	#define HWRM_TF_SESSION_REGISTER                  0x2c8UL455	#define HWRM_TF_SESSION_UNREGISTER                0x2c9UL456	#define HWRM_TF_SESSION_CLOSE                     0x2caUL457	#define HWRM_TF_SESSION_QCFG                      0x2cbUL458	#define HWRM_TF_SESSION_RESC_QCAPS                0x2ccUL459	#define HWRM_TF_SESSION_RESC_ALLOC                0x2cdUL460	#define HWRM_TF_SESSION_RESC_FREE                 0x2ceUL461	#define HWRM_TF_SESSION_RESC_FLUSH                0x2cfUL462	#define HWRM_TF_SESSION_RESC_INFO                 0x2d0UL463	#define HWRM_TF_SESSION_HOTUP_STATE_SET           0x2d1UL464	#define HWRM_TF_SESSION_HOTUP_STATE_GET           0x2d2UL465	#define HWRM_TF_TBL_TYPE_GET                      0x2daUL466	#define HWRM_TF_TBL_TYPE_SET                      0x2dbUL467	#define HWRM_TF_TBL_TYPE_BULK_GET                 0x2dcUL468	#define HWRM_TF_EM_INSERT                         0x2eaUL469	#define HWRM_TF_EM_DELETE                         0x2ebUL470	#define HWRM_TF_EM_HASH_INSERT                    0x2ecUL471	#define HWRM_TF_EM_MOVE                           0x2edUL472	#define HWRM_TF_TCAM_SET                          0x2f8UL473	#define HWRM_TF_TCAM_GET                          0x2f9UL474	#define HWRM_TF_TCAM_MOVE                         0x2faUL475	#define HWRM_TF_TCAM_FREE                         0x2fbUL476	#define HWRM_TF_GLOBAL_CFG_SET                    0x2fcUL477	#define HWRM_TF_GLOBAL_CFG_GET                    0x2fdUL478	#define HWRM_TF_IF_TBL_SET                        0x2feUL479	#define HWRM_TF_IF_TBL_GET                        0x2ffUL480	#define HWRM_TF_RESC_USAGE_SET                    0x300UL481	#define HWRM_TF_RESC_USAGE_QUERY                  0x301UL482	#define HWRM_TF_TBL_TYPE_ALLOC                    0x302UL483	#define HWRM_TF_TBL_TYPE_FREE                     0x303UL484	#define HWRM_TFC_TBL_SCOPE_QCAPS                  0x380UL485	#define HWRM_TFC_TBL_SCOPE_ID_ALLOC               0x381UL486	#define HWRM_TFC_TBL_SCOPE_CONFIG                 0x382UL487	#define HWRM_TFC_TBL_SCOPE_DECONFIG               0x383UL488	#define HWRM_TFC_TBL_SCOPE_FID_ADD                0x384UL489	#define HWRM_TFC_TBL_SCOPE_FID_REM                0x385UL490	#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC             0x386UL491	#define HWRM_TFC_TBL_SCOPE_POOL_FREE              0x387UL492	#define HWRM_TFC_SESSION_ID_ALLOC                 0x388UL493	#define HWRM_TFC_SESSION_FID_ADD                  0x389UL494	#define HWRM_TFC_SESSION_FID_REM                  0x38aUL495	#define HWRM_TFC_IDENT_ALLOC                      0x38bUL496	#define HWRM_TFC_IDENT_FREE                       0x38cUL497	#define HWRM_TFC_IDX_TBL_ALLOC                    0x38dUL498	#define HWRM_TFC_IDX_TBL_ALLOC_SET                0x38eUL499	#define HWRM_TFC_IDX_TBL_SET                      0x38fUL500	#define HWRM_TFC_IDX_TBL_GET                      0x390UL501	#define HWRM_TFC_IDX_TBL_FREE                     0x391UL502	#define HWRM_TFC_GLOBAL_ID_ALLOC                  0x392UL503	#define HWRM_TFC_TCAM_SET                         0x393UL504	#define HWRM_TFC_TCAM_GET                         0x394UL505	#define HWRM_TFC_TCAM_ALLOC                       0x395UL506	#define HWRM_TFC_TCAM_ALLOC_SET                   0x396UL507	#define HWRM_TFC_TCAM_FREE                        0x397UL508	#define HWRM_TFC_IF_TBL_SET                       0x398UL509	#define HWRM_TFC_IF_TBL_GET                       0x399UL510	#define HWRM_TFC_TBL_SCOPE_CONFIG_GET             0x39aUL511	#define HWRM_TFC_RESC_USAGE_QUERY                 0x39bUL512	#define HWRM_SV                                   0x400UL513	#define HWRM_DBG_SERDES_TEST                      0xff0eUL514	#define HWRM_DBG_LOG_BUFFER_FLUSH                 0xff0fUL515	#define HWRM_DBG_READ_DIRECT                      0xff10UL516	#define HWRM_DBG_READ_INDIRECT                    0xff11UL517	#define HWRM_DBG_WRITE_DIRECT                     0xff12UL518	#define HWRM_DBG_WRITE_INDIRECT                   0xff13UL519	#define HWRM_DBG_DUMP                             0xff14UL520	#define HWRM_DBG_ERASE_NVM                        0xff15UL521	#define HWRM_DBG_CFG                              0xff16UL522	#define HWRM_DBG_COREDUMP_LIST                    0xff17UL523	#define HWRM_DBG_COREDUMP_INITIATE                0xff18UL524	#define HWRM_DBG_COREDUMP_RETRIEVE                0xff19UL525	#define HWRM_DBG_FW_CLI                           0xff1aUL526	#define HWRM_DBG_I2C_CMD                          0xff1bUL527	#define HWRM_DBG_RING_INFO_GET                    0xff1cUL528	#define HWRM_DBG_CRASHDUMP_HEADER                 0xff1dUL529	#define HWRM_DBG_CRASHDUMP_ERASE                  0xff1eUL530	#define HWRM_DBG_DRV_TRACE                        0xff1fUL531	#define HWRM_DBG_QCAPS                            0xff20UL532	#define HWRM_DBG_QCFG                             0xff21UL533	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG             0xff22UL534	#define HWRM_DBG_USEQ_ALLOC                       0xff23UL535	#define HWRM_DBG_USEQ_FREE                        0xff24UL536	#define HWRM_DBG_USEQ_FLUSH                       0xff25UL537	#define HWRM_DBG_USEQ_QCAPS                       0xff26UL538	#define HWRM_DBG_USEQ_CW_CFG                      0xff27UL539	#define HWRM_DBG_USEQ_SCHED_CFG                   0xff28UL540	#define HWRM_DBG_USEQ_RUN                         0xff29UL541	#define HWRM_DBG_USEQ_DELIVERY_REQ                0xff2aUL542	#define HWRM_DBG_USEQ_RESP_HDR                    0xff2bUL543	#define HWRM_DBG_COREDUMP_CAPTURE                 0xff2cUL544	#define HWRM_DBG_PTRACE                           0xff2dUL545	#define HWRM_DBG_SIM_CABLE_STATE                  0xff2eUL546	#define HWRM_NVM_GET_VPD_FIELD_INFO               0xffeaUL547	#define HWRM_NVM_SET_VPD_FIELD_INFO               0xffebUL548	#define HWRM_NVM_DEFRAG                           0xffecUL549	#define HWRM_NVM_REQ_ARBITRATION                  0xffedUL550	#define HWRM_NVM_FACTORY_DEFAULTS                 0xffeeUL551	#define HWRM_NVM_VALIDATE_OPTION                  0xffefUL552	#define HWRM_NVM_FLUSH                            0xfff0UL553	#define HWRM_NVM_GET_VARIABLE                     0xfff1UL554	#define HWRM_NVM_SET_VARIABLE                     0xfff2UL555	#define HWRM_NVM_INSTALL_UPDATE                   0xfff3UL556	#define HWRM_NVM_MODIFY                           0xfff4UL557	#define HWRM_NVM_VERIFY_UPDATE                    0xfff5UL558	#define HWRM_NVM_GET_DEV_INFO                     0xfff6UL559	#define HWRM_NVM_ERASE_DIR_ENTRY                  0xfff7UL560	#define HWRM_NVM_MOD_DIR_ENTRY                    0xfff8UL561	#define HWRM_NVM_FIND_DIR_ENTRY                   0xfff9UL562	#define HWRM_NVM_GET_DIR_ENTRIES                  0xfffaUL563	#define HWRM_NVM_GET_DIR_INFO                     0xfffbUL564	#define HWRM_NVM_RAW_DUMP                         0xfffcUL565	#define HWRM_NVM_READ                             0xfffdUL566	#define HWRM_NVM_WRITE                            0xfffeUL567	#define HWRM_NVM_RAW_WRITE_BLK                    0xffffUL568	#define HWRM_LAST                                HWRM_NVM_RAW_WRITE_BLK569	__le16	unused_0[3];570};571 572/* ret_codes (size:64b/8B) */573struct ret_codes {574	__le16	error_code;575	#define HWRM_ERR_CODE_SUCCESS                      0x0UL576	#define HWRM_ERR_CODE_FAIL                         0x1UL577	#define HWRM_ERR_CODE_INVALID_PARAMS               0x2UL578	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED       0x3UL579	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR         0x4UL580	#define HWRM_ERR_CODE_INVALID_FLAGS                0x5UL581	#define HWRM_ERR_CODE_INVALID_ENABLES              0x6UL582	#define HWRM_ERR_CODE_UNSUPPORTED_TLV              0x7UL583	#define HWRM_ERR_CODE_NO_BUFFER                    0x8UL584	#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR       0x9UL585	#define HWRM_ERR_CODE_HOT_RESET_PROGRESS           0xaUL586	#define HWRM_ERR_CODE_HOT_RESET_FAIL               0xbUL587	#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL588	#define HWRM_ERR_CODE_KEY_HASH_COLLISION           0xdUL589	#define HWRM_ERR_CODE_KEY_ALREADY_EXISTS           0xeUL590	#define HWRM_ERR_CODE_HWRM_ERROR                   0xfUL591	#define HWRM_ERR_CODE_BUSY                         0x10UL592	#define HWRM_ERR_CODE_RESOURCE_LOCKED              0x11UL593	#define HWRM_ERR_CODE_PF_UNAVAILABLE               0x12UL594	#define HWRM_ERR_CODE_ENTITY_NOT_PRESENT           0x13UL595	#define HWRM_ERR_CODE_SECURE_SOC_ERROR             0x14UL596	#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE    0x8000UL597	#define HWRM_ERR_CODE_UNKNOWN_ERR                  0xfffeUL598	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED            0xffffUL599	#define HWRM_ERR_CODE_LAST                        HWRM_ERR_CODE_CMD_NOT_SUPPORTED600	__le16	unused_0[3];601};602 603/* hwrm_err_output (size:128b/16B) */604struct hwrm_err_output {605	__le16	error_code;606	__le16	req_type;607	__le16	seq_id;608	__le16	resp_len;609	__le32	opaque_0;610	__le16	opaque_1;611	u8	cmd_err;612	u8	valid;613};614#define HWRM_NA_SIGNATURE ((__le32)(-1))615#define HWRM_MAX_REQ_LEN 128616#define HWRM_MAX_RESP_LEN 704617#define HW_HASH_INDEX_SIZE 0x80618#define HW_HASH_KEY_SIZE 40619#define HWRM_RESP_VALID_KEY 1620#define HWRM_TARGET_ID_BONO 0xFFF8621#define HWRM_TARGET_ID_KONG 0xFFF9622#define HWRM_TARGET_ID_APE 0xFFFA623#define HWRM_TARGET_ID_TOOLS 0xFFFD624#define HWRM_VERSION_MAJOR 1625#define HWRM_VERSION_MINOR 10626#define HWRM_VERSION_UPDATE 3627#define HWRM_VERSION_RSVD 68628#define HWRM_VERSION_STR "1.10.3.68"629 630/* hwrm_ver_get_input (size:192b/24B) */631struct hwrm_ver_get_input {632	__le16	req_type;633	__le16	cmpl_ring;634	__le16	seq_id;635	__le16	target_id;636	__le64	resp_addr;637	u8	hwrm_intf_maj;638	u8	hwrm_intf_min;639	u8	hwrm_intf_upd;640	u8	unused_0[5];641};642 643/* hwrm_ver_get_output (size:1408b/176B) */644struct hwrm_ver_get_output {645	__le16	error_code;646	__le16	req_type;647	__le16	seq_id;648	__le16	resp_len;649	u8	hwrm_intf_maj_8b;650	u8	hwrm_intf_min_8b;651	u8	hwrm_intf_upd_8b;652	u8	hwrm_intf_rsvd_8b;653	u8	hwrm_fw_maj_8b;654	u8	hwrm_fw_min_8b;655	u8	hwrm_fw_bld_8b;656	u8	hwrm_fw_rsvd_8b;657	u8	mgmt_fw_maj_8b;658	u8	mgmt_fw_min_8b;659	u8	mgmt_fw_bld_8b;660	u8	mgmt_fw_rsvd_8b;661	u8	netctrl_fw_maj_8b;662	u8	netctrl_fw_min_8b;663	u8	netctrl_fw_bld_8b;664	u8	netctrl_fw_rsvd_8b;665	__le32	dev_caps_cfg;666	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED                  0x1UL667	#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED                  0x2UL668	#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED                      0x4UL669	#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED                       0x8UL670	#define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED                   0x10UL671	#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED              0x20UL672	#define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED     0x40UL673	#define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED         0x80UL674	#define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED                     0x100UL675	#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED                     0x200UL676	#define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED              0x400UL677	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED                        0x800UL678	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED              0x1000UL679	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED                      0x2000UL680	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED                    0x4000UL681	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE                      0x8000UL682	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE                       0x10000UL683	u8	roce_fw_maj_8b;684	u8	roce_fw_min_8b;685	u8	roce_fw_bld_8b;686	u8	roce_fw_rsvd_8b;687	char	hwrm_fw_name[16];688	char	mgmt_fw_name[16];689	char	netctrl_fw_name[16];690	char	active_pkg_name[16];691	char	roce_fw_name[16];692	__le16	chip_num;693	u8	chip_rev;694	u8	chip_metal;695	u8	chip_bond_id;696	u8	chip_platform_type;697	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC      0x0UL698	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA      0x1UL699	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL700	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST     VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM701	__le16	max_req_win_len;702	__le16	max_resp_len;703	__le16	def_req_timeout;704	u8	flags;705	#define VER_GET_RESP_FLAGS_DEV_NOT_RDY                   0x1UL706	#define VER_GET_RESP_FLAGS_EXT_VER_AVAIL                 0x2UL707	#define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE     0x4UL708	u8	unused_0[2];709	u8	always_1;710	__le16	hwrm_intf_major;711	__le16	hwrm_intf_minor;712	__le16	hwrm_intf_build;713	__le16	hwrm_intf_patch;714	__le16	hwrm_fw_major;715	__le16	hwrm_fw_minor;716	__le16	hwrm_fw_build;717	__le16	hwrm_fw_patch;718	__le16	mgmt_fw_major;719	__le16	mgmt_fw_minor;720	__le16	mgmt_fw_build;721	__le16	mgmt_fw_patch;722	__le16	netctrl_fw_major;723	__le16	netctrl_fw_minor;724	__le16	netctrl_fw_build;725	__le16	netctrl_fw_patch;726	__le16	roce_fw_major;727	__le16	roce_fw_minor;728	__le16	roce_fw_build;729	__le16	roce_fw_patch;730	__le16	max_ext_req_len;731	__le16	max_req_timeout;732	u8	unused_1[3];733	u8	valid;734};735 736/* eject_cmpl (size:128b/16B) */737struct eject_cmpl {738	__le16	type;739	#define EJECT_CMPL_TYPE_MASK       0x3fUL740	#define EJECT_CMPL_TYPE_SFT        0741	#define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL742	#define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT743	#define EJECT_CMPL_FLAGS_MASK      0xffc0UL744	#define EJECT_CMPL_FLAGS_SFT       6745	#define EJECT_CMPL_FLAGS_ERROR      0x40UL746	__le16	len;747	__le32	opaque;748	__le16	v;749	#define EJECT_CMPL_V                              0x1UL750	#define EJECT_CMPL_ERRORS_MASK                    0xfffeUL751	#define EJECT_CMPL_ERRORS_SFT                     1752	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        0xeUL753	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1754	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER     (0x0UL << 1)755	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)756	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT    (0x3UL << 1)757	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH         (0x5UL << 1)758	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST         EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH759	__le16	reserved16;760	__le32	unused_2;761};762 763/* hwrm_cmpl (size:128b/16B) */764struct hwrm_cmpl {765	__le16	type;766	#define CMPL_TYPE_MASK     0x3fUL767	#define CMPL_TYPE_SFT      0768	#define CMPL_TYPE_HWRM_DONE  0x20UL769	#define CMPL_TYPE_LAST      CMPL_TYPE_HWRM_DONE770	__le16	sequence_id;771	__le32	unused_1;772	__le32	v;773	#define CMPL_V     0x1UL774	__le32	unused_3;775};776 777/* hwrm_fwd_req_cmpl (size:128b/16B) */778struct hwrm_fwd_req_cmpl {779	__le16	req_len_type;780	#define FWD_REQ_CMPL_TYPE_MASK        0x3fUL781	#define FWD_REQ_CMPL_TYPE_SFT         0782	#define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  0x22UL783	#define FWD_REQ_CMPL_TYPE_LAST         FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ784	#define FWD_REQ_CMPL_REQ_LEN_MASK     0xffc0UL785	#define FWD_REQ_CMPL_REQ_LEN_SFT      6786	__le16	source_id;787	__le32	unused0;788	__le32	req_buf_addr_v[2];789	#define FWD_REQ_CMPL_V                0x1UL790	#define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL791	#define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1792};793 794/* hwrm_fwd_resp_cmpl (size:128b/16B) */795struct hwrm_fwd_resp_cmpl {796	__le16	type;797	#define FWD_RESP_CMPL_TYPE_MASK         0x3fUL798	#define FWD_RESP_CMPL_TYPE_SFT          0799	#define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  0x24UL800	#define FWD_RESP_CMPL_TYPE_LAST          FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP801	__le16	source_id;802	__le16	resp_len;803	__le16	unused_1;804	__le32	resp_buf_addr_v[2];805	#define FWD_RESP_CMPL_V                 0x1UL806	#define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL807	#define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1808};809 810/* hwrm_async_event_cmpl (size:128b/16B) */811struct hwrm_async_event_cmpl {812	__le16	type;813	#define ASYNC_EVENT_CMPL_TYPE_MASK            0x3fUL814	#define ASYNC_EVENT_CMPL_TYPE_SFT             0815	#define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  0x2eUL816	#define ASYNC_EVENT_CMPL_TYPE_LAST             ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT817	__le16	event_id;818	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE              0x0UL819	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE                 0x1UL820	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE               0x2UL821	#define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE               0x3UL822	#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED           0x4UL823	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED      0x5UL824	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE           0x6UL825	#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE             0x7UL826	#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY                    0x8UL827	#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY                  0x9UL828	#define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG                0xaUL829	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD                0x10UL830	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD                  0x11UL831	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT             0x12UL832	#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD                  0x20UL833	#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD                    0x21UL834	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR                          0x30UL835	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE              0x31UL836	#define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE        0x32UL837	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE                   0x33UL838	#define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE                 0x34UL839	#define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE             0x35UL840	#define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED                    0x36UL841	#define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION              0x37UL842	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ             0x38UL843	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE            0x39UL844	#define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE          0x3aUL845	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE                 0x3bUL846	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE                  0x3cUL847	#define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE       0x3dUL848	#define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE        0x3eUL849	#define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE                    0x3fUL850	#define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE               0x40UL851	#define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE         0x41UL852	#define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST                    0x42UL853	#define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE                      0x43UL854	#define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP                   0x44UL855	#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT                    0x45UL856	#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD       0x46UL857	#define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE                      0x47UL858	#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE       0x48UL859	#define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL860	#define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR                       0x4aUL861	#define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE             0x4bUL862	#define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER                0x4cUL863	#define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE                0x4dUL864	#define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE         0x4eUL865	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE                  0x4fUL866	#define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP                   0x50UL867	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID               0x51UL868	#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG                    0xfeUL869	#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                      0xffUL870	#define ASYNC_EVENT_CMPL_EVENT_ID_LAST                           ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR871	__le32	event_data2;872	u8	opaque_v;873	#define ASYNC_EVENT_CMPL_V          0x1UL874	#define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL875	#define ASYNC_EVENT_CMPL_OPAQUE_SFT 1876	u8	timestamp_lo;877	__le16	timestamp_hi;878	__le32	event_data1;879};880 881/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */882struct hwrm_async_event_cmpl_link_status_change {883	__le16	type;884	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK            0x3fUL885	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT             0886	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL887	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT888	__le16	event_id;889	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL890	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE891	__le32	event_data2;892	u8	opaque_v;893	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V          0x1UL894	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL895	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1896	u8	timestamp_lo;897	__le16	timestamp_hi;898	__le32	event_data1;899	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE     0x1UL900	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  0x0UL901	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP    0x1UL902	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP903	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK       0xeUL904	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT        1905	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK    0xffff0UL906	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT     4907	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK      0xff00000UL908	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT       20909};910 911/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */912struct hwrm_async_event_cmpl_port_conn_not_allowed {913	__le16	type;914	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK            0x3fUL915	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT             0916	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL917	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT918	__le16	event_id;919	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL920	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED921	__le32	event_data2;922	u8	opaque_v;923	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V          0x1UL924	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL925	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1926	u8	timestamp_lo;927	__le16	timestamp_hi;928	__le32	event_data1;929	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK                 0xffffUL930	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT                  0931	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK      0xff0000UL932	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT       16933	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE        (0x0UL << 16)934	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)935	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (0x2UL << 16)936	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN     (0x3UL << 16)937	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST       ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN938};939 940/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */941struct hwrm_async_event_cmpl_link_speed_cfg_change {942	__le16	type;943	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK            0x3fUL944	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT             0945	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL946	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT947	__le16	event_id;948	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL949	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE950	__le32	event_data2;951	u8	opaque_v;952	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V          0x1UL953	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL954	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1955	u8	timestamp_lo;956	__le16	timestamp_hi;957	__le32	event_data1;958	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK                     0xffffUL959	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT                      0960	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE     0x10000UL961	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG           0x20000UL962};963 964/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */965struct hwrm_async_event_cmpl_reset_notify {966	__le16	type;967	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK            0x3fUL968	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT             0969	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  0x2eUL970	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST             ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT971	__le16	event_id;972	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL973	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST        ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY974	__le32	event_data2;975	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL976	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0977	u8	opaque_v;978	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_V          0x1UL979	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL980	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1981	u8	timestamp_lo;982	__le16	timestamp_hi;983	__le32	event_data1;984	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK                  0xffUL985	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT                   0986	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE    0x1UL987	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN           0x2UL988	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST                   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN989	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK                    0xff00UL990	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT                     8991	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (0x1UL << 8)992	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL        (0x2UL << 8)993	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL    (0x3UL << 8)994	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET                (0x4UL << 8)995	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION             (0x5UL << 8)996	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST                     ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION997	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK           0xffff0000UL998	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16999};1000 1001/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */1002struct hwrm_async_event_cmpl_error_recovery {1003	__le16	type;1004	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK            0x3fUL1005	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT             01006	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT  0x2eUL1007	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT1008	__le16	event_id;1009	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL1010	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST          ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY1011	__le32	event_data2;1012	u8	opaque_v;1013	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V          0x1UL1014	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL1015	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 11016	u8	timestamp_lo;1017	__le16	timestamp_hi;1018	__le32	event_data1;1019	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK                 0xffUL1020	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT                  01021	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC           0x1UL1022	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED      0x2UL1023};1024 1025/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */1026struct hwrm_async_event_cmpl_ring_monitor_msg {1027	__le16	type;1028	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK            0x3fUL1029	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT             01030	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT  0x2eUL1031	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST             ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT1032	__le16	event_id;1033	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL1034	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST            ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG1035	__le32	event_data2;1036	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL1037	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 01038	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX    0x0UL1039	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX    0x1UL1040	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL  0x2UL1041	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL1042	u8	opaque_v;1043	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V          0x1UL1044	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL1045	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 11046	u8	timestamp_lo;1047	__le16	timestamp_hi;1048	__le32	event_data1;1049};1050 1051/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */1052struct hwrm_async_event_cmpl_vf_cfg_change {1053	__le16	type;1054	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK            0x3fUL1055	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT             01056	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL1057	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT1058	__le16	event_id;1059	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL1060	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST         ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE1061	__le32	event_data2;1062	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL1063	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 01064	u8	opaque_v;1065	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          0x1UL1066	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL1067	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 11068	u8	timestamp_lo;1069	__le16	timestamp_hi;1070	__le32	event_data1;1071	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE                0x1UL1072	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE                0x2UL1073	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE      0x4UL1074	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE          0x8UL1075	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE     0x10UL1076	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE      0x20UL1077};1078 1079/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */1080struct hwrm_async_event_cmpl_default_vnic_change {1081	__le16	type;1082	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK            0x3fUL1083	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT             01084	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL1085	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT1086	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK         0xffc0UL1087	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT          61088	__le16	event_id;1089	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL1090	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST                   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION1091	__le32	event_data2;1092	u8	opaque_v;1093	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V          0x1UL1094	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL1095	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 11096	u8	timestamp_lo;1097	__le16	timestamp_hi;1098	__le32	event_data1;1099	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK          0x3UL1100	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT           01101	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  0x1UL1102	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL1103	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST           ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE1104	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK                   0x3fcUL1105	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT                    21106	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK                   0x3fffc00UL1107	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT                    101108};1109 1110/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */1111struct hwrm_async_event_cmpl_hw_flow_aged {1112	__le16	type;1113	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK            0x3fUL1114	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             01115	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  0x2eUL1116	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST             ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT1117	__le16	event_id;1118	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL1119	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED1120	__le32	event_data2;1121	u8	opaque_v;1122	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          0x1UL1123	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL1124	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 11125	u8	timestamp_lo;1126	__le16	timestamp_hi;1127	__le32	event_data1;1128	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK       0x7fffffffUL1129	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT        01130	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION     0x80000000UL1131	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX    (0x0UL << 31)1132	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX    (0x1UL << 31)1133	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX1134};1135 1136/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */1137struct hwrm_async_event_cmpl_eem_cache_flush_req {1138	__le16	type;1139	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK            0x3fUL1140	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT             01141	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT  0x2eUL1142	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT1143	__le16	event_id;1144	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL1145	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST               ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ1146	__le32	event_data2;1147	u8	opaque_v;1148	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V          0x1UL1149	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL1150	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 11151	u8	timestamp_lo;1152	__le16	timestamp_hi;1153	__le32	event_data1;1154};1155 1156/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */1157struct hwrm_async_event_cmpl_eem_cache_flush_done {1158	__le16	type;1159	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK            0x3fUL1160	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT             01161	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT  0x2eUL1162	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT1163	__le16	event_id;1164	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL1165	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST                ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE1166	__le32	event_data2;1167	u8	opaque_v;1168	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V          0x1UL1169	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL1170	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 11171	u8	timestamp_lo;1172	__le16	timestamp_hi;1173	__le32	event_data1;1174	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL1175	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 01176};1177 1178/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */1179struct hwrm_async_event_cmpl_deferred_response {1180	__le16	type;1181	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK            0x3fUL1182	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT             01183	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT  0x2eUL1184	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT1185	__le16	event_id;1186	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL1187	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE1188	__le32	event_data2;1189	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL1190	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 01191	u8	opaque_v;1192	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V          0x1UL1193	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL1194	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 11195	u8	timestamp_lo;1196	__le16	timestamp_hi;1197	__le32	event_data1;1198};1199 1200/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */1201struct hwrm_async_event_cmpl_echo_request {1202	__le16	type;1203	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK            0x3fUL1204	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT             01205	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT  0x2eUL1206	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST             ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT1207	__le16	event_id;1208	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL1209	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST1210	__le32	event_data2;1211	u8	opaque_v;1212	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_V          0x1UL1213	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL1214	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 11215	u8	timestamp_lo;1216	__le16	timestamp_hi;1217	__le32	event_data1;1218};1219 1220/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */1221struct hwrm_async_event_cmpl_phc_update {1222	__le16	type;1223	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK            0x3fUL1224	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT             01225	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT  0x2eUL1226	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST             ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT1227	__le16	event_id;1228	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL1229	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST      ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE1230	__le32	event_data2;1231	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL1232	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 01233	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK   0xffff0000UL1234	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT    161235	u8	opaque_v;1236	#define ASYNC_EVENT_CMPL_PHC_UPDATE_V          0x1UL1237	#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL1238	#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 11239	u8	timestamp_lo;1240	__le16	timestamp_hi;1241	__le32	event_data1;1242	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK          0xfUL1243	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT           01244	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER      0x1UL1245	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY   0x2UL1246	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER    0x3UL1247	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE  0x4UL1248	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST           ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE1249	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK   0xffff0UL1250	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT    41251};1252 1253/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */1254struct hwrm_async_event_cmpl_pps_timestamp {1255	__le16	type;1256	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK            0x3fUL1257	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT             01258	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT  0x2eUL1259	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST             ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT1260	__le16	event_id;1261	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL1262	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST         ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP1263	__le32	event_data2;1264	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE              0x1UL1265	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL       0x0UL1266	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL       0x1UL1267	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST          ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL1268	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK         0xeUL1269	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT          11270	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL1271	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 41272	u8	opaque_v;1273	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V          0x1UL1274	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL1275	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 11276	u8	timestamp_lo;1277	__le16	timestamp_hi;1278	__le32	event_data1;1279	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL1280	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 01281};1282 1283/* hwrm_async_event_cmpl_error_report (size:128b/16B) */1284struct hwrm_async_event_cmpl_error_report {1285	__le16	type;1286	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK            0x3fUL1287	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT             01288	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT  0x2eUL1289	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT1290	__le16	event_id;1291	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL1292	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT1293	__le32	event_data2;1294	u8	opaque_v;1295	#define ASYNC_EVENT_CMPL_ERROR_REPORT_V          0x1UL1296	#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL1297	#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 11298	u8	timestamp_lo;1299	__le16	timestamp_hi;1300	__le32	event_data1;1301	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL1302	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 01303};1304 1305/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */1306struct hwrm_async_event_cmpl_hwrm_error {1307	__le16	type;1308	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK            0x3fUL1309	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT             01310	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT  0x2eUL1311	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST             ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT1312	__le16	event_id;1313	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL1314	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST      ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR1315	__le32	event_data2;1316	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK    0xffUL1317	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT     01318	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING   0x0UL1319	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL  0x1UL1320	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL     0x2UL1321	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST     ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL1322	u8	opaque_v;1323	#define ASYNC_EVENT_CMPL_HWRM_ERROR_V          0x1UL1324	#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL1325	#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 11326	u8	timestamp_lo;1327	__le16	timestamp_hi;1328	__le32	event_data1;1329	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP     0x1UL1330};1331 1332/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */1333struct hwrm_async_event_cmpl_error_report_base {1334	__le16	type;1335	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK            0x3fUL1336	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT             01337	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT  0x2eUL1338	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT1339	__le16	event_id;1340	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL1341	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT1342	__le32	event_data2;1343	u8	opaque_v;1344	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V          0x1UL1345	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL1346	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 11347	u8	timestamp_lo;1348	__le16	timestamp_hi;1349	__le32	event_data1;1350	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK                        0xffUL1351	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT                         01352	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED                      0x0UL1353	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM                   0x1UL1354	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL                0x2UL1355	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM                           0x3UL1356	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD       0x4UL1357	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD             0x5UL1358	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED  0x6UL1359	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST                         ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED1360};1361 1362/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */1363struct hwrm_async_event_cmpl_error_report_pause_storm {1364	__le16	type;1365	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK            0x3fUL1366	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT             01367	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT  0x2eUL1368	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT1369	__le16	event_id;1370	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL1371	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT1372	__le32	event_data2;1373	u8	opaque_v;1374	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V          0x1UL1375	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL1376	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 11377	u8	timestamp_lo;1378	__le16	timestamp_hi;1379	__le32	event_data1;1380	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK       0xffUL1381	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT        01382	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM  0x1UL1383	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM1384};1385 1386/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */1387struct hwrm_async_event_cmpl_error_report_invalid_signal {1388	__le16	type;1389	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK            0x3fUL1390	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT             01391	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT  0x2eUL1392	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT1393	__le16	event_id;1394	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL1395	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT1396	__le32	event_data2;1397	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL1398	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 01399	u8	opaque_v;1400	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V          0x1UL1401	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL1402	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 11403	u8	timestamp_lo;1404	__le16	timestamp_hi;1405	__le32	event_data1;1406	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK          0xffUL1407	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT           01408	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL  0x2UL1409	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST           ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL1410};1411 1412/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */1413struct hwrm_async_event_cmpl_error_report_nvm {1414	__le16	type;1415	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK            0x3fUL1416	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT             01417	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT  0x2eUL1418	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT1419	__le16	event_id;1420	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL1421	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT1422	__le32	event_data2;1423	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL1424	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 01425	u8	opaque_v;1426	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V          0x1UL1427	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL1428	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 11429	u8	timestamp_lo;1430	__le16	timestamp_hi;1431	__le32	event_data1;1432	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK     0xffUL1433	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT      01434	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR  0x3UL1435	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST      ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR1436	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK   0xff00UL1437	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT    81438	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE    (0x1UL << 8)1439	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE    (0x2UL << 8)1440	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST    ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE1441};1442 1443/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */1444struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {1445	__le16	type;1446	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK            0x3fUL1447	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT             01448	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT  0x2eUL1449	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT1450	__le16	event_id;1451	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL1452	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT1453	__le32	event_data2;1454	u8	opaque_v;1455	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V          0x1UL1456	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL1457	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 11458	u8	timestamp_lo;1459	__le16	timestamp_hi;1460	__le32	event_data1;1461	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK                   0xffUL1462	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT                    01463	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD  0x4UL1464	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST                    ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD1465	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK                        0xffffff00UL1466	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT                         81467};1468 1469/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */1470struct hwrm_async_event_cmpl_error_report_thermal {1471	__le16	type;1472	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK            0x3fUL1473	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT             01474	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT  0x2eUL1475	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT1476	__le16	event_id;1477	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL1478	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT1479	__le32	event_data2;1480	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK  0xffUL1481	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT   01482	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL1483	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 81484	u8	opaque_v;1485	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V          0x1UL1486	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL1487	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 11488	u8	timestamp_lo;1489	__le16	timestamp_hi;1490	__le32	event_data1;1491	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK          0xffUL1492	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT           01493	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT   0x5UL1494	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST           ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT1495	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK      0x700UL1496	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT       81497	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN        (0x0UL << 8)1498	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL    (0x1UL << 8)1499	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL       (0x2UL << 8)1500	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN    (0x3UL << 8)1501	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST       ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN1502	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR           0x800UL1503	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING  (0x0UL << 11)1504	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING  (0x1UL << 11)1505	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST       ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING1506};1507 1508/* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */1509struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported {1510	__le16	type;1511	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK            0x3fUL1512	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT             01513	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT  0x2eUL1514	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT1515	__le16	event_id;1516	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL1517	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT1518	__le32	event_data2;1519	u8	opaque_v;1520	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V          0x1UL1521	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL1522	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 11523	u8	timestamp_lo;1524	__le16	timestamp_hi;1525	__le32	event_data1;1526	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK                        0xffUL1527	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT                         01528	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED  0x6UL1529	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST                         ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED1530};1531 1532/* hwrm_func_reset_input (size:192b/24B) */1533struct hwrm_func_reset_input {1534	__le16	req_type;1535	__le16	cmpl_ring;1536	__le16	seq_id;1537	__le16	target_id;1538	__le64	resp_addr;1539	__le32	enables;1540	#define FUNC_RESET_REQ_ENABLES_VF_ID_VALID     0x1UL1541	__le16	vf_id;1542	u8	func_reset_level;1543	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL      0x0UL1544	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME       0x1UL1545	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL1546	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF       0x3UL1547	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST         FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF1548	u8	unused_0;1549};1550 1551/* hwrm_func_reset_output (size:128b/16B) */1552struct hwrm_func_reset_output {1553	__le16	error_code;1554	__le16	req_type;1555	__le16	seq_id;1556	__le16	resp_len;1557	u8	unused_0[7];1558	u8	valid;1559};1560 1561/* hwrm_func_getfid_input (size:192b/24B) */1562struct hwrm_func_getfid_input {1563	__le16	req_type;1564	__le16	cmpl_ring;1565	__le16	seq_id;1566	__le16	target_id;1567	__le64	resp_addr;1568	__le32	enables;1569	#define FUNC_GETFID_REQ_ENABLES_PCI_ID     0x1UL1570	__le16	pci_id;1571	u8	unused_0[2];1572};1573 1574/* hwrm_func_getfid_output (size:128b/16B) */1575struct hwrm_func_getfid_output {1576	__le16	error_code;1577	__le16	req_type;1578	__le16	seq_id;1579	__le16	resp_len;1580	__le16	fid;1581	u8	unused_0[5];1582	u8	valid;1583};1584 1585/* hwrm_func_vf_alloc_input (size:192b/24B) */1586struct hwrm_func_vf_alloc_input {1587	__le16	req_type;1588	__le16	cmpl_ring;1589	__le16	seq_id;1590	__le16	target_id;1591	__le64	resp_addr;1592	__le32	enables;1593	#define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID     0x1UL1594	__le16	first_vf_id;1595	__le16	num_vfs;1596};1597 1598/* hwrm_func_vf_alloc_output (size:128b/16B) */1599struct hwrm_func_vf_alloc_output {1600	__le16	error_code;1601	__le16	req_type;1602	__le16	seq_id;1603	__le16	resp_len;1604	__le16	first_vf_id;1605	u8	unused_0[5];1606	u8	valid;1607};1608 1609/* hwrm_func_vf_free_input (size:192b/24B) */1610struct hwrm_func_vf_free_input {1611	__le16	req_type;1612	__le16	cmpl_ring;1613	__le16	seq_id;1614	__le16	target_id;1615	__le64	resp_addr;1616	__le32	enables;1617	#define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID     0x1UL1618	__le16	first_vf_id;1619	__le16	num_vfs;1620};1621 1622/* hwrm_func_vf_free_output (size:128b/16B) */1623struct hwrm_func_vf_free_output {1624	__le16	error_code;1625	__le16	req_type;1626	__le16	seq_id;1627	__le16	resp_len;1628	u8	unused_0[7];1629	u8	valid;1630};1631 1632/* hwrm_func_vf_cfg_input (size:576b/72B) */1633struct hwrm_func_vf_cfg_input {1634	__le16	req_type;1635	__le16	cmpl_ring;1636	__le16	seq_id;1637	__le16	target_id;1638	__le64	resp_addr;1639	__le32	enables;1640	#define FUNC_VF_CFG_REQ_ENABLES_MTU                      0x1UL1641	#define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN               0x2UL1642	#define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR           0x4UL1643	#define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR            0x8UL1644	#define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS          0x10UL1645	#define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS           0x20UL1646	#define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS             0x40UL1647	#define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS             0x80UL1648	#define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS              0x100UL1649	#define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS                0x200UL1650	#define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS            0x400UL1651	#define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS         0x800UL1652	#define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS     0x1000UL1653	#define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS     0x2000UL1654	#define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS     0x4000UL1655	#define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS     0x8000UL1656	__le16	mtu;1657	__le16	guest_vlan;1658	__le16	async_event_cr;1659	u8	dflt_mac_addr[6];1660	__le32	flags;1661	#define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST             0x1UL1662	#define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST             0x2UL1663	#define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST           0x4UL1664	#define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST     0x8UL1665	#define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST       0x10UL1666	#define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST       0x20UL1667	#define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST           0x40UL1668	#define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST         0x80UL1669	#define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE       0x100UL1670	#define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE      0x200UL1671	__le16	num_rsscos_ctxs;1672	__le16	num_cmpl_rings;1673	__le16	num_tx_rings;1674	__le16	num_rx_rings;1675	__le16	num_l2_ctxs;1676	__le16	num_vnics;1677	__le16	num_stat_ctxs;1678	__le16	num_hw_ring_grps;1679	__le32	num_ktls_tx_key_ctxs;1680	__le32	num_ktls_rx_key_ctxs;1681	__le16	num_msix;1682	u8	unused[2];1683	__le32	num_quic_tx_key_ctxs;1684	__le32	num_quic_rx_key_ctxs;1685};1686 1687/* hwrm_func_vf_cfg_output (size:128b/16B) */1688struct hwrm_func_vf_cfg_output {1689	__le16	error_code;1690	__le16	req_type;1691	__le16	seq_id;1692	__le16	resp_len;1693	u8	unused_0[7];1694	u8	valid;1695};1696 1697/* hwrm_func_qcaps_input (size:192b/24B) */1698struct hwrm_func_qcaps_input {1699	__le16	req_type;1700	__le16	cmpl_ring;1701	__le16	seq_id;1702	__le16	target_id;1703	__le64	resp_addr;1704	__le16	fid;1705	u8	unused_0[6];1706};1707 1708/* hwrm_func_qcaps_output (size:1152b/144B) */1709struct hwrm_func_qcaps_output {1710	__le16	error_code;1711	__le16	req_type;1712	__le16	seq_id;1713	__le16	resp_len;1714	__le16	fid;1715	__le16	port_id;1716	__le32	flags;1717	#define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED                   0x1UL1718	#define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING               0x2UL1719	#define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED                         0x4UL1720	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED                     0x8UL1721	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED                     0x10UL1722	#define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED                0x20UL1723	#define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED                     0x40UL1724	#define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED                  0x80UL1725	#define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED                   0x100UL1726	#define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED               0x200UL1727	#define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED                   0x400UL1728	#define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED            0x800UL1729	#define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED            0x1000UL1730	#define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED             0x2000UL1731	#define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED               0x4000UL1732	#define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED              0x8000UL1733	#define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED                  0x10000UL1734	#define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED                  0x20000UL1735	#define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED                    0x40000UL1736	#define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED           0x80000UL1737	#define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE                         0x100000UL1738	#define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC                 0x200000UL1739	#define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE                     0x400000UL1740	#define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE                0x800000UL1741	#define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED                   0x1000000UL1742	#define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD                    0x2000000UL1743	#define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED     0x4000000UL1744	#define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED         0x8000000UL1745	#define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED                0x10000000UL1746	#define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED               0x20000000UL1747	#define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED                0x40000000UL1748	#define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED               0x80000000UL1749	u8	mac_address[6];1750	__le16	max_rsscos_ctx;1751	__le16	max_cmpl_rings;1752	__le16	max_tx_rings;1753	__le16	max_rx_rings;1754	__le16	max_l2_ctxs;1755	__le16	max_vnics;1756	__le16	first_vf_id;1757	__le16	max_vfs;1758	__le16	max_stat_ctx;1759	__le32	max_encap_records;1760	__le32	max_decap_records;1761	__le32	max_tx_em_flows;1762	__le32	max_tx_wm_flows;1763	__le32	max_rx_em_flows;1764	__le32	max_rx_wm_flows;1765	__le32	max_mcast_filters;1766	__le32	max_flow_id;1767	__le32	max_hw_ring_grps;1768	__le16	max_sp_tx_rings;1769	__le16	max_msix_vfs;1770	__le32	flags_ext;1771	#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED                          0x1UL1772	#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED                         0x2UL1773	#define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED                      0x4UL1774	#define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT                        0x8UL1775	#define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT                          0x10UL1776	#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT          0x20UL1777	#define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED                              0x40UL1778	#define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED                     0x80UL1779	#define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED                  0x100UL1780	#define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED                           0x200UL1781	#define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED                      0x400UL1782	#define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE                          0x800UL1783	#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE                     0x1000UL1784	#define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED                 0x2000UL1785	#define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED                       0x4000UL1786	#define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED                      0x8000UL1787	#define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED                          0x10000UL1788	#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED                           0x20000UL1789	#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED                           0x40000UL1790	#define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED               0x80000UL1791	#define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED                      0x100000UL1792	#define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED                0x200000UL1793	#define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED                              0x400000UL1794	#define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL                             0x800000UL1795	#define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED                            0x1000000UL1796	#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP                            0x2000000UL1797	#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED                             0x4000000UL1798	#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED                              0x8000000UL1799	#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED                     0x10000000UL1800	#define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED                        0x20000000UL1801	#define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED                 0x40000000UL1802	#define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED     0x80000000UL1803	u8	max_schqs;1804	u8	mpc_chnls_cap;1805	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE         0x1UL1806	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE         0x2UL1807	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA      0x4UL1808	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA      0x8UL1809	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE     0x10UL1810	__le16	max_key_ctxs_alloc;1811	__le32	flags_ext2;1812	#define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED      0x1UL1813	#define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED                        0x2UL1814	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED                       0x4UL1815	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED              0x8UL1816	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED        0x10UL1817	#define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED               0x20UL1818	#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED                     0x40UL1819	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED                       0x80UL1820	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED               0x100UL1821	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED              0x200UL1822	#define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED                      0x400UL1823	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED                 0x800UL1824	#define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED                0x1000UL1825	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED           0x2000UL1826	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED           0x4000UL1827	#define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED        0x8000UL1828	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED           0x10000UL1829	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED             0x20000UL1830	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED     0x40000UL1831	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED              0x80000UL1832	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED       0x100000UL1833	#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED                        0x200000UL1834	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED          0x400000UL1835	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED      0x800000UL1836	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED         0x1000000UL1837	#define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED                  0x2000000UL1838	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED          0x4000000UL1839	#define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED       0x8000000UL1840	#define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED                   0x10000000UL1841	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED             0x20000000UL1842	#define FUNC_QCAPS_RESP_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED            0x40000000UL1843	#define FUNC_QCAPS_RESP_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED               0x80000000UL1844	__le16	tunnel_disable_flag;1845	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN      0x1UL1846	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE        0x2UL1847	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE      0x4UL1848	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE      0x8UL1849	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE        0x10UL1850	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP     0x20UL1851	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS       0x40UL1852	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE      0x80UL1853	__le16	xid_partition_cap;1854	#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK     0x1UL1855	#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK     0x2UL1856	u8	device_serial_number[8];1857	__le16	ctxs_per_partition;1858	__le16	max_tso_segs;1859	__le32	roce_vf_max_av;1860	__le32	roce_vf_max_cq;1861	__le32	roce_vf_max_mrw;1862	__le32	roce_vf_max_qp;1863	__le32	roce_vf_max_srq;1864	__le32	roce_vf_max_gid;1865	__le32	flags_ext3;1866	#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP     0x1UL1867	u8	unused_3[7];1868	u8	valid;1869};1870 1871/* hwrm_func_qcfg_input (size:192b/24B) */1872struct hwrm_func_qcfg_input {1873	__le16	req_type;1874	__le16	cmpl_ring;1875	__le16	seq_id;1876	__le16	target_id;1877	__le64	resp_addr;1878	__le16	fid;1879	u8	unused_0[6];1880};1881 1882/* hwrm_func_qcfg_output (size:1280b/160B) */1883struct hwrm_func_qcfg_output {1884	__le16	error_code;1885	__le16	req_type;1886	__le16	seq_id;1887	__le16	resp_len;1888	__le16	fid;1889	__le16	port_id;1890	__le16	vlan;1891	__le16	flags;1892	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED     0x1UL1893	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED          0x2UL1894	#define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED        0x4UL1895	#define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED     0x8UL1896	#define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED        0x10UL1897	#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST                   0x20UL1898	#define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF                   0x40UL1899	#define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED          0x80UL1900	#define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS      0x100UL1901	#define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED            0x200UL1902	#define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED        0x400UL1903	#define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED         0x800UL1904	#define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED           0x1000UL1905	#define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT                   0x2000UL1906	#define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV            0x4000UL1907	#define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID           0x8000UL1908	u8	mac_address[6];1909	__le16	pci_id;1910	__le16	alloc_rsscos_ctx;1911	__le16	alloc_cmpl_rings;1912	__le16	alloc_tx_rings;1913	__le16	alloc_rx_rings;1914	__le16	alloc_l2_ctx;1915	__le16	alloc_vnics;1916	__le16	admin_mtu;1917	__le16	mru;1918	__le16	stat_ctx_id;1919	u8	port_partition_type;1920	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF     0x0UL1921	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS    0x1UL1922	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL1923	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL1924	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL1925	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL1926	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL1927	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST   FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN1928	u8	port_pf_cnt;1929	#define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL1930	#define FUNC_QCFG_RESP_PORT_PF_CNT_LAST   FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL1931	__le16	dflt_vnic_id;1932	__le16	max_mtu_configured;1933	__le32	min_bw;1934	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK             0xfffffffUL1935	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT              01936	#define FUNC_QCFG_RESP_MIN_BW_SCALE                     0x10000000UL1937	#define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS                  (0x0UL << 28)1938	#define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES                 (0x1UL << 28)1939	#define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES1940	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL1941	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT         291942	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)1943	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)1944	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)1945	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)1946	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)1947	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)1948	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID1949	__le32	max_bw;1950	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK             0xfffffffUL1951	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT              01952	#define FUNC_QCFG_RESP_MAX_BW_SCALE                     0x10000000UL1953	#define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS                  (0x0UL << 28)1954	#define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES                 (0x1UL << 28)1955	#define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES1956	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL1957	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT         291958	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)1959	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)1960	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)1961	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)1962	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)1963	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)1964	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID1965	u8	evb_mode;1966	#define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL1967	#define FUNC_QCFG_RESP_EVB_MODE_VEB    0x1UL1968	#define FUNC_QCFG_RESP_EVB_MODE_VEPA   0x2UL1969	#define FUNC_QCFG_RESP_EVB_MODE_LAST  FUNC_QCFG_RESP_EVB_MODE_VEPA1970	u8	options;1971	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK         0x3UL1972	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT          01973	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL1974	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL1975	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST          FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_1281976	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL1977	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT        21978	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)1979	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)1980	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)1981	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO1982	#define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK                   0xf0UL1983	#define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT                    41984	__le16	alloc_vfs;1985	__le32	alloc_mcast_filters;1986	__le32	alloc_hw_ring_grps;1987	__le16	alloc_sp_tx_rings;1988	__le16	alloc_stat_ctx;1989	__le16	alloc_msix;1990	__le16	registered_vfs;1991	__le16	l2_doorbell_bar_size_kb;1992	u8	active_endpoints;1993	u8	always_1;1994	__le32	reset_addr_poll;1995	__le16	legacy_l2_db_size_kb;1996	__le16	svif_info;1997	#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK      0x7fffUL1998	#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT       01999	#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID     0x8000UL2000	u8	mpc_chnls;2001	#define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED         0x1UL2002	#define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED         0x2UL2003	#define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED      0x4UL2004	#define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED      0x8UL2005	#define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED     0x10UL2006	u8	db_page_size;2007	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB   0x0UL2008	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB   0x1UL2009	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB  0x2UL2010	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB  0x3UL2011	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB  0x4UL2012	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL2013	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL2014	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL2015	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB   0x8UL2016	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB   0x9UL2017	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB   0xaUL2018	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB2019	__le16	roce_vnic_id;2020	__le32	partition_min_bw;2021	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK             0xfffffffUL2022	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT              02023	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE                     0x10000000UL2024	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS                  (0x0UL << 28)2025	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES                 (0x1UL << 28)2026	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES2027	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL2028	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT         292029	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)2030	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_1002031	__le32	partition_max_bw;2032	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK             0xfffffffUL2033	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT              02034	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE                     0x10000000UL2035	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS                  (0x0UL << 28)2036	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES                 (0x1UL << 28)2037	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES2038	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL2039	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT         292040	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)2041	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_1002042	__le16	host_mtu;2043	__le16	flags2;2044	#define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED     0x1UL2045	u8	unused_4[2];2046	u8	port_kdnet_mode;2047	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL2048	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED  0x1UL2049	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST    FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED2050	u8	kdnet_pcie_function;2051	__le16	port_kdnet_fid;2052	u8	unused_5[2];2053	__le32	num_ktls_tx_key_ctxs;2054	__le32	num_ktls_rx_key_ctxs;2055	u8	lag_id;2056	u8	parif;2057	u8	fw_lag_id;2058	u8	unused_6;2059	__le32	num_quic_tx_key_ctxs;2060	__le32	num_quic_rx_key_ctxs;2061	__le32	roce_max_av_per_vf;2062	__le32	roce_max_cq_per_vf;2063	__le32	roce_max_mrw_per_vf;2064	__le32	roce_max_qp_per_vf;2065	__le32	roce_max_srq_per_vf;2066	__le32	roce_max_gid_per_vf;2067	__le16	xid_partition_cfg;2068	#define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK     0x1UL2069	#define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK     0x2UL2070	u8	unused_7;2071	u8	valid;2072};2073 2074/* hwrm_func_cfg_input (size:1280b/160B) */2075struct hwrm_func_cfg_input {2076	__le16	req_type;2077	__le16	cmpl_ring;2078	__le16	seq_id;2079	__le16	target_id;2080	__le64	resp_addr;2081	__le16	fid;2082	__le16	num_msix;2083	__le32	flags;2084	#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE     0x1UL2085	#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE      0x2UL2086	#define FUNC_CFG_REQ_FLAGS_RSVD_MASK                      0x1fcUL2087	#define FUNC_CFG_REQ_FLAGS_RSVD_SFT                       22088	#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE        0x200UL2089	#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE       0x400UL2090	#define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST               0x800UL2091	#define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC         0x1000UL2092	#define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST                 0x2000UL2093	#define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST                 0x4000UL2094	#define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST               0x8000UL2095	#define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST         0x10000UL2096	#define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST           0x20000UL2097	#define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST           0x40000UL2098	#define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST               0x80000UL2099	#define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST             0x100000UL2100	#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE              0x200000UL2101	#define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC          0x400000UL2102	#define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST                 0x800000UL2103	#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE             0x1000000UL2104	#define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS        0x2000000UL2105	#define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS            0x4000000UL2106	#define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE           0x8000000UL2107	#define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE          0x10000000UL2108	#define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE             0x20000000UL2109	#define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE            0x40000000UL2110	__le32	enables;2111	#define FUNC_CFG_REQ_ENABLES_ADMIN_MTU                0x1UL2112	#define FUNC_CFG_REQ_ENABLES_MRU                      0x2UL2113	#define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS          0x4UL2114	#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS           0x8UL2115	#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS             0x10UL2116	#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS             0x20UL2117	#define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS              0x40UL2118	#define FUNC_CFG_REQ_ENABLES_NUM_VNICS                0x80UL2119	#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS            0x100UL2120	#define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR            0x200UL2121	#define FUNC_CFG_REQ_ENABLES_DFLT_VLAN                0x400UL2122	#define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR             0x800UL2123	#define FUNC_CFG_REQ_ENABLES_MIN_BW                   0x1000UL2124	#define FUNC_CFG_REQ_ENABLES_MAX_BW                   0x2000UL2125	#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR           0x4000UL2126	#define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE      0x8000UL2127	#define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS        0x10000UL2128	#define FUNC_CFG_REQ_ENABLES_EVB_MODE                 0x20000UL2129	#define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS        0x40000UL2130	#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS         0x80000UL2131	#define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE           0x100000UL2132	#define FUNC_CFG_REQ_ENABLES_NUM_MSIX                 0x200000UL2133	#define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE         0x400000UL2134	#define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT     0x800000UL2135	#define FUNC_CFG_REQ_ENABLES_SCHQ_ID                  0x1000000UL2136	#define FUNC_CFG_REQ_ENABLES_MPC_CHNLS                0x2000000UL2137	#define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW         0x4000000UL2138	#define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW         0x8000000UL2139	#define FUNC_CFG_REQ_ENABLES_TPID                     0x10000000UL2140	#define FUNC_CFG_REQ_ENABLES_HOST_MTU                 0x20000000UL2141	#define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS         0x40000000UL2142	#define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS         0x80000000UL2143	__le16	admin_mtu;2144	__le16	mru;2145	__le16	num_rsscos_ctxs;2146	__le16	num_cmpl_rings;2147	__le16	num_tx_rings;2148	__le16	num_rx_rings;2149	__le16	num_l2_ctxs;2150	__le16	num_vnics;2151	__le16	num_stat_ctxs;2152	__le16	num_hw_ring_grps;2153	u8	dflt_mac_addr[6];2154	__le16	dflt_vlan;2155	__be32	dflt_ip_addr[4];2156	__le32	min_bw;2157	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK             0xfffffffUL2158	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT              02159	#define FUNC_CFG_REQ_MIN_BW_SCALE                     0x10000000UL2160	#define FUNC_CFG_REQ_MIN_BW_SCALE_BITS                  (0x0UL << 28)2161	#define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES                 (0x1UL << 28)2162	#define FUNC_CFG_REQ_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_MIN_BW_SCALE_BYTES2163	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL2164	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT         292165	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)2166	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)2167	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)2168	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)2169	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)2170	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)2171	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID2172	__le32	max_bw;2173	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL2174	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT              02175	#define FUNC_CFG_REQ_MAX_BW_SCALE                     0x10000000UL2176	#define FUNC_CFG_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)2177	#define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)2178	#define FUNC_CFG_REQ_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_MAX_BW_SCALE_BYTES2179	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL2180	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT         292181	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)2182	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)2183	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)2184	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)2185	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)2186	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)2187	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID2188	__le16	async_event_cr;2189	u8	vlan_antispoof_mode;2190	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK                 0x0UL2191	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN           0x1UL2192	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE       0x2UL2193	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL2194	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST                   FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN2195	u8	allowed_vlan_pris;2196	u8	evb_mode;2197	#define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL2198	#define FUNC_CFG_REQ_EVB_MODE_VEB    0x1UL2199	#define FUNC_CFG_REQ_EVB_MODE_VEPA   0x2UL2200	#define FUNC_CFG_REQ_EVB_MODE_LAST  FUNC_CFG_REQ_EVB_MODE_VEPA2201	u8	options;2202	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK         0x3UL2203	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT          02204	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL2205	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL2206	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST          FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_1282207	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL2208	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT        22209	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)2210	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)2211	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)2212	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO2213	#define FUNC_CFG_REQ_OPTIONS_RSVD_MASK                   0xf0UL2214	#define FUNC_CFG_REQ_OPTIONS_RSVD_SFT                    42215	__le16	num_mcast_filters;2216	__le16	schq_id;2217	__le16	mpc_chnls;2218	#define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE          0x1UL2219	#define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE         0x2UL2220	#define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE          0x4UL2221	#define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE         0x8UL2222	#define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE       0x10UL2223	#define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE      0x20UL2224	#define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE       0x40UL2225	#define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE      0x80UL2226	#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE      0x100UL2227	#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE     0x200UL2228	__le32	partition_min_bw;2229	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK             0xfffffffUL2230	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT              02231	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE                     0x10000000UL2232	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS                  (0x0UL << 28)2233	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES                 (0x1UL << 28)2234	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES2235	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL2236	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT         292237	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)2238	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_1002239	__le32	partition_max_bw;2240	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK             0xfffffffUL2241	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT              02242	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE                     0x10000000UL2243	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS                  (0x0UL << 28)2244	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES                 (0x1UL << 28)2245	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES2246	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL2247	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT         292248	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)2249	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_1002250	__be16	tpid;2251	__le16	host_mtu;2252	__le32	flags2;2253	#define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST     0x1UL2254	#define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST     0x2UL2255	__le32	enables2;2256	#define FUNC_CFG_REQ_ENABLES2_KDNET                   0x1UL2257	#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE            0x2UL2258	#define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS        0x4UL2259	#define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS        0x8UL2260	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF      0x10UL2261	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF      0x20UL2262	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF     0x40UL2263	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF      0x80UL2264	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF     0x100UL2265	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF     0x200UL2266	#define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG       0x400UL2267	u8	port_kdnet_mode;2268	#define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL2269	#define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED  0x1UL2270	#define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST    FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED2271	u8	db_page_size;2272	#define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB   0x0UL2273	#define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB   0x1UL2274	#define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB  0x2UL2275	#define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB  0x3UL2276	#define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB  0x4UL2277	#define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL2278	#define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL2279	#define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL2280	#define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB   0x8UL2281	#define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB   0x9UL2282	#define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB   0xaUL2283	#define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB2284	u8	unused_1[2];2285	__le32	num_ktls_tx_key_ctxs;2286	__le32	num_ktls_rx_key_ctxs;2287	__le32	num_quic_tx_key_ctxs;2288	__le32	num_quic_rx_key_ctxs;2289	__le32	roce_max_av_per_vf;2290	__le32	roce_max_cq_per_vf;2291	__le32	roce_max_mrw_per_vf;2292	__le32	roce_max_qp_per_vf;2293	__le32	roce_max_srq_per_vf;2294	__le32	roce_max_gid_per_vf;2295	__le16	xid_partition_cfg;2296	#define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK     0x1UL2297	#define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK     0x2UL2298	__le16	unused_2;2299};2300 2301/* hwrm_func_cfg_output (size:128b/16B) */2302struct hwrm_func_cfg_output {2303	__le16	error_code;2304	__le16	req_type;2305	__le16	seq_id;2306	__le16	resp_len;2307	u8	unused_0[7];2308	u8	valid;2309};2310 2311/* hwrm_func_cfg_cmd_err (size:64b/8B) */2312struct hwrm_func_cfg_cmd_err {2313	u8	code;2314	#define FUNC_CFG_CMD_ERR_CODE_UNKNOWN                      0x0UL2315	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE       0x1UL2316	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX  0x2UL2317	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL2318	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT         0x4UL2319	#define FUNC_CFG_CMD_ERR_CODE_LAST                        FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT2320	u8	unused_0[7];2321};2322 2323/* hwrm_func_qstats_input (size:192b/24B) */2324struct hwrm_func_qstats_input {2325	__le16	req_type;2326	__le16	cmpl_ring;2327	__le16	seq_id;2328	__le16	target_id;2329	__le64	resp_addr;2330	__le16	fid;2331	u8	flags;2332	#define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY        0x1UL2333	#define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK     0x2UL2334	#define FUNC_QSTATS_REQ_FLAGS_L2_ONLY          0x4UL2335	u8	unused_0[5];2336};2337 2338/* hwrm_func_qstats_output (size:1408b/176B) */2339struct hwrm_func_qstats_output {2340	__le16	error_code;2341	__le16	req_type;2342	__le16	seq_id;2343	__le16	resp_len;2344	__le64	tx_ucast_pkts;2345	__le64	tx_mcast_pkts;2346	__le64	tx_bcast_pkts;2347	__le64	tx_discard_pkts;2348	__le64	tx_drop_pkts;2349	__le64	tx_ucast_bytes;2350	__le64	tx_mcast_bytes;2351	__le64	tx_bcast_bytes;2352	__le64	rx_ucast_pkts;2353	__le64	rx_mcast_pkts;2354	__le64	rx_bcast_pkts;2355	__le64	rx_discard_pkts;2356	__le64	rx_drop_pkts;2357	__le64	rx_ucast_bytes;2358	__le64	rx_mcast_bytes;2359	__le64	rx_bcast_bytes;2360	__le64	rx_agg_pkts;2361	__le64	rx_agg_bytes;2362	__le64	rx_agg_events;2363	__le64	rx_agg_aborts;2364	u8	clear_seq;2365	u8	unused_0[6];2366	u8	valid;2367};2368 2369/* hwrm_func_qstats_ext_input (size:256b/32B) */2370struct hwrm_func_qstats_ext_input {2371	__le16	req_type;2372	__le16	cmpl_ring;2373	__le16	seq_id;2374	__le16	target_id;2375	__le64	resp_addr;2376	__le16	fid;2377	u8	flags;2378	#define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY        0x1UL2379	#define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK     0x2UL2380	u8	unused_0[1];2381	__le32	enables;2382	#define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID     0x1UL2383	__le16	schq_id;2384	__le16	traffic_class;2385	u8	unused_1[4];2386};2387 2388/* hwrm_func_qstats_ext_output (size:1536b/192B) */2389struct hwrm_func_qstats_ext_output {2390	__le16	error_code;2391	__le16	req_type;2392	__le16	seq_id;2393	__le16	resp_len;2394	__le64	rx_ucast_pkts;2395	__le64	rx_mcast_pkts;2396	__le64	rx_bcast_pkts;2397	__le64	rx_discard_pkts;2398	__le64	rx_error_pkts;2399	__le64	rx_ucast_bytes;2400	__le64	rx_mcast_bytes;2401	__le64	rx_bcast_bytes;2402	__le64	tx_ucast_pkts;2403	__le64	tx_mcast_pkts;2404	__le64	tx_bcast_pkts;2405	__le64	tx_error_pkts;2406	__le64	tx_discard_pkts;2407	__le64	tx_ucast_bytes;2408	__le64	tx_mcast_bytes;2409	__le64	tx_bcast_bytes;2410	__le64	rx_tpa_eligible_pkt;2411	__le64	rx_tpa_eligible_bytes;2412	__le64	rx_tpa_pkt;2413	__le64	rx_tpa_bytes;2414	__le64	rx_tpa_errors;2415	__le64	rx_tpa_events;2416	u8	unused_0[7];2417	u8	valid;2418};2419 2420/* hwrm_func_clr_stats_input (size:192b/24B) */2421struct hwrm_func_clr_stats_input {2422	__le16	req_type;2423	__le16	cmpl_ring;2424	__le16	seq_id;2425	__le16	target_id;2426	__le64	resp_addr;2427	__le16	fid;2428	u8	unused_0[6];2429};2430 2431/* hwrm_func_clr_stats_output (size:128b/16B) */2432struct hwrm_func_clr_stats_output {2433	__le16	error_code;2434	__le16	req_type;2435	__le16	seq_id;2436	__le16	resp_len;2437	u8	unused_0[7];2438	u8	valid;2439};2440 2441/* hwrm_func_vf_resc_free_input (size:192b/24B) */2442struct hwrm_func_vf_resc_free_input {2443	__le16	req_type;2444	__le16	cmpl_ring;2445	__le16	seq_id;2446	__le16	target_id;2447	__le64	resp_addr;2448	__le16	vf_id;2449	u8	unused_0[6];2450};2451 2452/* hwrm_func_vf_resc_free_output (size:128b/16B) */2453struct hwrm_func_vf_resc_free_output {2454	__le16	error_code;2455	__le16	req_type;2456	__le16	seq_id;2457	__le16	resp_len;2458	u8	unused_0[7];2459	u8	valid;2460};2461 2462/* hwrm_func_drv_rgtr_input (size:896b/112B) */2463struct hwrm_func_drv_rgtr_input {2464	__le16	req_type;2465	__le16	cmpl_ring;2466	__le16	seq_id;2467	__le16	target_id;2468	__le64	resp_addr;2469	__le32	flags;2470	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE                     0x1UL2471	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE                    0x2UL2472	#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE                   0x4UL2473	#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE           0x8UL2474	#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT                0x10UL2475	#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT           0x20UL2476	#define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT                   0x40UL2477	#define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT               0x80UL2478	#define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT     0x100UL2479	#define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT                 0x200UL2480	#define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT           0x400UL2481	#define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE         0x800UL2482	#define FUNC_DRV_RGTR_REQ_FLAGS_TF_EGRESS_NIC_FLOW_MODE          0x1000UL2483	__le32	enables;2484	#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL2485	#define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL2486	#define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP           0x4UL2487	#define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD          0x8UL2488	#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD     0x10UL2489	__le16	os_type;2490	#define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN   0x0UL2491	#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER     0x1UL2492	#define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS     0xeUL2493	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS   0x12UL2494	#define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS   0x1dUL2495	#define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX     0x24UL2496	#define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD   0x2aUL2497	#define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI      0x68UL2498	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864    0x73UL2499	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL2500	#define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI      0x8000UL2501	#define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST     FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI2502	u8	ver_maj_8b;2503	u8	ver_min_8b;2504	u8	ver_upd_8b;2505	u8	unused_0[3];2506	__le32	timestamp;2507	u8	unused_1[4];2508	__le32	vf_req_fwd[8];2509	__le32	async_event_fwd[8];2510	__le16	ver_maj;2511	__le16	ver_min;2512	__le16	ver_upd;2513	__le16	ver_patch;2514};2515 2516/* hwrm_func_drv_rgtr_output (size:128b/16B) */2517struct hwrm_func_drv_rgtr_output {2518	__le16	error_code;2519	__le16	req_type;2520	__le16	seq_id;2521	__le16	resp_len;2522	__le32	flags;2523	#define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED     0x1UL2524	u8	unused_0[3];2525	u8	valid;2526};2527 2528/* hwrm_func_drv_unrgtr_input (size:192b/24B) */2529struct hwrm_func_drv_unrgtr_input {2530	__le16	req_type;2531	__le16	cmpl_ring;2532	__le16	seq_id;2533	__le16	target_id;2534	__le64	resp_addr;2535	__le32	flags;2536	#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL2537	u8	unused_0[4];2538};2539 2540/* hwrm_func_drv_unrgtr_output (size:128b/16B) */2541struct hwrm_func_drv_unrgtr_output {2542	__le16	error_code;2543	__le16	req_type;2544	__le16	seq_id;2545	__le16	resp_len;2546	u8	unused_0[7];2547	u8	valid;2548};2549 2550/* hwrm_func_buf_rgtr_input (size:1024b/128B) */2551struct hwrm_func_buf_rgtr_input {2552	__le16	req_type;2553	__le16	cmpl_ring;2554	__le16	seq_id;2555	__le16	target_id;2556	__le64	resp_addr;2557	__le32	enables;2558	#define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID            0x1UL2559	#define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR     0x2UL2560	__le16	vf_id;2561	__le16	req_buf_num_pages;2562	__le16	req_buf_page_size;2563	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL2564	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K  0xcUL2565	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K  0xdUL2566	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL2567	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M  0x15UL2568	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M  0x16UL2569	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G  0x1eUL2570	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G2571	__le16	req_buf_len;2572	__le16	resp_buf_len;2573	u8	unused_0[2];2574	__le64	req_buf_page_addr0;2575	__le64	req_buf_page_addr1;2576	__le64	req_buf_page_addr2;2577	__le64	req_buf_page_addr3;2578	__le64	req_buf_page_addr4;2579	__le64	req_buf_page_addr5;2580	__le64	req_buf_page_addr6;2581	__le64	req_buf_page_addr7;2582	__le64	req_buf_page_addr8;2583	__le64	req_buf_page_addr9;2584	__le64	error_buf_addr;2585	__le64	resp_buf_addr;2586};2587 2588/* hwrm_func_buf_rgtr_output (size:128b/16B) */2589struct hwrm_func_buf_rgtr_output {2590	__le16	error_code;2591	__le16	req_type;2592	__le16	seq_id;2593	__le16	resp_len;2594	u8	unused_0[7];2595	u8	valid;2596};2597 2598/* hwrm_func_drv_qver_input (size:192b/24B) */2599struct hwrm_func_drv_qver_input {2600	__le16	req_type;2601	__le16	cmpl_ring;2602	__le16	seq_id;2603	__le16	target_id;2604	__le64	resp_addr;2605	__le32	reserved;2606	__le16	fid;2607	u8	driver_type;2608	#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2   0x0UL2609	#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL2610	#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE2611	u8	unused_0;2612};2613 2614/* hwrm_func_drv_qver_output (size:256b/32B) */2615struct hwrm_func_drv_qver_output {2616	__le16	error_code;2617	__le16	req_type;2618	__le16	seq_id;2619	__le16	resp_len;2620	__le16	os_type;2621	#define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN   0x0UL2622	#define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER     0x1UL2623	#define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS     0xeUL2624	#define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS   0x12UL2625	#define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS   0x1dUL2626	#define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX     0x24UL2627	#define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD   0x2aUL2628	#define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI      0x68UL2629	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864    0x73UL2630	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL2631	#define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI      0x8000UL2632	#define FUNC_DRV_QVER_RESP_OS_TYPE_LAST     FUNC_DRV_QVER_RESP_OS_TYPE_UEFI2633	u8	ver_maj_8b;2634	u8	ver_min_8b;2635	u8	ver_upd_8b;2636	u8	unused_0[3];2637	__le16	ver_maj;2638	__le16	ver_min;2639	__le16	ver_upd;2640	__le16	ver_patch;2641	u8	unused_1[7];2642	u8	valid;2643};2644 2645/* hwrm_func_resource_qcaps_input (size:192b/24B) */2646struct hwrm_func_resource_qcaps_input {2647	__le16	req_type;2648	__le16	cmpl_ring;2649	__le16	seq_id;2650	__le16	target_id;2651	__le64	resp_addr;2652	__le16	fid;2653	u8	unused_0[6];2654};2655 2656/* hwrm_func_resource_qcaps_output (size:704b/88B) */2657struct hwrm_func_resource_qcaps_output {2658	__le16	error_code;2659	__le16	req_type;2660	__le16	seq_id;2661	__le16	resp_len;2662	__le16	max_vfs;2663	__le16	max_msix;2664	__le16	vf_reservation_strategy;2665	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL        0x0UL2666	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL        0x1UL2667	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL2668	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST          FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC2669	__le16	min_rsscos_ctx;2670	__le16	max_rsscos_ctx;2671	__le16	min_cmpl_rings;2672	__le16	max_cmpl_rings;2673	__le16	min_tx_rings;2674	__le16	max_tx_rings;2675	__le16	min_rx_rings;2676	__le16	max_rx_rings;2677	__le16	min_l2_ctxs;2678	__le16	max_l2_ctxs;2679	__le16	min_vnics;2680	__le16	max_vnics;2681	__le16	min_stat_ctx;2682	__le16	max_stat_ctx;2683	__le16	min_hw_ring_grps;2684	__le16	max_hw_ring_grps;2685	__le16	max_tx_scheduler_inputs;2686	__le16	flags;2687	#define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED     0x1UL2688	__le16	min_msix;2689	__le32	min_ktls_tx_key_ctxs;2690	__le32	max_ktls_tx_key_ctxs;2691	__le32	min_ktls_rx_key_ctxs;2692	__le32	max_ktls_rx_key_ctxs;2693	__le32	min_quic_tx_key_ctxs;2694	__le32	max_quic_tx_key_ctxs;2695	__le32	min_quic_rx_key_ctxs;2696	__le32	max_quic_rx_key_ctxs;2697	u8	unused_0[3];2698	u8	valid;2699};2700 2701/* hwrm_func_vf_resource_cfg_input (size:704b/88B) */2702struct hwrm_func_vf_resource_cfg_input {2703	__le16	req_type;2704	__le16	cmpl_ring;2705	__le16	seq_id;2706	__le16	target_id;2707	__le64	resp_addr;2708	__le16	vf_id;2709	__le16	max_msix;2710	__le16	min_rsscos_ctx;2711	__le16	max_rsscos_ctx;2712	__le16	min_cmpl_rings;2713	__le16	max_cmpl_rings;2714	__le16	min_tx_rings;2715	__le16	max_tx_rings;2716	__le16	min_rx_rings;2717	__le16	max_rx_rings;2718	__le16	min_l2_ctxs;2719	__le16	max_l2_ctxs;2720	__le16	min_vnics;2721	__le16	max_vnics;2722	__le16	min_stat_ctx;2723	__le16	max_stat_ctx;2724	__le16	min_hw_ring_grps;2725	__le16	max_hw_ring_grps;2726	__le16	flags;2727	#define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED     0x1UL2728	__le16	min_msix;2729	__le32	min_ktls_tx_key_ctxs;2730	__le32	max_ktls_tx_key_ctxs;2731	__le32	min_ktls_rx_key_ctxs;2732	__le32	max_ktls_rx_key_ctxs;2733	__le32	min_quic_tx_key_ctxs;2734	__le32	max_quic_tx_key_ctxs;2735	__le32	min_quic_rx_key_ctxs;2736	__le32	max_quic_rx_key_ctxs;2737};2738 2739/* hwrm_func_vf_resource_cfg_output (size:384b/48B) */2740struct hwrm_func_vf_resource_cfg_output {2741	__le16	error_code;2742	__le16	req_type;2743	__le16	seq_id;2744	__le16	resp_len;2745	__le16	reserved_rsscos_ctx;2746	__le16	reserved_cmpl_rings;2747	__le16	reserved_tx_rings;2748	__le16	reserved_rx_rings;2749	__le16	reserved_l2_ctxs;2750	__le16	reserved_vnics;2751	__le16	reserved_stat_ctx;2752	__le16	reserved_hw_ring_grps;2753	__le32	reserved_ktls_tx_key_ctxs;2754	__le32	reserved_ktls_rx_key_ctxs;2755	__le32	reserved_quic_tx_key_ctxs;2756	__le32	reserved_quic_rx_key_ctxs;2757	u8	unused_0[7];2758	u8	valid;2759};2760 2761/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */2762struct hwrm_func_backing_store_qcaps_input {2763	__le16	req_type;2764	__le16	cmpl_ring;2765	__le16	seq_id;2766	__le16	target_id;2767	__le64	resp_addr;2768};2769 2770/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */2771struct hwrm_func_backing_store_qcaps_output {2772	__le16	error_code;2773	__le16	req_type;2774	__le16	seq_id;2775	__le16	resp_len;2776	__le32	qp_max_entries;2777	__le16	qp_min_qp1_entries;2778	__le16	qp_max_l2_entries;2779	__le16	qp_entry_size;2780	__le16	srq_max_l2_entries;2781	__le32	srq_max_entries;2782	__le16	srq_entry_size;2783	__le16	cq_max_l2_entries;2784	__le32	cq_max_entries;2785	__le16	cq_entry_size;2786	__le16	vnic_max_vnic_entries;2787	__le16	vnic_max_ring_table_entries;2788	__le16	vnic_entry_size;2789	__le32	stat_max_entries;2790	__le16	stat_entry_size;2791	__le16	tqm_entry_size;2792	__le32	tqm_min_entries_per_ring;2793	__le32	tqm_max_entries_per_ring;2794	__le32	mrav_max_entries;2795	__le16	mrav_entry_size;2796	__le16	tim_entry_size;2797	__le32	tim_max_entries;2798	__le16	mrav_num_entries_units;2799	u8	tqm_entries_multiple;2800	u8	ctx_kind_initializer;2801	__le16	ctx_init_mask;2802	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP       0x1UL2803	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ      0x2UL2804	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ       0x4UL2805	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC     0x8UL2806	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT     0x10UL2807	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV     0x20UL2808	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC      0x40UL2809	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC      0x80UL2810	u8	qp_init_offset;2811	u8	srq_init_offset;2812	u8	cq_init_offset;2813	u8	vnic_init_offset;2814	u8	tqm_fp_rings_count;2815	u8	stat_init_offset;2816	u8	mrav_init_offset;2817	u8	tqm_fp_rings_count_ext;2818	u8	tkc_init_offset;2819	u8	rkc_init_offset;2820	__le16	tkc_entry_size;2821	__le16	rkc_entry_size;2822	__le32	tkc_max_entries;2823	__le32	rkc_max_entries;2824	__le16	fast_qpmd_qp_num_entries;2825	u8	rsvd1[5];2826	u8	valid;2827};2828 2829/* tqm_fp_ring_cfg (size:128b/16B) */2830struct tqm_fp_ring_cfg {2831	u8	tqm_ring_pg_size_tqm_ring_lvl;2832	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK      0xfUL2833	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT       02834	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0       0x0UL2835	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1       0x1UL2836	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2       0x2UL2837	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST       TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_22838	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK  0xf0UL2839	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT   42840	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)2841	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)2842	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)2843	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)2844	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)2845	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)2846	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST   TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G2847	u8	unused[3];2848	__le32	tqm_ring_num_entries;2849	__le64	tqm_ring_page_dir;2850};2851 2852/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */2853struct hwrm_func_backing_store_cfg_input {2854	__le16	req_type;2855	__le16	cmpl_ring;2856	__le16	seq_id;2857	__le16	target_id;2858	__le64	resp_addr;2859	__le32	flags;2860	#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE               0x1UL2861	#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT     0x2UL2862	__le32	enables;2863	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP               0x1UL2864	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ              0x2UL2865	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ               0x4UL2866	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC             0x8UL2867	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT             0x10UL2868	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP           0x20UL2869	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0        0x40UL2870	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1        0x80UL2871	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2        0x100UL2872	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3        0x200UL2873	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4        0x400UL2874	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5        0x800UL2875	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6        0x1000UL2876	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7        0x2000UL2877	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV             0x4000UL2878	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM              0x8000UL2879	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8        0x10000UL2880	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9        0x20000UL2881	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10       0x40000UL2882	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC              0x80000UL2883	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC              0x100000UL2884	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD     0x200000UL2885	u8	qpc_pg_size_qpc_lvl;2886	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK      0xfUL2887	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT       02888	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0       0x0UL2889	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1       0x1UL2890	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2       0x2UL2891	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_22892	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK  0xf0UL2893	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT   42894	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K   (0x0UL << 4)2895	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K   (0x1UL << 4)2896	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K  (0x2UL << 4)2897	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M   (0x3UL << 4)2898	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M   (0x4UL << 4)2899	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G   (0x5UL << 4)2900	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G2901	u8	srq_pg_size_srq_lvl;2902	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK      0xfUL2903	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT       02904	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0       0x0UL2905	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1       0x1UL2906	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2       0x2UL2907	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_22908	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK  0xf0UL2909	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT   42910	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)2911	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)2912	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)2913	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)2914	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)2915	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)2916	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G2917	u8	cq_pg_size_cq_lvl;2918	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK      0xfUL2919	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT       02920	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0       0x0UL2921	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1       0x1UL2922	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2       0x2UL2923	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_22924	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK  0xf0UL2925	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT   42926	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K   (0x0UL << 4)2927	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K   (0x1UL << 4)2928	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K  (0x2UL << 4)2929	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M   (0x3UL << 4)2930	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M   (0x4UL << 4)2931	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G   (0x5UL << 4)2932	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G2933	u8	vnic_pg_size_vnic_lvl;2934	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK      0xfUL2935	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT       02936	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0       0x0UL2937	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1       0x1UL2938	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2       0x2UL2939	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_22940	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK  0xf0UL2941	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT   42942	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)2943	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)2944	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)2945	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)2946	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)2947	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)2948	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G2949	u8	stat_pg_size_stat_lvl;2950	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK      0xfUL2951	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT       02952	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0       0x0UL2953	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1       0x1UL2954	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2       0x2UL2955	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_22956	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK  0xf0UL2957	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT   42958	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K   (0x0UL << 4)2959	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K   (0x1UL << 4)2960	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K  (0x2UL << 4)2961	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M   (0x3UL << 4)2962	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M   (0x4UL << 4)2963	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G   (0x5UL << 4)2964	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G2965	u8	tqm_sp_pg_size_tqm_sp_lvl;2966	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK      0xfUL2967	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT       02968	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0       0x0UL2969	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1       0x1UL2970	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2       0x2UL2971	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_22972	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK  0xf0UL2973	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT   42974	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)2975	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)2976	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)2977	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)2978	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)2979	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)2980	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G2981	u8	tqm_ring0_pg_size_tqm_ring0_lvl;2982	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK      0xfUL2983	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT       02984	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0       0x0UL2985	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1       0x1UL2986	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2       0x2UL2987	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_22988	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK  0xf0UL2989	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT   42990	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)2991	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)2992	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)2993	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)2994	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)2995	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)2996	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G2997	u8	tqm_ring1_pg_size_tqm_ring1_lvl;2998	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK      0xfUL2999	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT       03000	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0       0x0UL3001	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1       0x1UL3002	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2       0x2UL3003	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_23004	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK  0xf0UL3005	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT   43006	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)3007	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)3008	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)3009	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)3010	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)3011	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)3012	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G3013	u8	tqm_ring2_pg_size_tqm_ring2_lvl;3014	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK      0xfUL3015	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT       03016	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0       0x0UL3017	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1       0x1UL3018	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2       0x2UL3019	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_23020	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK  0xf0UL3021	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT   43022	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)3023	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)3024	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)3025	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)3026	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)3027	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)3028	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G3029	u8	tqm_ring3_pg_size_tqm_ring3_lvl;3030	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK      0xfUL3031	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT       03032	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0       0x0UL3033	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1       0x1UL3034	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2       0x2UL3035	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_23036	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK  0xf0UL3037	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT   43038	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)3039	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)3040	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)3041	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)3042	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)3043	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)3044	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G3045	u8	tqm_ring4_pg_size_tqm_ring4_lvl;3046	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK      0xfUL3047	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT       03048	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0       0x0UL3049	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1       0x1UL3050	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2       0x2UL3051	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_23052	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK  0xf0UL3053	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT   43054	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)3055	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)3056	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)3057	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)3058	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)3059	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)3060	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G3061	u8	tqm_ring5_pg_size_tqm_ring5_lvl;3062	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK      0xfUL3063	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT       03064	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0       0x0UL3065	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1       0x1UL3066	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2       0x2UL3067	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_23068	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK  0xf0UL3069	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT   43070	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)3071	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)3072	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)3073	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)3074	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)3075	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)3076	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G3077	u8	tqm_ring6_pg_size_tqm_ring6_lvl;3078	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK      0xfUL3079	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT       03080	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0       0x0UL3081	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1       0x1UL3082	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2       0x2UL3083	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_23084	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK  0xf0UL3085	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT   43086	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)3087	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)3088	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)3089	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)3090	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)3091	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)3092	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G3093	u8	tqm_ring7_pg_size_tqm_ring7_lvl;3094	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK      0xfUL3095	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT       03096	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0       0x0UL3097	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1       0x1UL3098	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2       0x2UL3099	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_23100	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK  0xf0UL3101	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT   43102	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)3103	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)3104	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)3105	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)3106	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)3107	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)3108	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G3109	u8	mrav_pg_size_mrav_lvl;3110	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK      0xfUL3111	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT       03112	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0       0x0UL3113	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1       0x1UL3114	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2       0x2UL3115	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_23116	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK  0xf0UL3117	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT   43118	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)3119	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)3120	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)3121	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)3122	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)3123	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)3124	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G3125	u8	tim_pg_size_tim_lvl;3126	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK      0xfUL3127	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT       03128	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0       0x0UL3129	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1       0x1UL3130	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2       0x2UL3131	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_23132	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK  0xf0UL3133	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT   43134	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K   (0x0UL << 4)3135	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K   (0x1UL << 4)3136	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K  (0x2UL << 4)3137	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M   (0x3UL << 4)3138	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M   (0x4UL << 4)3139	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G   (0x5UL << 4)3140	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G3141	__le64	qpc_page_dir;3142	__le64	srq_page_dir;3143	__le64	cq_page_dir;3144	__le64	vnic_page_dir;3145	__le64	stat_page_dir;3146	__le64	tqm_sp_page_dir;3147	__le64	tqm_ring0_page_dir;3148	__le64	tqm_ring1_page_dir;3149	__le64	tqm_ring2_page_dir;3150	__le64	tqm_ring3_page_dir;3151	__le64	tqm_ring4_page_dir;3152	__le64	tqm_ring5_page_dir;3153	__le64	tqm_ring6_page_dir;3154	__le64	tqm_ring7_page_dir;3155	__le64	mrav_page_dir;3156	__le64	tim_page_dir;3157	__le32	qp_num_entries;3158	__le32	srq_num_entries;3159	__le32	cq_num_entries;3160	__le32	stat_num_entries;3161	__le32	tqm_sp_num_entries;3162	__le32	tqm_ring0_num_entries;3163	__le32	tqm_ring1_num_entries;3164	__le32	tqm_ring2_num_entries;3165	__le32	tqm_ring3_num_entries;3166	__le32	tqm_ring4_num_entries;3167	__le32	tqm_ring5_num_entries;3168	__le32	tqm_ring6_num_entries;3169	__le32	tqm_ring7_num_entries;3170	__le32	mrav_num_entries;3171	__le32	tim_num_entries;3172	__le16	qp_num_qp1_entries;3173	__le16	qp_num_l2_entries;3174	__le16	qp_entry_size;3175	__le16	srq_num_l2_entries;3176	__le16	srq_entry_size;3177	__le16	cq_num_l2_entries;3178	__le16	cq_entry_size;3179	__le16	vnic_num_vnic_entries;3180	__le16	vnic_num_ring_table_entries;3181	__le16	vnic_entry_size;3182	__le16	stat_entry_size;3183	__le16	tqm_entry_size;3184	__le16	mrav_entry_size;3185	__le16	tim_entry_size;3186	u8	tqm_ring8_pg_size_tqm_ring_lvl;3187	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK      0xfUL3188	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT       03189	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0       0x0UL3190	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1       0x1UL3191	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2       0x2UL3192	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_23193	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK  0xf0UL3194	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT   43195	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)3196	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)3197	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)3198	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)3199	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)3200	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)3201	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G3202	u8	ring8_unused[3];3203	__le32	tqm_ring8_num_entries;3204	__le64	tqm_ring8_page_dir;3205	u8	tqm_ring9_pg_size_tqm_ring_lvl;3206	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK      0xfUL3207	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT       03208	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0       0x0UL3209	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1       0x1UL3210	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2       0x2UL3211	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_23212	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK  0xf0UL3213	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT   43214	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)3215	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)3216	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)3217	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)3218	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)3219	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)3220	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G3221	u8	ring9_unused[3];3222	__le32	tqm_ring9_num_entries;3223	__le64	tqm_ring9_page_dir;3224	u8	tqm_ring10_pg_size_tqm_ring_lvl;3225	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK      0xfUL3226	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT       03227	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0       0x0UL3228	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1       0x1UL3229	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2       0x2UL3230	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_23231	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK  0xf0UL3232	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT   43233	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)3234	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)3235	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)3236	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)3237	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)3238	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)3239	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G3240	u8	ring10_unused[3];3241	__le32	tqm_ring10_num_entries;3242	__le64	tqm_ring10_page_dir;3243	__le32	tkc_num_entries;3244	__le32	rkc_num_entries;3245	__le64	tkc_page_dir;3246	__le64	rkc_page_dir;3247	__le16	tkc_entry_size;3248	__le16	rkc_entry_size;3249	u8	tkc_pg_size_tkc_lvl;3250	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK      0xfUL3251	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT       03252	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0       0x0UL3253	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1       0x1UL3254	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2       0x2UL3255	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_23256	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK  0xf0UL3257	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT   43258	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K   (0x0UL << 4)3259	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K   (0x1UL << 4)3260	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K  (0x2UL << 4)3261	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M   (0x3UL << 4)3262	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M   (0x4UL << 4)3263	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G   (0x5UL << 4)3264	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G3265	u8	rkc_pg_size_rkc_lvl;3266	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK      0xfUL3267	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT       03268	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0       0x0UL3269	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1       0x1UL3270	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2       0x2UL3271	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_23272	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK  0xf0UL3273	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT   43274	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K   (0x0UL << 4)3275	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K   (0x1UL << 4)3276	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K  (0x2UL << 4)3277	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M   (0x3UL << 4)3278	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M   (0x4UL << 4)3279	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G   (0x5UL << 4)3280	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G3281	__le16	qp_num_fast_qpmd_entries;3282};3283 3284/* hwrm_func_backing_store_cfg_output (size:128b/16B) */3285struct hwrm_func_backing_store_cfg_output {3286	__le16	error_code;3287	__le16	req_type;3288	__le16	seq_id;3289	__le16	resp_len;3290	u8	unused_0[7];3291	u8	valid;3292};3293 3294/* hwrm_error_recovery_qcfg_input (size:192b/24B) */3295struct hwrm_error_recovery_qcfg_input {3296	__le16	req_type;3297	__le16	cmpl_ring;3298	__le16	seq_id;3299	__le16	target_id;3300	__le64	resp_addr;3301	u8	unused_0[8];3302};3303 3304/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */3305struct hwrm_error_recovery_qcfg_output {3306	__le16	error_code;3307	__le16	req_type;3308	__le16	seq_id;3309	__le16	resp_len;3310	__le32	flags;3311	#define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST       0x1UL3312	#define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU     0x2UL3313	__le32	driver_polling_freq;3314	__le32	master_func_wait_period;3315	__le32	normal_func_wait_period;3316	__le32	master_func_wait_period_after_reset;3317	__le32	max_bailout_time_after_reset;3318	__le32	fw_health_status_reg;3319	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK    0x3UL3320	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT     03321	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG  0x0UL3322	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC       0x1UL3323	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0      0x2UL3324	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1      0x3UL3325	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR13326	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK          0xfffffffcUL3327	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT           23328	__le32	fw_heartbeat_reg;3329	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK    0x3UL3330	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT     03331	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG  0x0UL3332	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC       0x1UL3333	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0      0x2UL3334	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1      0x3UL3335	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR13336	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK          0xfffffffcUL3337	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT           23338	__le32	fw_reset_cnt_reg;3339	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK    0x3UL3340	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT     03341	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL3342	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC       0x1UL3343	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0      0x2UL3344	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1      0x3UL3345	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR13346	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK          0xfffffffcUL3347	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT           23348	__le32	reset_inprogress_reg;3349	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK    0x3UL3350	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT     03351	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG  0x0UL3352	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC       0x1UL3353	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0      0x2UL3354	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1      0x3UL3355	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR13356	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK          0xfffffffcUL3357	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT           23358	__le32	reset_inprogress_reg_mask;3359	u8	unused_0[3];3360	u8	reg_array_cnt;3361	__le32	reset_reg[16];3362	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK    0x3UL3363	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT     03364	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG  0x0UL3365	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC       0x1UL3366	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0      0x2UL3367	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1      0x3UL3368	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR13369	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK          0xfffffffcUL3370	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT           23371	__le32	reset_reg_val[16];3372	u8	delay_after_reset[16];3373	__le32	err_recovery_cnt_reg;3374	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK    0x3UL3375	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT     03376	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL3377	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC       0x1UL3378	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0      0x2UL3379	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1      0x3UL3380	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR13381	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK          0xfffffffcUL3382	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT           23383	u8	unused_1[3];3384	u8	valid;3385};3386 3387/* hwrm_func_echo_response_input (size:192b/24B) */3388struct hwrm_func_echo_response_input {3389	__le16	req_type;3390	__le16	cmpl_ring;3391	__le16	seq_id;3392	__le16	target_id;3393	__le64	resp_addr;3394	__le32	event_data1;3395	__le32	event_data2;3396};3397 3398/* hwrm_func_echo_response_output (size:128b/16B) */3399struct hwrm_func_echo_response_output {3400	__le16	error_code;3401	__le16	req_type;3402	__le16	seq_id;3403	__le16	resp_len;3404	u8	unused_0[7];3405	u8	valid;3406};3407 3408/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */3409struct hwrm_func_ptp_pin_qcfg_input {3410	__le16	req_type;3411	__le16	cmpl_ring;3412	__le16	seq_id;3413	__le16	target_id;3414	__le64	resp_addr;3415	u8	unused_0[8];3416};3417 3418/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */3419struct hwrm_func_ptp_pin_qcfg_output {3420	__le16	error_code;3421	__le16	req_type;3422	__le16	seq_id;3423	__le16	resp_len;3424	u8	num_pins;3425	u8	state;3426	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED     0x1UL3427	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED     0x2UL3428	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED     0x4UL3429	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED     0x8UL3430	u8	pin0_usage;3431	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE     0x0UL3432	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN   0x1UL3433	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT  0x2UL3434	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN  0x3UL3435	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL3436	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT3437	u8	pin1_usage;3438	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE     0x0UL3439	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN   0x1UL3440	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT  0x2UL3441	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN  0x3UL3442	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL3443	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT3444	u8	pin2_usage;3445	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE                      0x0UL3446	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN                    0x1UL3447	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT                   0x2UL3448	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN                   0x3UL3449	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT                  0x4UL3450	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL3451	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL3452	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST                     FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT3453	u8	pin3_usage;3454	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE                      0x0UL3455	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN                    0x1UL3456	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT                   0x2UL3457	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN                   0x3UL3458	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT                  0x4UL3459	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL3460	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL3461	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST                     FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT3462	u8	unused_0;3463	u8	valid;3464};3465 3466/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */3467struct hwrm_func_ptp_pin_cfg_input {3468	__le16	req_type;3469	__le16	cmpl_ring;3470	__le16	seq_id;3471	__le16	target_id;3472	__le64	resp_addr;3473	__le32	enables;3474	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE     0x1UL3475	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE     0x2UL3476	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE     0x4UL3477	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE     0x8UL3478	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE     0x10UL3479	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE     0x20UL3480	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE     0x40UL3481	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE     0x80UL3482	u8	pin0_state;3483	#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL3484	#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED  0x1UL3485	#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED3486	u8	pin0_usage;3487	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE     0x0UL3488	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN   0x1UL3489	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT  0x2UL3490	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN  0x3UL3491	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL3492	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT3493	u8	pin1_state;3494	#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL3495	#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED  0x1UL3496	#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED3497	u8	pin1_usage;3498	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE     0x0UL3499	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN   0x1UL3500	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT  0x2UL3501	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN  0x3UL3502	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL3503	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT3504	u8	pin2_state;3505	#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL3506	#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED  0x1UL3507	#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED3508	u8	pin2_usage;3509	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE                      0x0UL3510	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN                    0x1UL3511	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT                   0x2UL3512	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN                   0x3UL3513	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT                  0x4UL3514	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL3515	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL3516	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST                     FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT3517	u8	pin3_state;3518	#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL3519	#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED  0x1UL3520	#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED3521	u8	pin3_usage;3522	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE                      0x0UL3523	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN                    0x1UL3524	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT                   0x2UL3525	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN                   0x3UL3526	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT                  0x4UL3527	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL3528	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL3529	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST                     FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT3530	u8	unused_0[4];3531};3532 3533/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */3534struct hwrm_func_ptp_pin_cfg_output {3535	__le16	error_code;3536	__le16	req_type;3537	__le16	seq_id;3538	__le16	resp_len;3539	u8	unused_0[7];3540	u8	valid;3541};3542 3543/* hwrm_func_ptp_cfg_input (size:384b/48B) */3544struct hwrm_func_ptp_cfg_input {3545	__le16	req_type;3546	__le16	cmpl_ring;3547	__le16	seq_id;3548	__le16	target_id;3549	__le64	resp_addr;3550	__le16	enables;3551	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT               0x1UL3552	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE     0x2UL3553	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE      0x4UL3554	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD     0x8UL3555	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP         0x10UL3556	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE      0x20UL3557	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME                0x40UL3558	u8	ptp_pps_event;3559	#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL     0x1UL3560	#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL     0x2UL3561	u8	ptp_freq_adj_dll_source;3562	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE    0x0UL3563	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0  0x1UL3564	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1  0x2UL3565	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2  0x3UL3566	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3  0x4UL3567	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0  0x5UL3568	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1  0x6UL3569	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2  0x7UL3570	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3  0x8UL3571	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL3572	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST   FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID3573	u8	ptp_freq_adj_dll_phase;3574	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL3575	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K   0x1UL3576	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K   0x2UL3577	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M  0x3UL3578	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M  0x4UL3579	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M3580	u8	unused_0[3];3581	__le32	ptp_freq_adj_ext_period;3582	__le32	ptp_freq_adj_ext_up;3583	__le32	ptp_freq_adj_ext_phase_lower;3584	__le32	ptp_freq_adj_ext_phase_upper;3585	__le64	ptp_set_time;3586};3587 3588/* hwrm_func_ptp_cfg_output (size:128b/16B) */3589struct hwrm_func_ptp_cfg_output {3590	__le16	error_code;3591	__le16	req_type;3592	__le16	seq_id;3593	__le16	resp_len;3594	u8	unused_0[7];3595	u8	valid;3596};3597 3598/* hwrm_func_ptp_ts_query_input (size:192b/24B) */3599struct hwrm_func_ptp_ts_query_input {3600	__le16	req_type;3601	__le16	cmpl_ring;3602	__le16	seq_id;3603	__le16	target_id;3604	__le64	resp_addr;3605	__le32	flags;3606	#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME     0x1UL3607	#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME     0x2UL3608	u8	unused_0[4];3609};3610 3611/* hwrm_func_ptp_ts_query_output (size:320b/40B) */3612struct hwrm_func_ptp_ts_query_output {3613	__le16	error_code;3614	__le16	req_type;3615	__le16	seq_id;3616	__le16	resp_len;3617	__le64	pps_event_ts;3618	__le64	ptm_local_ts;3619	__le64	ptm_system_ts;3620	__le32	ptm_link_delay;3621	u8	unused_0[3];3622	u8	valid;3623};3624 3625/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */3626struct hwrm_func_ptp_ext_cfg_input {3627	__le16	req_type;3628	__le16	cmpl_ring;3629	__le16	seq_id;3630	__le16	target_id;3631	__le64	resp_addr;3632	__le16	enables;3633	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID     0x1UL3634	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID        0x2UL3635	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE       0x4UL3636	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER     0x8UL3637	__le16	phc_master_fid;3638	__le16	phc_sec_fid;3639	u8	phc_sec_mode;3640	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH  0x0UL3641	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL     0x1UL3642	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL3643	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST   FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY3644	u8	unused_0;3645	__le32	failover_timer;3646	u8	unused_1[4];3647};3648 3649/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */3650struct hwrm_func_ptp_ext_cfg_output {3651	__le16	error_code;3652	__le16	req_type;3653	__le16	seq_id;3654	__le16	resp_len;3655	u8	unused_0[7];3656	u8	valid;3657};3658 3659/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */3660struct hwrm_func_ptp_ext_qcfg_input {3661	__le16	req_type;3662	__le16	cmpl_ring;3663	__le16	seq_id;3664	__le16	target_id;3665	__le64	resp_addr;3666	u8	unused_0[8];3667};3668 3669/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */3670struct hwrm_func_ptp_ext_qcfg_output {3671	__le16	error_code;3672	__le16	req_type;3673	__le16	seq_id;3674	__le16	resp_len;3675	__le16	phc_master_fid;3676	__le16	phc_sec_fid;3677	__le16	phc_active_fid0;3678	__le16	phc_active_fid1;3679	__le32	last_failover_event;3680	__le16	from_fid;3681	__le16	to_fid;3682	u8	unused_0[7];3683	u8	valid;3684};3685 3686/* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */3687struct hwrm_func_backing_store_cfg_v2_input {3688	__le16	req_type;3689	__le16	cmpl_ring;3690	__le16	seq_id;3691	__le16	target_id;3692	__le64	resp_addr;3693	__le16	type;3694	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP                  0x0UL3695	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ                 0x1UL3696	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ                  0x2UL3697	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC                0x3UL3698	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT                0x4UL3699	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING         0x5UL3700	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING         0x6UL3701	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV                0xeUL3702	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM                 0xfUL3703	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK               0x13UL3704	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK               0x14UL3705	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING         0x15UL3706	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW        0x16UL3707	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW        0x17UL3708	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW       0x18UL3709	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW        0x19UL3710	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE           0x1cUL3711	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION       0x1dUL3712	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE           0x1eUL3713	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE          0x1fUL3714	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE           0x20UL3715	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE          0x21UL3716	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE         0x22UL3717	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE       0x23UL3718	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE     0x24UL3719	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL3720	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA0_TRACE           0x26UL3721	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE           0x27UL3722	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE           0x28UL3723	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE         0x29UL3724	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID             0xffffUL3725	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST               FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID3726	__le16	instance;3727	__le32	flags;3728	#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE        0x1UL3729	#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE     0x2UL3730	#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND           0x4UL3731	__le64	page_dir;3732	__le32	num_entries;3733	__le16	entry_size;3734	u8	page_size_pbl_level;3735	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK  0xfUL3736	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT   03737	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0   0x0UL3738	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1   0x1UL3739	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2   0x2UL3740	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST   FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_23741	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK  0xf0UL3742	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT   43743	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K   (0x0UL << 4)3744	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K   (0x1UL << 4)3745	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K  (0x2UL << 4)3746	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M   (0x3UL << 4)3747	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M   (0x4UL << 4)3748	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G   (0x5UL << 4)3749	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST   FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G3750	u8	subtype_valid_cnt;3751	__le32	split_entry_0;3752	__le32	split_entry_1;3753	__le32	split_entry_2;3754	__le32	split_entry_3;3755};3756 3757/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */3758struct hwrm_func_backing_store_cfg_v2_output {3759	__le16	error_code;3760	__le16	req_type;3761	__le16	seq_id;3762	__le16	resp_len;3763	u8	rsvd0[7];3764	u8	valid;3765};3766 3767/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */3768struct hwrm_func_backing_store_qcfg_v2_input {3769	__le16	req_type;3770	__le16	cmpl_ring;3771	__le16	seq_id;3772	__le16	target_id;3773	__le64	resp_addr;3774	__le16	type;3775	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP                  0x0UL3776	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ                 0x1UL3777	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ                  0x2UL3778	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC                0x3UL3779	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT                0x4UL3780	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING         0x5UL3781	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING         0x6UL3782	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV                0xeUL3783	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM                 0xfUL3784	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK               0x13UL3785	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK               0x14UL3786	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING         0x15UL3787	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW        0x16UL3788	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW        0x17UL3789	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW       0x18UL3790	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW        0x19UL3791	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE           0x1cUL3792	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL3793	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE           0x1eUL3794	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE          0x1fUL3795	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE           0x20UL3796	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE          0x21UL3797	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE         0x22UL3798	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE       0x23UL3799	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE     0x24UL3800	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL3801	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA0_TRACE           0x26UL3802	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE           0x27UL3803	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE           0x28UL3804	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE         0x29UL3805	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID             0xffffUL3806	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST               FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID3807	__le16	instance;3808	u8	rsvd[4];3809};3810 3811/* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */3812struct hwrm_func_backing_store_qcfg_v2_output {3813	__le16	error_code;3814	__le16	req_type;3815	__le16	seq_id;3816	__le16	resp_len;3817	__le16	type;3818	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP                  0x0UL3819	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ                 0x1UL3820	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ                  0x2UL3821	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC                0x3UL3822	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT                0x4UL3823	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING         0x5UL3824	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING         0x6UL3825	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV                0xeUL3826	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM                 0xfUL3827	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK               0x13UL3828	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK               0x14UL3829	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING         0x15UL3830	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE           0x1cUL3831	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION       0x1dUL3832	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE           0x1eUL3833	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE          0x1fUL3834	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE           0x20UL3835	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE          0x21UL3836	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE         0x22UL3837	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE       0x23UL3838	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE     0x24UL3839	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL3840	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA0_TRACE           0x26UL3841	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA1_TRACE           0x27UL3842	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA2_TRACE           0x28UL3843	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP1_TRACE         0x29UL3844	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID             0xffffUL3845	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST               FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID3846	__le16	instance;3847	__le32	flags;3848	__le64	page_dir;3849	__le32	num_entries;3850	u8	page_size_pbl_level;3851	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK  0xfUL3852	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT   03853	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0   0x0UL3854	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1   0x1UL3855	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2   0x2UL3856	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST   FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_23857	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK  0xf0UL3858	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT   43859	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K   (0x0UL << 4)3860	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K   (0x1UL << 4)3861	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K  (0x2UL << 4)3862	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M   (0x3UL << 4)3863	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M   (0x4UL << 4)3864	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G   (0x5UL << 4)3865	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST   FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G3866	u8	subtype_valid_cnt;3867	u8	rsvd[2];3868	__le32	split_entry_0;3869	__le32	split_entry_1;3870	__le32	split_entry_2;3871	__le32	split_entry_3;3872	u8	rsvd2[7];3873	u8	valid;3874};3875 3876/* qpc_split_entries (size:128b/16B) */3877struct qpc_split_entries {3878	__le32	qp_num_l2_entries;3879	__le32	qp_num_qp1_entries;3880	__le32	qp_num_fast_qpmd_entries;3881	__le32	rsvd;3882};3883 3884/* srq_split_entries (size:128b/16B) */3885struct srq_split_entries {3886	__le32	srq_num_l2_entries;3887	__le32	rsvd;3888	__le32	rsvd2[2];3889};3890 3891/* cq_split_entries (size:128b/16B) */3892struct cq_split_entries {3893	__le32	cq_num_l2_entries;3894	__le32	rsvd;3895	__le32	rsvd2[2];3896};3897 3898/* vnic_split_entries (size:128b/16B) */3899struct vnic_split_entries {3900	__le32	vnic_num_vnic_entries;3901	__le32	rsvd;3902	__le32	rsvd2[2];3903};3904 3905/* mrav_split_entries (size:128b/16B) */3906struct mrav_split_entries {3907	__le32	mrav_num_av_entries;3908	__le32	rsvd;3909	__le32	rsvd2[2];3910};3911 3912/* ts_split_entries (size:128b/16B) */3913struct ts_split_entries {3914	__le32	region_num_entries;3915	u8	tsid;3916	u8	lkup_static_bkt_cnt_exp[2];3917	u8	rsvd;3918	__le32	rsvd2[2];3919};3920 3921/* ck_split_entries (size:128b/16B) */3922struct ck_split_entries {3923	__le32	num_quic_entries;3924	__le32	rsvd;3925	__le32	rsvd2[2];3926};3927 3928/* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */3929struct hwrm_func_backing_store_qcaps_v2_input {3930	__le16	req_type;3931	__le16	cmpl_ring;3932	__le16	seq_id;3933	__le16	target_id;3934	__le64	resp_addr;3935	__le16	type;3936	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP                  0x0UL3937	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ                 0x1UL3938	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ                  0x2UL3939	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC                0x3UL3940	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT                0x4UL3941	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING         0x5UL3942	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING         0x6UL3943	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV                0xeUL3944	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM                 0xfUL3945	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK               0x13UL3946	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK               0x14UL3947	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING         0x15UL3948	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW        0x16UL3949	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW        0x17UL3950	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW       0x18UL3951	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW        0x19UL3952	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE           0x1cUL3953	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION       0x1dUL3954	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE           0x1eUL3955	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE          0x1fUL3956	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE           0x20UL3957	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE          0x21UL3958	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE         0x22UL3959	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE       0x23UL3960	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE     0x24UL3961	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL3962	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE           0x26UL3963	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE           0x27UL3964	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE           0x28UL3965	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE         0x29UL3966	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID             0xffffUL3967	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST               FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID3968	u8	rsvd[6];3969};3970 3971/* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */3972struct hwrm_func_backing_store_qcaps_v2_output {3973	__le16	error_code;3974	__le16	req_type;3975	__le16	seq_id;3976	__le16	resp_len;3977	__le16	type;3978	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP                  0x0UL3979	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ                 0x1UL3980	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ                  0x2UL3981	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC                0x3UL3982	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT                0x4UL3983	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING         0x5UL3984	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING         0x6UL3985	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV                0xeUL3986	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM                 0xfUL3987	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK               0x13UL3988	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK               0x14UL3989	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING         0x15UL3990	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW        0x16UL3991	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW        0x17UL3992	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW       0x18UL3993	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW        0x19UL3994	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE           0x1cUL3995	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION       0x1dUL3996	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE           0x1eUL3997	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE          0x1fUL3998	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE           0x20UL3999	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE          0x21UL4000	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE         0x22UL4001	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE       0x23UL4002	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE     0x24UL4003	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL4004	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA0_TRACE           0x26UL4005	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE           0x27UL4006	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE           0x28UL4007	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE         0x29UL4008	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID             0xffffUL4009	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST               FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID4010	__le16	entry_size;4011	__le32	flags;4012	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT            0x1UL4013	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID                      0x2UL4014	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY           0x4UL4015	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC     0x8UL4016	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE                    0x10UL4017	__le32	instance_bit_map;4018	u8	ctx_init_value;4019	u8	ctx_init_offset;4020	u8	entry_multiple;4021	u8	rsvd;4022	__le32	max_num_entries;4023	__le32	min_num_entries;4024	__le16	next_valid_type;4025	u8	subtype_valid_cnt;4026	u8	exact_cnt_bit_map;4027	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT     0x1UL4028	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT     0x2UL4029	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT     0x4UL4030	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT     0x8UL4031	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK             0xf0UL4032	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT              44033	__le32	split_entry_0;4034	__le32	split_entry_1;4035	__le32	split_entry_2;4036	__le32	split_entry_3;4037	u8	rsvd3[3];4038	u8	valid;4039};4040 4041/* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */4042struct hwrm_func_dbr_pacing_qcfg_input {4043	__le16	req_type;4044	__le16	cmpl_ring;4045	__le16	seq_id;4046	__le16	target_id;4047	__le64	resp_addr;4048};4049 4050/* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */4051struct hwrm_func_dbr_pacing_qcfg_output {4052	__le16	error_code;4053	__le16	req_type;4054	__le16	seq_id;4055	__le16	resp_len;4056	u8	flags;4057	#define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED     0x1UL4058	u8	unused_0[7];4059	__le32	dbr_stat_db_fifo_reg;4060	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK    0x3UL4061	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT     04062	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG  0x0UL4063	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC       0x1UL4064	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0      0x2UL4065	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1      0x3UL4066	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST     FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR14067	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK          0xfffffffcUL4068	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT           24069	__le32	dbr_stat_db_fifo_reg_watermark_mask;4070	u8	dbr_stat_db_fifo_reg_watermark_shift;4071	u8	unused_1[3];4072	__le32	dbr_stat_db_fifo_reg_fifo_room_mask;4073	u8	dbr_stat_db_fifo_reg_fifo_room_shift;4074	u8	unused_2[3];4075	__le32	dbr_throttling_aeq_arm_reg;4076	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK    0x3UL4077	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT     04078	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG  0x0UL4079	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC       0x1UL4080	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0      0x2UL4081	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1      0x3UL4082	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST     FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR14083	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK          0xfffffffcUL4084	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT           24085	u8	dbr_throttling_aeq_arm_reg_val;4086	u8	unused_3[3];4087	__le32	dbr_stat_db_max_fifo_depth;4088	__le32	primary_nq_id;4089	__le32	pacing_threshold;4090	u8	unused_4[7];4091	u8	valid;4092};4093 4094/* hwrm_func_drv_if_change_input (size:192b/24B) */4095struct hwrm_func_drv_if_change_input {4096	__le16	req_type;4097	__le16	cmpl_ring;4098	__le16	seq_id;4099	__le16	target_id;4100	__le64	resp_addr;4101	__le32	flags;4102	#define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP     0x1UL4103	__le32	unused;4104};4105 4106/* hwrm_func_drv_if_change_output (size:128b/16B) */4107struct hwrm_func_drv_if_change_output {4108	__le16	error_code;4109	__le16	req_type;4110	__le16	seq_id;4111	__le16	resp_len;4112	__le32	flags;4113	#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE           0x1UL4114	#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE     0x2UL4115	#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE           0x4UL4116	u8	unused_0[3];4117	u8	valid;4118};4119 4120/* hwrm_port_phy_cfg_input (size:512b/64B) */4121struct hwrm_port_phy_cfg_input {4122	__le16	req_type;4123	__le16	cmpl_ring;4124	__le16	seq_id;4125	__le16	target_id;4126	__le64	resp_addr;4127	__le32	flags;4128	#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY                  0x1UL4129	#define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED                 0x2UL4130	#define PORT_PHY_CFG_REQ_FLAGS_FORCE                      0x4UL4131	#define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG            0x8UL4132	#define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE                 0x10UL4133	#define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE                0x20UL4134	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE          0x40UL4135	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE         0x80UL4136	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE         0x100UL4137	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE        0x200UL4138	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE        0x400UL4139	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE       0x800UL4140	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE        0x1000UL4141	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE       0x2000UL4142	#define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN             0x4000UL4143	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE       0x8000UL4144	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE      0x10000UL4145	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE      0x20000UL4146	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE     0x40000UL4147	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE       0x80000UL4148	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE      0x100000UL4149	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE      0x200000UL4150	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE     0x400000UL4151	__le32	enables;4152	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE                     0x1UL4153	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX                   0x2UL4154	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE                    0x4UL4155	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED               0x8UL4156	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK          0x10UL4157	#define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED                     0x20UL4158	#define PORT_PHY_CFG_REQ_ENABLES_LPBK                          0x40UL4159	#define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS                   0x80UL4160	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE                   0x100UL4161	#define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK           0x200UL4162	#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER                  0x400UL4163	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED         0x800UL4164	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK     0x1000UL4165	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2            0x2000UL4166	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK        0x4000UL4167	__le16	port_id;4168	__le16	force_link_speed;4169	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL4170	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB   0xaUL4171	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB   0x14UL4172	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL4173	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB  0x64UL4174	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB  0xc8UL4175	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB  0xfaUL4176	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB  0x190UL4177	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB  0x1f4UL4178	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL4179	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB  0xffffUL4180	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB4181	u8	auto_mode;4182	#define PORT_PHY_CFG_REQ_AUTO_MODE_NONE         0x0UL4183	#define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS   0x1UL4184	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED    0x2UL4185	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL4186	#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK   0x4UL4187	#define PORT_PHY_CFG_REQ_AUTO_MODE_LAST        PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK4188	u8	auto_duplex;4189	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL4190	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL4191	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL4192	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH4193	u8	auto_pause;4194	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX                0x1UL4195	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX                0x2UL4196	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL4197	u8	mgmt_flag;4198	#define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE     0x1UL4199	#define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID       0x80UL4200	__le16	auto_link_speed;4201	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL4202	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL4203	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB   0x14UL4204	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL4205	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB  0x64UL4206	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB  0xc8UL4207	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB  0xfaUL4208	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB  0x190UL4209	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB  0x1f4UL4210	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL4211	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB  0xffffUL4212	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB4213	__le16	auto_link_speed_mask;4214	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL4215	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB       0x2UL4216	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL4217	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB         0x8UL4218	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB         0x10UL4219	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL4220	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB        0x40UL4221	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB        0x80UL4222	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB        0x100UL4223	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB        0x200UL4224	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB        0x400UL4225	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB       0x800UL4226	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL4227	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB        0x2000UL4228	u8	wirespeed;4229	#define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL4230	#define PORT_PHY_CFG_REQ_WIRESPEED_ON  0x1UL4231	#define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON4232	u8	lpbk;4233	#define PORT_PHY_CFG_REQ_LPBK_NONE     0x0UL4234	#define PORT_PHY_CFG_REQ_LPBK_LOCAL    0x1UL4235	#define PORT_PHY_CFG_REQ_LPBK_REMOTE   0x2UL4236	#define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL4237	#define PORT_PHY_CFG_REQ_LPBK_LAST    PORT_PHY_CFG_REQ_LPBK_EXTERNAL4238	u8	force_pause;4239	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX     0x1UL4240	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX     0x2UL4241	u8	unused_1;4242	__le32	preemphasis;4243	__le16	eee_link_speed_mask;4244	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1     0x1UL4245	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB     0x2UL4246	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2     0x4UL4247	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB       0x8UL4248	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3     0x10UL4249	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4     0x20UL4250	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB      0x40UL4251	__le16	force_pam4_link_speed;4252	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL4253	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL4254	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL4255	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB4256	__le32	tx_lpi_timer;4257	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL4258	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 04259	__le16	auto_link_pam4_speed_mask;4260	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G      0x1UL4261	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G     0x2UL4262	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G     0x4UL4263	__le16	force_link_speeds2;4264	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB            0xaUL4265	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB           0x64UL4266	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB           0xfaUL4267	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB           0x190UL4268	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB           0x1f4UL4269	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB          0x3e8UL4270	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL4271	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL4272	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL4273	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL4274	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL4275	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL4276	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL4277	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL4278	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_1124279	__le16	auto_link_speeds2_mask;4280	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB                0x1UL4281	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB               0x2UL4282	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB               0x4UL4283	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB               0x8UL4284	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB               0x10UL4285	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB              0x20UL4286	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56       0x40UL4287	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56      0x80UL4288	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56      0x100UL4289	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56      0x200UL4290	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112     0x400UL4291	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112     0x800UL4292	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112     0x1000UL4293	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112     0x2000UL4294	u8	unused_2[6];4295};4296 4297/* hwrm_port_phy_cfg_output (size:128b/16B) */4298struct hwrm_port_phy_cfg_output {4299	__le16	error_code;4300	__le16	req_type;4301	__le16	seq_id;4302	__le16	resp_len;4303	u8	unused_0[7];4304	u8	valid;4305};4306 4307/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */4308struct hwrm_port_phy_cfg_cmd_err {4309	u8	code;4310	#define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN       0x0UL4311	#define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL4312	#define PORT_PHY_CFG_CMD_ERR_CODE_RETRY         0x2UL4313	#define PORT_PHY_CFG_CMD_ERR_CODE_LAST         PORT_PHY_CFG_CMD_ERR_CODE_RETRY4314	u8	unused_0[7];4315};4316 4317/* hwrm_port_phy_qcfg_input (size:192b/24B) */4318struct hwrm_port_phy_qcfg_input {4319	__le16	req_type;4320	__le16	cmpl_ring;4321	__le16	seq_id;4322	__le16	target_id;4323	__le64	resp_addr;4324	__le16	port_id;4325	u8	unused_0[6];4326};4327 4328/* hwrm_port_phy_qcfg_output (size:832b/104B) */4329struct hwrm_port_phy_qcfg_output {4330	__le16	error_code;4331	__le16	req_type;4332	__le16	seq_id;4333	__le16	resp_len;4334	u8	link;4335	#define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL4336	#define PORT_PHY_QCFG_RESP_LINK_SIGNAL  0x1UL4337	#define PORT_PHY_QCFG_RESP_LINK_LINK    0x2UL4338	#define PORT_PHY_QCFG_RESP_LINK_LAST   PORT_PHY_QCFG_RESP_LINK_LINK4339	u8	active_fec_signal_mode;4340	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK                0xfUL4341	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT                 04342	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ                   0x0UL4343	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4                  0x1UL4344	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112              0x2UL4345	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST                 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_1124346	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK                 0xf0UL4347	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT                  44348	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE        (0x0UL << 4)4349	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE    (0x1UL << 4)4350	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE    (0x2UL << 4)4351	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE   (0x3UL << 4)4352	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE  (0x4UL << 4)4353	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE   (0x5UL << 4)4354	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE  (0x6UL << 4)4355	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST                  PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE4356	__le16	link_speed;4357	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL4358	#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB   0xaUL4359	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB   0x14UL4360	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL4361	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB  0x64UL4362	#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB  0xc8UL4363	#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB  0xfaUL4364	#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB  0x190UL4365	#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB  0x1f4UL4366	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL4367	#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL4368	#define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL4369	#define PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 0x1f40UL4370	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL4371	#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB4372	u8	duplex_cfg;4373	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL4374	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL4375	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL4376	u8	pause;4377	#define PORT_PHY_QCFG_RESP_PAUSE_TX     0x1UL4378	#define PORT_PHY_QCFG_RESP_PAUSE_RX     0x2UL4379	__le16	support_speeds;4380	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD     0x1UL4381	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB       0x2UL4382	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD       0x4UL4383	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB         0x8UL4384	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB         0x10UL4385	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB       0x20UL4386	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB        0x40UL4387	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB        0x80UL4388	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB        0x100UL4389	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB        0x200UL4390	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB        0x400UL4391	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB       0x800UL4392	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD      0x1000UL4393	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB        0x2000UL4394	__le16	force_link_speed;4395	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL4396	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB   0xaUL4397	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB   0x14UL4398	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL4399	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB  0x64UL4400	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB  0xc8UL4401	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB  0xfaUL4402	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB  0x190UL4403	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB  0x1f4UL4404	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL4405	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB  0xffffUL4406	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB4407	u8	auto_mode;4408	#define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE         0x0UL4409	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS   0x1UL4410	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED    0x2UL4411	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL4412	#define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK   0x4UL4413	#define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK4414	u8	auto_pause;4415	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX                0x1UL4416	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX                0x2UL4417	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL4418	__le16	auto_link_speed;4419	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL4420	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB   0xaUL4421	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB   0x14UL4422	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL4423	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB  0x64UL4424	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB  0xc8UL4425	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB  0xfaUL4426	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB  0x190UL4427	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB  0x1f4UL4428	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL4429	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB  0xffffUL4430	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB4431	__le16	auto_link_speed_mask;4432	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL4433	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB       0x2UL4434	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL4435	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB         0x8UL4436	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB         0x10UL4437	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL4438	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB        0x40UL4439	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB        0x80UL4440	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB        0x100UL4441	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB        0x200UL4442	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB        0x400UL4443	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB       0x800UL4444	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL4445	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB        0x2000UL4446	u8	wirespeed;4447	#define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL4448	#define PORT_PHY_QCFG_RESP_WIRESPEED_ON  0x1UL4449	#define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON4450	u8	lpbk;4451	#define PORT_PHY_QCFG_RESP_LPBK_NONE     0x0UL4452	#define PORT_PHY_QCFG_RESP_LPBK_LOCAL    0x1UL4453	#define PORT_PHY_QCFG_RESP_LPBK_REMOTE   0x2UL4454	#define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL4455	#define PORT_PHY_QCFG_RESP_LPBK_LAST    PORT_PHY_QCFG_RESP_LPBK_EXTERNAL4456	u8	force_pause;4457	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX     0x1UL4458	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX     0x2UL4459	u8	module_status;4460	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE          0x0UL4461	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX     0x1UL4462	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG    0x2UL4463	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN       0x3UL4464	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED   0x4UL4465	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT  0x5UL4466	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_OVERHEATED    0x6UL4467	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL4468	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST         PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE4469	__le32	preemphasis;4470	u8	phy_maj;4471	u8	phy_min;4472	u8	phy_bld;4473	u8	phy_type;4474	#define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN          0x0UL4475	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR           0x1UL4476	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4          0x2UL4477	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR           0x3UL4478	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR           0x4UL4479	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2          0x5UL4480	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX           0x6UL4481	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR           0x7UL4482	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET            0x8UL4483	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE           0x9UL4484	#define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY      0xaUL4485	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L  0xbUL4486	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S  0xcUL4487	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N  0xdUL4488	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR       0xeUL4489	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4     0xfUL4490	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4     0x10UL4491	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4     0x11UL4492	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4     0x12UL4493	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10    0x13UL4494	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4      0x14UL4495	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4      0x15UL4496	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4      0x16UL4497	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4      0x17UL4498	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL4499	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET         0x19UL4500	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX        0x1aUL4501	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX        0x1bUL4502	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4     0x1cUL4503	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4     0x1dUL4504	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4     0x1eUL4505	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4     0x1fUL4506	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR       0x20UL4507	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR       0x21UL4508	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR       0x22UL4509	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER       0x23UL4510	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2     0x24UL4511	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2     0x25UL4512	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2     0x26UL4513	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2     0x27UL4514	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR      0x28UL4515	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR      0x29UL4516	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR      0x2aUL4517	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER      0x2bUL4518	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2     0x2cUL4519	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2     0x2dUL4520	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2     0x2eUL4521	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2     0x2fUL4522	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8     0x30UL4523	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8     0x31UL4524	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8     0x32UL4525	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8     0x33UL4526	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4     0x34UL4527	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4     0x35UL4528	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4     0x36UL4529	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4     0x37UL4530	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASECR8     0x38UL4531	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASESR8     0x39UL4532	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASELR8     0x3aUL4533	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8     0x3bUL4534	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8     0x3cUL4535	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8     0x3dUL4536	#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR84537	u8	media_type;4538	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL4539	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP      0x1UL4540	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC     0x2UL4541	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE   0x3UL4542	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST   PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE4543	u8	xcvr_pkg_type;4544	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL4545	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL4546	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST         PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL4547	u8	eee_config_phy_addr;4548	#define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK              0x1fUL4549	#define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT               04550	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK            0xe0UL4551	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT             54552	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED      0x20UL4553	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE       0x40UL4554	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI       0x80UL4555	u8	parallel_detect;4556	#define PORT_PHY_QCFG_RESP_PARALLEL_DETECT     0x1UL4557	__le16	link_partner_adv_speeds;4558	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD     0x1UL4559	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB       0x2UL4560	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD       0x4UL4561	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB         0x8UL4562	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB         0x10UL4563	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB       0x20UL4564	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB        0x40UL4565	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB        0x80UL4566	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB        0x100UL4567	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB        0x200UL4568	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB        0x400UL4569	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB       0x800UL4570	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD      0x1000UL4571	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB        0x2000UL4572	u8	link_partner_adv_auto_mode;4573	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE         0x0UL4574	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS   0x1UL4575	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED    0x2UL4576	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL4577	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK   0x4UL4578	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK4579	u8	link_partner_adv_pause;4580	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX     0x1UL4581	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX     0x2UL4582	__le16	adv_eee_link_speed_mask;4583	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL4584	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL4585	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL4586	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL4587	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL4588	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL4589	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL4590	__le16	link_partner_adv_eee_link_speed_mask;4591	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL4592	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL4593	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL4594	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL4595	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL4596	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL4597	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL4598	__le32	xcvr_identifier_type_tx_lpi_timer;4599	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK            0xffffffUL4600	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT             04601	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK    0xff000000UL4602	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT     244603	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)4604	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP       (0x3UL << 24)4605	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP      (0xcUL << 24)4606	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (0xdUL << 24)4607	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28    (0x11UL << 24)4608	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD    (0x18UL << 24)4609	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112   (0x1eUL << 24)4610	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD     (0x1fUL << 24)4611	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP      (0x20UL << 24)4612	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST     PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP4613	__le16	fec_cfg;4614	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED           0x1UL4615	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED        0x2UL4616	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED          0x4UL4617	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED       0x8UL4618	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED         0x10UL4619	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED       0x20UL4620	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED         0x40UL4621	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED      0x80UL4622	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED        0x100UL4623	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED     0x200UL4624	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED       0x400UL4625	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED      0x800UL4626	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED        0x1000UL4627	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED     0x2000UL4628	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED       0x4000UL4629	u8	duplex_state;4630	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL4631	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL4632	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL4633	u8	option_flags;4634	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT     0x1UL4635	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN     0x2UL4636	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED     0x4UL4637	char	phy_vendor_name[16];4638	char	phy_vendor_partnumber[16];4639	__le16	support_pam4_speeds;4640	#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G      0x1UL4641	#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G     0x2UL4642	#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G     0x4UL4643	__le16	force_pam4_link_speed;4644	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL4645	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL4646	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL4647	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB4648	__le16	auto_pam4_link_speed_mask;4649	#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G      0x1UL4650	#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G     0x2UL4651	#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G     0x4UL4652	u8	link_partner_pam4_adv_speeds;4653	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB      0x1UL4654	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB     0x2UL4655	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB     0x4UL4656	u8	link_down_reason;4657	#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF     0x1UL4658	__le16	support_speeds2;4659	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB                0x1UL4660	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB               0x2UL4661	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB               0x4UL4662	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB               0x8UL4663	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB               0x10UL4664	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB              0x20UL4665	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56       0x40UL4666	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56      0x80UL4667	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56      0x100UL4668	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56      0x200UL4669	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112     0x400UL4670	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112     0x800UL4671	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112     0x1000UL4672	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112     0x2000UL4673	__le16	force_link_speeds2;4674	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB            0xaUL4675	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB           0x64UL4676	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB           0xfaUL4677	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB           0x190UL4678	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB           0x1f4UL4679	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB          0x3e8UL4680	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL4681	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL4682	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL4683	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL4684	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL4685	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL4686	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL4687	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL4688	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_1124689	__le16	auto_link_speeds2;4690	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB                0x1UL4691	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB               0x2UL4692	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB               0x4UL4693	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB               0x8UL4694	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB               0x10UL4695	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB              0x20UL4696	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56       0x40UL4697	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56      0x80UL4698	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56      0x100UL4699	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56      0x200UL4700	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112     0x400UL4701	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112     0x800UL4702	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112     0x1000UL4703	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112     0x2000UL4704	u8	active_lanes;4705	u8	valid;4706};4707 4708/* hwrm_port_mac_cfg_input (size:448b/56B) */4709struct hwrm_port_mac_cfg_input {4710	__le16	req_type;4711	__le16	cmpl_ring;4712	__le16	seq_id;4713	__le16	target_id;4714	__le64	resp_addr;4715	__le32	flags;4716	#define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK                    0x1UL4717	#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE           0x2UL4718	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE         0x4UL4719	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE            0x8UL4720	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE      0x10UL4721	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE     0x20UL4722	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE      0x40UL4723	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE     0x80UL4724	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE                0x100UL4725	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE               0x200UL4726	#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE          0x400UL4727	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE        0x800UL4728	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE           0x1000UL4729	#define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS            0x2000UL4730	#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE      0x4000UL4731	#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE     0x8000UL4732	__le32	enables;4733	#define PORT_MAC_CFG_REQ_ENABLES_IPG                            0x1UL4734	#define PORT_MAC_CFG_REQ_ENABLES_LPBK                           0x2UL4735	#define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI           0x4UL4736	#define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI         0x10UL4737	#define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI               0x20UL4738	#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE     0x40UL4739	#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE     0x80UL4740	#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG                  0x100UL4741	#define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB               0x200UL4742	#define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE                  0x400UL4743	#define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL               0x800UL4744	__le16	port_id;4745	u8	ipg;4746	u8	lpbk;4747	#define PORT_MAC_CFG_REQ_LPBK_NONE   0x0UL4748	#define PORT_MAC_CFG_REQ_LPBK_LOCAL  0x1UL4749	#define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL4750	#define PORT_MAC_CFG_REQ_LPBK_LAST  PORT_MAC_CFG_REQ_LPBK_REMOTE4751	u8	vlan_pri2cos_map_pri;4752	u8	reserved1;4753	u8	tunnel_pri2cos_map_pri;4754	u8	dscp2pri_map_pri;4755	__le16	rx_ts_capture_ptp_msg_type;4756	__le16	tx_ts_capture_ptp_msg_type;4757	u8	cos_field_cfg;4758	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1                     0x1UL4759	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK         0x6UL4760	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT          14761	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST      (0x0UL << 1)4762	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER          (0x1UL << 1)4763	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST      (0x2UL << 1)4764	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED    (0x3UL << 1)4765	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST          PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED4766	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK       0x18UL4767	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT        34768	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST    (0x0UL << 3)4769	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER        (0x1UL << 3)4770	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST    (0x2UL << 3)4771	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (0x3UL << 3)4772	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST        PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED4773	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK          0xe0UL4774	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT           54775	u8	unused_0[3];4776	__le32	ptp_freq_adj_ppb;4777	u8	unused_1[3];4778	u8	ptp_load_control;4779	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE      0x0UL4780	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL4781	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL4782	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST     PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT4783	__le64	ptp_adj_phase;4784};4785 4786/* hwrm_port_mac_cfg_output (size:128b/16B) */4787struct hwrm_port_mac_cfg_output {4788	__le16	error_code;4789	__le16	req_type;4790	__le16	seq_id;4791	__le16	resp_len;4792	__le16	mru;4793	__le16	mtu;4794	u8	ipg;4795	u8	lpbk;4796	#define PORT_MAC_CFG_RESP_LPBK_NONE   0x0UL4797	#define PORT_MAC_CFG_RESP_LPBK_LOCAL  0x1UL4798	#define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL4799	#define PORT_MAC_CFG_RESP_LPBK_LAST  PORT_MAC_CFG_RESP_LPBK_REMOTE4800	u8	unused_0;4801	u8	valid;4802};4803 4804/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */4805struct hwrm_port_mac_ptp_qcfg_input {4806	__le16	req_type;4807	__le16	cmpl_ring;4808	__le16	seq_id;4809	__le16	target_id;4810	__le64	resp_addr;4811	__le16	port_id;4812	u8	unused_0[6];4813};4814 4815/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */4816struct hwrm_port_mac_ptp_qcfg_output {4817	__le16	error_code;4818	__le16	req_type;4819	__le16	seq_id;4820	__le16	resp_len;4821	u8	flags;4822	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS                       0x1UL4823	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS                      0x4UL4824	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS                         0x8UL4825	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK     0x10UL4826	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED                      0x20UL4827	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME                        0x40UL4828	u8	unused_0[3];4829	__le32	rx_ts_reg_off_lower;4830	__le32	rx_ts_reg_off_upper;4831	__le32	rx_ts_reg_off_seq_id;4832	__le32	rx_ts_reg_off_src_id_0;4833	__le32	rx_ts_reg_off_src_id_1;4834	__le32	rx_ts_reg_off_src_id_2;4835	__le32	rx_ts_reg_off_domain_id;4836	__le32	rx_ts_reg_off_fifo;4837	__le32	rx_ts_reg_off_fifo_adv;4838	__le32	rx_ts_reg_off_granularity;4839	__le32	tx_ts_reg_off_lower;4840	__le32	tx_ts_reg_off_upper;4841	__le32	tx_ts_reg_off_seq_id;4842	__le32	tx_ts_reg_off_fifo;4843	__le32	tx_ts_reg_off_granularity;4844	__le32	ts_ref_clock_reg_lower;4845	__le32	ts_ref_clock_reg_upper;4846	u8	unused_1[7];4847	u8	valid;4848};4849 4850/* tx_port_stats (size:3264b/408B) */4851struct tx_port_stats {4852	__le64	tx_64b_frames;4853	__le64	tx_65b_127b_frames;4854	__le64	tx_128b_255b_frames;4855	__le64	tx_256b_511b_frames;4856	__le64	tx_512b_1023b_frames;4857	__le64	tx_1024b_1518b_frames;4858	__le64	tx_good_vlan_frames;4859	__le64	tx_1519b_2047b_frames;4860	__le64	tx_2048b_4095b_frames;4861	__le64	tx_4096b_9216b_frames;4862	__le64	tx_9217b_16383b_frames;4863	__le64	tx_good_frames;4864	__le64	tx_total_frames;4865	__le64	tx_ucast_frames;4866	__le64	tx_mcast_frames;4867	__le64	tx_bcast_frames;4868	__le64	tx_pause_frames;4869	__le64	tx_pfc_frames;4870	__le64	tx_jabber_frames;4871	__le64	tx_fcs_err_frames;4872	__le64	tx_control_frames;4873	__le64	tx_oversz_frames;4874	__le64	tx_single_dfrl_frames;4875	__le64	tx_multi_dfrl_frames;4876	__le64	tx_single_coll_frames;4877	__le64	tx_multi_coll_frames;4878	__le64	tx_late_coll_frames;4879	__le64	tx_excessive_coll_frames;4880	__le64	tx_frag_frames;4881	__le64	tx_err;4882	__le64	tx_tagged_frames;4883	__le64	tx_dbl_tagged_frames;4884	__le64	tx_runt_frames;4885	__le64	tx_fifo_underruns;4886	__le64	tx_pfc_ena_frames_pri0;4887	__le64	tx_pfc_ena_frames_pri1;4888	__le64	tx_pfc_ena_frames_pri2;4889	__le64	tx_pfc_ena_frames_pri3;4890	__le64	tx_pfc_ena_frames_pri4;4891	__le64	tx_pfc_ena_frames_pri5;4892	__le64	tx_pfc_ena_frames_pri6;4893	__le64	tx_pfc_ena_frames_pri7;4894	__le64	tx_eee_lpi_events;4895	__le64	tx_eee_lpi_duration;4896	__le64	tx_llfc_logical_msgs;4897	__le64	tx_hcfc_msgs;4898	__le64	tx_total_collisions;4899	__le64	tx_bytes;4900	__le64	tx_xthol_frames;4901	__le64	tx_stat_discard;4902	__le64	tx_stat_error;4903};4904 4905/* rx_port_stats (size:4224b/528B) */4906struct rx_port_stats {4907	__le64	rx_64b_frames;4908	__le64	rx_65b_127b_frames;4909	__le64	rx_128b_255b_frames;4910	__le64	rx_256b_511b_frames;4911	__le64	rx_512b_1023b_frames;4912	__le64	rx_1024b_1518b_frames;4913	__le64	rx_good_vlan_frames;4914	__le64	rx_1519b_2047b_frames;4915	__le64	rx_2048b_4095b_frames;4916	__le64	rx_4096b_9216b_frames;4917	__le64	rx_9217b_16383b_frames;4918	__le64	rx_total_frames;4919	__le64	rx_ucast_frames;4920	__le64	rx_mcast_frames;4921	__le64	rx_bcast_frames;4922	__le64	rx_fcs_err_frames;4923	__le64	rx_ctrl_frames;4924	__le64	rx_pause_frames;4925	__le64	rx_pfc_frames;4926	__le64	rx_unsupported_opcode_frames;4927	__le64	rx_unsupported_da_pausepfc_frames;4928	__le64	rx_wrong_sa_frames;4929	__le64	rx_align_err_frames;4930	__le64	rx_oor_len_frames;4931	__le64	rx_code_err_frames;4932	__le64	rx_false_carrier_frames;4933	__le64	rx_ovrsz_frames;4934	__le64	rx_jbr_frames;4935	__le64	rx_mtu_err_frames;4936	__le64	rx_match_crc_frames;4937	__le64	rx_promiscuous_frames;4938	__le64	rx_tagged_frames;4939	__le64	rx_double_tagged_frames;4940	__le64	rx_trunc_frames;4941	__le64	rx_good_frames;4942	__le64	rx_pfc_xon2xoff_frames_pri0;4943	__le64	rx_pfc_xon2xoff_frames_pri1;4944	__le64	rx_pfc_xon2xoff_frames_pri2;4945	__le64	rx_pfc_xon2xoff_frames_pri3;4946	__le64	rx_pfc_xon2xoff_frames_pri4;4947	__le64	rx_pfc_xon2xoff_frames_pri5;4948	__le64	rx_pfc_xon2xoff_frames_pri6;4949	__le64	rx_pfc_xon2xoff_frames_pri7;4950	__le64	rx_pfc_ena_frames_pri0;4951	__le64	rx_pfc_ena_frames_pri1;4952	__le64	rx_pfc_ena_frames_pri2;4953	__le64	rx_pfc_ena_frames_pri3;4954	__le64	rx_pfc_ena_frames_pri4;4955	__le64	rx_pfc_ena_frames_pri5;4956	__le64	rx_pfc_ena_frames_pri6;4957	__le64	rx_pfc_ena_frames_pri7;4958	__le64	rx_sch_crc_err_frames;4959	__le64	rx_undrsz_frames;4960	__le64	rx_frag_frames;4961	__le64	rx_eee_lpi_events;4962	__le64	rx_eee_lpi_duration;4963	__le64	rx_llfc_physical_msgs;4964	__le64	rx_llfc_logical_msgs;4965	__le64	rx_llfc_msgs_with_crc_err;4966	__le64	rx_hcfc_msgs;4967	__le64	rx_hcfc_msgs_with_crc_err;4968	__le64	rx_bytes;4969	__le64	rx_runt_bytes;4970	__le64	rx_runt_frames;4971	__le64	rx_stat_discard;4972	__le64	rx_stat_err;4973};4974 4975/* hwrm_port_qstats_input (size:320b/40B) */4976struct hwrm_port_qstats_input {4977	__le16	req_type;4978	__le16	cmpl_ring;4979	__le16	seq_id;4980	__le16	target_id;4981	__le64	resp_addr;4982	__le16	port_id;4983	u8	flags;4984	#define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL4985	u8	unused_0[5];4986	__le64	tx_stat_host_addr;4987	__le64	rx_stat_host_addr;4988};4989 4990/* hwrm_port_qstats_output (size:128b/16B) */4991struct hwrm_port_qstats_output {4992	__le16	error_code;4993	__le16	req_type;4994	__le16	seq_id;4995	__le16	resp_len;4996	__le16	tx_stat_size;4997	__le16	rx_stat_size;4998	u8	flags;4999	#define PORT_QSTATS_RESP_FLAGS_CLEARED     0x1UL5000	u8	unused_0[2];5001	u8	valid;5002};5003 5004/* tx_port_stats_ext (size:2048b/256B) */5005struct tx_port_stats_ext {5006	__le64	tx_bytes_cos0;5007	__le64	tx_bytes_cos1;5008	__le64	tx_bytes_cos2;5009	__le64	tx_bytes_cos3;5010	__le64	tx_bytes_cos4;5011	__le64	tx_bytes_cos5;5012	__le64	tx_bytes_cos6;5013	__le64	tx_bytes_cos7;5014	__le64	tx_packets_cos0;5015	__le64	tx_packets_cos1;5016	__le64	tx_packets_cos2;5017	__le64	tx_packets_cos3;5018	__le64	tx_packets_cos4;5019	__le64	tx_packets_cos5;5020	__le64	tx_packets_cos6;5021	__le64	tx_packets_cos7;5022	__le64	pfc_pri0_tx_duration_us;5023	__le64	pfc_pri0_tx_transitions;5024	__le64	pfc_pri1_tx_duration_us;5025	__le64	pfc_pri1_tx_transitions;5026	__le64	pfc_pri2_tx_duration_us;5027	__le64	pfc_pri2_tx_transitions;5028	__le64	pfc_pri3_tx_duration_us;5029	__le64	pfc_pri3_tx_transitions;5030	__le64	pfc_pri4_tx_duration_us;5031	__le64	pfc_pri4_tx_transitions;5032	__le64	pfc_pri5_tx_duration_us;5033	__le64	pfc_pri5_tx_transitions;5034	__le64	pfc_pri6_tx_duration_us;5035	__le64	pfc_pri6_tx_transitions;5036	__le64	pfc_pri7_tx_duration_us;5037	__le64	pfc_pri7_tx_transitions;5038};5039 5040/* rx_port_stats_ext (size:3904b/488B) */5041struct rx_port_stats_ext {5042	__le64	link_down_events;5043	__le64	continuous_pause_events;5044	__le64	resume_pause_events;5045	__le64	continuous_roce_pause_events;5046	__le64	resume_roce_pause_events;5047	__le64	rx_bytes_cos0;5048	__le64	rx_bytes_cos1;5049	__le64	rx_bytes_cos2;5050	__le64	rx_bytes_cos3;5051	__le64	rx_bytes_cos4;5052	__le64	rx_bytes_cos5;5053	__le64	rx_bytes_cos6;5054	__le64	rx_bytes_cos7;5055	__le64	rx_packets_cos0;5056	__le64	rx_packets_cos1;5057	__le64	rx_packets_cos2;5058	__le64	rx_packets_cos3;5059	__le64	rx_packets_cos4;5060	__le64	rx_packets_cos5;5061	__le64	rx_packets_cos6;5062	__le64	rx_packets_cos7;5063	__le64	pfc_pri0_rx_duration_us;5064	__le64	pfc_pri0_rx_transitions;5065	__le64	pfc_pri1_rx_duration_us;5066	__le64	pfc_pri1_rx_transitions;5067	__le64	pfc_pri2_rx_duration_us;5068	__le64	pfc_pri2_rx_transitions;5069	__le64	pfc_pri3_rx_duration_us;5070	__le64	pfc_pri3_rx_transitions;5071	__le64	pfc_pri4_rx_duration_us;5072	__le64	pfc_pri4_rx_transitions;5073	__le64	pfc_pri5_rx_duration_us;5074	__le64	pfc_pri5_rx_transitions;5075	__le64	pfc_pri6_rx_duration_us;5076	__le64	pfc_pri6_rx_transitions;5077	__le64	pfc_pri7_rx_duration_us;5078	__le64	pfc_pri7_rx_transitions;5079	__le64	rx_bits;5080	__le64	rx_buffer_passed_threshold;5081	__le64	rx_pcs_symbol_err;5082	__le64	rx_corrected_bits;5083	__le64	rx_discard_bytes_cos0;5084	__le64	rx_discard_bytes_cos1;5085	__le64	rx_discard_bytes_cos2;5086	__le64	rx_discard_bytes_cos3;5087	__le64	rx_discard_bytes_cos4;5088	__le64	rx_discard_bytes_cos5;5089	__le64	rx_discard_bytes_cos6;5090	__le64	rx_discard_bytes_cos7;5091	__le64	rx_discard_packets_cos0;5092	__le64	rx_discard_packets_cos1;5093	__le64	rx_discard_packets_cos2;5094	__le64	rx_discard_packets_cos3;5095	__le64	rx_discard_packets_cos4;5096	__le64	rx_discard_packets_cos5;5097	__le64	rx_discard_packets_cos6;5098	__le64	rx_discard_packets_cos7;5099	__le64	rx_fec_corrected_blocks;5100	__le64	rx_fec_uncorrectable_blocks;5101	__le64	rx_filter_miss;5102	__le64	rx_fec_symbol_err;5103};5104 5105/* hwrm_port_qstats_ext_input (size:320b/40B) */5106struct hwrm_port_qstats_ext_input {5107	__le16	req_type;5108	__le16	cmpl_ring;5109	__le16	seq_id;5110	__le16	target_id;5111	__le64	resp_addr;5112	__le16	port_id;5113	__le16	tx_stat_size;5114	__le16	rx_stat_size;5115	u8	flags;5116	#define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK     0x1UL5117	u8	unused_0;5118	__le64	tx_stat_host_addr;5119	__le64	rx_stat_host_addr;5120};5121 5122/* hwrm_port_qstats_ext_output (size:128b/16B) */5123struct hwrm_port_qstats_ext_output {5124	__le16	error_code;5125	__le16	req_type;5126	__le16	seq_id;5127	__le16	resp_len;5128	__le16	tx_stat_size;5129	__le16	rx_stat_size;5130	__le16	total_active_cos_queues;5131	u8	flags;5132	#define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED     0x1UL5133	#define PORT_QSTATS_EXT_RESP_FLAGS_CLEARED                           0x2UL5134	u8	valid;5135};5136 5137/* hwrm_port_lpbk_qstats_input (size:256b/32B) */5138struct hwrm_port_lpbk_qstats_input {5139	__le16	req_type;5140	__le16	cmpl_ring;5141	__le16	seq_id;5142	__le16	target_id;5143	__le64	resp_addr;5144	__le16	lpbk_stat_size;5145	u8	flags;5146	#define PORT_LPBK_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL5147	u8	unused_0[5];5148	__le64	lpbk_stat_host_addr;5149};5150 5151/* hwrm_port_lpbk_qstats_output (size:128b/16B) */5152struct hwrm_port_lpbk_qstats_output {5153	__le16	error_code;5154	__le16	req_type;5155	__le16	seq_id;5156	__le16	resp_len;5157	__le16	lpbk_stat_size;5158	u8	unused_0[5];5159	u8	valid;5160};5161 5162/* port_lpbk_stats (size:640b/80B) */5163struct port_lpbk_stats {5164	__le64	lpbk_ucast_frames;5165	__le64	lpbk_mcast_frames;5166	__le64	lpbk_bcast_frames;5167	__le64	lpbk_ucast_bytes;5168	__le64	lpbk_mcast_bytes;5169	__le64	lpbk_bcast_bytes;5170	__le64	lpbk_tx_discards;5171	__le64	lpbk_tx_errors;5172	__le64	lpbk_rx_discards;5173	__le64	lpbk_rx_errors;5174};5175 5176/* hwrm_port_ecn_qstats_input (size:256b/32B) */5177struct hwrm_port_ecn_qstats_input {5178	__le16	req_type;5179	__le16	cmpl_ring;5180	__le16	seq_id;5181	__le16	target_id;5182	__le64	resp_addr;5183	__le16	port_id;5184	__le16	ecn_stat_buf_size;5185	u8	flags;5186	#define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL5187	u8	unused_0[3];5188	__le64	ecn_stat_host_addr;5189};5190 5191/* hwrm_port_ecn_qstats_output (size:128b/16B) */5192struct hwrm_port_ecn_qstats_output {5193	__le16	error_code;5194	__le16	req_type;5195	__le16	seq_id;5196	__le16	resp_len;5197	__le16	ecn_stat_buf_size;5198	u8	mark_en;5199	u8	unused_0[4];5200	u8	valid;5201};5202 5203/* port_stats_ecn (size:512b/64B) */5204struct port_stats_ecn {5205	__le64	mark_cnt_cos0;5206	__le64	mark_cnt_cos1;5207	__le64	mark_cnt_cos2;5208	__le64	mark_cnt_cos3;5209	__le64	mark_cnt_cos4;5210	__le64	mark_cnt_cos5;5211	__le64	mark_cnt_cos6;5212	__le64	mark_cnt_cos7;5213};5214 5215/* hwrm_port_clr_stats_input (size:192b/24B) */5216struct hwrm_port_clr_stats_input {5217	__le16	req_type;5218	__le16	cmpl_ring;5219	__le16	seq_id;5220	__le16	target_id;5221	__le64	resp_addr;5222	__le16	port_id;5223	u8	flags;5224	#define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS     0x1UL5225	u8	unused_0[5];5226};5227 5228/* hwrm_port_clr_stats_output (size:128b/16B) */5229struct hwrm_port_clr_stats_output {5230	__le16	error_code;5231	__le16	req_type;5232	__le16	seq_id;5233	__le16	resp_len;5234	u8	unused_0[7];5235	u8	valid;5236};5237 5238/* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */5239struct hwrm_port_lpbk_clr_stats_input {5240	__le16	req_type;5241	__le16	cmpl_ring;5242	__le16	seq_id;5243	__le16	target_id;5244	__le64	resp_addr;5245	__le16	port_id;5246	u8	unused_0[6];5247};5248 5249/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */5250struct hwrm_port_lpbk_clr_stats_output {5251	__le16	error_code;5252	__le16	req_type;5253	__le16	seq_id;5254	__le16	resp_len;5255	u8	unused_0[7];5256	u8	valid;5257};5258 5259/* hwrm_port_ts_query_input (size:320b/40B) */5260struct hwrm_port_ts_query_input {5261	__le16	req_type;5262	__le16	cmpl_ring;5263	__le16	seq_id;5264	__le16	target_id;5265	__le64	resp_addr;5266	__le32	flags;5267	#define PORT_TS_QUERY_REQ_FLAGS_PATH             0x1UL5268	#define PORT_TS_QUERY_REQ_FLAGS_PATH_TX            0x0UL5269	#define PORT_TS_QUERY_REQ_FLAGS_PATH_RX            0x1UL5270	#define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST         PORT_TS_QUERY_REQ_FLAGS_PATH_RX5271	#define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME     0x2UL5272	__le16	port_id;5273	u8	unused_0[2];5274	__le16	enables;5275	#define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT     0x1UL5276	#define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID         0x2UL5277	#define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET     0x4UL5278	__le16	ts_req_timeout;5279	__le32	ptp_seq_id;5280	__le16	ptp_hdr_offset;5281	u8	unused_1[6];5282};5283 5284/* hwrm_port_ts_query_output (size:192b/24B) */5285struct hwrm_port_ts_query_output {5286	__le16	error_code;5287	__le16	req_type;5288	__le16	seq_id;5289	__le16	resp_len;5290	__le64	ptp_msg_ts;5291	__le16	ptp_msg_seqid;5292	u8	unused_0[5];5293	u8	valid;5294};5295 5296/* hwrm_port_phy_qcaps_input (size:192b/24B) */5297struct hwrm_port_phy_qcaps_input {5298	__le16	req_type;5299	__le16	cmpl_ring;5300	__le16	seq_id;5301	__le16	target_id;5302	__le64	resp_addr;5303	__le16	port_id;5304	u8	unused_0[6];5305};5306 5307/* hwrm_port_phy_qcaps_output (size:320b/40B) */5308struct hwrm_port_phy_qcaps_output {5309	__le16	error_code;5310	__le16	req_type;5311	__le16	seq_id;5312	__le16	resp_len;5313	u8	flags;5314	#define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED                    0x1UL5315	#define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED          0x2UL5316	#define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED           0x4UL5317	#define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED         0x8UL5318	#define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET     0x10UL5319	#define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED         0x20UL5320	#define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN             0x40UL5321	#define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS                           0x80UL5322	u8	port_cnt;5323	#define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL5324	#define PORT_PHY_QCAPS_RESP_PORT_CNT_1       0x1UL5325	#define PORT_PHY_QCAPS_RESP_PORT_CNT_2       0x2UL5326	#define PORT_PHY_QCAPS_RESP_PORT_CNT_3       0x3UL5327	#define PORT_PHY_QCAPS_RESP_PORT_CNT_4       0x4UL5328	#define PORT_PHY_QCAPS_RESP_PORT_CNT_12      0xcUL5329	#define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST   PORT_PHY_QCAPS_RESP_PORT_CNT_125330	__le16	supported_speeds_force_mode;5331	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD     0x1UL5332	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB       0x2UL5333	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD       0x4UL5334	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB         0x8UL5335	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB         0x10UL5336	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB       0x20UL5337	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB        0x40UL5338	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB        0x80UL5339	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB        0x100UL5340	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB        0x200UL5341	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB        0x400UL5342	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB       0x800UL5343	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD      0x1000UL5344	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB        0x2000UL5345	__le16	supported_speeds_auto_mode;5346	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD     0x1UL5347	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB       0x2UL5348	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD       0x4UL5349	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB         0x8UL5350	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB         0x10UL5351	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB       0x20UL5352	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB        0x40UL5353	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB        0x80UL5354	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB        0x100UL5355	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB        0x200UL5356	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB        0x400UL5357	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB       0x800UL5358	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD      0x1000UL5359	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB        0x2000UL5360	__le16	supported_speeds_eee_mode;5361	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1     0x1UL5362	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB     0x2UL5363	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2     0x4UL5364	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB       0x8UL5365	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3     0x10UL5366	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4     0x20UL5367	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB      0x40UL5368	__le32	tx_lpi_timer_low;5369	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL5370	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 05371	#define PORT_PHY_QCAPS_RESP_RSVD2_MASK           0xff000000UL5372	#define PORT_PHY_QCAPS_RESP_RSVD2_SFT            245373	__le32	valid_tx_lpi_timer_high;5374	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL5375	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 05376	#define PORT_PHY_QCAPS_RESP_RSVD_MASK             0xff000000UL5377	#define PORT_PHY_QCAPS_RESP_RSVD_SFT              245378	__le16	supported_pam4_speeds_auto_mode;5379	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G      0x1UL5380	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G     0x2UL5381	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G     0x4UL5382	__le16	supported_pam4_speeds_force_mode;5383	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G      0x1UL5384	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G     0x2UL5385	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G     0x4UL5386	__le16	flags2;5387	#define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED           0x1UL5388	#define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED             0x2UL5389	#define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED         0x4UL5390	#define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED           0x8UL5391	#define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED     0x10UL5392	u8	internal_port_cnt;5393	u8	unused_0;5394	__le16	supported_speeds2_force_mode;5395	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB                0x1UL5396	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB               0x2UL5397	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB               0x4UL5398	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB               0x8UL5399	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB               0x10UL5400	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB              0x20UL5401	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56       0x40UL5402	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56      0x80UL5403	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56      0x100UL5404	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56      0x200UL5405	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112     0x400UL5406	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112     0x800UL5407	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112     0x1000UL5408	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112     0x2000UL5409	__le16	supported_speeds2_auto_mode;5410	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB                0x1UL5411	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB               0x2UL5412	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB               0x4UL5413	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB               0x8UL5414	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB               0x10UL5415	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB              0x20UL5416	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56       0x40UL5417	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56      0x80UL5418	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56      0x100UL5419	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56      0x200UL5420	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112     0x400UL5421	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112     0x800UL5422	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112     0x1000UL5423	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112     0x2000UL5424	u8	unused_1[3];5425	u8	valid;5426};5427 5428/* hwrm_port_phy_i2c_read_input (size:320b/40B) */5429struct hwrm_port_phy_i2c_read_input {5430	__le16	req_type;5431	__le16	cmpl_ring;5432	__le16	seq_id;5433	__le16	target_id;5434	__le64	resp_addr;5435	__le32	flags;5436	__le32	enables;5437	#define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET     0x1UL5438	#define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER     0x2UL5439	__le16	port_id;5440	u8	i2c_slave_addr;5441	u8	bank_number;5442	__le16	page_number;5443	__le16	page_offset;5444	u8	data_length;5445	u8	unused_1[7];5446};5447 5448/* hwrm_port_phy_i2c_read_output (size:640b/80B) */5449struct hwrm_port_phy_i2c_read_output {5450	__le16	error_code;5451	__le16	req_type;5452	__le16	seq_id;5453	__le16	resp_len;5454	__le32	data[16];5455	u8	unused_0[7];5456	u8	valid;5457};5458 5459/* hwrm_port_phy_mdio_write_input (size:320b/40B) */5460struct hwrm_port_phy_mdio_write_input {5461	__le16	req_type;5462	__le16	cmpl_ring;5463	__le16	seq_id;5464	__le16	target_id;5465	__le64	resp_addr;5466	__le32	unused_0[2];5467	__le16	port_id;5468	u8	phy_addr;5469	u8	dev_addr;5470	__le16	reg_addr;5471	__le16	reg_data;5472	u8	cl45_mdio;5473	u8	unused_1[7];5474};5475 5476/* hwrm_port_phy_mdio_write_output (size:128b/16B) */5477struct hwrm_port_phy_mdio_write_output {5478	__le16	error_code;5479	__le16	req_type;5480	__le16	seq_id;5481	__le16	resp_len;5482	u8	unused_0[7];5483	u8	valid;5484};5485 5486/* hwrm_port_phy_mdio_read_input (size:256b/32B) */5487struct hwrm_port_phy_mdio_read_input {5488	__le16	req_type;5489	__le16	cmpl_ring;5490	__le16	seq_id;5491	__le16	target_id;5492	__le64	resp_addr;5493	__le32	unused_0[2];5494	__le16	port_id;5495	u8	phy_addr;5496	u8	dev_addr;5497	__le16	reg_addr;5498	u8	cl45_mdio;5499	u8	unused_1;5500};5501 5502/* hwrm_port_phy_mdio_read_output (size:128b/16B) */5503struct hwrm_port_phy_mdio_read_output {5504	__le16	error_code;5505	__le16	req_type;5506	__le16	seq_id;5507	__le16	resp_len;5508	__le16	reg_data;5509	u8	unused_0[5];5510	u8	valid;5511};5512 5513/* hwrm_port_led_cfg_input (size:512b/64B) */5514struct hwrm_port_led_cfg_input {5515	__le16	req_type;5516	__le16	cmpl_ring;5517	__le16	seq_id;5518	__le16	target_id;5519	__le64	resp_addr;5520	__le32	enables;5521	#define PORT_LED_CFG_REQ_ENABLES_LED0_ID            0x1UL5522	#define PORT_LED_CFG_REQ_ENABLES_LED0_STATE         0x2UL5523	#define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR         0x4UL5524	#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON      0x8UL5525	#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF     0x10UL5526	#define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID      0x20UL5527	#define PORT_LED_CFG_REQ_ENABLES_LED1_ID            0x40UL5528	#define PORT_LED_CFG_REQ_ENABLES_LED1_STATE         0x80UL5529	#define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR         0x100UL5530	#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON      0x200UL5531	#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF     0x400UL5532	#define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID      0x800UL5533	#define PORT_LED_CFG_REQ_ENABLES_LED2_ID            0x1000UL5534	#define PORT_LED_CFG_REQ_ENABLES_LED2_STATE         0x2000UL5535	#define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR         0x4000UL5536	#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON      0x8000UL5537	#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF     0x10000UL5538	#define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID      0x20000UL5539	#define PORT_LED_CFG_REQ_ENABLES_LED3_ID            0x40000UL5540	#define PORT_LED_CFG_REQ_ENABLES_LED3_STATE         0x80000UL5541	#define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR         0x100000UL5542	#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON      0x200000UL5543	#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF     0x400000UL5544	#define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID      0x800000UL5545	__le16	port_id;5546	u8	num_leds;5547	u8	rsvd;5548	u8	led0_id;5549	u8	led0_state;5550	#define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT  0x0UL5551	#define PORT_LED_CFG_REQ_LED0_STATE_OFF      0x1UL5552	#define PORT_LED_CFG_REQ_LED0_STATE_ON       0x2UL5553	#define PORT_LED_CFG_REQ_LED0_STATE_BLINK    0x3UL5554	#define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL5555	#define PORT_LED_CFG_REQ_LED0_STATE_LAST    PORT_LED_CFG_REQ_LED0_STATE_BLINKALT5556	u8	led0_color;5557	#define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT    0x0UL5558	#define PORT_LED_CFG_REQ_LED0_COLOR_AMBER      0x1UL5559	#define PORT_LED_CFG_REQ_LED0_COLOR_GREEN      0x2UL5560	#define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL5561	#define PORT_LED_CFG_REQ_LED0_COLOR_LAST      PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER5562	u8	unused_0;5563	__le16	led0_blink_on;5564	__le16	led0_blink_off;5565	u8	led0_group_id;5566	u8	rsvd0;5567	u8	led1_id;5568	u8	led1_state;5569	#define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT  0x0UL5570	#define PORT_LED_CFG_REQ_LED1_STATE_OFF      0x1UL5571	#define PORT_LED_CFG_REQ_LED1_STATE_ON       0x2UL5572	#define PORT_LED_CFG_REQ_LED1_STATE_BLINK    0x3UL5573	#define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL5574	#define PORT_LED_CFG_REQ_LED1_STATE_LAST    PORT_LED_CFG_REQ_LED1_STATE_BLINKALT5575	u8	led1_color;5576	#define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT    0x0UL5577	#define PORT_LED_CFG_REQ_LED1_COLOR_AMBER      0x1UL5578	#define PORT_LED_CFG_REQ_LED1_COLOR_GREEN      0x2UL5579	#define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL5580	#define PORT_LED_CFG_REQ_LED1_COLOR_LAST      PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER5581	u8	unused_1;5582	__le16	led1_blink_on;5583	__le16	led1_blink_off;5584	u8	led1_group_id;5585	u8	rsvd1;5586	u8	led2_id;5587	u8	led2_state;5588	#define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT  0x0UL5589	#define PORT_LED_CFG_REQ_LED2_STATE_OFF      0x1UL5590	#define PORT_LED_CFG_REQ_LED2_STATE_ON       0x2UL5591	#define PORT_LED_CFG_REQ_LED2_STATE_BLINK    0x3UL5592	#define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL5593	#define PORT_LED_CFG_REQ_LED2_STATE_LAST    PORT_LED_CFG_REQ_LED2_STATE_BLINKALT5594	u8	led2_color;5595	#define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT    0x0UL5596	#define PORT_LED_CFG_REQ_LED2_COLOR_AMBER      0x1UL5597	#define PORT_LED_CFG_REQ_LED2_COLOR_GREEN      0x2UL5598	#define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL5599	#define PORT_LED_CFG_REQ_LED2_COLOR_LAST      PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER5600	u8	unused_2;5601	__le16	led2_blink_on;5602	__le16	led2_blink_off;5603	u8	led2_group_id;5604	u8	rsvd2;5605	u8	led3_id;5606	u8	led3_state;5607	#define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT  0x0UL5608	#define PORT_LED_CFG_REQ_LED3_STATE_OFF      0x1UL5609	#define PORT_LED_CFG_REQ_LED3_STATE_ON       0x2UL5610	#define PORT_LED_CFG_REQ_LED3_STATE_BLINK    0x3UL5611	#define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL5612	#define PORT_LED_CFG_REQ_LED3_STATE_LAST    PORT_LED_CFG_REQ_LED3_STATE_BLINKALT5613	u8	led3_color;5614	#define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT    0x0UL5615	#define PORT_LED_CFG_REQ_LED3_COLOR_AMBER      0x1UL5616	#define PORT_LED_CFG_REQ_LED3_COLOR_GREEN      0x2UL5617	#define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL5618	#define PORT_LED_CFG_REQ_LED3_COLOR_LAST      PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER5619	u8	unused_3;5620	__le16	led3_blink_on;5621	__le16	led3_blink_off;5622	u8	led3_group_id;5623	u8	rsvd3;5624};5625 5626/* hwrm_port_led_cfg_output (size:128b/16B) */5627struct hwrm_port_led_cfg_output {5628	__le16	error_code;5629	__le16	req_type;5630	__le16	seq_id;5631	__le16	resp_len;5632	u8	unused_0[7];5633	u8	valid;5634};5635 5636/* hwrm_port_led_qcfg_input (size:192b/24B) */5637struct hwrm_port_led_qcfg_input {5638	__le16	req_type;5639	__le16	cmpl_ring;5640	__le16	seq_id;5641	__le16	target_id;5642	__le64	resp_addr;5643	__le16	port_id;5644	u8	unused_0[6];5645};5646 5647/* hwrm_port_led_qcfg_output (size:448b/56B) */5648struct hwrm_port_led_qcfg_output {5649	__le16	error_code;5650	__le16	req_type;5651	__le16	seq_id;5652	__le16	resp_len;5653	u8	num_leds;5654	u8	led0_id;5655	u8	led0_type;5656	#define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED    0x0UL5657	#define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL5658	#define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID  0xffUL5659	#define PORT_LED_QCFG_RESP_LED0_TYPE_LAST    PORT_LED_QCFG_RESP_LED0_TYPE_INVALID5660	u8	led0_state;5661	#define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT  0x0UL5662	#define PORT_LED_QCFG_RESP_LED0_STATE_OFF      0x1UL5663	#define PORT_LED_QCFG_RESP_LED0_STATE_ON       0x2UL5664	#define PORT_LED_QCFG_RESP_LED0_STATE_BLINK    0x3UL5665	#define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL5666	#define PORT_LED_QCFG_RESP_LED0_STATE_LAST    PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT5667	u8	led0_color;5668	#define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT    0x0UL5669	#define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER      0x1UL5670	#define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN      0x2UL5671	#define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL5672	#define PORT_LED_QCFG_RESP_LED0_COLOR_LAST      PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER5673	u8	unused_0;5674	__le16	led0_blink_on;5675	__le16	led0_blink_off;5676	u8	led0_group_id;5677	u8	led1_id;5678	u8	led1_type;5679	#define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED    0x0UL5680	#define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL5681	#define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID  0xffUL5682	#define PORT_LED_QCFG_RESP_LED1_TYPE_LAST    PORT_LED_QCFG_RESP_LED1_TYPE_INVALID5683	u8	led1_state;5684	#define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT  0x0UL5685	#define PORT_LED_QCFG_RESP_LED1_STATE_OFF      0x1UL5686	#define PORT_LED_QCFG_RESP_LED1_STATE_ON       0x2UL5687	#define PORT_LED_QCFG_RESP_LED1_STATE_BLINK    0x3UL5688	#define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL5689	#define PORT_LED_QCFG_RESP_LED1_STATE_LAST    PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT5690	u8	led1_color;5691	#define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT    0x0UL5692	#define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER      0x1UL5693	#define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN      0x2UL5694	#define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL5695	#define PORT_LED_QCFG_RESP_LED1_COLOR_LAST      PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER5696	u8	unused_1;5697	__le16	led1_blink_on;5698	__le16	led1_blink_off;5699	u8	led1_group_id;5700	u8	led2_id;5701	u8	led2_type;5702	#define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED    0x0UL5703	#define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL5704	#define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID  0xffUL5705	#define PORT_LED_QCFG_RESP_LED2_TYPE_LAST    PORT_LED_QCFG_RESP_LED2_TYPE_INVALID5706	u8	led2_state;5707	#define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT  0x0UL5708	#define PORT_LED_QCFG_RESP_LED2_STATE_OFF      0x1UL5709	#define PORT_LED_QCFG_RESP_LED2_STATE_ON       0x2UL5710	#define PORT_LED_QCFG_RESP_LED2_STATE_BLINK    0x3UL5711	#define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL5712	#define PORT_LED_QCFG_RESP_LED2_STATE_LAST    PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT5713	u8	led2_color;5714	#define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT    0x0UL5715	#define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER      0x1UL5716	#define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN      0x2UL5717	#define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL5718	#define PORT_LED_QCFG_RESP_LED2_COLOR_LAST      PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER5719	u8	unused_2;5720	__le16	led2_blink_on;5721	__le16	led2_blink_off;5722	u8	led2_group_id;5723	u8	led3_id;5724	u8	led3_type;5725	#define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED    0x0UL5726	#define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL5727	#define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID  0xffUL5728	#define PORT_LED_QCFG_RESP_LED3_TYPE_LAST    PORT_LED_QCFG_RESP_LED3_TYPE_INVALID5729	u8	led3_state;5730	#define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT  0x0UL5731	#define PORT_LED_QCFG_RESP_LED3_STATE_OFF      0x1UL5732	#define PORT_LED_QCFG_RESP_LED3_STATE_ON       0x2UL5733	#define PORT_LED_QCFG_RESP_LED3_STATE_BLINK    0x3UL5734	#define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL5735	#define PORT_LED_QCFG_RESP_LED3_STATE_LAST    PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT5736	u8	led3_color;5737	#define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT    0x0UL5738	#define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER      0x1UL5739	#define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN      0x2UL5740	#define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL5741	#define PORT_LED_QCFG_RESP_LED3_COLOR_LAST      PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER5742	u8	unused_3;5743	__le16	led3_blink_on;5744	__le16	led3_blink_off;5745	u8	led3_group_id;5746	u8	unused_4[6];5747	u8	valid;5748};5749 5750/* hwrm_port_led_qcaps_input (size:192b/24B) */5751struct hwrm_port_led_qcaps_input {5752	__le16	req_type;5753	__le16	cmpl_ring;5754	__le16	seq_id;5755	__le16	target_id;5756	__le64	resp_addr;5757	__le16	port_id;5758	u8	unused_0[6];5759};5760 5761/* hwrm_port_led_qcaps_output (size:384b/48B) */5762struct hwrm_port_led_qcaps_output {5763	__le16	error_code;5764	__le16	req_type;5765	__le16	seq_id;5766	__le16	resp_len;5767	u8	num_leds;5768	u8	unused[3];5769	u8	led0_id;5770	u8	led0_type;5771	#define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED    0x0UL5772	#define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL5773	#define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID  0xffUL5774	#define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST    PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID5775	u8	led0_group_id;5776	u8	unused_0;5777	__le16	led0_state_caps;5778	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED                 0x1UL5779	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED           0x2UL5780	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED            0x4UL5781	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED         0x8UL5782	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL5783	__le16	led0_color_caps;5784	#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD                0x1UL5785	#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED     0x2UL5786	#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED     0x4UL5787	u8	led1_id;5788	u8	led1_type;5789	#define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED    0x0UL5790	#define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL5791	#define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID  0xffUL5792	#define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST    PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID5793	u8	led1_group_id;5794	u8	unused_1;5795	__le16	led1_state_caps;5796	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED                 0x1UL5797	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED           0x2UL5798	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED            0x4UL5799	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED         0x8UL5800	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL5801	__le16	led1_color_caps;5802	#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD                0x1UL5803	#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED     0x2UL5804	#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED     0x4UL5805	u8	led2_id;5806	u8	led2_type;5807	#define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED    0x0UL5808	#define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL5809	#define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID  0xffUL5810	#define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST    PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID5811	u8	led2_group_id;5812	u8	unused_2;5813	__le16	led2_state_caps;5814	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED                 0x1UL5815	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED           0x2UL5816	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED            0x4UL5817	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED         0x8UL5818	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL5819	__le16	led2_color_caps;5820	#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD                0x1UL5821	#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED     0x2UL5822	#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED     0x4UL5823	u8	led3_id;5824	u8	led3_type;5825	#define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED    0x0UL5826	#define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL5827	#define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID  0xffUL5828	#define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST    PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID5829	u8	led3_group_id;5830	u8	unused_3;5831	__le16	led3_state_caps;5832	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED                 0x1UL5833	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED           0x2UL5834	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED            0x4UL5835	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED         0x8UL5836	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL5837	__le16	led3_color_caps;5838	#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD                0x1UL5839	#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED     0x2UL5840	#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED     0x4UL5841	u8	unused_4[3];5842	u8	valid;5843};5844 5845/* hwrm_port_mac_qcaps_input (size:192b/24B) */5846struct hwrm_port_mac_qcaps_input {5847	__le16	req_type;5848	__le16	cmpl_ring;5849	__le16	seq_id;5850	__le16	target_id;5851	__le64	resp_addr;5852	__le16	port_id;5853	u8	unused_0[6];5854};5855 5856/* hwrm_port_mac_qcaps_output (size:128b/16B) */5857struct hwrm_port_mac_qcaps_output {5858	__le16	error_code;5859	__le16	req_type;5860	__le16	seq_id;5861	__le16	resp_len;5862	u8	flags;5863	#define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED     0x1UL5864	#define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED        0x2UL5865	u8	unused_0[6];5866	u8	valid;5867};5868 5869/* hwrm_queue_qportcfg_input (size:192b/24B) */5870struct hwrm_queue_qportcfg_input {5871	__le16	req_type;5872	__le16	cmpl_ring;5873	__le16	seq_id;5874	__le16	target_id;5875	__le64	resp_addr;5876	__le32	flags;5877	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH     0x1UL5878	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX    0x0UL5879	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX    0x1UL5880	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX5881	__le16	port_id;5882	u8	drv_qmap_cap;5883	#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL5884	#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED  0x1UL5885	#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST    QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED5886	u8	unused_0;5887};5888 5889/* hwrm_queue_qportcfg_output (size:1344b/168B) */5890struct hwrm_queue_qportcfg_output {5891	__le16	error_code;5892	__le16	req_type;5893	__le16	seq_id;5894	__le16	resp_len;5895	u8	max_configurable_queues;5896	u8	max_configurable_lossless_queues;5897	u8	queue_cfg_allowed;5898	u8	queue_cfg_info;5899	#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG             0x1UL5900	#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE     0x2UL5901	u8	queue_pfcenable_cfg_allowed;5902	u8	queue_pri2cos_cfg_allowed;5903	u8	queue_cos2bw_cfg_allowed;5904	u8	queue_id0;5905	u8	queue_id0_service_profile;5906	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY          0x0UL5907	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS       0x1UL5908	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5909	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5910	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5911	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN        0xffUL5912	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN5913	u8	queue_id1;5914	u8	queue_id1_service_profile;5915	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY          0x0UL5916	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS       0x1UL5917	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5918	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5919	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5920	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN        0xffUL5921	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN5922	u8	queue_id2;5923	u8	queue_id2_service_profile;5924	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY          0x0UL5925	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS       0x1UL5926	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5927	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5928	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5929	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN        0xffUL5930	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN5931	u8	queue_id3;5932	u8	queue_id3_service_profile;5933	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY          0x0UL5934	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS       0x1UL5935	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5936	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5937	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5938	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN        0xffUL5939	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN5940	u8	queue_id4;5941	u8	queue_id4_service_profile;5942	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY          0x0UL5943	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS       0x1UL5944	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5945	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5946	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5947	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN        0xffUL5948	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN5949	u8	queue_id5;5950	u8	queue_id5_service_profile;5951	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY          0x0UL5952	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS       0x1UL5953	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5954	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5955	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5956	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN        0xffUL5957	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN5958	u8	queue_id6;5959	u8	queue_id6_service_profile;5960	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY          0x0UL5961	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS       0x1UL5962	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5963	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5964	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5965	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN        0xffUL5966	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN5967	u8	queue_id7;5968	u8	queue_id7_service_profile;5969	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY          0x0UL5970	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS       0x1UL5971	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL5972	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL5973	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL5974	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN        0xffUL5975	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN5976	u8	queue_id0_service_profile_type;5977	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE     0x1UL5978	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC      0x2UL5979	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP      0x4UL5980	char	qid0_name[16];5981	char	qid1_name[16];5982	char	qid2_name[16];5983	char	qid3_name[16];5984	char	qid4_name[16];5985	char	qid5_name[16];5986	char	qid6_name[16];5987	char	qid7_name[16];5988	u8	queue_id1_service_profile_type;5989	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE     0x1UL5990	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC      0x2UL5991	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP      0x4UL5992	u8	queue_id2_service_profile_type;5993	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE     0x1UL5994	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC      0x2UL5995	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP      0x4UL5996	u8	queue_id3_service_profile_type;5997	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE     0x1UL5998	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC      0x2UL5999	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP      0x4UL6000	u8	queue_id4_service_profile_type;6001	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE     0x1UL6002	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC      0x2UL6003	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP      0x4UL6004	u8	queue_id5_service_profile_type;6005	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE     0x1UL6006	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC      0x2UL6007	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP      0x4UL6008	u8	queue_id6_service_profile_type;6009	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE     0x1UL6010	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC      0x2UL6011	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP      0x4UL6012	u8	queue_id7_service_profile_type;6013	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE     0x1UL6014	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC      0x2UL6015	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP      0x4UL6016	u8	valid;6017};6018 6019/* hwrm_queue_qcfg_input (size:192b/24B) */6020struct hwrm_queue_qcfg_input {6021	__le16	req_type;6022	__le16	cmpl_ring;6023	__le16	seq_id;6024	__le16	target_id;6025	__le64	resp_addr;6026	__le32	flags;6027	#define QUEUE_QCFG_REQ_FLAGS_PATH     0x1UL6028	#define QUEUE_QCFG_REQ_FLAGS_PATH_TX    0x0UL6029	#define QUEUE_QCFG_REQ_FLAGS_PATH_RX    0x1UL6030	#define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX6031	__le32	queue_id;6032};6033 6034/* hwrm_queue_qcfg_output (size:128b/16B) */6035struct hwrm_queue_qcfg_output {6036	__le16	error_code;6037	__le16	req_type;6038	__le16	seq_id;6039	__le16	resp_len;6040	__le32	queue_len;6041	u8	service_profile;6042	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY    0x0UL6043	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL6044	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN  0xffUL6045	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST    QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN6046	u8	queue_cfg_info;6047	#define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL6048	u8	unused_0;6049	u8	valid;6050};6051 6052/* hwrm_queue_cfg_input (size:320b/40B) */6053struct hwrm_queue_cfg_input {6054	__le16	req_type;6055	__le16	cmpl_ring;6056	__le16	seq_id;6057	__le16	target_id;6058	__le64	resp_addr;6059	__le32	flags;6060	#define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL6061	#define QUEUE_CFG_REQ_FLAGS_PATH_SFT  06062	#define QUEUE_CFG_REQ_FLAGS_PATH_TX     0x0UL6063	#define QUEUE_CFG_REQ_FLAGS_PATH_RX     0x1UL6064	#define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL6065	#define QUEUE_CFG_REQ_FLAGS_PATH_LAST  QUEUE_CFG_REQ_FLAGS_PATH_BIDIR6066	__le32	enables;6067	#define QUEUE_CFG_REQ_ENABLES_DFLT_LEN            0x1UL6068	#define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE     0x2UL6069	__le32	queue_id;6070	__le32	dflt_len;6071	u8	service_profile;6072	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY    0x0UL6073	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL6074	#define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN  0xffUL6075	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST    QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN6076	u8	unused_0[7];6077};6078 6079/* hwrm_queue_cfg_output (size:128b/16B) */6080struct hwrm_queue_cfg_output {6081	__le16	error_code;6082	__le16	req_type;6083	__le16	seq_id;6084	__le16	resp_len;6085	u8	unused_0[7];6086	u8	valid;6087};6088 6089/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */6090struct hwrm_queue_pfcenable_qcfg_input {6091	__le16	req_type;6092	__le16	cmpl_ring;6093	__le16	seq_id;6094	__le16	target_id;6095	__le64	resp_addr;6096	__le16	port_id;6097	u8	unused_0[6];6098};6099 6100/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */6101struct hwrm_queue_pfcenable_qcfg_output {6102	__le16	error_code;6103	__le16	req_type;6104	__le16	seq_id;6105	__le16	resp_len;6106	__le32	flags;6107	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED              0x1UL6108	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED              0x2UL6109	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED              0x4UL6110	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED              0x8UL6111	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED              0x10UL6112	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED              0x20UL6113	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED              0x40UL6114	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED              0x80UL6115	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED     0x100UL6116	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED     0x200UL6117	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED     0x400UL6118	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED     0x800UL6119	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED     0x1000UL6120	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED     0x2000UL6121	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED     0x4000UL6122	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED     0x8000UL6123	u8	unused_0[3];6124	u8	valid;6125};6126 6127/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */6128struct hwrm_queue_pfcenable_cfg_input {6129	__le16	req_type;6130	__le16	cmpl_ring;6131	__le16	seq_id;6132	__le16	target_id;6133	__le64	resp_addr;6134	__le32	flags;6135	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED              0x1UL6136	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED              0x2UL6137	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED              0x4UL6138	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED              0x8UL6139	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED              0x10UL6140	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED              0x20UL6141	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED              0x40UL6142	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED              0x80UL6143	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED     0x100UL6144	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED     0x200UL6145	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED     0x400UL6146	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED     0x800UL6147	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED     0x1000UL6148	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED     0x2000UL6149	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED     0x4000UL6150	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED     0x8000UL6151	__le16	port_id;6152	u8	unused_0[2];6153};6154 6155/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */6156struct hwrm_queue_pfcenable_cfg_output {6157	__le16	error_code;6158	__le16	req_type;6159	__le16	seq_id;6160	__le16	resp_len;6161	u8	unused_0[7];6162	u8	valid;6163};6164 6165/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */6166struct hwrm_queue_pri2cos_qcfg_input {6167	__le16	req_type;6168	__le16	cmpl_ring;6169	__le16	seq_id;6170	__le16	target_id;6171	__le64	resp_addr;6172	__le32	flags;6173	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH      0x1UL6174	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX     0x0UL6175	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX     0x1UL6176	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX6177	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN     0x2UL6178	u8	port_id;6179	u8	unused_0[3];6180};6181 6182/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */6183struct hwrm_queue_pri2cos_qcfg_output {6184	__le16	error_code;6185	__le16	req_type;6186	__le16	seq_id;6187	__le16	resp_len;6188	u8	pri0_cos_queue_id;6189	u8	pri1_cos_queue_id;6190	u8	pri2_cos_queue_id;6191	u8	pri3_cos_queue_id;6192	u8	pri4_cos_queue_id;6193	u8	pri5_cos_queue_id;6194	u8	pri6_cos_queue_id;6195	u8	pri7_cos_queue_id;6196	u8	queue_cfg_info;6197	#define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL6198	u8	unused_0[6];6199	u8	valid;6200};6201 6202/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */6203struct hwrm_queue_pri2cos_cfg_input {6204	__le16	req_type;6205	__le16	cmpl_ring;6206	__le16	seq_id;6207	__le16	target_id;6208	__le64	resp_addr;6209	__le32	flags;6210	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL6211	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT  06212	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX     0x0UL6213	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX     0x1UL6214	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL6215	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR6216	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN     0x4UL6217	__le32	enables;6218	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID     0x1UL6219	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID     0x2UL6220	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID     0x4UL6221	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID     0x8UL6222	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID     0x10UL6223	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID     0x20UL6224	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID     0x40UL6225	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID     0x80UL6226	u8	port_id;6227	u8	pri0_cos_queue_id;6228	u8	pri1_cos_queue_id;6229	u8	pri2_cos_queue_id;6230	u8	pri3_cos_queue_id;6231	u8	pri4_cos_queue_id;6232	u8	pri5_cos_queue_id;6233	u8	pri6_cos_queue_id;6234	u8	pri7_cos_queue_id;6235	u8	unused_0[7];6236};6237 6238/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */6239struct hwrm_queue_pri2cos_cfg_output {6240	__le16	error_code;6241	__le16	req_type;6242	__le16	seq_id;6243	__le16	resp_len;6244	u8	unused_0[7];6245	u8	valid;6246};6247 6248/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */6249struct hwrm_queue_cos2bw_qcfg_input {6250	__le16	req_type;6251	__le16	cmpl_ring;6252	__le16	seq_id;6253	__le16	target_id;6254	__le64	resp_addr;6255	__le16	port_id;6256	u8	unused_0[6];6257};6258 6259/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */6260struct hwrm_queue_cos2bw_qcfg_output {6261	__le16	error_code;6262	__le16	req_type;6263	__le16	seq_id;6264	__le16	resp_len;6265	u8	queue_id0;6266	u8	unused_0;6267	__le16	unused_1;6268	__le32	queue_id0_min_bw;6269	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL6270	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              06271	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL6272	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)6273	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)6274	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES6275	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6276	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         296277	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6278	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6279	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6280	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6281	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6282	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6283	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID6284	__le32	queue_id0_max_bw;6285	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL6286	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              06287	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL6288	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)6289	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)6290	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES6291	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6292	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         296293	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6294	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6295	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6296	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6297	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6298	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6299	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID6300	u8	queue_id0_tsa_assign;6301	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL6302	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL6303	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL6304	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL6305	u8	queue_id0_pri_lvl;6306	u8	queue_id0_bw_weight;6307	struct {6308		u8	queue_id;6309		__le32	queue_id_min_bw;6310	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK             0xfffffffUL6311	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT              06312	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE                     0x10000000UL6313	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS                  (0x0UL << 28)6314	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES                 (0x1UL << 28)6315	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES6316	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6317	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT         296318	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6319	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6320	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6321	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6322	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6323	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6324	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID6325		__le32	queue_id_max_bw;6326	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK             0xfffffffUL6327	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT              06328	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE                     0x10000000UL6329	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS                  (0x0UL << 28)6330	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES                 (0x1UL << 28)6331	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES6332	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6333	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT         296334	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6335	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6336	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6337	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6338	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6339	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6340	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID6341		u8	queue_id_tsa_assign;6342	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP             0x0UL6343	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS            0x1UL6344	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL6345	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST  0xffUL6346		u8	queue_id_pri_lvl;6347		u8	queue_id_bw_weight;6348	} __packed cfg[7];6349	u8	unused_2[4];6350	u8	valid;6351};6352 6353/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */6354struct hwrm_queue_cos2bw_cfg_input {6355	__le16	req_type;6356	__le16	cmpl_ring;6357	__le16	seq_id;6358	__le16	target_id;6359	__le64	resp_addr;6360	__le32	flags;6361	__le32	enables;6362	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID     0x1UL6363	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID     0x2UL6364	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID     0x4UL6365	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID     0x8UL6366	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID     0x10UL6367	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID     0x20UL6368	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID     0x40UL6369	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID     0x80UL6370	__le16	port_id;6371	u8	queue_id0;6372	u8	unused_0;6373	__le32	queue_id0_min_bw;6374	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL6375	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              06376	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL6377	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)6378	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)6379	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES6380	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6381	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         296382	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6383	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6384	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6385	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6386	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6387	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6388	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID6389	__le32	queue_id0_max_bw;6390	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL6391	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              06392	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL6393	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)6394	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)6395	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES6396	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6397	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         296398	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6399	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6400	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6401	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6402	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6403	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6404	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID6405	u8	queue_id0_tsa_assign;6406	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL6407	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL6408	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL6409	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL6410	u8	queue_id0_pri_lvl;6411	u8	queue_id0_bw_weight;6412	struct {6413		u8	queue_id;6414		__le32	queue_id_min_bw;6415	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK             0xfffffffUL6416	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT              06417	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE                     0x10000000UL6418	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS                  (0x0UL << 28)6419	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES                 (0x1UL << 28)6420	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES6421	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6422	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT         296423	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6424	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6425	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6426	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6427	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6428	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6429	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID6430		__le32	queue_id_max_bw;6431	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK             0xfffffffUL6432	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT              06433	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE                     0x10000000UL6434	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS                  (0x0UL << 28)6435	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES                 (0x1UL << 28)6436	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES6437	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL6438	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT         296439	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)6440	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)6441	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)6442	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)6443	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)6444	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)6445	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID6446		u8	queue_id_tsa_assign;6447	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP             0x0UL6448	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS            0x1UL6449	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL6450	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST  0xffUL6451		u8	queue_id_pri_lvl;6452		u8	queue_id_bw_weight;6453	} __packed cfg[7];6454	u8	unused_1[5];6455};6456 6457/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */6458struct hwrm_queue_cos2bw_cfg_output {6459	__le16	error_code;6460	__le16	req_type;6461	__le16	seq_id;6462	__le16	resp_len;6463	u8	unused_0[7];6464	u8	valid;6465};6466 6467/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */6468struct hwrm_queue_dscp_qcaps_input {6469	__le16	req_type;6470	__le16	cmpl_ring;6471	__le16	seq_id;6472	__le16	target_id;6473	__le64	resp_addr;6474	u8	port_id;6475	u8	unused_0[7];6476};6477 6478/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */6479struct hwrm_queue_dscp_qcaps_output {6480	__le16	error_code;6481	__le16	req_type;6482	__le16	seq_id;6483	__le16	resp_len;6484	u8	num_dscp_bits;6485	u8	unused_0;6486	__le16	max_entries;6487	u8	unused_1[3];6488	u8	valid;6489};6490 6491/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */6492struct hwrm_queue_dscp2pri_qcfg_input {6493	__le16	req_type;6494	__le16	cmpl_ring;6495	__le16	seq_id;6496	__le16	target_id;6497	__le64	resp_addr;6498	__le64	dest_data_addr;6499	u8	port_id;6500	u8	unused_0;6501	__le16	dest_data_buffer_size;6502	u8	unused_1[4];6503};6504 6505/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */6506struct hwrm_queue_dscp2pri_qcfg_output {6507	__le16	error_code;6508	__le16	req_type;6509	__le16	seq_id;6510	__le16	resp_len;6511	__le16	entry_cnt;6512	u8	default_pri;6513	u8	unused_0[4];6514	u8	valid;6515};6516 6517/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */6518struct hwrm_queue_dscp2pri_cfg_input {6519	__le16	req_type;6520	__le16	cmpl_ring;6521	__le16	seq_id;6522	__le16	target_id;6523	__le64	resp_addr;6524	__le64	src_data_addr;6525	__le32	flags;6526	#define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI     0x1UL6527	__le32	enables;6528	#define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI     0x1UL6529	u8	port_id;6530	u8	default_pri;6531	__le16	entry_cnt;6532	u8	unused_0[4];6533};6534 6535/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */6536struct hwrm_queue_dscp2pri_cfg_output {6537	__le16	error_code;6538	__le16	req_type;6539	__le16	seq_id;6540	__le16	resp_len;6541	u8	unused_0[7];6542	u8	valid;6543};6544 6545/* hwrm_vnic_alloc_input (size:192b/24B) */6546struct hwrm_vnic_alloc_input {6547	__le16	req_type;6548	__le16	cmpl_ring;6549	__le16	seq_id;6550	__le16	target_id;6551	__le64	resp_addr;6552	__le32	flags;6553	#define VNIC_ALLOC_REQ_FLAGS_DEFAULT                  0x1UL6554	#define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID     0x2UL6555	__le16	virtio_net_fid;6556	u8	unused_0[2];6557};6558 6559/* hwrm_vnic_alloc_output (size:128b/16B) */6560struct hwrm_vnic_alloc_output {6561	__le16	error_code;6562	__le16	req_type;6563	__le16	seq_id;6564	__le16	resp_len;6565	__le32	vnic_id;6566	u8	unused_0[3];6567	u8	valid;6568};6569 6570/* hwrm_vnic_update_input (size:256b/32B) */6571struct hwrm_vnic_update_input {6572	__le16	req_type;6573	__le16	cmpl_ring;6574	__le16	seq_id;6575	__le16	target_id;6576	__le64	resp_addr;6577	__le32	vnic_id;6578	__le32	enables;6579	#define VNIC_UPDATE_REQ_ENABLES_VNIC_STATE_VALID               0x1UL6580	#define VNIC_UPDATE_REQ_ENABLES_MRU_VALID                      0x2UL6581	#define VNIC_UPDATE_REQ_ENABLES_METADATA_FORMAT_TYPE_VALID     0x4UL6582	u8	vnic_state;6583	#define VNIC_UPDATE_REQ_VNIC_STATE_NORMAL 0x0UL6584	#define VNIC_UPDATE_REQ_VNIC_STATE_DROP   0x1UL6585	#define VNIC_UPDATE_REQ_VNIC_STATE_LAST  VNIC_UPDATE_REQ_VNIC_STATE_DROP6586	u8	metadata_format_type;6587	#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_0 0x0UL6588	#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_1 0x1UL6589	#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_2 0x2UL6590	#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_3 0x3UL6591	#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 0x4UL6592	#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_LAST VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_46593	__le16	mru;6594	u8	unused_1[4];6595};6596 6597/* hwrm_vnic_update_output (size:128b/16B) */6598struct hwrm_vnic_update_output {6599	__le16	error_code;6600	__le16	req_type;6601	__le16	seq_id;6602	__le16	resp_len;6603	u8	unused_0[7];6604	u8	valid;6605};6606 6607/* hwrm_vnic_free_input (size:192b/24B) */6608struct hwrm_vnic_free_input {6609	__le16	req_type;6610	__le16	cmpl_ring;6611	__le16	seq_id;6612	__le16	target_id;6613	__le64	resp_addr;6614	__le32	vnic_id;6615	u8	unused_0[4];6616};6617 6618/* hwrm_vnic_free_output (size:128b/16B) */6619struct hwrm_vnic_free_output {6620	__le16	error_code;6621	__le16	req_type;6622	__le16	seq_id;6623	__le16	resp_len;6624	u8	unused_0[7];6625	u8	valid;6626};6627 6628/* hwrm_vnic_cfg_input (size:384b/48B) */6629struct hwrm_vnic_cfg_input {6630	__le16	req_type;6631	__le16	cmpl_ring;6632	__le16	seq_id;6633	__le16	target_id;6634	__le64	resp_addr;6635	__le32	flags;6636	#define VNIC_CFG_REQ_FLAGS_DEFAULT                              0x1UL6637	#define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE                      0x2UL6638	#define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE                        0x4UL6639	#define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE                  0x8UL6640	#define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE                  0x10UL6641	#define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE                     0x20UL6642	#define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE     0x40UL6643	#define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE                 0x80UL6644	__le32	enables;6645	#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP            0x1UL6646	#define VNIC_CFG_REQ_ENABLES_RSS_RULE                 0x2UL6647	#define VNIC_CFG_REQ_ENABLES_COS_RULE                 0x4UL6648	#define VNIC_CFG_REQ_ENABLES_LB_RULE                  0x8UL6649	#define VNIC_CFG_REQ_ENABLES_MRU                      0x10UL6650	#define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID       0x20UL6651	#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID     0x40UL6652	#define VNIC_CFG_REQ_ENABLES_QUEUE_ID                 0x80UL6653	#define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE          0x100UL6654	#define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE              0x200UL6655	__le16	vnic_id;6656	__le16	dflt_ring_grp;6657	__le16	rss_rule;6658	__le16	cos_rule;6659	__le16	lb_rule;6660	__le16	mru;6661	__le16	default_rx_ring_id;6662	__le16	default_cmpl_ring_id;6663	__le16	queue_id;6664	u8	rx_csum_v2_mode;6665	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL6666	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK  0x1UL6667	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX     0x2UL6668	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST   VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX6669	u8	l2_cqe_mode;6670	#define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT    0x0UL6671	#define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL6672	#define VNIC_CFG_REQ_L2_CQE_MODE_MIXED      0x2UL6673	#define VNIC_CFG_REQ_L2_CQE_MODE_LAST      VNIC_CFG_REQ_L2_CQE_MODE_MIXED6674	u8	unused0[4];6675};6676 6677/* hwrm_vnic_cfg_output (size:128b/16B) */6678struct hwrm_vnic_cfg_output {6679	__le16	error_code;6680	__le16	req_type;6681	__le16	seq_id;6682	__le16	resp_len;6683	u8	unused_0[7];6684	u8	valid;6685};6686 6687/* hwrm_vnic_qcaps_input (size:192b/24B) */6688struct hwrm_vnic_qcaps_input {6689	__le16	req_type;6690	__le16	cmpl_ring;6691	__le16	seq_id;6692	__le16	target_id;6693	__le64	resp_addr;6694	__le32	enables;6695	u8	unused_0[4];6696};6697 6698/* hwrm_vnic_qcaps_output (size:192b/24B) */6699struct hwrm_vnic_qcaps_output {6700	__le16	error_code;6701	__le16	req_type;6702	__le16	seq_id;6703	__le16	resp_len;6704	__le16	mru;6705	u8	unused_0[2];6706	__le32	flags;6707	#define VNIC_QCAPS_RESP_FLAGS_UNUSED                                  0x1UL6708	#define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP                          0x2UL6709	#define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP                            0x4UL6710	#define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP                      0x8UL6711	#define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP                      0x10UL6712	#define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP                         0x20UL6713	#define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP         0x40UL6714	#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP                       0x80UL6715	#define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP                      0x100UL6716	#define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP                          0x200UL6717	#define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP                          0x400UL6718	#define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP               0x800UL6719	#define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP                     0x1000UL6720	#define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP                0x2000UL6721	#define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP                 0x4000UL6722	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP           0x8000UL6723	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP                0x10000UL6724	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP     0x20000UL6725	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP                 0x40000UL6726	#define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP                          0x80000UL6727	#define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP                         0x100000UL6728	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP               0x200000UL6729	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP              0x400000UL6730	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP               0x800000UL6731	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP              0x1000000UL6732	#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP            0x2000000UL6733	#define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE                    0x4000000UL6734	#define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED              0x8000000UL6735	#define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP                  0x10000000UL6736	#define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP                       0x20000000UL6737	#define VNIC_QCAPS_RESP_FLAGS_RE_FLUSH_CAP                            0x40000000UL6738	__le16	max_aggs_supported;6739	u8	unused_1[5];6740	u8	valid;6741};6742 6743/* hwrm_vnic_tpa_cfg_input (size:384b/48B) */6744struct hwrm_vnic_tpa_cfg_input {6745	__le16	req_type;6746	__le16	cmpl_ring;6747	__le16	seq_id;6748	__le16	target_id;6749	__le64	resp_addr;6750	__le32	flags;6751	#define VNIC_TPA_CFG_REQ_FLAGS_TPA                       0x1UL6752	#define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA                 0x2UL6753	#define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE            0x4UL6754	#define VNIC_TPA_CFG_REQ_FLAGS_GRO                       0x8UL6755	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN              0x10UL6756	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL6757	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK            0x40UL6758	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK             0x80UL6759	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO           0x100UL6760	__le32	enables;6761	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS      0x1UL6762	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS          0x2UL6763	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER     0x4UL6764	#define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN       0x8UL6765	#define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN        0x10UL6766	__le16	vnic_id;6767	__le16	max_agg_segs;6768	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1   0x0UL6769	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2   0x1UL6770	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4   0x2UL6771	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8   0x3UL6772	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL6773	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX6774	__le16	max_aggs;6775	#define VNIC_TPA_CFG_REQ_MAX_AGGS_1   0x0UL6776	#define VNIC_TPA_CFG_REQ_MAX_AGGS_2   0x1UL6777	#define VNIC_TPA_CFG_REQ_MAX_AGGS_4   0x2UL6778	#define VNIC_TPA_CFG_REQ_MAX_AGGS_8   0x3UL6779	#define VNIC_TPA_CFG_REQ_MAX_AGGS_16  0x4UL6780	#define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL6781	#define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX6782	u8	unused_0[2];6783	__le32	max_agg_timer;6784	__le32	min_agg_len;6785	__le32	tnl_tpa_en_bitmap;6786	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN           0x1UL6787	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE          0x2UL6788	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE           0x4UL6789	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE             0x8UL6790	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4            0x10UL6791	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6            0x20UL6792	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE       0x40UL6793	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1     0x80UL6794	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1       0x100UL6795	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1           0x200UL6796	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2           0x400UL6797	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3           0x800UL6798	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4           0x1000UL6799	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5           0x2000UL6800	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6           0x4000UL6801	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7           0x8000UL6802	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8           0x10000UL6803	u8	unused_1[4];6804};6805 6806/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */6807struct hwrm_vnic_tpa_cfg_output {6808	__le16	error_code;6809	__le16	req_type;6810	__le16	seq_id;6811	__le16	resp_len;6812	u8	unused_0[7];6813	u8	valid;6814};6815 6816/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */6817struct hwrm_vnic_tpa_qcfg_input {6818	__le16	req_type;6819	__le16	cmpl_ring;6820	__le16	seq_id;6821	__le16	target_id;6822	__le64	resp_addr;6823	__le16	vnic_id;6824	u8	unused_0[6];6825};6826 6827/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */6828struct hwrm_vnic_tpa_qcfg_output {6829	__le16	error_code;6830	__le16	req_type;6831	__le16	seq_id;6832	__le16	resp_len;6833	__le32	flags;6834	#define VNIC_TPA_QCFG_RESP_FLAGS_TPA                       0x1UL6835	#define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA                 0x2UL6836	#define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE            0x4UL6837	#define VNIC_TPA_QCFG_RESP_FLAGS_GRO                       0x8UL6838	#define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN              0x10UL6839	#define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL6840	#define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK            0x40UL6841	#define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK             0x80UL6842	__le16	max_agg_segs;6843	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1   0x0UL6844	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2   0x1UL6845	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4   0x2UL6846	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8   0x3UL6847	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL6848	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX6849	__le16	max_aggs;6850	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_1   0x0UL6851	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_2   0x1UL6852	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_4   0x2UL6853	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_8   0x3UL6854	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_16  0x4UL6855	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL6856	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX6857	__le32	max_agg_timer;6858	__le32	min_agg_len;6859	__le32	tnl_tpa_en_bitmap;6860	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN           0x1UL6861	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE          0x2UL6862	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE           0x4UL6863	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE             0x8UL6864	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4            0x10UL6865	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6            0x20UL6866	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE       0x40UL6867	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1     0x80UL6868	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1       0x100UL6869	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1           0x200UL6870	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2           0x400UL6871	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3           0x800UL6872	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4           0x1000UL6873	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5           0x2000UL6874	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6           0x4000UL6875	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7           0x8000UL6876	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8           0x10000UL6877	u8	unused_0[3];6878	u8	valid;6879};6880 6881/* hwrm_vnic_rss_cfg_input (size:384b/48B) */6882struct hwrm_vnic_rss_cfg_input {6883	__le16	req_type;6884	__le16	cmpl_ring;6885	__le16	seq_id;6886	__le16	target_id;6887	__le64	resp_addr;6888	__le32	hash_type;6889	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4                0x1UL6890	#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4            0x2UL6891	#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4            0x4UL6892	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6                0x8UL6893	#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6            0x10UL6894	#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6            0x20UL6895	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL     0x40UL6896	#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4         0x80UL6897	#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4        0x100UL6898	#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6         0x200UL6899	#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6        0x400UL6900	__le16	vnic_id;6901	u8	ring_table_pair_index;6902	u8	hash_mode_flags;6903	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT         0x1UL6904	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4     0x2UL6905	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2     0x4UL6906	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL6907	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL6908	__le64	ring_grp_tbl_addr;6909	__le64	hash_key_tbl_addr;6910	__le16	rss_ctx_idx;6911	u8	flags;6912	#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE               0x1UL6913	#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE               0x2UL6914	#define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT     0x4UL6915	u8	ring_select_mode;6916	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ          0x0UL6917	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR               0x1UL6918	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL6919	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST             VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM6920	u8	unused_1[4];6921};6922 6923/* hwrm_vnic_rss_cfg_output (size:128b/16B) */6924struct hwrm_vnic_rss_cfg_output {6925	__le16	error_code;6926	__le16	req_type;6927	__le16	seq_id;6928	__le16	resp_len;6929	u8	unused_0[7];6930	u8	valid;6931};6932 6933/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */6934struct hwrm_vnic_rss_cfg_cmd_err {6935	u8	code;6936	#define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN             0x0UL6937	#define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL6938	#define VNIC_RSS_CFG_CMD_ERR_CODE_LAST               VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY6939	u8	unused_0[7];6940};6941 6942/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */6943struct hwrm_vnic_rss_qcfg_input {6944	__le16	req_type;6945	__le16	cmpl_ring;6946	__le16	seq_id;6947	__le16	target_id;6948	__le64	resp_addr;6949	__le16	rss_ctx_idx;6950	__le16	vnic_id;6951	u8	unused_0[4];6952};6953 6954/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */6955struct hwrm_vnic_rss_qcfg_output {6956	__le16	error_code;6957	__le16	req_type;6958	__le16	seq_id;6959	__le16	resp_len;6960	__le32	hash_type;6961	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4                0x1UL6962	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4            0x2UL6963	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4            0x4UL6964	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6                0x8UL6965	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6            0x10UL6966	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6            0x20UL6967	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL     0x40UL6968	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4         0x80UL6969	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4        0x100UL6970	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6         0x200UL6971	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6        0x400UL6972	u8	unused_0[4];6973	__le32	hash_key[10];6974	u8	hash_mode_flags;6975	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT         0x1UL6976	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4     0x2UL6977	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2     0x4UL6978	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL6979	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL6980	u8	ring_select_mode;6981	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ          0x0UL6982	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR               0x1UL6983	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL6984	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST             VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM6985	u8	unused_1[5];6986	u8	valid;6987};6988 6989/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */6990struct hwrm_vnic_plcmodes_cfg_input {6991	__le16	req_type;6992	__le16	cmpl_ring;6993	__le16	seq_id;6994	__le16	target_id;6995	__le64	resp_addr;6996	__le32	flags;6997	#define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT     0x1UL6998	#define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT       0x2UL6999	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4              0x4UL7000	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6              0x8UL7001	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE              0x10UL7002	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE              0x20UL7003	#define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT      0x40UL7004	__le32	enables;7005	#define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID      0x1UL7006	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID        0x2UL7007	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID     0x4UL7008	#define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID           0x8UL7009	__le32	vnic_id;7010	__le16	jumbo_thresh;7011	__le16	hds_offset;7012	__le16	hds_threshold;7013	__le16	max_bds;7014	u8	unused_0[4];7015};7016 7017/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */7018struct hwrm_vnic_plcmodes_cfg_output {7019	__le16	error_code;7020	__le16	req_type;7021	__le16	seq_id;7022	__le16	resp_len;7023	u8	unused_0[7];7024	u8	valid;7025};7026 7027/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */7028struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {7029	__le16	req_type;7030	__le16	cmpl_ring;7031	__le16	seq_id;7032	__le16	target_id;7033	__le64	resp_addr;7034};7035 7036/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */7037struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {7038	__le16	error_code;7039	__le16	req_type;7040	__le16	seq_id;7041	__le16	resp_len;7042	__le16	rss_cos_lb_ctx_id;7043	u8	unused_0[5];7044	u8	valid;7045};7046 7047/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */7048struct hwrm_vnic_rss_cos_lb_ctx_free_input {7049	__le16	req_type;7050	__le16	cmpl_ring;7051	__le16	seq_id;7052	__le16	target_id;7053	__le64	resp_addr;7054	__le16	rss_cos_lb_ctx_id;7055	u8	unused_0[6];7056};7057 7058/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */7059struct hwrm_vnic_rss_cos_lb_ctx_free_output {7060	__le16	error_code;7061	__le16	req_type;7062	__le16	seq_id;7063	__le16	resp_len;7064	u8	unused_0[7];7065	u8	valid;7066};7067 7068/* hwrm_ring_alloc_input (size:704b/88B) */7069struct hwrm_ring_alloc_input {7070	__le16	req_type;7071	__le16	cmpl_ring;7072	__le16	seq_id;7073	__le16	target_id;7074	__le64	resp_addr;7075	__le32	enables;7076	#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG           0x2UL7077	#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID      0x8UL7078	#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID           0x20UL7079	#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID       0x40UL7080	#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID       0x80UL7081	#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID      0x100UL7082	#define RING_ALLOC_REQ_ENABLES_SCHQ_ID                0x200UL7083	#define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE         0x400UL7084	#define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID     0x800UL7085	u8	ring_type;7086	#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL   0x0UL7087	#define RING_ALLOC_REQ_RING_TYPE_TX        0x1UL7088	#define RING_ALLOC_REQ_RING_TYPE_RX        0x2UL7089	#define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL7090	#define RING_ALLOC_REQ_RING_TYPE_RX_AGG    0x4UL7091	#define RING_ALLOC_REQ_RING_TYPE_NQ        0x5UL7092	#define RING_ALLOC_REQ_RING_TYPE_LAST     RING_ALLOC_REQ_RING_TYPE_NQ7093	u8	cmpl_coal_cnt;7094	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL7095	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4   0x1UL7096	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8   0x2UL7097	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12  0x3UL7098	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16  0x4UL7099	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24  0x5UL7100	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32  0x6UL7101	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48  0x7UL7102	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64  0x8UL7103	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96  0x9UL7104	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL7105	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL7106	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL7107	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL7108	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL7109	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL7110	#define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST    RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX7111	__le16	flags;7112	#define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD                        0x1UL7113	#define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION     0x2UL7114	#define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING                     0x4UL7115	#define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE             0x8UL7116	__le64	page_tbl_addr;7117	__le32	fbo;7118	u8	page_size;7119	u8	page_tbl_depth;7120	__le16	schq_id;7121	__le32	length;7122	__le16	logical_id;7123	__le16	cmpl_ring_id;7124	__le16	queue_id;7125	__le16	rx_buf_size;7126	__le16	rx_ring_id;7127	__le16	nq_ring_id;7128	__le16	ring_arb_cfg;7129	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK      0xfUL7130	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT       07131	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP          0x1UL7132	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ         0x2UL7133	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST       RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ7134	#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK            0xf0UL7135	#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT             47136	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL7137	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 87138	__le16	steering_tag;7139	__le32	reserved3;7140	__le32	stat_ctx_id;7141	__le32	reserved4;7142	__le32	max_bw;7143	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL7144	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT              07145	#define RING_ALLOC_REQ_MAX_BW_SCALE                     0x10000000UL7146	#define RING_ALLOC_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)7147	#define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)7148	#define RING_ALLOC_REQ_MAX_BW_SCALE_LAST                 RING_ALLOC_REQ_MAX_BW_SCALE_BYTES7149	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL7150	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT         297151	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)7152	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)7153	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)7154	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)7155	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)7156	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)7157	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST         RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID7158	u8	int_mode;7159	#define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL7160	#define RING_ALLOC_REQ_INT_MODE_RSVD   0x1UL7161	#define RING_ALLOC_REQ_INT_MODE_MSIX   0x2UL7162	#define RING_ALLOC_REQ_INT_MODE_POLL   0x3UL7163	#define RING_ALLOC_REQ_INT_MODE_LAST  RING_ALLOC_REQ_INT_MODE_POLL7164	u8	mpc_chnls_type;7165	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE     0x0UL7166	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE     0x1UL7167	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA  0x2UL7168	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA  0x3UL7169	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL7170	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST   RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE7171	u8	unused_4[2];7172	__le64	cq_handle;7173};7174 7175/* hwrm_ring_alloc_output (size:128b/16B) */7176struct hwrm_ring_alloc_output {7177	__le16	error_code;7178	__le16	req_type;7179	__le16	seq_id;7180	__le16	resp_len;7181	__le16	ring_id;7182	__le16	logical_ring_id;7183	u8	push_buffer_index;7184	#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL7185	#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL7186	#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST       RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER7187	u8	unused_0[2];7188	u8	valid;7189};7190 7191/* hwrm_ring_free_input (size:256b/32B) */7192struct hwrm_ring_free_input {7193	__le16	req_type;7194	__le16	cmpl_ring;7195	__le16	seq_id;7196	__le16	target_id;7197	__le64	resp_addr;7198	u8	ring_type;7199	#define RING_FREE_REQ_RING_TYPE_L2_CMPL   0x0UL7200	#define RING_FREE_REQ_RING_TYPE_TX        0x1UL7201	#define RING_FREE_REQ_RING_TYPE_RX        0x2UL7202	#define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL7203	#define RING_FREE_REQ_RING_TYPE_RX_AGG    0x4UL7204	#define RING_FREE_REQ_RING_TYPE_NQ        0x5UL7205	#define RING_FREE_REQ_RING_TYPE_LAST     RING_FREE_REQ_RING_TYPE_NQ7206	u8	flags;7207	#define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL7208	#define RING_FREE_REQ_FLAGS_LAST             RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID7209	__le16	ring_id;7210	__le32	prod_idx;7211	__le32	opaque;7212	__le32	unused_1;7213};7214 7215/* hwrm_ring_free_output (size:128b/16B) */7216struct hwrm_ring_free_output {7217	__le16	error_code;7218	__le16	req_type;7219	__le16	seq_id;7220	__le16	resp_len;7221	u8	unused_0[7];7222	u8	valid;7223};7224 7225/* hwrm_ring_reset_input (size:192b/24B) */7226struct hwrm_ring_reset_input {7227	__le16	req_type;7228	__le16	cmpl_ring;7229	__le16	seq_id;7230	__le16	target_id;7231	__le64	resp_addr;7232	u8	ring_type;7233	#define RING_RESET_REQ_RING_TYPE_L2_CMPL     0x0UL7234	#define RING_RESET_REQ_RING_TYPE_TX          0x1UL7235	#define RING_RESET_REQ_RING_TYPE_RX          0x2UL7236	#define RING_RESET_REQ_RING_TYPE_ROCE_CMPL   0x3UL7237	#define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL7238	#define RING_RESET_REQ_RING_TYPE_LAST       RING_RESET_REQ_RING_TYPE_RX_RING_GRP7239	u8	unused_0;7240	__le16	ring_id;7241	u8	unused_1[4];7242};7243 7244/* hwrm_ring_reset_output (size:128b/16B) */7245struct hwrm_ring_reset_output {7246	__le16	error_code;7247	__le16	req_type;7248	__le16	seq_id;7249	__le16	resp_len;7250	u8	push_buffer_index;7251	#define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL7252	#define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL7253	#define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST       RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER7254	u8	unused_0[3];7255	u8	consumer_idx[3];7256	u8	valid;7257};7258 7259/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */7260struct hwrm_ring_aggint_qcaps_input {7261	__le16	req_type;7262	__le16	cmpl_ring;7263	__le16	seq_id;7264	__le16	target_id;7265	__le64	resp_addr;7266};7267 7268/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */7269struct hwrm_ring_aggint_qcaps_output {7270	__le16	error_code;7271	__le16	req_type;7272	__le16	seq_id;7273	__le16	resp_len;7274	__le32	cmpl_params;7275	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN                  0x1UL7276	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX                  0x2UL7277	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET                      0x4UL7278	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE                        0x8UL7279	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR                0x10UL7280	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT     0x20UL7281	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR                0x40UL7282	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT     0x80UL7283	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT                0x100UL7284	__le32	nq_params;7285	#define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN     0x1UL7286	__le16	num_cmpl_dma_aggr_min;7287	__le16	num_cmpl_dma_aggr_max;7288	__le16	num_cmpl_dma_aggr_during_int_min;7289	__le16	num_cmpl_dma_aggr_during_int_max;7290	__le16	cmpl_aggr_dma_tmr_min;7291	__le16	cmpl_aggr_dma_tmr_max;7292	__le16	cmpl_aggr_dma_tmr_during_int_min;7293	__le16	cmpl_aggr_dma_tmr_during_int_max;7294	__le16	int_lat_tmr_min_min;7295	__le16	int_lat_tmr_min_max;7296	__le16	int_lat_tmr_max_min;7297	__le16	int_lat_tmr_max_max;7298	__le16	num_cmpl_aggr_int_min;7299	__le16	num_cmpl_aggr_int_max;7300	__le16	timer_units;7301	u8	unused_0[1];7302	u8	valid;7303};7304 7305/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */7306struct hwrm_ring_cmpl_ring_qaggint_params_input {7307	__le16	req_type;7308	__le16	cmpl_ring;7309	__le16	seq_id;7310	__le16	target_id;7311	__le64	resp_addr;7312	__le16	ring_id;7313	__le16	flags;7314	#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL7315	#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 07316	#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ        0x4UL7317	u8	unused_0[4];7318};7319 7320/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */7321struct hwrm_ring_cmpl_ring_qaggint_params_output {7322	__le16	error_code;7323	__le16	req_type;7324	__le16	seq_id;7325	__le16	resp_len;7326	__le16	flags;7327	#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET     0x1UL7328	#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE       0x2UL7329	__le16	num_cmpl_dma_aggr;7330	__le16	num_cmpl_dma_aggr_during_int;7331	__le16	cmpl_aggr_dma_tmr;7332	__le16	cmpl_aggr_dma_tmr_during_int;7333	__le16	int_lat_tmr_min;7334	__le16	int_lat_tmr_max;7335	__le16	num_cmpl_aggr_int;7336	u8	unused_0[7];7337	u8	valid;7338};7339 7340/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */7341struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {7342	__le16	req_type;7343	__le16	cmpl_ring;7344	__le16	seq_id;7345	__le16	target_id;7346	__le64	resp_addr;7347	__le16	ring_id;7348	__le16	flags;7349	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET     0x1UL7350	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE       0x2UL7351	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ           0x4UL7352	__le16	num_cmpl_dma_aggr;7353	__le16	num_cmpl_dma_aggr_during_int;7354	__le16	cmpl_aggr_dma_tmr;7355	__le16	cmpl_aggr_dma_tmr_during_int;7356	__le16	int_lat_tmr_min;7357	__le16	int_lat_tmr_max;7358	__le16	num_cmpl_aggr_int;7359	__le16	enables;7360	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR                0x1UL7361	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT     0x2UL7362	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR                0x4UL7363	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN                  0x8UL7364	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX                  0x10UL7365	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT                0x20UL7366	u8	unused_0[4];7367};7368 7369/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */7370struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {7371	__le16	error_code;7372	__le16	req_type;7373	__le16	seq_id;7374	__le16	resp_len;7375	u8	unused_0[7];7376	u8	valid;7377};7378 7379/* hwrm_ring_grp_alloc_input (size:192b/24B) */7380struct hwrm_ring_grp_alloc_input {7381	__le16	req_type;7382	__le16	cmpl_ring;7383	__le16	seq_id;7384	__le16	target_id;7385	__le64	resp_addr;7386	__le16	cr;7387	__le16	rr;7388	__le16	ar;7389	__le16	sc;7390};7391 7392/* hwrm_ring_grp_alloc_output (size:128b/16B) */7393struct hwrm_ring_grp_alloc_output {7394	__le16	error_code;7395	__le16	req_type;7396	__le16	seq_id;7397	__le16	resp_len;7398	__le32	ring_group_id;7399	u8	unused_0[3];7400	u8	valid;7401};7402 7403/* hwrm_ring_grp_free_input (size:192b/24B) */7404struct hwrm_ring_grp_free_input {7405	__le16	req_type;7406	__le16	cmpl_ring;7407	__le16	seq_id;7408	__le16	target_id;7409	__le64	resp_addr;7410	__le32	ring_group_id;7411	u8	unused_0[4];7412};7413 7414/* hwrm_ring_grp_free_output (size:128b/16B) */7415struct hwrm_ring_grp_free_output {7416	__le16	error_code;7417	__le16	req_type;7418	__le16	seq_id;7419	__le16	resp_len;7420	u8	unused_0[7];7421	u8	valid;7422};7423 7424#define DEFAULT_FLOW_ID 0xFFFFFFFFUL7425#define ROCEV1_FLOW_ID 0xFFFFFFFEUL7426#define ROCEV2_FLOW_ID 0xFFFFFFFDUL7427#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL7428 7429/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */7430struct hwrm_cfa_l2_filter_alloc_input {7431	__le16	req_type;7432	__le16	cmpl_ring;7433	__le16	seq_id;7434	__le16	target_id;7435	__le64	resp_addr;7436	__le32	flags;7437	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH              0x1UL7438	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX             0x0UL7439	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX             0x1UL7440	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX7441	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK          0x2UL7442	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP              0x4UL7443	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST         0x8UL7444	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK      0x30UL7445	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT       47446	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 4)7447	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 4)7448	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 4)7449	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE7450	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE       0x40UL7451	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID      0x80UL7452	__le32	enables;7453	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR             0x1UL7454	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK        0x2UL7455	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN            0x4UL7456	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK       0x8UL7457	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN            0x10UL7458	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK       0x20UL7459	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR           0x40UL7460	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK      0x80UL7461	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN          0x100UL7462	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK     0x200UL7463	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN          0x400UL7464	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK     0x800UL7465	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE            0x1000UL7466	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID              0x2000UL7467	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE         0x4000UL7468	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID              0x8000UL7469	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID      0x10000UL7470	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS           0x20000UL7471	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS         0x40000UL7472	u8	l2_addr[6];7473	u8	num_vlans;7474	u8	t_num_vlans;7475	u8	l2_addr_mask[6];7476	__le16	l2_ovlan;7477	__le16	l2_ovlan_mask;7478	__le16	l2_ivlan;7479	__le16	l2_ivlan_mask;7480	u8	unused_1[2];7481	u8	t_l2_addr[6];7482	u8	unused_2[2];7483	u8	t_l2_addr_mask[6];7484	__le16	t_l2_ovlan;7485	__le16	t_l2_ovlan_mask;7486	__le16	t_l2_ivlan;7487	__le16	t_l2_ivlan_mask;7488	u8	src_type;7489	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL7490	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF    0x1UL7491	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF    0x2UL7492	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC  0x3UL7493	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG  0x4UL7494	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE   0x5UL7495	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO  0x6UL7496	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG  0x7UL7497	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG7498	u8	unused_3;7499	__le32	src_id;7500	u8	tunnel_type;7501	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL7502	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL7503	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL7504	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL7505	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL7506	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL7507	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL7508	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL7509	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL7510	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL7511	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL7512	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL7513	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL7514	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL7515	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL7516	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL7517	u8	unused_4;7518	__le16	dst_id;7519	__le16	mirror_vnic_id;7520	u8	pri_hint;7521	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER    0x0UL7522	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL7523	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL7524	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX          0x3UL7525	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN          0x4UL7526	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST        CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN7527	u8	unused_5;7528	__le32	unused_6;7529	__le64	l2_filter_id_hint;7530};7531 7532/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */7533struct hwrm_cfa_l2_filter_alloc_output {7534	__le16	error_code;7535	__le16	req_type;7536	__le16	seq_id;7537	__le16	resp_len;7538	__le64	l2_filter_id;7539	__le32	flow_id;7540	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL7541	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 07542	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL7543	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)7544	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)7545	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT7546	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL7547	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)7548	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)7549	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX7550	u8	unused_0[3];7551	u8	valid;7552};7553 7554/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */7555struct hwrm_cfa_l2_filter_free_input {7556	__le16	req_type;7557	__le16	cmpl_ring;7558	__le16	seq_id;7559	__le16	target_id;7560	__le64	resp_addr;7561	__le64	l2_filter_id;7562};7563 7564/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */7565struct hwrm_cfa_l2_filter_free_output {7566	__le16	error_code;7567	__le16	req_type;7568	__le16	seq_id;7569	__le16	resp_len;7570	u8	unused_0[7];7571	u8	valid;7572};7573 7574/* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */7575struct hwrm_cfa_l2_filter_cfg_input {7576	__le16	req_type;7577	__le16	cmpl_ring;7578	__le16	seq_id;7579	__le16	target_id;7580	__le64	resp_addr;7581	__le32	flags;7582	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH                  0x1UL7583	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX                 0x0UL7584	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX                 0x1UL7585	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST              CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX7586	#define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP                  0x2UL7587	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK          0xcUL7588	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT           27589	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2      (0x0UL << 2)7590	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2              (0x1UL << 2)7591	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE            (0x2UL << 2)7592	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST           CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE7593	#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK         0x30UL7594	#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT          47595	#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE      (0x0UL << 4)7596	#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP    (0x1UL << 4)7597	#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP    (0x2UL << 4)7598	#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP  (0x3UL << 4)7599	#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST          CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP7600	__le32	enables;7601	#define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID                 0x1UL7602	#define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID     0x2UL7603	#define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC              0x4UL7604	#define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID          0x8UL7605	__le64	l2_filter_id;7606	__le32	dst_id;7607	__le32	new_mirror_vnic_id;7608	__le32	prof_func;7609	__le32	l2_context_id;7610};7611 7612/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */7613struct hwrm_cfa_l2_filter_cfg_output {7614	__le16	error_code;7615	__le16	req_type;7616	__le16	seq_id;7617	__le16	resp_len;7618	u8	unused_0[7];7619	u8	valid;7620};7621 7622/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */7623struct hwrm_cfa_l2_set_rx_mask_input {7624	__le16	req_type;7625	__le16	cmpl_ring;7626	__le16	seq_id;7627	__le16	target_id;7628	__le64	resp_addr;7629	__le32	vnic_id;7630	__le32	mask;7631	#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST               0x2UL7632	#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST           0x4UL7633	#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST               0x8UL7634	#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS         0x10UL7635	#define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST           0x20UL7636	#define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY            0x40UL7637	#define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN        0x80UL7638	#define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN     0x100UL7639	__le64	mc_tbl_addr;7640	__le32	num_mc_entries;7641	u8	unused_0[4];7642	__le64	vlan_tag_tbl_addr;7643	__le32	num_vlan_tags;7644	u8	unused_1[4];7645};7646 7647/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */7648struct hwrm_cfa_l2_set_rx_mask_output {7649	__le16	error_code;7650	__le16	req_type;7651	__le16	seq_id;7652	__le16	resp_len;7653	u8	unused_0[7];7654	u8	valid;7655};7656 7657/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */7658struct hwrm_cfa_l2_set_rx_mask_cmd_err {7659	u8	code;7660	#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN                    0x0UL7661	#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL7662	#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST                      CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR7663	u8	unused_0[7];7664};7665 7666/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */7667struct hwrm_cfa_tunnel_filter_alloc_input {7668	__le16	req_type;7669	__le16	cmpl_ring;7670	__le16	seq_id;7671	__le16	target_id;7672	__le64	resp_addr;7673	__le32	flags;7674	#define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL7675	__le32	enables;7676	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID       0x1UL7677	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR            0x2UL7678	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN           0x4UL7679	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR            0x8UL7680	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE       0x10UL7681	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE     0x20UL7682	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR          0x40UL7683	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x80UL7684	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI                0x100UL7685	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID        0x200UL7686	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x400UL7687	__le64	l2_filter_id;7688	u8	l2_addr[6];7689	__le16	l2_ivlan;7690	__le32	l3_addr[4];7691	__le32	t_l3_addr[4];7692	u8	l3_addr_type;7693	u8	t_l3_addr_type;7694	u8	tunnel_type;7695	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL7696	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL7697	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL7698	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL7699	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL7700	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL7701	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL7702	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL7703	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL7704	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL7705	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL7706	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL7707	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL7708	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL7709	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL7710	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL7711	u8	tunnel_flags;7712	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR     0x1UL7713	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1          0x2UL7714	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0         0x4UL7715	__le32	vni;7716	__le32	dst_vnic_id;7717	__le32	mirror_vnic_id;7718};7719 7720/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */7721struct hwrm_cfa_tunnel_filter_alloc_output {7722	__le16	error_code;7723	__le16	req_type;7724	__le16	seq_id;7725	__le16	resp_len;7726	__le64	tunnel_filter_id;7727	__le32	flow_id;7728	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL7729	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 07730	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL7731	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)7732	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)7733	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT7734	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL7735	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)7736	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)7737	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX7738	u8	unused_0[3];7739	u8	valid;7740};7741 7742/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */7743struct hwrm_cfa_tunnel_filter_free_input {7744	__le16	req_type;7745	__le16	cmpl_ring;7746	__le16	seq_id;7747	__le16	target_id;7748	__le64	resp_addr;7749	__le64	tunnel_filter_id;7750};7751 7752/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */7753struct hwrm_cfa_tunnel_filter_free_output {7754	__le16	error_code;7755	__le16	req_type;7756	__le16	seq_id;7757	__le16	resp_len;7758	u8	unused_0[7];7759	u8	valid;7760};7761 7762/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */7763struct hwrm_vxlan_ipv4_hdr {7764	u8	ver_hlen;7765	#define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL7766	#define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 07767	#define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK      0xf0UL7768	#define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT       47769	u8	tos;7770	__be16	ip_id;7771	__be16	flags_frag_offset;7772	u8	ttl;7773	u8	protocol;7774	__be32	src_ip_addr;7775	__be32	dest_ip_addr;7776};7777 7778/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */7779struct hwrm_vxlan_ipv6_hdr {7780	__be32	ver_tc_flow_label;7781	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT         0x1cUL7782	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK        0xf0000000UL7783	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT          0x14UL7784	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK         0xff00000UL7785	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT  0x0UL7786	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL7787	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST           VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK7788	__be16	payload_len;7789	u8	next_hdr;7790	u8	ttl;7791	__be32	src_ip_addr[4];7792	__be32	dest_ip_addr[4];7793};7794 7795/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */7796struct hwrm_cfa_encap_data_vxlan {7797	u8	src_mac_addr[6];7798	__le16	unused_0;7799	u8	dst_mac_addr[6];7800	u8	num_vlan_tags;7801	u8	unused_1;7802	__be16	ovlan_tpid;7803	__be16	ovlan_tci;7804	__be16	ivlan_tpid;7805	__be16	ivlan_tci;7806	__le32	l3[10];7807	#define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL7808	#define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL7809	#define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL7810	#define CFA_ENCAP_DATA_VXLAN_L3_LAST    CFA_ENCAP_DATA_VXLAN_L3_VER_IPV67811	__be16	src_port;7812	__be16	dst_port;7813	__be32	vni;7814	u8	hdr_rsvd0[3];7815	u8	hdr_rsvd1;7816	u8	hdr_flags;7817	u8	unused[3];7818};7819 7820/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */7821struct hwrm_cfa_encap_record_alloc_input {7822	__le16	req_type;7823	__le16	cmpl_ring;7824	__le16	seq_id;7825	__le16	target_id;7826	__le64	resp_addr;7827	__le32	flags;7828	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL7829	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL     0x2UL7830	u8	encap_type;7831	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN        0x1UL7832	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE        0x2UL7833	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE        0x3UL7834	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP         0x4UL7835	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE       0x5UL7836	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS         0x6UL7837	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN         0x7UL7838	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE        0x8UL7839	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4     0x9UL7840	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1     0xaUL7841	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE     0xbUL7842	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL7843	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE    0x10UL7844	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST        CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE7845	u8	unused_0[3];7846	__le32	encap_data[20];7847};7848 7849/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */7850struct hwrm_cfa_encap_record_alloc_output {7851	__le16	error_code;7852	__le16	req_type;7853	__le16	seq_id;7854	__le16	resp_len;7855	__le32	encap_record_id;7856	u8	unused_0[3];7857	u8	valid;7858};7859 7860/* hwrm_cfa_encap_record_free_input (size:192b/24B) */7861struct hwrm_cfa_encap_record_free_input {7862	__le16	req_type;7863	__le16	cmpl_ring;7864	__le16	seq_id;7865	__le16	target_id;7866	__le64	resp_addr;7867	__le32	encap_record_id;7868	u8	unused_0[4];7869};7870 7871/* hwrm_cfa_encap_record_free_output (size:128b/16B) */7872struct hwrm_cfa_encap_record_free_output {7873	__le16	error_code;7874	__le16	req_type;7875	__le16	seq_id;7876	__le16	resp_len;7877	u8	unused_0[7];7878	u8	valid;7879};7880 7881/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */7882struct hwrm_cfa_ntuple_filter_alloc_input {7883	__le16	req_type;7884	__le16	cmpl_ring;7885	__le16	seq_id;7886	__le16	target_id;7887	__le64	resp_addr;7888	__le32	flags;7889	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK              0x1UL7890	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP                  0x2UL7891	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER                 0x4UL7892	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID              0x8UL7893	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY             0x10UL7894	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX     0x20UL7895	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT         0x40UL7896	__le32	enables;7897	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID         0x1UL7898	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE            0x2UL7899	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE          0x4UL7900	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR          0x8UL7901	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE          0x10UL7902	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR           0x20UL7903	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK      0x40UL7904	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR           0x80UL7905	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK      0x100UL7906	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL          0x200UL7907	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT             0x400UL7908	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK        0x800UL7909	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT             0x1000UL7910	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK        0x2000UL7911	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT             0x4000UL7912	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID     0x8000UL7913	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID               0x10000UL7914	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID       0x20000UL7915	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR          0x40000UL7916	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX     0x80000UL7917	__le64	l2_filter_id;7918	u8	src_macaddr[6];7919	__be16	ethertype;7920	u8	ip_addr_type;7921	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL7922	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL7923	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL7924	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV67925	u8	ip_protocol;7926	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL7927	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL7928	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL7929	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP    0x1UL7930	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6  0x3aUL7931	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD    0xffUL7932	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD7933	__le16	dst_id;7934	__le16	rfs_ring_tbl_idx;7935	u8	tunnel_type;7936	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL7937	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL7938	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL7939	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL7940	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL7941	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL7942	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL7943	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL7944	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL7945	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL7946	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL7947	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL7948	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL7949	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL7950	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL7951	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL7952	u8	pri_hint;7953	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL7954	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE     0x1UL7955	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW     0x2UL7956	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST   0x3UL7957	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST    0x4UL7958	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST     CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST7959	__be32	src_ipaddr[4];7960	__be32	src_ipaddr_mask[4];7961	__be32	dst_ipaddr[4];7962	__be32	dst_ipaddr_mask[4];7963	__be16	src_port;7964	__be16	src_port_mask;7965	__be16	dst_port;7966	__be16	dst_port_mask;7967	__le64	ntuple_filter_id_hint;7968};7969 7970/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */7971struct hwrm_cfa_ntuple_filter_alloc_output {7972	__le16	error_code;7973	__le16	req_type;7974	__le16	seq_id;7975	__le16	resp_len;7976	__le64	ntuple_filter_id;7977	__le32	flow_id;7978	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL7979	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 07980	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL7981	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)7982	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)7983	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT7984	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL7985	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)7986	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)7987	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX7988	u8	unused_0[3];7989	u8	valid;7990};7991 7992/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */7993struct hwrm_cfa_ntuple_filter_alloc_cmd_err {7994	u8	code;7995	#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN                   0x0UL7996	#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL7997	#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST                     CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR7998	u8	unused_0[7];7999};8000 8001/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */8002struct hwrm_cfa_ntuple_filter_free_input {8003	__le16	req_type;8004	__le16	cmpl_ring;8005	__le16	seq_id;8006	__le16	target_id;8007	__le64	resp_addr;8008	__le64	ntuple_filter_id;8009};8010 8011/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */8012struct hwrm_cfa_ntuple_filter_free_output {8013	__le16	error_code;8014	__le16	req_type;8015	__le16	seq_id;8016	__le16	resp_len;8017	u8	unused_0[7];8018	u8	valid;8019};8020 8021/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */8022struct hwrm_cfa_ntuple_filter_cfg_input {8023	__le16	req_type;8024	__le16	cmpl_ring;8025	__le16	seq_id;8026	__le16	target_id;8027	__le64	resp_addr;8028	__le32	enables;8029	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL8030	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL8031	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL8032	__le32	flags;8033	#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID              0x1UL8034	#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX     0x2UL8035	#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT         0x4UL8036	__le64	ntuple_filter_id;8037	__le32	new_dst_id;8038	__le32	new_mirror_vnic_id;8039	__le16	new_meter_instance_id;8040	#define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL8041	#define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST   CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID8042	u8	unused_1[6];8043};8044 8045/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */8046struct hwrm_cfa_ntuple_filter_cfg_output {8047	__le16	error_code;8048	__le16	req_type;8049	__le16	seq_id;8050	__le16	resp_len;8051	u8	unused_0[7];8052	u8	valid;8053};8054 8055/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */8056struct hwrm_cfa_decap_filter_alloc_input {8057	__le16	req_type;8058	__le16	cmpl_ring;8059	__le16	seq_id;8060	__le16	target_id;8061	__le64	resp_addr;8062	__le32	flags;8063	#define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL     0x1UL8064	__le32	enables;8065	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x1UL8066	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID          0x2UL8067	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR        0x4UL8068	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR        0x8UL8069	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID          0x10UL8070	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID          0x20UL8071	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID        0x40UL8072	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID        0x80UL8073	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE          0x100UL8074	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR         0x200UL8075	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR         0x400UL8076	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE        0x800UL8077	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL        0x1000UL8078	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT           0x2000UL8079	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT           0x4000UL8080	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID             0x8000UL8081	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x10000UL8082	__be32	tunnel_id;8083	u8	tunnel_type;8084	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL8085	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL8086	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL8087	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL8088	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL8089	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL8090	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL8091	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL8092	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL8093	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL8094	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL8095	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL8096	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL8097	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL8098	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL8099	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL8100	u8	unused_0;8101	__le16	unused_1;8102	u8	src_macaddr[6];8103	u8	unused_2[2];8104	u8	dst_macaddr[6];8105	__be16	ovlan_vid;8106	__be16	ivlan_vid;8107	__be16	t_ovlan_vid;8108	__be16	t_ivlan_vid;8109	__be16	ethertype;8110	u8	ip_addr_type;8111	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL8112	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL8113	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL8114	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV68115	u8	ip_protocol;8116	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL8117	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL8118	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL8119	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP8120	__le16	unused_3;8121	__le32	unused_4;8122	__be32	src_ipaddr[4];8123	__be32	dst_ipaddr[4];8124	__be16	src_port;8125	__be16	dst_port;8126	__le16	dst_id;8127	__le16	l2_ctxt_ref_id;8128};8129 8130/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */8131struct hwrm_cfa_decap_filter_alloc_output {8132	__le16	error_code;8133	__le16	req_type;8134	__le16	seq_id;8135	__le16	resp_len;8136	__le32	decap_filter_id;8137	u8	unused_0[3];8138	u8	valid;8139};8140 8141/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */8142struct hwrm_cfa_decap_filter_free_input {8143	__le16	req_type;8144	__le16	cmpl_ring;8145	__le16	seq_id;8146	__le16	target_id;8147	__le64	resp_addr;8148	__le32	decap_filter_id;8149	u8	unused_0[4];8150};8151 8152/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */8153struct hwrm_cfa_decap_filter_free_output {8154	__le16	error_code;8155	__le16	req_type;8156	__le16	seq_id;8157	__le16	resp_len;8158	u8	unused_0[7];8159	u8	valid;8160};8161 8162/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */8163struct hwrm_cfa_flow_alloc_input {8164	__le16	req_type;8165	__le16	cmpl_ring;8166	__le16	seq_id;8167	__le16	target_id;8168	__le64	resp_addr;8169	__le16	flags;8170	#define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL                 0x1UL8171	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK          0x6UL8172	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT           18173	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE            (0x0UL << 1)8174	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE             (0x1UL << 1)8175	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO             (0x2UL << 1)8176	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO8177	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK          0x38UL8178	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT           38179	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2              (0x0UL << 3)8180	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4            (0x1UL << 3)8181	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6            (0x2UL << 3)8182	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV68183	#define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX                0x40UL8184	#define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX                0x80UL8185	#define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI     0x100UL8186	#define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN      0x200UL8187	__le16	src_fid;8188	__le32	tunnel_handle;8189	__le16	action_flags;8190	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD                       0x1UL8191	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE                   0x2UL8192	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP                      0x4UL8193	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER                     0x8UL8194	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL                    0x10UL8195	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC                   0x20UL8196	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST                  0x40UL8197	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS          0x80UL8198	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE         0x100UL8199	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT             0x200UL8200	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP                 0x400UL8201	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED        0x800UL8202	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT                  0x1000UL8203	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC     0x2000UL8204	__le16	dst_fid;8205	__be16	l2_rewrite_vlan_tpid;8206	__be16	l2_rewrite_vlan_tci;8207	__le16	act_meter_id;8208	__le16	ref_flow_handle;8209	__be16	ethertype;8210	__be16	outer_vlan_tci;8211	__be16	dmac[3];8212	__be16	inner_vlan_tci;8213	__be16	smac[3];8214	u8	ip_dst_mask_len;8215	u8	ip_src_mask_len;8216	__be32	ip_dst[4];8217	__be32	ip_src[4];8218	__be16	l4_src_port;8219	__be16	l4_src_port_mask;8220	__be16	l4_dst_port;8221	__be16	l4_dst_port_mask;8222	__be32	nat_ip_address[4];8223	__be16	l2_rewrite_dmac[3];8224	__be16	nat_port;8225	__be16	l2_rewrite_smac[3];8226	u8	ip_proto;8227	u8	tunnel_type;8228	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL8229	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL8230	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL8231	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL8232	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL8233	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL8234	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL8235	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL8236	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL8237	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL8238	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL8239	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL8240	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL8241	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL8242	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL8243	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL8244};8245 8246/* hwrm_cfa_flow_alloc_output (size:256b/32B) */8247struct hwrm_cfa_flow_alloc_output {8248	__le16	error_code;8249	__le16	req_type;8250	__le16	seq_id;8251	__le16	resp_len;8252	__le16	flow_handle;8253	u8	unused_0[2];8254	__le32	flow_id;8255	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL8256	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 08257	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL8258	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)8259	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)8260	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT8261	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL8262	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)8263	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)8264	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX8265	__le64	ext_flow_handle;8266	__le32	flow_counter_id;8267	u8	unused_1[3];8268	u8	valid;8269};8270 8271/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */8272struct hwrm_cfa_flow_alloc_cmd_err {8273	u8	code;8274	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN         0x0UL8275	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL8276	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD   0x2UL8277	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER    0x3UL8278	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM  0x4UL8279	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION  0x5UL8280	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS      0x6UL8281	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB    0x7UL8282	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST           CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB8283	u8	unused_0[7];8284};8285 8286/* hwrm_cfa_flow_free_input (size:256b/32B) */8287struct hwrm_cfa_flow_free_input {8288	__le16	req_type;8289	__le16	cmpl_ring;8290	__le16	seq_id;8291	__le16	target_id;8292	__le64	resp_addr;8293	__le16	flow_handle;8294	__le16	unused_0;8295	__le32	flow_counter_id;8296	__le64	ext_flow_handle;8297};8298 8299/* hwrm_cfa_flow_free_output (size:256b/32B) */8300struct hwrm_cfa_flow_free_output {8301	__le16	error_code;8302	__le16	req_type;8303	__le16	seq_id;8304	__le16	resp_len;8305	__le64	packet;8306	__le64	byte;8307	u8	unused_0[7];8308	u8	valid;8309};8310 8311/* hwrm_cfa_flow_info_input (size:256b/32B) */8312struct hwrm_cfa_flow_info_input {8313	__le16	req_type;8314	__le16	cmpl_ring;8315	__le16	seq_id;8316	__le16	target_id;8317	__le64	resp_addr;8318	__le16	flow_handle;8319	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK      0xfffUL8320	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT       0x1000UL8321	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT    0x2000UL8322	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX        0x3000UL8323	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT    0x4000UL8324	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX        0x8000UL8325	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX    0x9000UL8326	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL8327	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX        0xb000UL8328	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL8329	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST         CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX8330	u8	unused_0[6];8331	__le64	ext_flow_handle;8332};8333 8334/* hwrm_cfa_flow_info_output (size:5632b/704B) */8335struct hwrm_cfa_flow_info_output {8336	__le16	error_code;8337	__le16	req_type;8338	__le16	seq_id;8339	__le16	resp_len;8340	u8	flags;8341	#define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX     0x1UL8342	#define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX     0x2UL8343	u8	profile;8344	__le16	src_fid;8345	__le16	dst_fid;8346	__le16	l2_ctxt_id;8347	__le64	em_info;8348	__le64	tcam_info;8349	__le64	vfp_tcam_info;8350	__le16	ar_id;8351	__le16	flow_handle;8352	__le32	tunnel_handle;8353	__le16	flow_timer;8354	u8	unused_0[6];8355	__le32	flow_key_data[130];8356	__le32	flow_action_info[30];8357	u8	unused_1[7];8358	u8	valid;8359};8360 8361/* hwrm_cfa_flow_stats_input (size:640b/80B) */8362struct hwrm_cfa_flow_stats_input {8363	__le16	req_type;8364	__le16	cmpl_ring;8365	__le16	seq_id;8366	__le16	target_id;8367	__le64	resp_addr;8368	__le16	num_flows;8369	__le16	flow_handle_0;8370	__le16	flow_handle_1;8371	__le16	flow_handle_2;8372	__le16	flow_handle_3;8373	__le16	flow_handle_4;8374	__le16	flow_handle_5;8375	__le16	flow_handle_6;8376	__le16	flow_handle_7;8377	__le16	flow_handle_8;8378	__le16	flow_handle_9;8379	u8	unused_0[2];8380	__le32	flow_id_0;8381	__le32	flow_id_1;8382	__le32	flow_id_2;8383	__le32	flow_id_3;8384	__le32	flow_id_4;8385	__le32	flow_id_5;8386	__le32	flow_id_6;8387	__le32	flow_id_7;8388	__le32	flow_id_8;8389	__le32	flow_id_9;8390};8391 8392/* hwrm_cfa_flow_stats_output (size:1408b/176B) */8393struct hwrm_cfa_flow_stats_output {8394	__le16	error_code;8395	__le16	req_type;8396	__le16	seq_id;8397	__le16	resp_len;8398	__le64	packet_0;8399	__le64	packet_1;8400	__le64	packet_2;8401	__le64	packet_3;8402	__le64	packet_4;8403	__le64	packet_5;8404	__le64	packet_6;8405	__le64	packet_7;8406	__le64	packet_8;8407	__le64	packet_9;8408	__le64	byte_0;8409	__le64	byte_1;8410	__le64	byte_2;8411	__le64	byte_3;8412	__le64	byte_4;8413	__le64	byte_5;8414	__le64	byte_6;8415	__le64	byte_7;8416	__le64	byte_8;8417	__le64	byte_9;8418	__le16	flow_hits;8419	u8	unused_0[5];8420	u8	valid;8421};8422 8423/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */8424struct hwrm_cfa_vfr_alloc_input {8425	__le16	req_type;8426	__le16	cmpl_ring;8427	__le16	seq_id;8428	__le16	target_id;8429	__le64	resp_addr;8430	__le16	vf_id;8431	__le16	reserved;8432	u8	unused_0[4];8433	char	vfr_name[32];8434};8435 8436/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */8437struct hwrm_cfa_vfr_alloc_output {8438	__le16	error_code;8439	__le16	req_type;8440	__le16	seq_id;8441	__le16	resp_len;8442	__le16	rx_cfa_code;8443	__le16	tx_cfa_action;8444	u8	unused_0[3];8445	u8	valid;8446};8447 8448/* hwrm_cfa_vfr_free_input (size:448b/56B) */8449struct hwrm_cfa_vfr_free_input {8450	__le16	req_type;8451	__le16	cmpl_ring;8452	__le16	seq_id;8453	__le16	target_id;8454	__le64	resp_addr;8455	char	vfr_name[32];8456	__le16	vf_id;8457	__le16	reserved;8458	u8	unused_0[4];8459};8460 8461/* hwrm_cfa_vfr_free_output (size:128b/16B) */8462struct hwrm_cfa_vfr_free_output {8463	__le16	error_code;8464	__le16	req_type;8465	__le16	seq_id;8466	__le16	resp_len;8467	u8	unused_0[7];8468	u8	valid;8469};8470 8471/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */8472struct hwrm_cfa_eem_qcaps_input {8473	__le16	req_type;8474	__le16	cmpl_ring;8475	__le16	seq_id;8476	__le16	target_id;8477	__le64	resp_addr;8478	__le32	flags;8479	#define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX               0x1UL8480	#define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX               0x2UL8481	#define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD     0x4UL8482	__le32	unused_0;8483};8484 8485/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */8486struct hwrm_cfa_eem_qcaps_output {8487	__le16	error_code;8488	__le16	req_type;8489	__le16	seq_id;8490	__le16	resp_len;8491	__le32	flags;8492	#define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX                                         0x1UL8493	#define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX                                         0x2UL8494	#define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED              0x4UL8495	#define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED     0x8UL8496	__le32	unused_0;8497	__le32	supported;8498	#define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE                       0x1UL8499	#define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE                       0x2UL8500	#define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE            0x4UL8501	#define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE     0x8UL8502	#define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE                        0x10UL8503	__le32	max_entries_supported;8504	__le16	key_entry_size;8505	__le16	record_entry_size;8506	__le16	efc_entry_size;8507	__le16	fid_entry_size;8508	u8	unused_1[7];8509	u8	valid;8510};8511 8512/* hwrm_cfa_eem_cfg_input (size:384b/48B) */8513struct hwrm_cfa_eem_cfg_input {8514	__le16	req_type;8515	__le16	cmpl_ring;8516	__le16	seq_id;8517	__le16	target_id;8518	__le64	resp_addr;8519	__le32	flags;8520	#define CFA_EEM_CFG_REQ_FLAGS_PATH_TX               0x1UL8521	#define CFA_EEM_CFG_REQ_FLAGS_PATH_RX               0x2UL8522	#define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD     0x4UL8523	#define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF          0x8UL8524	__le16	group_id;8525	__le16	unused_0;8526	__le32	num_entries;8527	__le32	unused_1;8528	__le16	key0_ctx_id;8529	__le16	key1_ctx_id;8530	__le16	record_ctx_id;8531	__le16	efc_ctx_id;8532	__le16	fid_ctx_id;8533	__le16	unused_2;8534	__le32	unused_3;8535};8536 8537/* hwrm_cfa_eem_cfg_output (size:128b/16B) */8538struct hwrm_cfa_eem_cfg_output {8539	__le16	error_code;8540	__le16	req_type;8541	__le16	seq_id;8542	__le16	resp_len;8543	u8	unused_0[7];8544	u8	valid;8545};8546 8547/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */8548struct hwrm_cfa_eem_qcfg_input {8549	__le16	req_type;8550	__le16	cmpl_ring;8551	__le16	seq_id;8552	__le16	target_id;8553	__le64	resp_addr;8554	__le32	flags;8555	#define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX     0x1UL8556	#define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX     0x2UL8557	__le32	unused_0;8558};8559 8560/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */8561struct hwrm_cfa_eem_qcfg_output {8562	__le16	error_code;8563	__le16	req_type;8564	__le16	seq_id;8565	__le16	resp_len;8566	__le32	flags;8567	#define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX               0x1UL8568	#define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX               0x2UL8569	#define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD     0x4UL8570	__le32	num_entries;8571	__le16	key0_ctx_id;8572	__le16	key1_ctx_id;8573	__le16	record_ctx_id;8574	__le16	efc_ctx_id;8575	__le16	fid_ctx_id;8576	u8	unused_2[5];8577	u8	valid;8578};8579 8580/* hwrm_cfa_eem_op_input (size:192b/24B) */8581struct hwrm_cfa_eem_op_input {8582	__le16	req_type;8583	__le16	cmpl_ring;8584	__le16	seq_id;8585	__le16	target_id;8586	__le64	resp_addr;8587	__le32	flags;8588	#define CFA_EEM_OP_REQ_FLAGS_PATH_TX     0x1UL8589	#define CFA_EEM_OP_REQ_FLAGS_PATH_RX     0x2UL8590	__le16	unused_0;8591	__le16	op;8592	#define CFA_EEM_OP_REQ_OP_RESERVED    0x0UL8593	#define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL8594	#define CFA_EEM_OP_REQ_OP_EEM_ENABLE  0x2UL8595	#define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL8596	#define CFA_EEM_OP_REQ_OP_LAST       CFA_EEM_OP_REQ_OP_EEM_CLEANUP8597};8598 8599/* hwrm_cfa_eem_op_output (size:128b/16B) */8600struct hwrm_cfa_eem_op_output {8601	__le16	error_code;8602	__le16	req_type;8603	__le16	seq_id;8604	__le16	resp_len;8605	u8	unused_0[7];8606	u8	valid;8607};8608 8609/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */8610struct hwrm_cfa_adv_flow_mgnt_qcaps_input {8611	__le16	req_type;8612	__le16	cmpl_ring;8613	__le16	seq_id;8614	__le16	target_id;8615	__le64	resp_addr;8616	__le32	unused_0[4];8617};8618 8619/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */8620struct hwrm_cfa_adv_flow_mgnt_qcaps_output {8621	__le16	error_code;8622	__le16	req_type;8623	__le16	seq_id;8624	__le16	resp_len;8625	__le32	flags;8626	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED                     0x1UL8627	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED                     0x2UL8628	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED                  0x4UL8629	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED                     0x8UL8630	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED              0x10UL8631	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED                        0x20UL8632	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED                        0x40UL8633	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED                 0x80UL8634	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED                   0x100UL8635	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED                      0x200UL8636	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED                                0x400UL8637	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED            0x800UL8638	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED                 0x1000UL8639	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED                0x2000UL8640	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED        0x4000UL8641	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE                              0x8000UL8642	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED     0x10000UL8643	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED                                0x20000UL8644	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED               0x40000UL8645	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED                     0x80000UL8646	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED        0x100000UL8647	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED                0x200000UL8648	u8	unused_0[3];8649	u8	valid;8650};8651 8652/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */8653struct hwrm_tunnel_dst_port_query_input {8654	__le16	req_type;8655	__le16	cmpl_ring;8656	__le16	seq_id;8657	__le16	target_id;8658	__le64	resp_addr;8659	u8	tunnel_type;8660	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN              0x1UL8661	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE             0x5UL8662	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4           0x9UL8663	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1           0xaUL8664	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE           0xbUL8665	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6       0xcUL8666	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE         0xdUL8667	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI              0xeUL8668	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6               0xfUL8669	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE          0x10UL8670	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE                0x11UL8671	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR       0x12UL8672	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL8673	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL8674	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL8675	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL8676	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL8677	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL8678	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL8679	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST              TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES078680	u8	tunnel_next_proto;8681	u8	unused_0[6];8682};8683 8684/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */8685struct hwrm_tunnel_dst_port_query_output {8686	__le16	error_code;8687	__le16	req_type;8688	__le16	seq_id;8689	__le16	resp_len;8690	__le16	tunnel_dst_port_id;8691	__be16	tunnel_dst_port_val;8692	u8	upar_in_use;8693	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0     0x1UL8694	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1     0x2UL8695	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2     0x4UL8696	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3     0x8UL8697	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4     0x10UL8698	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5     0x20UL8699	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6     0x40UL8700	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7     0x80UL8701	u8	status;8702	#define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL     0x1UL8703	#define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL     0x2UL8704	u8	unused_0;8705	u8	valid;8706};8707 8708/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */8709struct hwrm_tunnel_dst_port_alloc_input {8710	__le16	req_type;8711	__le16	cmpl_ring;8712	__le16	seq_id;8713	__le16	target_id;8714	__le64	resp_addr;8715	u8	tunnel_type;8716	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN              0x1UL8717	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE             0x5UL8718	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4           0x9UL8719	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1           0xaUL8720	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE           0xbUL8721	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6       0xcUL8722	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE         0xdUL8723	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI              0xeUL8724	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6               0xfUL8725	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE          0x10UL8726	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE                0x11UL8727	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR       0x12UL8728	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL8729	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL8730	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL8731	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL8732	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL8733	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL8734	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL8735	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST              TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES078736	u8	tunnel_next_proto;8737	__be16	tunnel_dst_port_val;8738	u8	unused_0[4];8739};8740 8741/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */8742struct hwrm_tunnel_dst_port_alloc_output {8743	__le16	error_code;8744	__le16	req_type;8745	__le16	seq_id;8746	__le16	resp_len;8747	__le16	tunnel_dst_port_id;8748	u8	error_info;8749	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS         0x0UL8750	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED   0x1UL8751	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL8752	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED     0x3UL8753	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST           TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED8754	u8	upar_in_use;8755	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0     0x1UL8756	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1     0x2UL8757	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2     0x4UL8758	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3     0x8UL8759	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4     0x10UL8760	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5     0x20UL8761	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6     0x40UL8762	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7     0x80UL8763	u8	unused_0[3];8764	u8	valid;8765};8766 8767/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */8768struct hwrm_tunnel_dst_port_free_input {8769	__le16	req_type;8770	__le16	cmpl_ring;8771	__le16	seq_id;8772	__le16	target_id;8773	__le64	resp_addr;8774	u8	tunnel_type;8775	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN              0x1UL8776	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE             0x5UL8777	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4           0x9UL8778	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1           0xaUL8779	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE           0xbUL8780	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6       0xcUL8781	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE         0xdUL8782	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI              0xeUL8783	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6               0xfUL8784	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE          0x10UL8785	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE                0x11UL8786	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR       0x12UL8787	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL8788	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL8789	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL8790	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL8791	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL8792	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL8793	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL8794	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST              TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES078795	u8	tunnel_next_proto;8796	__le16	tunnel_dst_port_id;8797	u8	unused_0[4];8798};8799 8800/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */8801struct hwrm_tunnel_dst_port_free_output {8802	__le16	error_code;8803	__le16	req_type;8804	__le16	seq_id;8805	__le16	resp_len;8806	u8	error_info;8807	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS           0x0UL8808	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER     0x1UL8809	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL8810	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST             TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED8811	u8	unused_1[6];8812	u8	valid;8813};8814 8815/* ctx_hw_stats (size:1280b/160B) */8816struct ctx_hw_stats {8817	__le64	rx_ucast_pkts;8818	__le64	rx_mcast_pkts;8819	__le64	rx_bcast_pkts;8820	__le64	rx_discard_pkts;8821	__le64	rx_error_pkts;8822	__le64	rx_ucast_bytes;8823	__le64	rx_mcast_bytes;8824	__le64	rx_bcast_bytes;8825	__le64	tx_ucast_pkts;8826	__le64	tx_mcast_pkts;8827	__le64	tx_bcast_pkts;8828	__le64	tx_error_pkts;8829	__le64	tx_discard_pkts;8830	__le64	tx_ucast_bytes;8831	__le64	tx_mcast_bytes;8832	__le64	tx_bcast_bytes;8833	__le64	tpa_pkts;8834	__le64	tpa_bytes;8835	__le64	tpa_events;8836	__le64	tpa_aborts;8837};8838 8839/* ctx_hw_stats_ext (size:1408b/176B) */8840struct ctx_hw_stats_ext {8841	__le64	rx_ucast_pkts;8842	__le64	rx_mcast_pkts;8843	__le64	rx_bcast_pkts;8844	__le64	rx_discard_pkts;8845	__le64	rx_error_pkts;8846	__le64	rx_ucast_bytes;8847	__le64	rx_mcast_bytes;8848	__le64	rx_bcast_bytes;8849	__le64	tx_ucast_pkts;8850	__le64	tx_mcast_pkts;8851	__le64	tx_bcast_pkts;8852	__le64	tx_error_pkts;8853	__le64	tx_discard_pkts;8854	__le64	tx_ucast_bytes;8855	__le64	tx_mcast_bytes;8856	__le64	tx_bcast_bytes;8857	__le64	rx_tpa_eligible_pkt;8858	__le64	rx_tpa_eligible_bytes;8859	__le64	rx_tpa_pkt;8860	__le64	rx_tpa_bytes;8861	__le64	rx_tpa_errors;8862	__le64	rx_tpa_events;8863};8864 8865/* hwrm_stat_ctx_alloc_input (size:384b/48B) */8866struct hwrm_stat_ctx_alloc_input {8867	__le16	req_type;8868	__le16	cmpl_ring;8869	__le16	seq_id;8870	__le16	target_id;8871	__le64	resp_addr;8872	__le64	stats_dma_addr;8873	__le32	update_period_ms;8874	u8	stat_ctx_flags;8875	#define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE             0x1UL8876	#define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_DUP_HOST_BUF     0x2UL8877	u8	unused_0;8878	__le16	stats_dma_length;8879	__le16	flags;8880	#define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID     0x1UL8881	__le16	steering_tag;8882	__le32	stat_ctx_id;8883	__le16	alloc_seq_id;8884	u8	unused_1[6];8885};8886 8887/* hwrm_stat_ctx_alloc_output (size:128b/16B) */8888struct hwrm_stat_ctx_alloc_output {8889	__le16	error_code;8890	__le16	req_type;8891	__le16	seq_id;8892	__le16	resp_len;8893	__le32	stat_ctx_id;8894	u8	unused_0[3];8895	u8	valid;8896};8897 8898/* hwrm_stat_ctx_free_input (size:192b/24B) */8899struct hwrm_stat_ctx_free_input {8900	__le16	req_type;8901	__le16	cmpl_ring;8902	__le16	seq_id;8903	__le16	target_id;8904	__le64	resp_addr;8905	__le32	stat_ctx_id;8906	u8	unused_0[4];8907};8908 8909/* hwrm_stat_ctx_free_output (size:128b/16B) */8910struct hwrm_stat_ctx_free_output {8911	__le16	error_code;8912	__le16	req_type;8913	__le16	seq_id;8914	__le16	resp_len;8915	__le32	stat_ctx_id;8916	u8	unused_0[3];8917	u8	valid;8918};8919 8920/* hwrm_stat_ctx_query_input (size:192b/24B) */8921struct hwrm_stat_ctx_query_input {8922	__le16	req_type;8923	__le16	cmpl_ring;8924	__le16	seq_id;8925	__le16	target_id;8926	__le64	resp_addr;8927	__le32	stat_ctx_id;8928	u8	flags;8929	#define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK     0x1UL8930	u8	unused_0[3];8931};8932 8933/* hwrm_stat_ctx_query_output (size:1408b/176B) */8934struct hwrm_stat_ctx_query_output {8935	__le16	error_code;8936	__le16	req_type;8937	__le16	seq_id;8938	__le16	resp_len;8939	__le64	tx_ucast_pkts;8940	__le64	tx_mcast_pkts;8941	__le64	tx_bcast_pkts;8942	__le64	tx_discard_pkts;8943	__le64	tx_error_pkts;8944	__le64	tx_ucast_bytes;8945	__le64	tx_mcast_bytes;8946	__le64	tx_bcast_bytes;8947	__le64	rx_ucast_pkts;8948	__le64	rx_mcast_pkts;8949	__le64	rx_bcast_pkts;8950	__le64	rx_discard_pkts;8951	__le64	rx_error_pkts;8952	__le64	rx_ucast_bytes;8953	__le64	rx_mcast_bytes;8954	__le64	rx_bcast_bytes;8955	__le64	rx_agg_pkts;8956	__le64	rx_agg_bytes;8957	__le64	rx_agg_events;8958	__le64	rx_agg_aborts;8959	u8	unused_0[7];8960	u8	valid;8961};8962 8963/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */8964struct hwrm_stat_ext_ctx_query_input {8965	__le16	req_type;8966	__le16	cmpl_ring;8967	__le16	seq_id;8968	__le16	target_id;8969	__le64	resp_addr;8970	__le32	stat_ctx_id;8971	u8	flags;8972	#define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK     0x1UL8973	u8	unused_0[3];8974};8975 8976/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */8977struct hwrm_stat_ext_ctx_query_output {8978	__le16	error_code;8979	__le16	req_type;8980	__le16	seq_id;8981	__le16	resp_len;8982	__le64	rx_ucast_pkts;8983	__le64	rx_mcast_pkts;8984	__le64	rx_bcast_pkts;8985	__le64	rx_discard_pkts;8986	__le64	rx_error_pkts;8987	__le64	rx_ucast_bytes;8988	__le64	rx_mcast_bytes;8989	__le64	rx_bcast_bytes;8990	__le64	tx_ucast_pkts;8991	__le64	tx_mcast_pkts;8992	__le64	tx_bcast_pkts;8993	__le64	tx_error_pkts;8994	__le64	tx_discard_pkts;8995	__le64	tx_ucast_bytes;8996	__le64	tx_mcast_bytes;8997	__le64	tx_bcast_bytes;8998	__le64	rx_tpa_eligible_pkt;8999	__le64	rx_tpa_eligible_bytes;9000	__le64	rx_tpa_pkt;9001	__le64	rx_tpa_bytes;9002	__le64	rx_tpa_errors;9003	__le64	rx_tpa_events;9004	u8	unused_0[7];9005	u8	valid;9006};9007 9008/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */9009struct hwrm_stat_ctx_clr_stats_input {9010	__le16	req_type;9011	__le16	cmpl_ring;9012	__le16	seq_id;9013	__le16	target_id;9014	__le64	resp_addr;9015	__le32	stat_ctx_id;9016	u8	unused_0[4];9017};9018 9019/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */9020struct hwrm_stat_ctx_clr_stats_output {9021	__le16	error_code;9022	__le16	req_type;9023	__le16	seq_id;9024	__le16	resp_len;9025	u8	unused_0[7];9026	u8	valid;9027};9028 9029/* hwrm_pcie_qstats_input (size:256b/32B) */9030struct hwrm_pcie_qstats_input {9031	__le16	req_type;9032	__le16	cmpl_ring;9033	__le16	seq_id;9034	__le16	target_id;9035	__le64	resp_addr;9036	__le16	pcie_stat_size;9037	u8	unused_0[6];9038	__le64	pcie_stat_host_addr;9039};9040 9041/* hwrm_pcie_qstats_output (size:128b/16B) */9042struct hwrm_pcie_qstats_output {9043	__le16	error_code;9044	__le16	req_type;9045	__le16	seq_id;9046	__le16	resp_len;9047	__le16	pcie_stat_size;9048	u8	unused_0[5];9049	u8	valid;9050};9051 9052/* pcie_ctx_hw_stats (size:768b/96B) */9053struct pcie_ctx_hw_stats {9054	__le64	pcie_pl_signal_integrity;9055	__le64	pcie_dl_signal_integrity;9056	__le64	pcie_tl_signal_integrity;9057	__le64	pcie_link_integrity;9058	__le64	pcie_tx_traffic_rate;9059	__le64	pcie_rx_traffic_rate;9060	__le64	pcie_tx_dllp_statistics;9061	__le64	pcie_rx_dllp_statistics;9062	__le64	pcie_equalization_time;9063	__le32	pcie_ltssm_histogram[4];9064	__le64	pcie_recovery_histogram;9065};9066 9067/* hwrm_stat_generic_qstats_input (size:256b/32B) */9068struct hwrm_stat_generic_qstats_input {9069	__le16	req_type;9070	__le16	cmpl_ring;9071	__le16	seq_id;9072	__le16	target_id;9073	__le64	resp_addr;9074	__le16	generic_stat_size;9075	u8	flags;9076	#define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL9077	u8	unused_0[5];9078	__le64	generic_stat_host_addr;9079};9080 9081/* hwrm_stat_generic_qstats_output (size:128b/16B) */9082struct hwrm_stat_generic_qstats_output {9083	__le16	error_code;9084	__le16	req_type;9085	__le16	seq_id;9086	__le16	resp_len;9087	__le16	generic_stat_size;9088	u8	unused_0[5];9089	u8	valid;9090};9091 9092/* generic_sw_hw_stats (size:1472b/184B) */9093struct generic_sw_hw_stats {9094	__le64	pcie_statistics_tx_tlp;9095	__le64	pcie_statistics_rx_tlp;9096	__le64	pcie_credit_fc_hdr_posted;9097	__le64	pcie_credit_fc_hdr_nonposted;9098	__le64	pcie_credit_fc_hdr_cmpl;9099	__le64	pcie_credit_fc_data_posted;9100	__le64	pcie_credit_fc_data_nonposted;9101	__le64	pcie_credit_fc_data_cmpl;9102	__le64	pcie_credit_fc_tgt_nonposted;9103	__le64	pcie_credit_fc_tgt_data_posted;9104	__le64	pcie_credit_fc_tgt_hdr_posted;9105	__le64	pcie_credit_fc_cmpl_hdr_posted;9106	__le64	pcie_credit_fc_cmpl_data_posted;9107	__le64	pcie_cmpl_longest;9108	__le64	pcie_cmpl_shortest;9109	__le64	cache_miss_count_cfcq;9110	__le64	cache_miss_count_cfcs;9111	__le64	cache_miss_count_cfcc;9112	__le64	cache_miss_count_cfcm;9113	__le64	hw_db_recov_dbs_dropped;9114	__le64	hw_db_recov_drops_serviced;9115	__le64	hw_db_recov_dbs_recovered;9116	__le64	hw_db_recov_oo_drop_count;9117};9118 9119/* hwrm_fw_reset_input (size:192b/24B) */9120struct hwrm_fw_reset_input {9121	__le16	req_type;9122	__le16	cmpl_ring;9123	__le16	seq_id;9124	__le16	target_id;9125	__le64	resp_addr;9126	u8	embedded_proc_type;9127	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT                  0x0UL9128	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT                  0x1UL9129	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL               0x2UL9130	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE                  0x3UL9131	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST                  0x4UL9132	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP                    0x5UL9133	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP                  0x6UL9134	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT  0x7UL9135	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL9136	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST                 FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION9137	u8	selfrst_status;9138	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE      0x0UL9139	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP      0x1UL9140	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST   0x2UL9141	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL9142	#define FW_RESET_REQ_SELFRST_STATUS_LAST            FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE9143	u8	host_idx;9144	u8	flags;9145	#define FW_RESET_REQ_FLAGS_RESET_GRACEFUL     0x1UL9146	#define FW_RESET_REQ_FLAGS_FW_ACTIVATION      0x2UL9147	u8	unused_0[4];9148};9149 9150/* hwrm_fw_reset_output (size:128b/16B) */9151struct hwrm_fw_reset_output {9152	__le16	error_code;9153	__le16	req_type;9154	__le16	seq_id;9155	__le16	resp_len;9156	u8	selfrst_status;9157	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE      0x0UL9158	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP      0x1UL9159	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST   0x2UL9160	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL9161	#define FW_RESET_RESP_SELFRST_STATUS_LAST            FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE9162	u8	unused_0[6];9163	u8	valid;9164};9165 9166/* hwrm_fw_qstatus_input (size:192b/24B) */9167struct hwrm_fw_qstatus_input {9168	__le16	req_type;9169	__le16	cmpl_ring;9170	__le16	seq_id;9171	__le16	target_id;9172	__le64	resp_addr;9173	u8	embedded_proc_type;9174	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT    0x0UL9175	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT    0x1UL9176	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL9177	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE    0x3UL9178	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST    0x4UL9179	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP      0x5UL9180	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP    0x6UL9181	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST   FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP9182	u8	unused_0[7];9183};9184 9185/* hwrm_fw_qstatus_output (size:128b/16B) */9186struct hwrm_fw_qstatus_output {9187	__le16	error_code;9188	__le16	req_type;9189	__le16	seq_id;9190	__le16	resp_len;9191	u8	selfrst_status;9192	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE    0x0UL9193	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP    0x1UL9194	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL9195	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER   0x3UL9196	#define FW_QSTATUS_RESP_SELFRST_STATUS_LAST          FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER9197	u8	nvm_option_action_status;9198	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE     0x0UL9199	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL9200	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL9201	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL9202	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST                  FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT9203	u8	unused_0[5];9204	u8	valid;9205};9206 9207/* hwrm_fw_set_time_input (size:256b/32B) */9208struct hwrm_fw_set_time_input {9209	__le16	req_type;9210	__le16	cmpl_ring;9211	__le16	seq_id;9212	__le16	target_id;9213	__le64	resp_addr;9214	__le16	year;9215	#define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL9216	#define FW_SET_TIME_REQ_YEAR_LAST   FW_SET_TIME_REQ_YEAR_UNKNOWN9217	u8	month;9218	u8	day;9219	u8	hour;9220	u8	minute;9221	u8	second;9222	u8	unused_0;9223	__le16	millisecond;9224	__le16	zone;9225	#define FW_SET_TIME_REQ_ZONE_UTC     09226	#define FW_SET_TIME_REQ_ZONE_UNKNOWN 655359227	#define FW_SET_TIME_REQ_ZONE_LAST   FW_SET_TIME_REQ_ZONE_UNKNOWN9228	u8	unused_1[4];9229};9230 9231/* hwrm_fw_set_time_output (size:128b/16B) */9232struct hwrm_fw_set_time_output {9233	__le16	error_code;9234	__le16	req_type;9235	__le16	seq_id;9236	__le16	resp_len;9237	u8	unused_0[7];9238	u8	valid;9239};9240 9241/* hwrm_struct_hdr (size:128b/16B) */9242struct hwrm_struct_hdr {9243	__le16	struct_id;9244	#define STRUCT_HDR_STRUCT_ID_LLDP_CFG           0x41bUL9245	#define STRUCT_HDR_STRUCT_ID_DCBX_ETS           0x41dUL9246	#define STRUCT_HDR_STRUCT_ID_DCBX_PFC           0x41fUL9247	#define STRUCT_HDR_STRUCT_ID_DCBX_APP           0x421UL9248	#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL9249	#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC       0x424UL9250	#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE        0x426UL9251	#define STRUCT_HDR_STRUCT_ID_POWER_BKUP         0x427UL9252	#define STRUCT_HDR_STRUCT_ID_PEER_MMAP          0x429UL9253	#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE         0x1UL9254	#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION   0xaUL9255	#define STRUCT_HDR_STRUCT_ID_RSS_V2             0x64UL9256	#define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF        0xc8UL9257	#define STRUCT_HDR_STRUCT_ID_LAST              STRUCT_HDR_STRUCT_ID_MSIX_PER_VF9258	__le16	len;9259	u8	version;9260	u8	count;9261	__le16	subtype;9262	__le16	next_offset;9263	#define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL9264	u8	unused_0[6];9265};9266 9267/* hwrm_struct_data_dcbx_app (size:64b/8B) */9268struct hwrm_struct_data_dcbx_app {9269	__be16	protocol_id;9270	u8	protocol_selector;9271	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE   0x1UL9272	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT     0x2UL9273	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT     0x3UL9274	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL9275	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST        STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT9276	u8	priority;9277	u8	valid;9278	u8	unused_0[3];9279};9280 9281/* hwrm_fw_set_structured_data_input (size:256b/32B) */9282struct hwrm_fw_set_structured_data_input {9283	__le16	req_type;9284	__le16	cmpl_ring;9285	__le16	seq_id;9286	__le16	target_id;9287	__le64	resp_addr;9288	__le64	src_data_addr;9289	__le16	data_len;9290	u8	hdr_cnt;9291	u8	unused_0[5];9292};9293 9294/* hwrm_fw_set_structured_data_output (size:128b/16B) */9295struct hwrm_fw_set_structured_data_output {9296	__le16	error_code;9297	__le16	req_type;9298	__le16	seq_id;9299	__le16	resp_len;9300	u8	unused_0[7];9301	u8	valid;9302};9303 9304/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */9305struct hwrm_fw_set_structured_data_cmd_err {9306	u8	code;9307	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN     0x0UL9308	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL9309	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT     0x2UL9310	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID      0x3UL9311	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST       FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID9312	u8	unused_0[7];9313};9314 9315/* hwrm_fw_get_structured_data_input (size:256b/32B) */9316struct hwrm_fw_get_structured_data_input {9317	__le16	req_type;9318	__le16	cmpl_ring;9319	__le16	seq_id;9320	__le16	target_id;9321	__le64	resp_addr;9322	__le64	dest_data_addr;9323	__le16	data_len;9324	__le16	structure_id;9325	__le16	subtype;9326	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED                  0x0UL9327	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL                     0xffffUL9328	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN       0x100UL9329	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER        0x101UL9330	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL9331	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN          0x200UL9332	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER           0x201UL9333	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL    0x202UL9334	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL        0x300UL9335	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST                   FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL9336	u8	count;9337	u8	unused_0;9338};9339 9340/* hwrm_fw_get_structured_data_output (size:128b/16B) */9341struct hwrm_fw_get_structured_data_output {9342	__le16	error_code;9343	__le16	req_type;9344	__le16	seq_id;9345	__le16	resp_len;9346	u8	hdr_cnt;9347	u8	unused_0[6];9348	u8	valid;9349};9350 9351/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */9352struct hwrm_fw_get_structured_data_cmd_err {9353	u8	code;9354	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL9355	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID  0x3UL9356	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST   FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID9357	u8	unused_0[7];9358};9359 9360/* hwrm_fw_livepatch_query_input (size:192b/24B) */9361struct hwrm_fw_livepatch_query_input {9362	__le16	req_type;9363	__le16	cmpl_ring;9364	__le16	seq_id;9365	__le16	target_id;9366	__le64	resp_addr;9367	u8	fw_target;9368	#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL9369	#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL9370	#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST     FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW9371	u8	unused_0[7];9372};9373 9374/* hwrm_fw_livepatch_query_output (size:640b/80B) */9375struct hwrm_fw_livepatch_query_output {9376	__le16	error_code;9377	__le16	req_type;9378	__le16	seq_id;9379	__le16	resp_len;9380	char	install_ver[32];9381	char	active_ver[32];9382	__le16	status_flags;9383	#define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL     0x1UL9384	#define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE      0x2UL9385	u8	unused_0[5];9386	u8	valid;9387};9388 9389/* hwrm_fw_livepatch_input (size:256b/32B) */9390struct hwrm_fw_livepatch_input {9391	__le16	req_type;9392	__le16	cmpl_ring;9393	__le16	seq_id;9394	__le16	target_id;9395	__le64	resp_addr;9396	u8	opcode;9397	#define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE   0x1UL9398	#define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL9399	#define FW_LIVEPATCH_REQ_OPCODE_LAST      FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE9400	u8	fw_target;9401	#define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL9402	#define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL9403	#define FW_LIVEPATCH_REQ_FW_TARGET_LAST     FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW9404	u8	loadtype;9405	#define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL   0x1UL9406	#define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL9407	#define FW_LIVEPATCH_REQ_LOADTYPE_LAST         FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT9408	u8	flags;9409	__le32	patch_len;9410	__le64	host_addr;9411};9412 9413/* hwrm_fw_livepatch_output (size:128b/16B) */9414struct hwrm_fw_livepatch_output {9415	__le16	error_code;9416	__le16	req_type;9417	__le16	seq_id;9418	__le16	resp_len;9419	u8	unused_0[7];9420	u8	valid;9421};9422 9423/* hwrm_fw_livepatch_cmd_err (size:64b/8B) */9424struct hwrm_fw_livepatch_cmd_err {9425	u8	code;9426	#define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN         0x0UL9427	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE  0x1UL9428	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET  0x2UL9429	#define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED   0x3UL9430	#define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED   0x4UL9431	#define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED     0x5UL9432	#define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL       0x6UL9433	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER  0x7UL9434	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE    0x8UL9435	#define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL9436	#define FW_LIVEPATCH_CMD_ERR_CODE_LAST           FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED9437	u8	unused_0[7];9438};9439 9440/* hwrm_exec_fwd_resp_input (size:1024b/128B) */9441struct hwrm_exec_fwd_resp_input {9442	__le16	req_type;9443	__le16	cmpl_ring;9444	__le16	seq_id;9445	__le16	target_id;9446	__le64	resp_addr;9447	__le32	encap_request[26];9448	__le16	encap_resp_target_id;9449	u8	unused_0[6];9450};9451 9452/* hwrm_exec_fwd_resp_output (size:128b/16B) */9453struct hwrm_exec_fwd_resp_output {9454	__le16	error_code;9455	__le16	req_type;9456	__le16	seq_id;9457	__le16	resp_len;9458	u8	unused_0[7];9459	u8	valid;9460};9461 9462/* hwrm_reject_fwd_resp_input (size:1024b/128B) */9463struct hwrm_reject_fwd_resp_input {9464	__le16	req_type;9465	__le16	cmpl_ring;9466	__le16	seq_id;9467	__le16	target_id;9468	__le64	resp_addr;9469	__le32	encap_request[26];9470	__le16	encap_resp_target_id;9471	u8	unused_0[6];9472};9473 9474/* hwrm_reject_fwd_resp_output (size:128b/16B) */9475struct hwrm_reject_fwd_resp_output {9476	__le16	error_code;9477	__le16	req_type;9478	__le16	seq_id;9479	__le16	resp_len;9480	u8	unused_0[7];9481	u8	valid;9482};9483 9484/* hwrm_fwd_resp_input (size:1024b/128B) */9485struct hwrm_fwd_resp_input {9486	__le16	req_type;9487	__le16	cmpl_ring;9488	__le16	seq_id;9489	__le16	target_id;9490	__le64	resp_addr;9491	__le16	encap_resp_target_id;9492	__le16	encap_resp_cmpl_ring;9493	__le16	encap_resp_len;9494	u8	unused_0;9495	u8	unused_1;9496	__le64	encap_resp_addr;9497	__le32	encap_resp[24];9498};9499 9500/* hwrm_fwd_resp_output (size:128b/16B) */9501struct hwrm_fwd_resp_output {9502	__le16	error_code;9503	__le16	req_type;9504	__le16	seq_id;9505	__le16	resp_len;9506	u8	unused_0[7];9507	u8	valid;9508};9509 9510/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */9511struct hwrm_fwd_async_event_cmpl_input {9512	__le16	req_type;9513	__le16	cmpl_ring;9514	__le16	seq_id;9515	__le16	target_id;9516	__le64	resp_addr;9517	__le16	encap_async_event_target_id;9518	u8	unused_0[6];9519	__le32	encap_async_event_cmpl[4];9520};9521 9522/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */9523struct hwrm_fwd_async_event_cmpl_output {9524	__le16	error_code;9525	__le16	req_type;9526	__le16	seq_id;9527	__le16	resp_len;9528	u8	unused_0[7];9529	u8	valid;9530};9531 9532/* hwrm_temp_monitor_query_input (size:128b/16B) */9533struct hwrm_temp_monitor_query_input {9534	__le16	req_type;9535	__le16	cmpl_ring;9536	__le16	seq_id;9537	__le16	target_id;9538	__le64	resp_addr;9539};9540 9541/* hwrm_temp_monitor_query_output (size:192b/24B) */9542struct hwrm_temp_monitor_query_output {9543	__le16	error_code;9544	__le16	req_type;9545	__le16	seq_id;9546	__le16	resp_len;9547	u8	temp;9548	u8	phy_temp;9549	u8	om_temp;9550	u8	flags;9551	#define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE             0x1UL9552	#define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE         0x2UL9553	#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT                 0x4UL9554	#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE          0x8UL9555	#define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE      0x10UL9556	#define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE     0x20UL9557	u8	temp2;9558	u8	phy_temp2;9559	u8	om_temp2;9560	u8	warn_threshold;9561	u8	critical_threshold;9562	u8	fatal_threshold;9563	u8	shutdown_threshold;9564	u8	unused_0[4];9565	u8	valid;9566};9567 9568/* hwrm_wol_filter_alloc_input (size:512b/64B) */9569struct hwrm_wol_filter_alloc_input {9570	__le16	req_type;9571	__le16	cmpl_ring;9572	__le16	seq_id;9573	__le16	target_id;9574	__le64	resp_addr;9575	__le32	flags;9576	__le32	enables;9577	#define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS           0x1UL9578	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET        0x2UL9579	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE      0x4UL9580	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR      0x8UL9581	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR     0x10UL9582	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE     0x20UL9583	__le16	port_id;9584	u8	wol_type;9585	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL9586	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP      0x1UL9587	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID  0xffUL9588	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST    WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID9589	u8	unused_0[5];9590	u8	mac_address[6];9591	__le16	pattern_offset;9592	__le16	pattern_buf_size;9593	__le16	pattern_mask_size;9594	u8	unused_1[4];9595	__le64	pattern_buf_addr;9596	__le64	pattern_mask_addr;9597};9598 9599/* hwrm_wol_filter_alloc_output (size:128b/16B) */9600struct hwrm_wol_filter_alloc_output {9601	__le16	error_code;9602	__le16	req_type;9603	__le16	seq_id;9604	__le16	resp_len;9605	u8	wol_filter_id;9606	u8	unused_0[6];9607	u8	valid;9608};9609 9610/* hwrm_wol_filter_free_input (size:256b/32B) */9611struct hwrm_wol_filter_free_input {9612	__le16	req_type;9613	__le16	cmpl_ring;9614	__le16	seq_id;9615	__le16	target_id;9616	__le64	resp_addr;9617	__le32	flags;9618	#define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS     0x1UL9619	__le32	enables;9620	#define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID     0x1UL9621	__le16	port_id;9622	u8	wol_filter_id;9623	u8	unused_0[5];9624};9625 9626/* hwrm_wol_filter_free_output (size:128b/16B) */9627struct hwrm_wol_filter_free_output {9628	__le16	error_code;9629	__le16	req_type;9630	__le16	seq_id;9631	__le16	resp_len;9632	u8	unused_0[7];9633	u8	valid;9634};9635 9636/* hwrm_wol_filter_qcfg_input (size:448b/56B) */9637struct hwrm_wol_filter_qcfg_input {9638	__le16	req_type;9639	__le16	cmpl_ring;9640	__le16	seq_id;9641	__le16	target_id;9642	__le64	resp_addr;9643	__le16	port_id;9644	__le16	handle;9645	u8	unused_0[4];9646	__le64	pattern_buf_addr;9647	__le16	pattern_buf_size;9648	u8	unused_1[6];9649	__le64	pattern_mask_addr;9650	__le16	pattern_mask_size;9651	u8	unused_2[6];9652};9653 9654/* hwrm_wol_filter_qcfg_output (size:256b/32B) */9655struct hwrm_wol_filter_qcfg_output {9656	__le16	error_code;9657	__le16	req_type;9658	__le16	seq_id;9659	__le16	resp_len;9660	__le16	next_handle;9661	u8	wol_filter_id;9662	u8	wol_type;9663	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL9664	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP      0x1UL9665	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID  0xffUL9666	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST    WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID9667	__le32	unused_0;9668	u8	mac_address[6];9669	__le16	pattern_offset;9670	__le16	pattern_size;9671	__le16	pattern_mask_size;9672	u8	unused_1[3];9673	u8	valid;9674};9675 9676/* hwrm_wol_reason_qcfg_input (size:320b/40B) */9677struct hwrm_wol_reason_qcfg_input {9678	__le16	req_type;9679	__le16	cmpl_ring;9680	__le16	seq_id;9681	__le16	target_id;9682	__le64	resp_addr;9683	__le16	port_id;9684	u8	unused_0[6];9685	__le64	wol_pkt_buf_addr;9686	__le16	wol_pkt_buf_size;9687	u8	unused_1[6];9688};9689 9690/* hwrm_wol_reason_qcfg_output (size:128b/16B) */9691struct hwrm_wol_reason_qcfg_output {9692	__le16	error_code;9693	__le16	req_type;9694	__le16	seq_id;9695	__le16	resp_len;9696	u8	wol_filter_id;9697	u8	wol_reason;9698	#define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL9699	#define WOL_REASON_QCFG_RESP_WOL_REASON_BMP      0x1UL9700	#define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID  0xffUL9701	#define WOL_REASON_QCFG_RESP_WOL_REASON_LAST    WOL_REASON_QCFG_RESP_WOL_REASON_INVALID9702	u8	wol_pkt_len;9703	u8	unused_0[4];9704	u8	valid;9705};9706 9707/* hwrm_dbg_read_direct_input (size:256b/32B) */9708struct hwrm_dbg_read_direct_input {9709	__le16	req_type;9710	__le16	cmpl_ring;9711	__le16	seq_id;9712	__le16	target_id;9713	__le64	resp_addr;9714	__le64	host_dest_addr;9715	__le32	read_addr;9716	__le32	read_len32;9717};9718 9719/* hwrm_dbg_read_direct_output (size:128b/16B) */9720struct hwrm_dbg_read_direct_output {9721	__le16	error_code;9722	__le16	req_type;9723	__le16	seq_id;9724	__le16	resp_len;9725	__le32	crc32;9726	u8	unused_0[3];9727	u8	valid;9728};9729 9730/* hwrm_dbg_qcaps_input (size:192b/24B) */9731struct hwrm_dbg_qcaps_input {9732	__le16	req_type;9733	__le16	cmpl_ring;9734	__le16	seq_id;9735	__le16	target_id;9736	__le64	resp_addr;9737	__le16	fid;9738	u8	unused_0[6];9739};9740 9741/* hwrm_dbg_qcaps_output (size:192b/24B) */9742struct hwrm_dbg_qcaps_output {9743	__le16	error_code;9744	__le16	req_type;9745	__le16	seq_id;9746	__le16	resp_len;9747	__le16	fid;9748	u8	unused_0[2];9749	__le32	coredump_component_disable_caps;9750	#define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM     0x1UL9751	__le32	flags;9752	#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM             0x1UL9753	#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR        0x2UL9754	#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR         0x4UL9755	#define DBG_QCAPS_RESP_FLAGS_USEQ                      0x8UL9756	#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR         0x10UL9757	#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE     0x20UL9758	#define DBG_QCAPS_RESP_FLAGS_PTRACE                    0x40UL9759	u8	unused_1[3];9760	u8	valid;9761};9762 9763/* hwrm_dbg_qcfg_input (size:192b/24B) */9764struct hwrm_dbg_qcfg_input {9765	__le16	req_type;9766	__le16	cmpl_ring;9767	__le16	seq_id;9768	__le16	target_id;9769	__le64	resp_addr;9770	__le16	fid;9771	__le16	flags;9772	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK         0x3UL9773	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT          09774	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM       0x0UL9775	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR  0x1UL9776	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR   0x2UL9777	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST          DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR9778	__le32	coredump_component_disable_flags;9779	#define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM     0x1UL9780};9781 9782/* hwrm_dbg_qcfg_output (size:256b/32B) */9783struct hwrm_dbg_qcfg_output {9784	__le16	error_code;9785	__le16	req_type;9786	__le16	seq_id;9787	__le16	resp_len;9788	__le16	fid;9789	u8	unused_0[2];9790	__le32	coredump_size;9791	__le32	flags;9792	#define DBG_QCFG_RESP_FLAGS_UART_LOG               0x1UL9793	#define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY     0x2UL9794	#define DBG_QCFG_RESP_FLAGS_FW_TRACE               0x4UL9795	#define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY     0x8UL9796	#define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY           0x10UL9797	#define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG             0x20UL9798	__le16	async_cmpl_ring;9799	u8	unused_2[2];9800	__le32	crashdump_size;9801	u8	unused_3[3];9802	u8	valid;9803};9804 9805/* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */9806struct hwrm_dbg_crashdump_medium_cfg_input {9807	__le16	req_type;9808	__le16	cmpl_ring;9809	__le16	seq_id;9810	__le16	target_id;9811	__le64	resp_addr;9812	__le16	output_dest_flags;9813	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR     0x1UL9814	__le16	pg_size_lvl;9815	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK      0x3UL9816	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT       09817	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0       0x0UL9818	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1       0x1UL9819	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2       0x2UL9820	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST       DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_29821	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK  0x1cUL9822	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT   29823	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K   (0x0UL << 2)9824	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K   (0x1UL << 2)9825	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K  (0x2UL << 2)9826	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M   (0x3UL << 2)9827	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M   (0x4UL << 2)9828	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G   (0x5UL << 2)9829	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST   DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G9830	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL9831	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT  59832	__le32	size;9833	__le32	coredump_component_disable_flags;9834	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM     0x1UL9835	__le32	unused_0;9836	__le64	pbl;9837};9838 9839/* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */9840struct hwrm_dbg_crashdump_medium_cfg_output {9841	__le16	error_code;9842	__le16	req_type;9843	__le16	seq_id;9844	__le16	resp_len;9845	u8	unused_1[7];9846	u8	valid;9847};9848 9849/* coredump_segment_record (size:128b/16B) */9850struct coredump_segment_record {9851	__le16	component_id;9852	__le16	segment_id;9853	__le16	max_instances;9854	u8	version_hi;9855	u8	version_low;9856	u8	seg_flags;9857	u8	compress_flags;9858	#define SFLAG_COMPRESSED_ZLIB     0x1UL9859	u8	unused_0[2];9860	__le32	segment_len;9861};9862 9863/* hwrm_dbg_coredump_list_input (size:256b/32B) */9864struct hwrm_dbg_coredump_list_input {9865	__le16	req_type;9866	__le16	cmpl_ring;9867	__le16	seq_id;9868	__le16	target_id;9869	__le64	resp_addr;9870	__le64	host_dest_addr;9871	__le32	host_buf_len;9872	__le16	seq_no;9873	u8	flags;9874	#define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP     0x1UL9875	u8	unused_0[1];9876};9877 9878/* hwrm_dbg_coredump_list_output (size:128b/16B) */9879struct hwrm_dbg_coredump_list_output {9880	__le16	error_code;9881	__le16	req_type;9882	__le16	seq_id;9883	__le16	resp_len;9884	u8	flags;9885	#define DBG_COREDUMP_LIST_RESP_FLAGS_MORE     0x1UL9886	u8	unused_0;9887	__le16	total_segments;9888	__le16	data_len;9889	u8	unused_1;9890	u8	valid;9891};9892 9893/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */9894struct hwrm_dbg_coredump_initiate_input {9895	__le16	req_type;9896	__le16	cmpl_ring;9897	__le16	seq_id;9898	__le16	target_id;9899	__le64	resp_addr;9900	__le16	component_id;9901	__le16	segment_id;9902	__le16	instance;9903	__le16	unused_0;9904	u8	seg_flags;9905	#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_LIVE_DATA                0x1UL9906	#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_CRASH_DATA               0x2UL9907	#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE     0x4UL9908	u8	unused_1[7];9909};9910 9911/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */9912struct hwrm_dbg_coredump_initiate_output {9913	__le16	error_code;9914	__le16	req_type;9915	__le16	seq_id;9916	__le16	resp_len;9917	u8	unused_0[7];9918	u8	valid;9919};9920 9921/* coredump_data_hdr (size:128b/16B) */9922struct coredump_data_hdr {9923	__le32	address;9924	__le32	flags_length;9925	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK     0xffffffUL9926	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT      09927	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS     0x1000000UL9928	__le32	instance;9929	__le32	next_offset;9930};9931 9932/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */9933struct hwrm_dbg_coredump_retrieve_input {9934	__le16	req_type;9935	__le16	cmpl_ring;9936	__le16	seq_id;9937	__le16	target_id;9938	__le64	resp_addr;9939	__le64	host_dest_addr;9940	__le32	host_buf_len;9941	__le32	unused_0;9942	__le16	component_id;9943	__le16	segment_id;9944	__le16	instance;9945	__le16	unused_1;9946	u8	seg_flags;9947	u8	unused_2;9948	__le16	unused_3;9949	__le32	unused_4;9950	__le32	seq_no;9951	__le32	unused_5;9952};9953 9954/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */9955struct hwrm_dbg_coredump_retrieve_output {9956	__le16	error_code;9957	__le16	req_type;9958	__le16	seq_id;9959	__le16	resp_len;9960	u8	flags;9961	#define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE     0x1UL9962	u8	unused_0;9963	__le16	data_len;9964	u8	unused_1[3];9965	u8	valid;9966};9967 9968/* hwrm_dbg_ring_info_get_input (size:192b/24B) */9969struct hwrm_dbg_ring_info_get_input {9970	__le16	req_type;9971	__le16	cmpl_ring;9972	__le16	seq_id;9973	__le16	target_id;9974	__le64	resp_addr;9975	u8	ring_type;9976	#define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL9977	#define DBG_RING_INFO_GET_REQ_RING_TYPE_TX      0x1UL9978	#define DBG_RING_INFO_GET_REQ_RING_TYPE_RX      0x2UL9979	#define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ      0x3UL9980	#define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST   DBG_RING_INFO_GET_REQ_RING_TYPE_NQ9981	u8	unused_0[3];9982	__le32	fw_ring_id;9983};9984 9985/* hwrm_dbg_ring_info_get_output (size:192b/24B) */9986struct hwrm_dbg_ring_info_get_output {9987	__le16	error_code;9988	__le16	req_type;9989	__le16	seq_id;9990	__le16	resp_len;9991	__le32	producer_index;9992	__le32	consumer_index;9993	__le32	cag_vector_ctrl;9994	__le16	st_tag;9995	u8	unused_0;9996	u8	valid;9997};9998 9999/* hwrm_nvm_read_input (size:320b/40B) */10000struct hwrm_nvm_read_input {10001	__le16	req_type;10002	__le16	cmpl_ring;10003	__le16	seq_id;10004	__le16	target_id;10005	__le64	resp_addr;10006	__le64	host_dest_addr;10007	__le16	dir_idx;10008	u8	unused_0[2];10009	__le32	offset;10010	__le32	len;10011	u8	unused_1[4];10012};10013 10014/* hwrm_nvm_read_output (size:128b/16B) */10015struct hwrm_nvm_read_output {10016	__le16	error_code;10017	__le16	req_type;10018	__le16	seq_id;10019	__le16	resp_len;10020	u8	unused_0[7];10021	u8	valid;10022};10023 10024/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */10025struct hwrm_nvm_get_dir_entries_input {10026	__le16	req_type;10027	__le16	cmpl_ring;10028	__le16	seq_id;10029	__le16	target_id;10030	__le64	resp_addr;10031	__le64	host_dest_addr;10032};10033 10034/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */10035struct hwrm_nvm_get_dir_entries_output {10036	__le16	error_code;10037	__le16	req_type;10038	__le16	seq_id;10039	__le16	resp_len;10040	u8	unused_0[7];10041	u8	valid;10042};10043 10044/* hwrm_nvm_get_dir_info_input (size:128b/16B) */10045struct hwrm_nvm_get_dir_info_input {10046	__le16	req_type;10047	__le16	cmpl_ring;10048	__le16	seq_id;10049	__le16	target_id;10050	__le64	resp_addr;10051};10052 10053/* hwrm_nvm_get_dir_info_output (size:192b/24B) */10054struct hwrm_nvm_get_dir_info_output {10055	__le16	error_code;10056	__le16	req_type;10057	__le16	seq_id;10058	__le16	resp_len;10059	__le32	entries;10060	__le32	entry_length;10061	u8	unused_0[7];10062	u8	valid;10063};10064 10065/* hwrm_nvm_write_input (size:448b/56B) */10066struct hwrm_nvm_write_input {10067	__le16	req_type;10068	__le16	cmpl_ring;10069	__le16	seq_id;10070	__le16	target_id;10071	__le64	resp_addr;10072	__le64	host_src_addr;10073	__le16	dir_type;10074	__le16	dir_ordinal;10075	__le16	dir_ext;10076	__le16	dir_attr;10077	__le32	dir_data_length;10078	__le16	option;10079	__le16	flags;10080	#define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG     0x1UL10081	#define NVM_WRITE_REQ_FLAGS_BATCH_MODE               0x2UL10082	#define NVM_WRITE_REQ_FLAGS_BATCH_LAST               0x4UL10083	__le32	dir_item_length;10084	__le32	offset;10085	__le32	len;10086	__le32	unused_0;10087};10088 10089/* hwrm_nvm_write_output (size:128b/16B) */10090struct hwrm_nvm_write_output {10091	__le16	error_code;10092	__le16	req_type;10093	__le16	seq_id;10094	__le16	resp_len;10095	__le32	dir_item_length;10096	__le16	dir_idx;10097	u8	unused_0;10098	u8	valid;10099};10100 10101/* hwrm_nvm_write_cmd_err (size:64b/8B) */10102struct hwrm_nvm_write_cmd_err {10103	u8	code;10104	#define NVM_WRITE_CMD_ERR_CODE_UNKNOWN  0x0UL10105	#define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL10106	#define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL10107	#define NVM_WRITE_CMD_ERR_CODE_LAST    NVM_WRITE_CMD_ERR_CODE_NO_SPACE10108	u8	unused_0[7];10109};10110 10111/* hwrm_nvm_modify_input (size:320b/40B) */10112struct hwrm_nvm_modify_input {10113	__le16	req_type;10114	__le16	cmpl_ring;10115	__le16	seq_id;10116	__le16	target_id;10117	__le64	resp_addr;10118	__le64	host_src_addr;10119	__le16	dir_idx;10120	__le16	flags;10121	#define NVM_MODIFY_REQ_FLAGS_BATCH_MODE     0x1UL10122	#define NVM_MODIFY_REQ_FLAGS_BATCH_LAST     0x2UL10123	__le32	offset;10124	__le32	len;10125	u8	unused_1[4];10126};10127 10128/* hwrm_nvm_modify_output (size:128b/16B) */10129struct hwrm_nvm_modify_output {10130	__le16	error_code;10131	__le16	req_type;10132	__le16	seq_id;10133	__le16	resp_len;10134	u8	unused_0[7];10135	u8	valid;10136};10137 10138/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */10139struct hwrm_nvm_find_dir_entry_input {10140	__le16	req_type;10141	__le16	cmpl_ring;10142	__le16	seq_id;10143	__le16	target_id;10144	__le64	resp_addr;10145	__le32	enables;10146	#define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID     0x1UL10147	__le16	dir_idx;10148	__le16	dir_type;10149	__le16	dir_ordinal;10150	__le16	dir_ext;10151	u8	opt_ordinal;10152	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL10153	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 010154	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ    0x0UL10155	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE    0x1UL10156	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT    0x2UL10157	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT10158	u8	unused_0[3];10159};10160 10161/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */10162struct hwrm_nvm_find_dir_entry_output {10163	__le16	error_code;10164	__le16	req_type;10165	__le16	seq_id;10166	__le16	resp_len;10167	__le32	dir_item_length;10168	__le32	dir_data_length;10169	__le32	fw_ver;10170	__le16	dir_ordinal;10171	__le16	dir_idx;10172	u8	unused_0[7];10173	u8	valid;10174};10175 10176/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */10177struct hwrm_nvm_erase_dir_entry_input {10178	__le16	req_type;10179	__le16	cmpl_ring;10180	__le16	seq_id;10181	__le16	target_id;10182	__le64	resp_addr;10183	__le16	dir_idx;10184	u8	unused_0[6];10185};10186 10187/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */10188struct hwrm_nvm_erase_dir_entry_output {10189	__le16	error_code;10190	__le16	req_type;10191	__le16	seq_id;10192	__le16	resp_len;10193	u8	unused_0[7];10194	u8	valid;10195};10196 10197/* hwrm_nvm_get_dev_info_input (size:192b/24B) */10198struct hwrm_nvm_get_dev_info_input {10199	__le16	req_type;10200	__le16	cmpl_ring;10201	__le16	seq_id;10202	__le16	target_id;10203	__le64	resp_addr;10204	u8	flags;10205	#define NVM_GET_DEV_INFO_REQ_FLAGS_SECURITY_SOC_NVM     0x1UL10206	u8	unused_0[7];10207};10208 10209/* hwrm_nvm_get_dev_info_output (size:768b/96B) */10210struct hwrm_nvm_get_dev_info_output {10211	__le16	error_code;10212	__le16	req_type;10213	__le16	seq_id;10214	__le16	resp_len;10215	__le16	manufacturer_id;10216	__le16	device_id;10217	__le32	sector_size;10218	__le32	nvram_size;10219	__le32	reserved_size;10220	__le32	available_size;10221	u8	nvm_cfg_ver_maj;10222	u8	nvm_cfg_ver_min;10223	u8	nvm_cfg_ver_upd;10224	u8	flags;10225	#define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID     0x1UL10226	char	pkg_name[16];10227	__le16	hwrm_fw_major;10228	__le16	hwrm_fw_minor;10229	__le16	hwrm_fw_build;10230	__le16	hwrm_fw_patch;10231	__le16	mgmt_fw_major;10232	__le16	mgmt_fw_minor;10233	__le16	mgmt_fw_build;10234	__le16	mgmt_fw_patch;10235	__le16	roce_fw_major;10236	__le16	roce_fw_minor;10237	__le16	roce_fw_build;10238	__le16	roce_fw_patch;10239	__le16	netctrl_fw_major;10240	__le16	netctrl_fw_minor;10241	__le16	netctrl_fw_build;10242	__le16	netctrl_fw_patch;10243	__le16	srt2_fw_major;10244	__le16	srt2_fw_minor;10245	__le16	srt2_fw_build;10246	__le16	srt2_fw_patch;10247	u8	unused_0[7];10248	u8	valid;10249};10250 10251/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */10252struct hwrm_nvm_mod_dir_entry_input {10253	__le16	req_type;10254	__le16	cmpl_ring;10255	__le16	seq_id;10256	__le16	target_id;10257	__le64	resp_addr;10258	__le32	enables;10259	#define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM     0x1UL10260	__le16	dir_idx;10261	__le16	dir_ordinal;10262	__le16	dir_ext;10263	__le16	dir_attr;10264	__le32	checksum;10265};10266 10267/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */10268struct hwrm_nvm_mod_dir_entry_output {10269	__le16	error_code;10270	__le16	req_type;10271	__le16	seq_id;10272	__le16	resp_len;10273	u8	unused_0[7];10274	u8	valid;10275};10276 10277/* hwrm_nvm_verify_update_input (size:192b/24B) */10278struct hwrm_nvm_verify_update_input {10279	__le16	req_type;10280	__le16	cmpl_ring;10281	__le16	seq_id;10282	__le16	target_id;10283	__le64	resp_addr;10284	__le16	dir_type;10285	__le16	dir_ordinal;10286	__le16	dir_ext;10287	u8	unused_0[2];10288};10289 10290/* hwrm_nvm_verify_update_output (size:128b/16B) */10291struct hwrm_nvm_verify_update_output {10292	__le16	error_code;10293	__le16	req_type;10294	__le16	seq_id;10295	__le16	resp_len;10296	u8	unused_0[7];10297	u8	valid;10298};10299 10300/* hwrm_nvm_install_update_input (size:192b/24B) */10301struct hwrm_nvm_install_update_input {10302	__le16	req_type;10303	__le16	cmpl_ring;10304	__le16	seq_id;10305	__le16	target_id;10306	__le64	resp_addr;10307	__le32	install_type;10308	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL10309	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL    0xffffffffUL10310	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST  NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL10311	__le16	flags;10312	#define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE     0x1UL10313	#define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG      0x2UL10314	#define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG      0x4UL10315	#define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY            0x8UL10316	u8	unused_0[2];10317};10318 10319/* hwrm_nvm_install_update_output (size:192b/24B) */10320struct hwrm_nvm_install_update_output {10321	__le16	error_code;10322	__le16	req_type;10323	__le16	seq_id;10324	__le16	resp_len;10325	__le64	installed_items;10326	u8	result;10327	#define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS                      0x0UL10328	#define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE                      0xffUL10329	#define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE               0xfdUL10330	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER      0xfbUL10331	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER       0xf3UL10332	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE         0xf2UL10333	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER          0xecUL10334	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE            0xebUL10335	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM          0xeaUL10336	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH          0xe9UL10337	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST             0xe8UL10338	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER              0xe7UL10339	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM             0xe6UL10340	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM        0xe5UL10341	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH          0xe4UL10342	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE            0xe1UL10343	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV         0xceUL10344	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID        0xcdUL10345	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR    0xccUL10346	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID        0xcbUL10347	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM         0xc5UL10348	#define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM               0xc4UL10349	#define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM             0xc3UL10350	#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR       0xb9UL10351	#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR           0xb8UL10352	#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL10353	#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND               0xb0UL10354	#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED                  0xa7UL10355	#define NVM_INSTALL_UPDATE_RESP_RESULT_LAST                        NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED10356	u8	problem_item;10357	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE    0x0UL10358	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL10359	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST   NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE10360	u8	reset_required;10361	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE  0x0UL10362	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI   0x1UL10363	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL10364	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER10365	u8	unused_0[4];10366	u8	valid;10367};10368 10369/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */10370struct hwrm_nvm_install_update_cmd_err {10371	u8	code;10372	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN            0x0UL10373	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR           0x1UL10374	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE           0x2UL10375	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK      0x3UL10376	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL10377	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST              NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT10378	u8	unused_0[7];10379};10380 10381/* hwrm_nvm_get_variable_input (size:320b/40B) */10382struct hwrm_nvm_get_variable_input {10383	__le16	req_type;10384	__le16	cmpl_ring;10385	__le16	seq_id;10386	__le16	target_id;10387	__le64	resp_addr;10388	__le64	dest_data_addr;10389	__le16	data_len;10390	__le16	option_num;10391	#define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL10392	#define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL10393	#define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF10394	__le16	dimensions;10395	__le16	index_0;10396	__le16	index_1;10397	__le16	index_2;10398	__le16	index_3;10399	u8	flags;10400	#define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT     0x1UL10401	u8	unused_0;10402};10403 10404/* hwrm_nvm_get_variable_output (size:128b/16B) */10405struct hwrm_nvm_get_variable_output {10406	__le16	error_code;10407	__le16	req_type;10408	__le16	seq_id;10409	__le16	resp_len;10410	__le16	data_len;10411	__le16	option_num;10412	#define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0    0x0UL10413	#define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL10414	#define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST     NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF10415	u8	unused_0[3];10416	u8	valid;10417};10418 10419/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */10420struct hwrm_nvm_get_variable_cmd_err {10421	u8	code;10422	#define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL10423	#define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL10424	#define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL10425	#define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL10426	#define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST         NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT10427	u8	unused_0[7];10428};10429 10430/* hwrm_nvm_set_variable_input (size:320b/40B) */10431struct hwrm_nvm_set_variable_input {10432	__le16	req_type;10433	__le16	cmpl_ring;10434	__le16	seq_id;10435	__le16	target_id;10436	__le64	resp_addr;10437	__le64	src_data_addr;10438	__le16	data_len;10439	__le16	option_num;10440	#define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL10441	#define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL10442	#define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF10443	__le16	dimensions;10444	__le16	index_0;10445	__le16	index_1;10446	__le16	index_2;10447	__le16	index_3;10448	u8	flags;10449	#define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH                0x1UL10450	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK          0xeUL10451	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT           110452	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE            (0x0UL << 1)10453	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1       (0x1UL << 1)10454	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256          (0x2UL << 1)10455	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH  (0x3UL << 1)10456	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST           NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH10457	#define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK        0x70UL10458	#define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT         410459	#define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT            0x80UL10460	u8	unused_0;10461};10462 10463/* hwrm_nvm_set_variable_output (size:128b/16B) */10464struct hwrm_nvm_set_variable_output {10465	__le16	error_code;10466	__le16	req_type;10467	__le16	seq_id;10468	__le16	resp_len;10469	u8	unused_0[7];10470	u8	valid;10471};10472 10473/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */10474struct hwrm_nvm_set_variable_cmd_err {10475	u8	code;10476	#define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL10477	#define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL10478	#define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL10479	#define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST         NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR10480	u8	unused_0[7];10481};10482 10483/* hwrm_selftest_qlist_input (size:128b/16B) */10484struct hwrm_selftest_qlist_input {10485	__le16	req_type;10486	__le16	cmpl_ring;10487	__le16	seq_id;10488	__le16	target_id;10489	__le64	resp_addr;10490};10491 10492/* hwrm_selftest_qlist_output (size:2240b/280B) */10493struct hwrm_selftest_qlist_output {10494	__le16	error_code;10495	__le16	req_type;10496	__le16	seq_id;10497	__le16	resp_len;10498	u8	num_tests;10499	u8	available_tests;10500	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST                 0x1UL10501	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST                0x2UL10502	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST            0x4UL10503	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST              0x8UL10504	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST         0x10UL10505	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST     0x20UL10506	u8	offline_tests;10507	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST                 0x1UL10508	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST                0x2UL10509	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST            0x4UL10510	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST              0x8UL10511	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST         0x10UL10512	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST     0x20UL10513	u8	unused_0;10514	__le16	test_timeout;10515	u8	unused_1[2];10516	char	test_name[8][32];10517	u8	eyescope_target_BER_support;10518	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED  0x0UL10519	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED  0x1UL10520	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL10521	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL10522	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL10523	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST              SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED10524	u8	unused_2[6];10525	u8	valid;10526};10527 10528/* hwrm_selftest_exec_input (size:192b/24B) */10529struct hwrm_selftest_exec_input {10530	__le16	req_type;10531	__le16	cmpl_ring;10532	__le16	seq_id;10533	__le16	target_id;10534	__le64	resp_addr;10535	u8	flags;10536	#define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST                 0x1UL10537	#define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST                0x2UL10538	#define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST            0x4UL10539	#define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST              0x8UL10540	#define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST         0x10UL10541	#define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST     0x20UL10542	u8	unused_0[7];10543};10544 10545/* hwrm_selftest_exec_output (size:128b/16B) */10546struct hwrm_selftest_exec_output {10547	__le16	error_code;10548	__le16	req_type;10549	__le16	seq_id;10550	__le16	resp_len;10551	u8	requested_tests;10552	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST                 0x1UL10553	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST                0x2UL10554	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST            0x4UL10555	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST              0x8UL10556	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST         0x10UL10557	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST     0x20UL10558	u8	test_success;10559	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST                 0x1UL10560	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST                0x2UL10561	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST            0x4UL10562	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST              0x8UL10563	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST         0x10UL10564	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST     0x20UL10565	u8	unused_0[5];10566	u8	valid;10567};10568 10569/* hwrm_selftest_irq_input (size:128b/16B) */10570struct hwrm_selftest_irq_input {10571	__le16	req_type;10572	__le16	cmpl_ring;10573	__le16	seq_id;10574	__le16	target_id;10575	__le64	resp_addr;10576};10577 10578/* hwrm_selftest_irq_output (size:128b/16B) */10579struct hwrm_selftest_irq_output {10580	__le16	error_code;10581	__le16	req_type;10582	__le16	seq_id;10583	__le16	resp_len;10584	u8	unused_0[7];10585	u8	valid;10586};10587 10588/* dbc_dbc (size:64b/8B) */10589struct dbc_dbc {10590	__le32	index;10591	#define DBC_DBC_INDEX_MASK 0xffffffUL10592	#define DBC_DBC_INDEX_SFT  010593	#define DBC_DBC_EPOCH      0x1000000UL10594	#define DBC_DBC_TOGGLE_MASK 0x6000000UL10595	#define DBC_DBC_TOGGLE_SFT 2510596	__le32	type_path_xid;10597	#define DBC_DBC_XID_MASK          0xfffffUL10598	#define DBC_DBC_XID_SFT           010599	#define DBC_DBC_PATH_MASK         0x3000000UL10600	#define DBC_DBC_PATH_SFT          2410601	#define DBC_DBC_PATH_ROCE           (0x0UL << 24)10602	#define DBC_DBC_PATH_L2             (0x1UL << 24)10603	#define DBC_DBC_PATH_ENGINE         (0x2UL << 24)10604	#define DBC_DBC_PATH_LAST          DBC_DBC_PATH_ENGINE10605	#define DBC_DBC_VALID             0x4000000UL10606	#define DBC_DBC_DEBUG_TRACE       0x8000000UL10607	#define DBC_DBC_TYPE_MASK         0xf0000000UL10608	#define DBC_DBC_TYPE_SFT          2810609	#define DBC_DBC_TYPE_SQ             (0x0UL << 28)10610	#define DBC_DBC_TYPE_RQ             (0x1UL << 28)10611	#define DBC_DBC_TYPE_SRQ            (0x2UL << 28)10612	#define DBC_DBC_TYPE_SRQ_ARM        (0x3UL << 28)10613	#define DBC_DBC_TYPE_CQ             (0x4UL << 28)10614	#define DBC_DBC_TYPE_CQ_ARMSE       (0x5UL << 28)10615	#define DBC_DBC_TYPE_CQ_ARMALL      (0x6UL << 28)10616	#define DBC_DBC_TYPE_CQ_ARMENA      (0x7UL << 28)10617	#define DBC_DBC_TYPE_SRQ_ARMENA     (0x8UL << 28)10618	#define DBC_DBC_TYPE_CQ_CUTOFF_ACK  (0x9UL << 28)10619	#define DBC_DBC_TYPE_NQ             (0xaUL << 28)10620	#define DBC_DBC_TYPE_NQ_ARM         (0xbUL << 28)10621	#define DBC_DBC_TYPE_NQ_MASK        (0xeUL << 28)10622	#define DBC_DBC_TYPE_NULL           (0xfUL << 28)10623	#define DBC_DBC_TYPE_LAST          DBC_DBC_TYPE_NULL10624};10625 10626/* db_push_start (size:64b/8B) */10627struct db_push_start {10628	u64	db;10629	#define DB_PUSH_START_DB_INDEX_MASK     0xffffffUL10630	#define DB_PUSH_START_DB_INDEX_SFT      010631	#define DB_PUSH_START_DB_PI_LO_MASK     0xff000000UL10632	#define DB_PUSH_START_DB_PI_LO_SFT      2410633	#define DB_PUSH_START_DB_XID_MASK       0xfffff00000000ULL10634	#define DB_PUSH_START_DB_XID_SFT        3210635	#define DB_PUSH_START_DB_PI_HI_MASK     0xf0000000000000ULL10636	#define DB_PUSH_START_DB_PI_HI_SFT      5210637	#define DB_PUSH_START_DB_TYPE_MASK      0xf000000000000000ULL10638	#define DB_PUSH_START_DB_TYPE_SFT       6010639	#define DB_PUSH_START_DB_TYPE_PUSH_START  (0xcULL << 60)10640	#define DB_PUSH_START_DB_TYPE_PUSH_END    (0xdULL << 60)10641	#define DB_PUSH_START_DB_TYPE_LAST       DB_PUSH_START_DB_TYPE_PUSH_END10642};10643 10644/* db_push_end (size:64b/8B) */10645struct db_push_end {10646	u64	db;10647	#define DB_PUSH_END_DB_INDEX_MASK      0xffffffUL10648	#define DB_PUSH_END_DB_INDEX_SFT       010649	#define DB_PUSH_END_DB_PI_LO_MASK      0xff000000UL10650	#define DB_PUSH_END_DB_PI_LO_SFT       2410651	#define DB_PUSH_END_DB_XID_MASK        0xfffff00000000ULL10652	#define DB_PUSH_END_DB_XID_SFT         3210653	#define DB_PUSH_END_DB_PI_HI_MASK      0xf0000000000000ULL10654	#define DB_PUSH_END_DB_PI_HI_SFT       5210655	#define DB_PUSH_END_DB_PATH_MASK       0x300000000000000ULL10656	#define DB_PUSH_END_DB_PATH_SFT        5610657	#define DB_PUSH_END_DB_PATH_ROCE         (0x0ULL << 56)10658	#define DB_PUSH_END_DB_PATH_L2           (0x1ULL << 56)10659	#define DB_PUSH_END_DB_PATH_ENGINE       (0x2ULL << 56)10660	#define DB_PUSH_END_DB_PATH_LAST        DB_PUSH_END_DB_PATH_ENGINE10661	#define DB_PUSH_END_DB_DEBUG_TRACE     0x800000000000000ULL10662	#define DB_PUSH_END_DB_TYPE_MASK       0xf000000000000000ULL10663	#define DB_PUSH_END_DB_TYPE_SFT        6010664	#define DB_PUSH_END_DB_TYPE_PUSH_START   (0xcULL << 60)10665	#define DB_PUSH_END_DB_TYPE_PUSH_END     (0xdULL << 60)10666	#define DB_PUSH_END_DB_TYPE_LAST        DB_PUSH_END_DB_TYPE_PUSH_END10667};10668 10669/* db_push_info (size:64b/8B) */10670struct db_push_info {10671	u32	push_size_push_index;10672	#define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL10673	#define DB_PUSH_INFO_PUSH_INDEX_SFT 010674	#define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL10675	#define DB_PUSH_INFO_PUSH_SIZE_SFT  2410676	u32	reserved32;10677};10678 10679/* fw_status_reg (size:32b/4B) */10680struct fw_status_reg {10681	u32	fw_status;10682	#define FW_STATUS_REG_CODE_MASK              0xffffUL10683	#define FW_STATUS_REG_CODE_SFT               010684	#define FW_STATUS_REG_CODE_READY               0x8000UL10685	#define FW_STATUS_REG_CODE_LAST               FW_STATUS_REG_CODE_READY10686	#define FW_STATUS_REG_IMAGE_DEGRADED         0x10000UL10687	#define FW_STATUS_REG_RECOVERABLE            0x20000UL10688	#define FW_STATUS_REG_CRASHDUMP_ONGOING      0x40000UL10689	#define FW_STATUS_REG_CRASHDUMP_COMPLETE     0x80000UL10690	#define FW_STATUS_REG_SHUTDOWN               0x100000UL10691	#define FW_STATUS_REG_CRASHED_NO_MASTER      0x200000UL10692	#define FW_STATUS_REG_RECOVERING             0x400000UL10693	#define FW_STATUS_REG_MANU_DEBUG_STATUS      0x800000UL10694};10695 10696/* hcomm_status (size:64b/8B) */10697struct hcomm_status {10698	u32	sig_ver;10699	#define HCOMM_STATUS_VER_MASK      0xffUL10700	#define HCOMM_STATUS_VER_SFT       010701	#define HCOMM_STATUS_VER_LATEST      0x1UL10702	#define HCOMM_STATUS_VER_LAST       HCOMM_STATUS_VER_LATEST10703	#define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL10704	#define HCOMM_STATUS_SIGNATURE_SFT 810705	#define HCOMM_STATUS_SIGNATURE_VAL   (0x484353UL << 8)10706	#define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL10707	u32	fw_status_loc;10708	#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK    0x3UL10709	#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT     010710	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG  0x0UL10711	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC       0x1UL10712	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0      0x2UL10713	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1      0x3UL10714	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST     HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR110715	#define HCOMM_STATUS_TRUE_OFFSET_MASK        0xfffffffcUL10716	#define HCOMM_STATUS_TRUE_OFFSET_SFT         210717};10718#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL10719 10720#endif /* _BNXT_HSI_H_ */10721