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1/* cnic.h: QLogic CNIC core network driver.2 *3 * Copyright (c) 2006-2014 Broadcom Corporation4 * Copyright (c) 2014 QLogic Corporation5 *6 * This program is free software; you can redistribute it and/or modify7 * it under the terms of the GNU General Public License as published by8 * the Free Software Foundation.9 *10 */11 12 13#ifndef CNIC_H14#define CNIC_H15 16#define HC_INDEX_ISCSI_EQ_CONS 617 18#define HC_INDEX_FCOE_EQ_CONS 319 20#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 521#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 122 23#define KWQ_PAGE_CNT 424#define KCQ_PAGE_CNT 1625 26#define KWQ_CID 2427#define KCQ_CID 2528 29/*30 * krnlq_context definition31 */32#define L5_KRNLQ_FLAGS 0x0000000033#define L5_KRNLQ_SIZE 0x0000000034#define L5_KRNLQ_TYPE 0x0000000035#define KRNLQ_FLAGS_PG_SZ (0xf<<0)36#define KRNLQ_FLAGS_PG_SZ_256 (0<<0)37#define KRNLQ_FLAGS_PG_SZ_512 (1<<0)38#define KRNLQ_FLAGS_PG_SZ_1K (2<<0)39#define KRNLQ_FLAGS_PG_SZ_2K (3<<0)40#define KRNLQ_FLAGS_PG_SZ_4K (4<<0)41#define KRNLQ_FLAGS_PG_SZ_8K (5<<0)42#define KRNLQ_FLAGS_PG_SZ_16K (6<<0)43#define KRNLQ_FLAGS_PG_SZ_32K (7<<0)44#define KRNLQ_FLAGS_PG_SZ_64K (8<<0)45#define KRNLQ_FLAGS_PG_SZ_128K (9<<0)46#define KRNLQ_FLAGS_PG_SZ_256K (10<<0)47#define KRNLQ_FLAGS_PG_SZ_512K (11<<0)48#define KRNLQ_FLAGS_PG_SZ_1M (12<<0)49#define KRNLQ_FLAGS_PG_SZ_2M (13<<0)50#define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15)51#define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16)52#define KRNLQ_TYPE_TYPE (0xf<<28)53#define KRNLQ_TYPE_TYPE_EMPTY (0<<28)54#define KRNLQ_TYPE_TYPE_KRNLQ (6<<28)55 56#define L5_KRNLQ_HOST_QIDX 0x0000000457#define L5_KRNLQ_HOST_FW_QIDX 0x0000000858#define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c59#define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c60#define L5_KRNLQ_NX_QE_HADDR_HI 0x0000001061#define L5_KRNLQ_NX_QE_HADDR_LO 0x0000001462#define L5_KRNLQ_PGTBL_PGIDX 0x0000001863#define L5_KRNLQ_NX_PG_QIDX 0x0000001864#define L5_KRNLQ_PGTBL_NPAGES 0x0000001c65#define L5_KRNLQ_QIDX_INCR 0x0000001c66#define L5_KRNLQ_PGTBL_HADDR_HI 0x0000002067#define L5_KRNLQ_PGTBL_HADDR_LO 0x0000002468 69#define BNX2_PG_CTX_MAP 0x1a003470#define BNX2_ISCSI_CTX_MAP 0x1a007471 72#define MAX_COMPLETED_KCQE 6473 74#define MAX_CNIC_L5_CONTEXT 25675 76#define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT77 78#define MAX_ISCSI_TBL_SZ 25679 80#define CNIC_LOCAL_PORT_MIN 6000081#define CNIC_LOCAL_PORT_MAX 6102482#define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)83 84#define KWQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kwqe))85#define KCQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kcqe))86#define MAX_KWQE_CNT (KWQE_CNT - 1)87#define MAX_KCQE_CNT (KCQE_CNT - 1)88 89#define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1)90#define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1)91 92#define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BNX2_PAGE_BITS - 5))93#define KWQ_IDX(x) ((x) & MAX_KWQE_CNT)94 95#define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BNX2_PAGE_BITS - 5))96#define KCQ_IDX(x) ((x) & MAX_KCQE_CNT)97 98#define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \99 (MAX_KCQE_CNT - 1)) ? \100 (x) + 2 : (x) + 1101 102#define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp)103#define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp)104#define BNX2X_KWQ_DATA(cp, x) \105 &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)]106 107#define DEF_IPID_START 0x8000108 109#define DEF_KA_TIMEOUT 10000110#define DEF_KA_INTERVAL 300000111#define DEF_KA_MAX_PROBE_COUNT 3112#define DEF_TOS 0113#define DEF_TTL 0xfe114#define DEF_SND_SEQ_SCALE 0115#define DEF_RCV_BUF 0xffff116#define DEF_SND_BUF 0xffff117#define DEF_SEED 0118#define DEF_MAX_RT_TIME 500119#define DEF_MAX_DA_COUNT 2120#define DEF_SWS_TIMER 1000121#define DEF_MAX_CWND 0xffff122 123struct cnic_ctx {124 u32 cid;125 void *ctx;126 dma_addr_t mapping;127};128 129#define BNX2_MAX_CID 0x2000130 131struct cnic_dma {132 int num_pages;133 void **pg_arr;134 dma_addr_t *pg_map_arr;135 int pgtbl_size;136 u32 *pgtbl;137 dma_addr_t pgtbl_map;138};139 140struct cnic_id_tbl {141 spinlock_t lock;142 u32 start;143 u32 max;144 u32 next;145 unsigned long *table;146};147 148#define CNIC_KWQ16_DATA_SIZE 128149 150struct kwqe_16_data {151 u8 data[CNIC_KWQ16_DATA_SIZE];152};153 154struct cnic_iscsi {155 struct cnic_dma task_array_info;156 struct cnic_dma r2tq_info;157 struct cnic_dma hq_info;158};159 160struct cnic_context {161 u32 cid;162 struct kwqe_16_data *kwqe_data;163 dma_addr_t kwqe_data_mapping;164 wait_queue_head_t waitq;165 int wait_cond;166 unsigned long timestamp;167 unsigned long ctx_flags;168#define CTX_FL_OFFLD_START 0169#define CTX_FL_DELETE_WAIT 1170#define CTX_FL_CID_ERROR 2171 u8 ulp_proto_id;172 union {173 struct cnic_iscsi *iscsi;174 } proto;175};176 177struct kcq_info {178 struct cnic_dma dma;179 struct kcqe **kcq;180 181 u16 *hw_prod_idx_ptr;182 u16 sw_prod_idx;183 u16 *status_idx_ptr;184 u32 io_addr;185 186 u16 (*next_idx)(u16);187 u16 (*hw_idx)(u16);188};189 190#define UIO_USE_TX_DOORBELL 0x017855DB191 192struct cnic_uio_dev {193 struct uio_info cnic_uinfo;194 u32 uio_dev;195 196 int l2_ring_size;197 void *l2_ring;198 dma_addr_t l2_ring_map;199 200 int l2_buf_size;201 void *l2_buf;202 dma_addr_t l2_buf_map;203 204 struct cnic_dev *dev;205 struct pci_dev *pdev;206 struct list_head list;207};208 209struct cnic_local {210 211 spinlock_t cnic_ulp_lock;212 void *ulp_handle[MAX_CNIC_ULP_TYPE];213 unsigned long ulp_flags[MAX_CNIC_ULP_TYPE];214#define ULP_F_INIT 0215#define ULP_F_START 1216#define ULP_F_CALL_PENDING 2217 struct cnic_ulp_ops __rcu *ulp_ops[MAX_CNIC_ULP_TYPE];218 219 unsigned long cnic_local_flags;220#define CNIC_LCL_FL_KWQ_INIT 0x0221#define CNIC_LCL_FL_L2_WAIT 0x1222#define CNIC_LCL_FL_RINGS_INITED 0x2223#define CNIC_LCL_FL_STOP_ISCSI 0x4224 225 struct cnic_dev *dev;226 227 struct cnic_eth_dev *ethdev;228 229 struct cnic_uio_dev *udev;230 231 int l2_rx_ring_size;232 int l2_single_buf_size;233 234 u16 *rx_cons_ptr;235 u16 *tx_cons_ptr;236 u16 rx_cons;237 u16 tx_cons;238 239 struct cnic_dma kwq_info;240 struct kwqe **kwq;241 242 struct cnic_dma kwq_16_data_info;243 244 u16 max_kwq_idx;245 246 u16 kwq_prod_idx;247 u32 kwq_io_addr;248 249 u16 *kwq_con_idx_ptr;250 u16 kwq_con_idx;251 252 struct kcq_info kcq1;253 struct kcq_info kcq2;254 255 union {256 void *gen;257 struct status_block_msix *bnx2;258 struct host_hc_status_block_e1x *bnx2x_e1x;259 /* index values - which counter to update */260 #define SM_RX_ID 0261 #define SM_TX_ID 1262 } status_blk;263 dma_addr_t status_blk_map;264 265 struct host_sp_status_block *bnx2x_def_status_blk;266 267 u32 status_blk_num;268 u32 bnx2x_igu_sb_id;269 u32 int_num;270 u32 last_status_idx;271 struct work_struct cnic_irq_bh_work;272 273 struct kcqe *completed_kcq[MAX_COMPLETED_KCQE];274 275 struct cnic_sock *csk_tbl;276 struct cnic_id_tbl csk_port_tbl;277 278 struct cnic_dma gbl_buf_info;279 280 struct cnic_iscsi *iscsi_tbl;281 struct cnic_context *ctx_tbl;282 struct cnic_id_tbl cid_tbl;283 atomic_t iscsi_conn;284 u32 iscsi_start_cid;285 286 u32 fcoe_init_cid;287 u32 fcoe_start_cid;288 struct cnic_id_tbl fcoe_cid_tbl;289 290 u32 max_cid_space;291 292 /* per connection parameters */293 int num_iscsi_tasks;294 int num_ccells;295 int task_array_size;296 int r2tq_size;297 int hq_size;298 int num_cqs;299 300 struct delayed_work delete_task;301 302 struct cnic_ctx *ctx_arr;303 int ctx_blks;304 int ctx_blk_size;305 unsigned long ctx_align;306 int cids_per_blk;307 308 u32 chip_id;309 int func;310 311 u32 shmem_base;312 313 struct cnic_ops *cnic_ops;314 int (*start_hw)(struct cnic_dev *);315 void (*stop_hw)(struct cnic_dev *);316 void (*setup_pgtbl)(struct cnic_dev *,317 struct cnic_dma *);318 int (*alloc_resc)(struct cnic_dev *);319 void (*free_resc)(struct cnic_dev *);320 int (*start_cm)(struct cnic_dev *);321 void (*stop_cm)(struct cnic_dev *);322 void (*enable_int)(struct cnic_dev *);323 void (*disable_int_sync)(struct cnic_dev *);324 void (*ack_int)(struct cnic_dev *);325 void (*arm_int)(struct cnic_dev *, u32 index);326 void (*close_conn)(struct cnic_sock *, u32 opcode);327};328 329struct bnx2x_bd_chain_next {330 u32 addr_lo;331 u32 addr_hi;332 u8 reserved[8];333};334 335#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)336 337#define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN)338#define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT)339 340#define CDU_REGION_NUMBER_XCM_AG 2341#define CDU_REGION_NUMBER_UCM_AG 4342 343#define CDU_VALID_DATA(_cid, _region, _type) \344 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))345 346#define CDU_CRC8(_cid, _region, _type) \347 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))348 349#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \350 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))351 352#define BNX2X_CONTEXT_MEM_SIZE 1024353#define BNX2X_FCOE_CID 16354 355#define BNX2X_ISCSI_START_CID 18356#define BNX2X_ISCSI_NUM_CONNECTIONS 128357#define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128358#define BNX2X_ISCSI_MAX_PENDING_R2TS 4359#define BNX2X_ISCSI_R2TQE_SIZE 8360#define BNX2X_ISCSI_HQ_BD_SIZE 64361#define BNX2X_ISCSI_GLB_BUF_SIZE 64362#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff363#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff364 365#define BNX2X_FCOE_NUM_CONNECTIONS 1024366 367#define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ368 369#define BNX2X_CHIP_IS_E2_PLUS(bp) (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))370 371#define BNX2X_RX_DESC_CNT (BNX2_PAGE_SIZE / \372 sizeof(struct eth_rx_bd))373#define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2)374#define BNX2X_RCQ_DESC_CNT (BNX2_PAGE_SIZE / \375 sizeof(union eth_rx_cqe))376#define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1)377 378#define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \379 (BNX2X_MAX_RCQ_DESC_CNT - 1)) ? \380 ((x) + 2) : ((x) + 1)381 382#define BNX2X_DEF_SB_ID HC_SP_SB_ID383 384#define BNX2X_SHMEM_MF_BLK_OFFSET 0x7e4385 386#define BNX2X_SHMEM_ADDR(base, field) (base + \387 offsetof(struct shmem_region, field))388 389#define BNX2X_SHMEM2_ADDR(base, field) (base + \390 offsetof(struct shmem2_region, field))391 392#define BNX2X_SHMEM2_HAS(base, field) \393 ((base) && \394 (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \395 offsetof(struct shmem2_region, field)))396 397#define BNX2X_MF_CFG_ADDR(base, field) \398 ((base) + offsetof(struct mf_cfg, field))399 400#ifndef ETH_MAX_RX_CLIENTS_E2401#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H402#endif403 404#define CNIC_FUNC(cp) ((cp)->func)405 406#define BNX2X_HW_CID(bp, x) ((BP_PORT(bp) << 23) | \407 (BP_VN(bp) << 17) | (x))408 409#define BNX2X_SW_CID(x) (x & 0x1ffff)410 411#define BNX2X_CL_QZONE_ID(bp, cli) \412 (BNX2X_CHIP_IS_E2_PLUS(bp) ? cli : \413 cli + (BP_PORT(bp) * ETH_MAX_RX_CLIENTS_E1H))414 415#ifndef MAX_STAT_COUNTER_ID416#define MAX_STAT_COUNTER_ID \417 (CHIP_IS_E1H(bp) ? MAX_STAT_COUNTER_ID_E1H : \418 ((BNX2X_CHIP_IS_E2_PLUS(bp)) ? MAX_STAT_COUNTER_ID_E2 : \419 MAX_STAT_COUNTER_ID_E1))420#endif421 422#define CNIC_SUPPORTS_FCOE(cp) \423 (BNX2X_CHIP_IS_E2_PLUS(bp) && !NO_FCOE(bp))424 425#define CNIC_RAMROD_TMO (HZ / 4)426 427#endif428 429