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1/**********************************************************************2 * Author: Cavium, Inc.3 *4 * Contact: support@cavium.com5 * Please include "LiquidIO" in the subject.6 *7 * Copyright (c) 2003-2016 Cavium, Inc.8 *9 * This file is free software; you can redistribute it and/or modify10 * it under the terms of the GNU General Public License, Version 2, as11 * published by the Free Software Foundation.12 *13 * This file is distributed in the hope that it will be useful, but14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or16 * NONINFRINGEMENT. See the GNU General Public License for more details.17 ***********************************************************************/18/*! \file cn66xx_regs.h19 * \brief Host Driver: Register Address and Register Mask values for20 * Octeon CN66XX devices.21 */22 23#ifndef __CN66XX_REGS_H__24#define __CN66XX_REGS_H__25 26#define CN6XXX_XPANSION_BAR 0x3027 28#define CN6XXX_MSI_CAP 0x5029#define CN6XXX_MSI_ADDR_LO 0x5430#define CN6XXX_MSI_ADDR_HI 0x5831#define CN6XXX_MSI_DATA 0x5C32 33#define CN6XXX_PCIE_CAP 0x7034#define CN6XXX_PCIE_DEVCAP 0x7435#define CN6XXX_PCIE_DEVCTL 0x7836#define CN6XXX_PCIE_LINKCAP 0x7C37#define CN6XXX_PCIE_LINKCTL 0x8038#define CN6XXX_PCIE_SLOTCAP 0x8439#define CN6XXX_PCIE_SLOTCTL 0x8840 41#define CN6XXX_PCIE_ENH_CAP 0x10042#define CN6XXX_PCIE_UNCORR_ERR_STATUS 0x10443#define CN6XXX_PCIE_UNCORR_ERR_MASK 0x10844#define CN6XXX_PCIE_UNCORR_ERR 0x10C45#define CN6XXX_PCIE_CORR_ERR_STATUS 0x11046#define CN6XXX_PCIE_CORR_ERR_MASK 0x11447#define CN6XXX_PCIE_ADV_ERR_CAP 0x11848 49#define CN6XXX_PCIE_ACK_REPLAY_TIMER 0x70050#define CN6XXX_PCIE_OTHER_MSG 0x70451#define CN6XXX_PCIE_PORT_FORCE_LINK 0x70852#define CN6XXX_PCIE_ACK_FREQ 0x70C53#define CN6XXX_PCIE_PORT_LINK_CTL 0x71054#define CN6XXX_PCIE_LANE_SKEW 0x71455#define CN6XXX_PCIE_SYM_NUM 0x71856#define CN6XXX_PCIE_FLTMSK 0x72057 58/* ############## BAR0 Registers ################ */59 60#define CN6XXX_SLI_CTL_PORT0 0x005061#define CN6XXX_SLI_CTL_PORT1 0x006062 63#define CN6XXX_SLI_WINDOW_CTL 0x02E064#define CN6XXX_SLI_DBG_DATA 0x031065#define CN6XXX_SLI_SCRATCH1 0x03C066#define CN6XXX_SLI_SCRATCH2 0x03D067#define CN6XXX_SLI_CTL_STATUS 0x057068 69#define CN6XXX_WIN_WR_ADDR_LO 0x000070#define CN6XXX_WIN_WR_ADDR_HI 0x000471#define CN6XXX_WIN_WR_ADDR64 CN6XXX_WIN_WR_ADDR_LO72 73#define CN6XXX_WIN_RD_ADDR_LO 0x001074#define CN6XXX_WIN_RD_ADDR_HI 0x001475#define CN6XXX_WIN_RD_ADDR64 CN6XXX_WIN_RD_ADDR_LO76 77#define CN6XXX_WIN_WR_DATA_LO 0x002078#define CN6XXX_WIN_WR_DATA_HI 0x002479#define CN6XXX_WIN_WR_DATA64 CN6XXX_WIN_WR_DATA_LO80 81#define CN6XXX_WIN_RD_DATA_LO 0x004082#define CN6XXX_WIN_RD_DATA_HI 0x004483#define CN6XXX_WIN_RD_DATA64 CN6XXX_WIN_RD_DATA_LO84 85#define CN6XXX_WIN_WR_MASK_LO 0x003086#define CN6XXX_WIN_WR_MASK_HI 0x003487#define CN6XXX_WIN_WR_MASK_REG CN6XXX_WIN_WR_MASK_LO88 89/* 1 register (32-bit) to enable Input queues */90#define CN6XXX_SLI_PKT_INSTR_ENB 0x100091 92/* 1 register (32-bit) to enable Output queues */93#define CN6XXX_SLI_PKT_OUT_ENB 0x101094 95/* 1 register (32-bit) to determine whether Output queues are in reset. */96#define CN6XXX_SLI_PORT_IN_RST_OQ 0x11F097 98/* 1 register (32-bit) to determine whether Input queues are in reset. */99#define CN6XXX_SLI_PORT_IN_RST_IQ 0x11F4100 101/*###################### REQUEST QUEUE #########################*/102 103/* 1 register (32-bit) - instr. size of each input queue. */104#define CN6XXX_SLI_PKT_INSTR_SIZE 0x1020105 106/* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */107#define CN6XXX_SLI_IQ_INSTR_COUNT_START 0x2000108 109/* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */110#define CN6XXX_SLI_IQ_BASE_ADDR_START64 0x2800111 112/* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */113#define CN6XXX_SLI_IQ_DOORBELL_START 0x2C00114 115/* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */116#define CN6XXX_SLI_IQ_SIZE_START 0x3000117 118/* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */119#define CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 0x3400120 121/* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */122#define CN66XX_SLI_INPUT_BP_START64 0x3800123 124/* Each Input Queue register is at a 16-byte Offset in BAR0 */125#define CN6XXX_IQ_OFFSET 0x10126 127/* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data &128 * gather list fetches. SLI_PKT_INPUT_CONTROL.129 */130#define CN6XXX_SLI_PKT_INPUT_CONTROL 0x1170131 132/* 1 register (64-bit) - Number of instructions to read at one time133 * - 2 bits for each input ring. SLI_PKT_INSTR_RD_SIZE.134 */135#define CN6XXX_SLI_PKT_INSTR_RD_SIZE 0x11A0136 137/* 1 register (64-bit) - Assign Input ring to MAC port138 * - 2 bits for each input ring. SLI_PKT_IN_PCIE_PORT.139 */140#define CN6XXX_SLI_IN_PCIE_PORT 0x11B0141 142/*------- Request Queue Macros ---------*/143#define CN6XXX_SLI_IQ_BASE_ADDR64(iq) \144 (CN6XXX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN6XXX_IQ_OFFSET))145 146#define CN6XXX_SLI_IQ_SIZE(iq) \147 (CN6XXX_SLI_IQ_SIZE_START + ((iq) * CN6XXX_IQ_OFFSET))148 149#define CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq) \150 (CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 + ((iq) * CN6XXX_IQ_OFFSET))151 152#define CN6XXX_SLI_IQ_DOORBELL(iq) \153 (CN6XXX_SLI_IQ_DOORBELL_START + ((iq) * CN6XXX_IQ_OFFSET))154 155#define CN6XXX_SLI_IQ_INSTR_COUNT(iq) \156 (CN6XXX_SLI_IQ_INSTR_COUNT_START + ((iq) * CN6XXX_IQ_OFFSET))157 158#define CN66XX_SLI_IQ_BP64(iq) \159 (CN66XX_SLI_INPUT_BP_START64 + ((iq) * CN6XXX_IQ_OFFSET))160 161/*------------------ Masks ----------------*/162#define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22)163#define CN6XXX_INPUT_CTL_DATA_NS BIT(8)164#define CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP BIT(6)165#define CN6XXX_INPUT_CTL_DATA_RO BIT(5)166#define CN6XXX_INPUT_CTL_USE_CSR BIT(4)167#define CN6XXX_INPUT_CTL_GATHER_NS BIT(3)168#define CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP BIT(2)169#define CN6XXX_INPUT_CTL_GATHER_RO BIT(1)170 171#ifdef __BIG_ENDIAN_BITFIELD172#define CN6XXX_INPUT_CTL_MASK \173 (CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP \174 | CN6XXX_INPUT_CTL_USE_CSR \175 | CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP)176#else177#define CN6XXX_INPUT_CTL_MASK \178 (CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP \179 | CN6XXX_INPUT_CTL_USE_CSR)180#endif181 182/*############################ OUTPUT QUEUE #########################*/183 184/* 32 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */185#define CN6XXX_SLI_OQ0_BUFF_INFO_SIZE 0x0C00186 187/* 32 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */188#define CN6XXX_SLI_OQ_BASE_ADDR_START64 0x1400189 190/* 32 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */191#define CN6XXX_SLI_OQ_PKT_CREDITS_START 0x1800192 193/* 32 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */194#define CN6XXX_SLI_OQ_SIZE_START 0x1C00195 196/* 32 registers for Output Queue Packet Count - SLI_PKT0_CNTS */197#define CN6XXX_SLI_OQ_PKT_SENT_START 0x2400198 199/* Each Output Queue register is at a 16-byte Offset in BAR0 */200#define CN6XXX_OQ_OFFSET 0x10201 202/* 1 register (32-bit) - 1 bit for each output queue203 * - Relaxed Ordering setting for reading Output Queues descriptors204 * - SLI_PKT_SLIST_ROR205 */206#define CN6XXX_SLI_PKT_SLIST_ROR 0x1030207 208/* 1 register (32-bit) - 1 bit for each output queue209 * - No Snoop mode for reading Output Queues descriptors210 * - SLI_PKT_SLIST_NS211 */212#define CN6XXX_SLI_PKT_SLIST_NS 0x1040213 214/* 1 register (64-bit) - 2 bits for each output queue215 * - Endian-Swap mode for reading Output Queue descriptors216 * - SLI_PKT_SLIST_ES217 */218#define CN6XXX_SLI_PKT_SLIST_ES64 0x1050219 220/* 1 register (32-bit) - 1 bit for each output queue221 * - InfoPtr mode for Output Queues.222 * - SLI_PKT_IPTR223 */224#define CN6XXX_SLI_PKT_IPTR 0x1070225 226/* 1 register (32-bit) - 1 bit for each output queue227 * - DPTR format selector for Output queues.228 * - SLI_PKT_DPADDR229 */230#define CN6XXX_SLI_PKT_DPADDR 0x1080231 232/* 1 register (32-bit) - 1 bit for each output queue233 * - Relaxed Ordering setting for reading Output Queues data234 * - SLI_PKT_DATA_OUT_ROR235 */236#define CN6XXX_SLI_PKT_DATA_OUT_ROR 0x1090237 238/* 1 register (32-bit) - 1 bit for each output queue239 * - No Snoop mode for reading Output Queues data240 * - SLI_PKT_DATA_OUT_NS241 */242#define CN6XXX_SLI_PKT_DATA_OUT_NS 0x10A0243 244/* 1 register (64-bit) - 2 bits for each output queue245 * - Endian-Swap mode for reading Output Queue data246 * - SLI_PKT_DATA_OUT_ES247 */248#define CN6XXX_SLI_PKT_DATA_OUT_ES64 0x10B0249 250/* 1 register (32-bit) - 1 bit for each output queue251 * - Controls whether SLI_PKTn_CNTS is incremented for bytes or for packets.252 * - SLI_PKT_OUT_BMODE253 */254#define CN6XXX_SLI_PKT_OUT_BMODE 0x10D0255 256/* 1 register (64-bit) - 2 bits for each output queue257 * - Assign PCIE port for Output queues258 * - SLI_PKT_PCIE_PORT.259 */260#define CN6XXX_SLI_PKT_PCIE_PORT64 0x10E0261 262/* 1 (64-bit) register for Output Queue Packet Count Interrupt Threshold263 * & Time Threshold. The same setting applies to all 32 queues.264 * The register is defined as a 64-bit registers, but we use the265 * 32-bit offsets to define distinct addresses.266 */267#define CN6XXX_SLI_OQ_INT_LEVEL_PKTS 0x1120268#define CN6XXX_SLI_OQ_INT_LEVEL_TIME 0x1124269 270/* 1 (64-bit register) for Output Queue backpressure across all rings. */271#define CN6XXX_SLI_OQ_WMARK 0x1180272 273/* 1 register to control output queue global backpressure & ring enable. */274#define CN6XXX_SLI_PKT_CTL 0x1220275 276/*------- Output Queue Macros ---------*/277#define CN6XXX_SLI_OQ_BASE_ADDR64(oq) \278 (CN6XXX_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN6XXX_OQ_OFFSET))279 280#define CN6XXX_SLI_OQ_SIZE(oq) \281 (CN6XXX_SLI_OQ_SIZE_START + ((oq) * CN6XXX_OQ_OFFSET))282 283#define CN6XXX_SLI_OQ_BUFF_INFO_SIZE(oq) \284 (CN6XXX_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN6XXX_OQ_OFFSET))285 286#define CN6XXX_SLI_OQ_PKTS_SENT(oq) \287 (CN6XXX_SLI_OQ_PKT_SENT_START + ((oq) * CN6XXX_OQ_OFFSET))288 289#define CN6XXX_SLI_OQ_PKTS_CREDIT(oq) \290 (CN6XXX_SLI_OQ_PKT_CREDITS_START + ((oq) * CN6XXX_OQ_OFFSET))291 292/*######################### DMA Counters #########################*/293 294/* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */295#define CN6XXX_DMA_CNT_START 0x0400296 297/* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values298 * SLI_DMA_0_TIM299 */300#define CN6XXX_DMA_TIM_START 0x0420301 302/* 2 registers (64-bit) - DMA count & Time Interrupt threshold -303 * SLI_DMA_0_INT_LEVEL304 */305#define CN6XXX_DMA_INT_LEVEL_START 0x03E0306 307/* Each DMA register is at a 16-byte Offset in BAR0 */308#define CN6XXX_DMA_OFFSET 0x10309 310/*---------- DMA Counter Macros ---------*/311#define CN6XXX_DMA_CNT(dq) \312 (CN6XXX_DMA_CNT_START + ((dq) * CN6XXX_DMA_OFFSET))313 314#define CN6XXX_DMA_INT_LEVEL(dq) \315 (CN6XXX_DMA_INT_LEVEL_START + ((dq) * CN6XXX_DMA_OFFSET))316 317#define CN6XXX_DMA_PKT_INT_LEVEL(dq) \318 (CN6XXX_DMA_INT_LEVEL_START + ((dq) * CN6XXX_DMA_OFFSET))319 320#define CN6XXX_DMA_TIME_INT_LEVEL(dq) \321 (CN6XXX_DMA_INT_LEVEL_START + 4 + ((dq) * CN6XXX_DMA_OFFSET))322 323#define CN6XXX_DMA_TIM(dq) \324 (CN6XXX_DMA_TIM_START + ((dq) * CN6XXX_DMA_OFFSET))325 326/*######################## INTERRUPTS #########################*/327 328/* 1 register (64-bit) for Interrupt Summary */329#define CN6XXX_SLI_INT_SUM64 0x0330330 331/* 1 register (64-bit) for Interrupt Enable */332#define CN6XXX_SLI_INT_ENB64_PORT0 0x0340333#define CN6XXX_SLI_INT_ENB64_PORT1 0x0350334 335/* 1 register (32-bit) to enable Output Queue Packet/Byte Count Interrupt */336#define CN6XXX_SLI_PKT_CNT_INT_ENB 0x1150337 338/* 1 register (32-bit) to enable Output Queue Packet Timer Interrupt */339#define CN6XXX_SLI_PKT_TIME_INT_ENB 0x1160340 341/* 1 register (32-bit) to indicate which Output Queue reached pkt threshold */342#define CN6XXX_SLI_PKT_CNT_INT 0x1130343 344/* 1 register (32-bit) to indicate which Output Queue reached time threshold */345#define CN6XXX_SLI_PKT_TIME_INT 0x1140346 347/*------------------ Interrupt Masks ----------------*/348 349#define CN6XXX_INTR_RML_TIMEOUT_ERR BIT(1)350#define CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR BIT(2)351#define CN6XXX_INTR_IO2BIG_ERR BIT(3)352#define CN6XXX_INTR_PKT_COUNT BIT(4)353#define CN6XXX_INTR_PKT_TIME BIT(5)354#define CN6XXX_INTR_M0UPB0_ERR BIT(8)355#define CN6XXX_INTR_M0UPWI_ERR BIT(9)356#define CN6XXX_INTR_M0UNB0_ERR BIT(10)357#define CN6XXX_INTR_M0UNWI_ERR BIT(11)358#define CN6XXX_INTR_M1UPB0_ERR BIT(12)359#define CN6XXX_INTR_M1UPWI_ERR BIT(13)360#define CN6XXX_INTR_M1UNB0_ERR BIT(14)361#define CN6XXX_INTR_M1UNWI_ERR BIT(15)362#define CN6XXX_INTR_MIO_INT0 BIT(16)363#define CN6XXX_INTR_MIO_INT1 BIT(17)364#define CN6XXX_INTR_MAC_INT0 BIT(18)365#define CN6XXX_INTR_MAC_INT1 BIT(19)366 367#define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)368#define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)369#define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)370#define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)371#define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)372#define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)373#define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48)374#define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49)375#define CN6XXX_INTR_POUT_ERR BIT_ULL(50)376#define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51)377#define CN6XXX_INTR_PGL_ERR BIT_ULL(52)378#define CN6XXX_INTR_PDI_ERR BIT_ULL(53)379#define CN6XXX_INTR_POP_ERR BIT_ULL(54)380#define CN6XXX_INTR_PINS_ERR BIT_ULL(55)381#define CN6XXX_INTR_SPRT0_ERR BIT_ULL(56)382#define CN6XXX_INTR_SPRT1_ERR BIT_ULL(57)383#define CN6XXX_INTR_ILL_PAD_ERR BIT_ULL(60)384 385#define CN6XXX_INTR_DMA0_DATA (CN6XXX_INTR_DMA0_TIME)386 387#define CN6XXX_INTR_DMA1_DATA (CN6XXX_INTR_DMA1_TIME)388 389#define CN6XXX_INTR_DMA_DATA \390 (CN6XXX_INTR_DMA0_DATA | CN6XXX_INTR_DMA1_DATA)391 392#define CN6XXX_INTR_PKT_DATA (CN6XXX_INTR_PKT_TIME | \393 CN6XXX_INTR_PKT_COUNT)394 395/* Sum of interrupts for all PCI-Express Data Interrupts */396#define CN6XXX_INTR_PCIE_DATA \397 (CN6XXX_INTR_DMA_DATA | CN6XXX_INTR_PKT_DATA)398 399#define CN6XXX_INTR_MIO \400 (CN6XXX_INTR_MIO_INT0 | CN6XXX_INTR_MIO_INT1)401 402#define CN6XXX_INTR_MAC \403 (CN6XXX_INTR_MAC_INT0 | CN6XXX_INTR_MAC_INT1)404 405/* Sum of interrupts for error events */406#define CN6XXX_INTR_ERR \407 (CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR \408 | CN6XXX_INTR_IO2BIG_ERR \409 | CN6XXX_INTR_M0UPB0_ERR \410 | CN6XXX_INTR_M0UPWI_ERR \411 | CN6XXX_INTR_M0UNB0_ERR \412 | CN6XXX_INTR_M0UNWI_ERR \413 | CN6XXX_INTR_M1UPB0_ERR \414 | CN6XXX_INTR_M1UPWI_ERR \415 | CN6XXX_INTR_M1UNB0_ERR \416 | CN6XXX_INTR_M1UNWI_ERR \417 | CN6XXX_INTR_INSTR_DB_OF_ERR \418 | CN6XXX_INTR_SLIST_DB_OF_ERR \419 | CN6XXX_INTR_POUT_ERR \420 | CN6XXX_INTR_PIN_BP_ERR \421 | CN6XXX_INTR_PGL_ERR \422 | CN6XXX_INTR_PDI_ERR \423 | CN6XXX_INTR_POP_ERR \424 | CN6XXX_INTR_PINS_ERR \425 | CN6XXX_INTR_SPRT0_ERR \426 | CN6XXX_INTR_SPRT1_ERR \427 | CN6XXX_INTR_ILL_PAD_ERR)428 429/* Programmed Mask for Interrupt Sum */430#define CN6XXX_INTR_MASK \431 (CN6XXX_INTR_PCIE_DATA \432 | CN6XXX_INTR_DMA0_FORCE \433 | CN6XXX_INTR_DMA1_FORCE \434 | CN6XXX_INTR_MIO \435 | CN6XXX_INTR_MAC \436 | CN6XXX_INTR_ERR)437 438#define CN6XXX_SLI_S2M_PORT0_CTL 0x3D80439#define CN6XXX_SLI_S2M_PORT1_CTL 0x3D90440#define CN6XXX_SLI_S2M_PORTX_CTL(port) \441 (CN6XXX_SLI_S2M_PORT0_CTL + ((port) * 0x10))442 443#define CN6XXX_SLI_INT_ENB64(port) \444 (CN6XXX_SLI_INT_ENB64_PORT0 + ((port) * 0x10))445 446#define CN6XXX_SLI_MAC_NUMBER 0x3E00447 448/* CN6XXX BAR1 Index registers. */449#define CN6XXX_PEM_BAR1_INDEX000 0x00011800C00000A8ULL450#define CN6XXX_PEM_OFFSET 0x0000000001000000ULL451 452#define CN6XXX_BAR1_INDEX_START CN6XXX_PEM_BAR1_INDEX000453#define CN6XXX_PCI_BAR1_OFFSET 0x8454 455#define CN6XXX_BAR1_REG(idx, port) \456 (CN6XXX_BAR1_INDEX_START + ((port) * CN6XXX_PEM_OFFSET) + \457 (CN6XXX_PCI_BAR1_OFFSET * (idx)))458 459/*############################ DPI #########################*/460 461#define CN6XXX_DPI_CTL 0x0001df0000000040ULL462 463#define CN6XXX_DPI_DMA_CONTROL 0x0001df0000000048ULL464 465#define CN6XXX_DPI_REQ_GBL_ENB 0x0001df0000000050ULL466 467#define CN6XXX_DPI_REQ_ERR_RSP 0x0001df0000000058ULL468 469#define CN6XXX_DPI_REQ_ERR_RST 0x0001df0000000060ULL470 471#define CN6XXX_DPI_DMA_ENG0_ENB 0x0001df0000000080ULL472 473#define CN6XXX_DPI_DMA_ENG_ENB(q_no) \474 (CN6XXX_DPI_DMA_ENG0_ENB + ((q_no) * 8))475 476#define CN6XXX_DPI_DMA_ENG0_BUF 0x0001df0000000880ULL477 478#define CN6XXX_DPI_DMA_ENG_BUF(q_no) \479 (CN6XXX_DPI_DMA_ENG0_BUF + ((q_no) * 8))480 481#define CN6XXX_DPI_SLI_PRT0_CFG 0x0001df0000000900ULL482#define CN6XXX_DPI_SLI_PRT1_CFG 0x0001df0000000908ULL483#define CN6XXX_DPI_SLI_PRTX_CFG(port) \484 (CN6XXX_DPI_SLI_PRT0_CFG + ((port) * 0x10))485 486#define CN6XXX_DPI_DMA_COMMIT_MODE BIT_ULL(58)487#define CN6XXX_DPI_DMA_PKT_HP BIT_ULL(57)488#define CN6XXX_DPI_DMA_PKT_EN BIT_ULL(56)489#define CN6XXX_DPI_DMA_O_ES BIT_ULL(15)490#define CN6XXX_DPI_DMA_O_MODE BIT_ULL(14)491 492#define CN6XXX_DPI_DMA_CTL_MASK \493 (CN6XXX_DPI_DMA_COMMIT_MODE | \494 CN6XXX_DPI_DMA_PKT_HP | \495 CN6XXX_DPI_DMA_PKT_EN | \496 CN6XXX_DPI_DMA_O_ES | \497 CN6XXX_DPI_DMA_O_MODE)498 499/*############################ CIU #########################*/500 501#define CN6XXX_CIU_SOFT_BIST 0x0001070000000738ULL502#define CN6XXX_CIU_SOFT_RST 0x0001070000000740ULL503 504/*############################ MIO #########################*/505#define CN6XXX_MIO_PTP_CLOCK_CFG 0x0001070000000f00ULL506#define CN6XXX_MIO_PTP_CLOCK_LO 0x0001070000000f08ULL507#define CN6XXX_MIO_PTP_CLOCK_HI 0x0001070000000f10ULL508#define CN6XXX_MIO_PTP_CLOCK_COMP 0x0001070000000f18ULL509#define CN6XXX_MIO_PTP_TIMESTAMP 0x0001070000000f20ULL510#define CN6XXX_MIO_PTP_EVT_CNT 0x0001070000000f28ULL511#define CN6XXX_MIO_PTP_CKOUT_THRESH_LO 0x0001070000000f30ULL512#define CN6XXX_MIO_PTP_CKOUT_THRESH_HI 0x0001070000000f38ULL513#define CN6XXX_MIO_PTP_CKOUT_HI_INCR 0x0001070000000f40ULL514#define CN6XXX_MIO_PTP_CKOUT_LO_INCR 0x0001070000000f48ULL515#define CN6XXX_MIO_PTP_PPS_THRESH_LO 0x0001070000000f50ULL516#define CN6XXX_MIO_PTP_PPS_THRESH_HI 0x0001070000000f58ULL517#define CN6XXX_MIO_PTP_PPS_HI_INCR 0x0001070000000f60ULL518#define CN6XXX_MIO_PTP_PPS_LO_INCR 0x0001070000000f68ULL519 520#define CN6XXX_MIO_QLM4_CFG 0x00011800000015B0ULL521#define CN6XXX_MIO_RST_BOOT 0x0001180000001600ULL522 523#define CN6XXX_MIO_QLM_CFG_MASK 0x7524 525/*############################ LMC #########################*/526 527#define CN6XXX_LMC0_RESET_CTL 0x0001180088000180ULL528#define CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL529 530#endif531