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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2015 Cavium, Inc.4 */5 6#ifndef THUNDER_BGX_H7#define THUNDER_BGX_H8 9/* PCI device ID */10#define PCI_DEVICE_ID_THUNDER_BGX 0xA02611#define PCI_DEVICE_ID_THUNDER_RGX 0xA05412 13/* Subsystem device IDs */14#define PCI_SUBSYS_DEVID_88XX_BGX 0xA12615#define PCI_SUBSYS_DEVID_81XX_BGX 0xA22616#define PCI_SUBSYS_DEVID_81XX_RGX 0xA25417#define PCI_SUBSYS_DEVID_83XX_BGX 0xA32618 19#define MAX_BGX_THUNDER 8 /* Max 2 nodes, 4 per node */20#define MAX_BGX_PER_CN88XX 221#define MAX_BGX_PER_CN81XX 3 /* 2 BGXs + 1 RGX */22#define MAX_BGX_PER_CN83XX 423#define MAX_LMAC_PER_BGX 424#define MAX_BGX_CHANS_PER_LMAC 1625#define MAX_DMAC_PER_LMAC 826#define MAX_FRAME_SIZE 921627#define DEFAULT_PAUSE_TIME 0xFFFF28 29#define BGX_ID_MASK 0x330#define LMAC_ID_MASK 0x331 32#define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 233 34/* Registers */35#define BGX_CMRX_CFG 0x0036#define CMR_PKT_TX_EN BIT_ULL(13)37#define CMR_PKT_RX_EN BIT_ULL(14)38#define CMR_EN BIT_ULL(15)39#define BGX_CMR_GLOBAL_CFG 0x0840#define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)41#define BGX_CMRX_RX_ID_MAP 0x6042#define BGX_CMRX_RX_STAT0 0x7043#define BGX_CMRX_RX_STAT1 0x7844#define BGX_CMRX_RX_STAT2 0x8045#define BGX_CMRX_RX_STAT3 0x8846#define BGX_CMRX_RX_STAT4 0x9047#define BGX_CMRX_RX_STAT5 0x9848#define BGX_CMRX_RX_STAT6 0xA049#define BGX_CMRX_RX_STAT7 0xA850#define BGX_CMRX_RX_STAT8 0xB051#define BGX_CMRX_RX_STAT9 0xB852#define BGX_CMRX_RX_STAT10 0xC053#define BGX_CMRX_RX_BP_DROP 0xC854#define BGX_CMRX_RX_DMAC_CTL 0x0E855#define BGX_CMRX_RX_FIFO_LEN 0x10856#define BGX_CMR_RX_DMACX_CAM 0x20057#define RX_DMACX_CAM_EN BIT_ULL(48)58#define RX_DMACX_CAM_LMACID(x) (((u64)x) << 49)59#define RX_DMAC_COUNT 3260#define BGX_CMR_RX_STEERING 0x30061#define RX_TRAFFIC_STEER_RULE_COUNT 862#define BGX_CMR_CHAN_MSK_AND 0x45063#define BGX_CMR_BIST_STATUS 0x46064#define BGX_CMR_RX_LMACS 0x46865#define BGX_CMRX_TX_FIFO_LEN 0x51866#define BGX_CMRX_TX_STAT0 0x60067#define BGX_CMRX_TX_STAT1 0x60868#define BGX_CMRX_TX_STAT2 0x61069#define BGX_CMRX_TX_STAT3 0x61870#define BGX_CMRX_TX_STAT4 0x62071#define BGX_CMRX_TX_STAT5 0x62872#define BGX_CMRX_TX_STAT6 0x63073#define BGX_CMRX_TX_STAT7 0x63874#define BGX_CMRX_TX_STAT8 0x64075#define BGX_CMRX_TX_STAT9 0x64876#define BGX_CMRX_TX_STAT10 0x65077#define BGX_CMRX_TX_STAT11 0x65878#define BGX_CMRX_TX_STAT12 0x66079#define BGX_CMRX_TX_STAT13 0x66880#define BGX_CMRX_TX_STAT14 0x67081#define BGX_CMRX_TX_STAT15 0x67882#define BGX_CMRX_TX_STAT16 0x68083#define BGX_CMRX_TX_STAT17 0x68884#define BGX_CMR_TX_LMACS 0x100085 86#define BGX_SPUX_CONTROL1 0x1000087#define SPU_CTL_LOW_POWER BIT_ULL(11)88#define SPU_CTL_LOOPBACK BIT_ULL(14)89#define SPU_CTL_RESET BIT_ULL(15)90#define BGX_SPUX_STATUS1 0x1000891#define SPU_STATUS1_RCV_LNK BIT_ULL(2)92#define BGX_SPUX_STATUS2 0x1002093#define SPU_STATUS2_RCVFLT BIT_ULL(10)94#define BGX_SPUX_BX_STATUS 0x1002895#define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12)96#define BGX_SPUX_BR_STATUS1 0x1003097#define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0)98#define SPU_BR_STATUS_RCV_LNK BIT_ULL(12)99#define BGX_SPUX_BR_PMD_CRTL 0x10068100#define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1)101#define BGX_SPUX_BR_PMD_LP_CUP 0x10078102#define BGX_SPUX_BR_PMD_LD_CUP 0x10088103#define BGX_SPUX_BR_PMD_LD_REP 0x10090104#define BGX_SPUX_FEC_CONTROL 0x100A0105#define SPU_FEC_CTL_FEC_EN BIT_ULL(0)106#define SPU_FEC_CTL_ERR_EN BIT_ULL(1)107#define BGX_SPUX_AN_CONTROL 0x100C8108#define SPU_AN_CTL_AN_EN BIT_ULL(12)109#define SPU_AN_CTL_XNP_EN BIT_ULL(13)110#define BGX_SPUX_AN_ADV 0x100D8111#define BGX_SPUX_MISC_CONTROL 0x10218112#define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10)113#define SPU_MISC_CTL_RX_DIS BIT_ULL(12)114#define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */115#define BGX_SPUX_INT_W1S 0x10228116#define BGX_SPUX_INT_ENA_W1C 0x10230117#define BGX_SPUX_INT_ENA_W1S 0x10238118#define BGX_SPU_DBG_CONTROL 0x10300119#define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18)120#define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29)121 122#define BGX_SMUX_RX_INT 0x20000123#define BGX_SMUX_RX_FRM_CTL 0x20020124#define BGX_PKT_RX_PTP_EN BIT_ULL(12)125#define BGX_SMUX_RX_JABBER 0x20030126#define BGX_SMUX_RX_CTL 0x20048127#define SMU_RX_CTL_STATUS (3ull << 0)128#define BGX_SMUX_TX_APPEND 0x20100129#define SMU_TX_APPEND_FCS_D BIT_ULL(2)130#define BGX_SMUX_TX_PAUSE_PKT_TIME 0x20110131#define BGX_SMUX_TX_MIN_PKT 0x20118132#define BGX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120133#define BGX_SMUX_TX_PAUSE_ZERO 0x20138134#define BGX_SMUX_TX_INT 0x20140135#define BGX_SMUX_TX_CTL 0x20178136#define SMU_TX_CTL_DIC_EN BIT_ULL(0)137#define SMU_TX_CTL_UNI_EN BIT_ULL(1)138#define SMU_TX_CTL_LNK_STATUS (3ull << 4)139#define BGX_SMUX_TX_THRESH 0x20180140#define BGX_SMUX_CTL 0x20200141#define SMU_CTL_RX_IDLE BIT_ULL(0)142#define SMU_CTL_TX_IDLE BIT_ULL(1)143#define BGX_SMUX_CBFC_CTL 0x20218144#define RX_EN BIT_ULL(0)145#define TX_EN BIT_ULL(1)146#define BCK_EN BIT_ULL(2)147#define DRP_EN BIT_ULL(3)148 149#define BGX_GMP_PCS_MRX_CTL 0x30000150#define PCS_MRX_CTL_RST_AN BIT_ULL(9)151#define PCS_MRX_CTL_PWR_DN BIT_ULL(11)152#define PCS_MRX_CTL_AN_EN BIT_ULL(12)153#define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14)154#define PCS_MRX_CTL_RESET BIT_ULL(15)155#define BGX_GMP_PCS_MRX_STATUS 0x30008156#define PCS_MRX_STATUS_LINK BIT_ULL(2)157#define PCS_MRX_STATUS_AN_CPT BIT_ULL(5)158#define BGX_GMP_PCS_ANX_ADV 0x30010159#define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020160#define BGX_GMP_PCS_LINKX_TIMER 0x30040161#define PCS_LINKX_TIMER_COUNT 0x1E84162#define BGX_GMP_PCS_SGM_AN_ADV 0x30068163#define BGX_GMP_PCS_MISCX_CTL 0x30078164#define PCS_MISC_CTL_MODE BIT_ULL(8)165#define PCS_MISC_CTL_DISP_EN BIT_ULL(13)166#define PCS_MISC_CTL_GMX_ENO BIT_ULL(11)167#define PCS_MISC_CTL_SAMP_PT_MASK 0x7Full168#define BGX_GMP_GMI_PRTX_CFG 0x38020169#define GMI_PORT_CFG_SPEED BIT_ULL(1)170#define GMI_PORT_CFG_DUPLEX BIT_ULL(2)171#define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3)172#define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8)173#define GMI_PORT_CFG_RX_IDLE BIT_ULL(12)174#define GMI_PORT_CFG_TX_IDLE BIT_ULL(13)175#define BGX_GMP_GMI_RXX_FRM_CTL 0x38028176#define BGX_GMP_GMI_RXX_JABBER 0x38038177#define BGX_GMP_GMI_TXX_THRESH 0x38210178#define BGX_GMP_GMI_TXX_APPEND 0x38218179#define BGX_GMP_GMI_TXX_SLOT 0x38220180#define BGX_GMP_GMI_TXX_BURST 0x38228181#define BGX_GMP_GMI_TXX_MIN_PKT 0x38240182#define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300183#define BGX_GMP_GMI_TXX_INT 0x38500184#define BGX_GMP_GMI_TXX_INT_W1S 0x38508185#define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510186#define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518187#define GMI_TXX_INT_PTP_LOST BIT_ULL(4)188#define GMI_TXX_INT_LATE_COL BIT_ULL(3)189#define GMI_TXX_INT_XSDEF BIT_ULL(2)190#define GMI_TXX_INT_XSCOL BIT_ULL(1)191#define GMI_TXX_INT_UNDFLW BIT_ULL(0)192 193#define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */194#define BGX_MSIX_VEC_0_29_CTL 0x400008195#define BGX_MSIX_PBA_0 0x4F0000196 197/* MSI-X interrupts */198#define BGX_MSIX_VECTORS 30199#define BGX_LMAC_VEC_OFFSET 7200#define BGX_MSIX_VEC_SHIFT 4201 202#define CMRX_INT 0203#define SPUX_INT 1204#define SMUX_RX_INT 2205#define SMUX_TX_INT 3206#define GMPX_PCS_INT 4207#define GMPX_GMI_RX_INT 5208#define GMPX_GMI_TX_INT 6209#define CMR_MEM_INT 28210#define SPU_MEM_INT 29211 212#define LMAC_INTR_LINK_UP BIT(0)213#define LMAC_INTR_LINK_DOWN BIT(1)214 215#define BGX_XCAST_BCAST_ACCEPT BIT(0)216#define BGX_XCAST_MCAST_ACCEPT BIT(1)217#define BGX_XCAST_MCAST_FILTER BIT(2)218 219void bgx_set_dmac_cam_filter(int node, int bgx_idx, int lmacid, u64 mac, u8 vf);220void bgx_reset_xcast_mode(int node, int bgx_idx, int lmacid, u8 vf);221void bgx_set_xcast_mode(int node, int bgx_idx, int lmacid, u8 mode);222void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable);223unsigned bgx_get_map(int node);224int bgx_get_lmac_count(int node, int bgx);225const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid);226void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac);227void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status);228void bgx_lmac_internal_loopback(int node, int bgx_idx,229 int lmac_idx, bool enable);230void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable);231void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause);232void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause);233 234void xcv_init_hw(void);235void xcv_setup_link(bool link_up, int link_speed);236 237u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx);238u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx);239#define BGX_RX_STATS_COUNT 11240#define BGX_TX_STATS_COUNT 18241 242struct bgx_stats {243 u64 rx_stats[BGX_RX_STATS_COUNT];244 u64 tx_stats[BGX_TX_STATS_COUNT];245};246 247enum LMAC_TYPE {248 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */249 BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */250 BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */251 BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */252 BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */253 BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */254 BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */255 BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */256 BGX_MODE_RGMII = 5,257 BGX_MODE_QSGMII = 6,258 BGX_MODE_INVALID = 7,259};260 261#endif /* THUNDER_BGX_H */262