148 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*****************************************************************************3 * *4 * File: elmer0.h *5 * $Revision: 1.6 $ *6 * $Date: 2005/06/21 22:49:43 $ *7 * Description: *8 * part of the Chelsio 10Gb Ethernet Driver. *9 * *10 * *11 * http://www.chelsio.com *12 * *13 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *14 * All rights reserved. *15 * *16 * Maintainers: maintainers@chelsio.com *17 * *18 * Authors: Dimitrios Michailidis <dm@chelsio.com> *19 * Tina Yang <tainay@chelsio.com> *20 * Felix Marti <felix@chelsio.com> *21 * Scott Bardone <sbardone@chelsio.com> *22 * Kurt Ottaway <kottaway@chelsio.com> *23 * Frank DiMambro <frank@chelsio.com> *24 * *25 * History: *26 * *27 ****************************************************************************/28 29#ifndef _CXGB_ELMER0_H_30#define _CXGB_ELMER0_H_31 32/* ELMER0 flavors */33enum {34 ELMER0_XC2S300E_6FT256_C,35 ELMER0_XC2S100E_6TQ144_C36};37 38/* ELMER0 registers */39#define A_ELMER0_VERSION 0x10000040#define A_ELMER0_PHY_CFG 0x10000441#define A_ELMER0_INT_ENABLE 0x10000842#define A_ELMER0_INT_CAUSE 0x10000c43#define A_ELMER0_GPI_CFG 0x10001044#define A_ELMER0_GPI_STAT 0x10001445#define A_ELMER0_GPO 0x10001846#define A_ELMER0_PORT0_MI1_CFG 0x40000047 48#define S_MI1_MDI_ENABLE 049#define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)50#define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U)51 52#define S_MI1_MDI_INVERT 153#define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)54#define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U)55 56#define S_MI1_PREAMBLE_ENABLE 257#define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)58#define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U)59 60#define S_MI1_SOF 361#define M_MI1_SOF 0x362#define V_MI1_SOF(x) ((x) << S_MI1_SOF)63#define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)64 65#define S_MI1_CLK_DIV 566#define M_MI1_CLK_DIV 0xff67#define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)68#define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)69 70#define A_ELMER0_PORT0_MI1_ADDR 0x40000471 72#define S_MI1_REG_ADDR 073#define M_MI1_REG_ADDR 0x1f74#define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)75#define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)76 77#define S_MI1_PHY_ADDR 578#define M_MI1_PHY_ADDR 0x1f79#define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)80#define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)81 82#define A_ELMER0_PORT0_MI1_DATA 0x40000883 84#define S_MI1_DATA 085#define M_MI1_DATA 0xffff86#define V_MI1_DATA(x) ((x) << S_MI1_DATA)87#define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)88 89#define A_ELMER0_PORT0_MI1_OP 0x40000c90 91#define S_MI1_OP 092#define M_MI1_OP 0x393#define V_MI1_OP(x) ((x) << S_MI1_OP)94#define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)95 96#define S_MI1_ADDR_AUTOINC 297#define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)98#define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U)99 100#define S_MI1_OP_BUSY 31101#define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)102#define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U)103 104#define A_ELMER0_PORT1_MI1_CFG 0x500000105#define A_ELMER0_PORT1_MI1_ADDR 0x500004106#define A_ELMER0_PORT1_MI1_DATA 0x500008107#define A_ELMER0_PORT1_MI1_OP 0x50000c108#define A_ELMER0_PORT2_MI1_CFG 0x600000109#define A_ELMER0_PORT2_MI1_ADDR 0x600004110#define A_ELMER0_PORT2_MI1_DATA 0x600008111#define A_ELMER0_PORT2_MI1_OP 0x60000c112#define A_ELMER0_PORT3_MI1_CFG 0x700000113#define A_ELMER0_PORT3_MI1_ADDR 0x700004114#define A_ELMER0_PORT3_MI1_DATA 0x700008115#define A_ELMER0_PORT3_MI1_OP 0x70000c116 117/* Simple bit definition for GPI and GP0 registers. */118#define ELMER0_GP_BIT0 0x0001119#define ELMER0_GP_BIT1 0x0002120#define ELMER0_GP_BIT2 0x0004121#define ELMER0_GP_BIT3 0x0008122#define ELMER0_GP_BIT4 0x0010123#define ELMER0_GP_BIT5 0x0020124#define ELMER0_GP_BIT6 0x0040125#define ELMER0_GP_BIT7 0x0080126#define ELMER0_GP_BIT8 0x0100127#define ELMER0_GP_BIT9 0x0200128#define ELMER0_GP_BIT10 0x0400129#define ELMER0_GP_BIT11 0x0800130#define ELMER0_GP_BIT12 0x1000131#define ELMER0_GP_BIT13 0x2000132#define ELMER0_GP_BIT14 0x4000133#define ELMER0_GP_BIT15 0x8000134#define ELMER0_GP_BIT16 0x10000135#define ELMER0_GP_BIT17 0x20000136#define ELMER0_GP_BIT18 0x40000137#define ELMER0_GP_BIT19 0x80000138 139#define MI1_OP_DIRECT_WRITE 1140#define MI1_OP_DIRECT_READ 2141 142#define MI1_OP_INDIRECT_ADDRESS 0143#define MI1_OP_INDIRECT_WRITE 1144#define MI1_OP_INDIRECT_READ_INC 2145#define MI1_OP_INDIRECT_READ 3146 147#endif /* _CXGB_ELMER0_H_ */148