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1/* SPDX-License-Identifier: GPL-2.0 */2/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */3 4/*5 * FPGA specific definitions6 */7 8#ifndef __CHELSIO_FPGA_DEFS_H__9#define __CHELSIO_FPGA_DEFS_H__10 11#define FPGA_PCIX_ADDR_VERSION 0xA0812#define FPGA_PCIX_ADDR_STAT 0xA0C13 14/* FPGA master interrupt Cause/Enable bits */15#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x116#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x217#define FPGA_PCIX_INTERRUPT_TP 0x418#define FPGA_PCIX_INTERRUPT_MC3 0x819#define FPGA_PCIX_INTERRUPT_GMAC 0x1020#define FPGA_PCIX_INTERRUPT_PCIX 0x2021 22/* TP interrupt register addresses */23#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA1024#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA1425#define FPGA_TP_ADDR_VERSION 0xA1826 27/* TP interrupt Cause/Enable bits */28#define FPGA_TP_INTERRUPT_MC4 0x129#define FPGA_TP_INTERRUPT_MC5 0x230 31/*32 * PM interrupt register addresses33 */34#define FPGA_MC3_REG_INTRENABLE 0xA2035#define FPGA_MC3_REG_INTRCAUSE 0xA2436#define FPGA_MC3_REG_VERSION 0xA2837 38/*39 * GMAC interrupt register addresses40 */41#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA3042#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA3443#define FPGA_GMAC_ADDR_VERSION 0xA3844 45/* GMAC Cause/Enable bits */46#define FPGA_GMAC_INTERRUPT_PORT0 0x147#define FPGA_GMAC_INTERRUPT_PORT1 0x248#define FPGA_GMAC_INTERRUPT_PORT2 0x449#define FPGA_GMAC_INTERRUPT_PORT3 0x850 51/* MI0 registers */52#define A_MI0_CLK 0xb0053 54#define S_MI0_CLK_DIV 055#define M_MI0_CLK_DIV 0xff56#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)57#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)58 59#define S_MI0_CLK_CNT 860#define M_MI0_CLK_CNT 0xff61#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)62#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)63 64#define A_MI0_CSR 0xb0465 66#define S_MI0_CSR_POLL 067#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)68#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U)69 70#define S_MI0_PREAMBLE 171#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)72#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U)73 74#define S_MI0_INTR_ENABLE 275#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)76#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U)77 78#define S_MI0_BUSY 379#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)80#define F_MI0_BUSY V_MI0_BUSY(1U)81 82#define S_MI0_MDIO 483#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)84#define F_MI0_MDIO V_MI0_MDIO(1U)85 86#define A_MI0_ADDR 0xb0887 88#define S_MI0_PHY_REG_ADDR 089#define M_MI0_PHY_REG_ADDR 0x1f90#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)91#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)92 93#define S_MI0_PHY_ADDR 594#define M_MI0_PHY_ADDR 0x1f95#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)96#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)97 98#define A_MI0_DATA_EXT 0xb0c99#define A_MI0_DATA_INT 0xb10100 101/* GMAC registers */102#define A_GMAC_MACID_LO 0x28103#define A_GMAC_MACID_HI 0x2c104#define A_GMAC_CSR 0x30105 106#define S_INTERFACE 0107#define M_INTERFACE 0x3108#define V_INTERFACE(x) ((x) << S_INTERFACE)109#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)110 111#define S_MAC_TX_ENABLE 2112#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)113#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U)114 115#define S_MAC_RX_ENABLE 3116#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)117#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U)118 119#define S_MAC_LB_ENABLE 4120#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)121#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U)122 123#define S_MAC_SPEED 5124#define M_MAC_SPEED 0x3125#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)126#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)127 128#define S_MAC_HD_FC_ENABLE 7129#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)130#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U)131 132#define S_MAC_HALF_DUPLEX 8133#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)134#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U)135 136#define S_MAC_PROMISC 9137#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)138#define F_MAC_PROMISC V_MAC_PROMISC(1U)139 140#define S_MAC_MC_ENABLE 10141#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)142#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U)143 144#define S_MAC_RESET 11145#define V_MAC_RESET(x) ((x) << S_MAC_RESET)146#define F_MAC_RESET V_MAC_RESET(1U)147 148#define S_MAC_RX_PAUSE_ENABLE 12149#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)150#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U)151 152#define S_MAC_TX_PAUSE_ENABLE 13153#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)154#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U)155 156#define S_MAC_LWM_ENABLE 14157#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)158#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U)159 160#define S_MAC_MAGIC_PKT_ENABLE 15161#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)162#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U)163 164#define S_MAC_ISL_ENABLE 16165#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)166#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U)167 168#define S_MAC_JUMBO_ENABLE 17169#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)170#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U)171 172#define S_MAC_RX_PAD_ENABLE 18173#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)174#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U)175 176#define S_MAC_RX_CRC_ENABLE 19177#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)178#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U)179 180#define A_GMAC_IFS 0x34181 182#define S_MAC_IFS2 0183#define M_MAC_IFS2 0x3f184#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)185#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)186 187#define S_MAC_IFS1 8188#define M_MAC_IFS1 0x7f189#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)190#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)191 192#define A_GMAC_JUMBO_FRAME_LEN 0x38193#define A_GMAC_LNK_DLY 0x3c194#define A_GMAC_PAUSETIME 0x40195#define A_GMAC_MCAST_LO 0x44196#define A_GMAC_MCAST_HI 0x48197#define A_GMAC_MCAST_MASK_LO 0x4c198#define A_GMAC_MCAST_MASK_HI 0x50199#define A_GMAC_RMT_CNT 0x54200#define A_GMAC_RMT_DATA 0x58201#define A_GMAC_BACKOFF_SEED 0x5c202#define A_GMAC_TXF_THRES 0x60203 204#define S_TXF_READ_THRESHOLD 0205#define M_TXF_READ_THRESHOLD 0xff206#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)207#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)208 209#define S_TXF_WRITE_THRESHOLD 16210#define M_TXF_WRITE_THRESHOLD 0xff211#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)212#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)213 214#define MAC_REG_BASE 0x600215#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))216 217#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)218#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)219#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)220#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)221#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)222#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)223#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)224#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)225#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)226#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)227#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)228#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)229#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)230#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)231#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)232 233#endif234