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1/* SPDX-License-Identifier: GPL-2.0-only */2/*****************************************************************************3 * *4 * File: regs.h *5 * $Revision: 1.8 $ *6 * $Date: 2005/06/21 18:29:48 $ *7 * Description: *8 * part of the Chelsio 10Gb Ethernet Driver. *9 * *10 * *11 * http://www.chelsio.com *12 * *13 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *14 * All rights reserved. *15 * *16 * Maintainers: maintainers@chelsio.com *17 * *18 * Authors: Dimitrios Michailidis <dm@chelsio.com> *19 * Tina Yang <tainay@chelsio.com> *20 * Felix Marti <felix@chelsio.com> *21 * Scott Bardone <sbardone@chelsio.com> *22 * Kurt Ottaway <kottaway@chelsio.com> *23 * Frank DiMambro <frank@chelsio.com> *24 * *25 * History: *26 * *27 ****************************************************************************/28 29#ifndef _CXGB_REGS_H_30#define _CXGB_REGS_H_31 32/* SGE registers */33#define A_SG_CONTROL 0x034 35#define S_CMDQ0_ENABLE 036#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)37#define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)38 39#define S_CMDQ1_ENABLE 140#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)41#define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)42 43#define S_FL0_ENABLE 244#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)45#define F_FL0_ENABLE V_FL0_ENABLE(1U)46 47#define S_FL1_ENABLE 348#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)49#define F_FL1_ENABLE V_FL1_ENABLE(1U)50 51#define S_CPL_ENABLE 452#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)53#define F_CPL_ENABLE V_CPL_ENABLE(1U)54 55#define S_RESPONSE_QUEUE_ENABLE 556#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)57#define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)58 59#define S_CMDQ_PRIORITY 660#define M_CMDQ_PRIORITY 0x361#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)62#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)63 64#define S_DISABLE_CMDQ0_GTS 865#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)66#define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U)67 68#define S_DISABLE_CMDQ1_GTS 969#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)70#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)71 72#define S_DISABLE_FL0_GTS 1073#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)74#define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)75 76#define S_DISABLE_FL1_GTS 1177#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)78#define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)79 80#define S_ENABLE_BIG_ENDIAN 1281#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)82#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)83 84#define S_FL_SELECTION_CRITERIA 1385#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)86#define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U)87 88#define S_ISCSI_COALESCE 1489#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)90#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)91 92#define S_RX_PKT_OFFSET 1593#define M_RX_PKT_OFFSET 0x794#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)95#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)96 97#define S_VLAN_XTRACT 1898#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)99#define F_VLAN_XTRACT V_VLAN_XTRACT(1U)100 101#define A_SG_DOORBELL 0x4102#define A_SG_CMD0BASELWR 0x8103#define A_SG_CMD0BASEUPR 0xc104#define A_SG_CMD1BASELWR 0x10105#define A_SG_CMD1BASEUPR 0x14106#define A_SG_FL0BASELWR 0x18107#define A_SG_FL0BASEUPR 0x1c108#define A_SG_FL1BASELWR 0x20109#define A_SG_FL1BASEUPR 0x24110#define A_SG_CMD0SIZE 0x28111 112#define S_CMDQ0_SIZE 0113#define M_CMDQ0_SIZE 0x1ffff114#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)115#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)116 117#define A_SG_FL0SIZE 0x2c118 119#define S_FL0_SIZE 0120#define M_FL0_SIZE 0x1ffff121#define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)122#define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)123 124#define A_SG_RSPSIZE 0x30125 126#define S_RESPQ_SIZE 0127#define M_RESPQ_SIZE 0x1ffff128#define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)129#define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)130 131#define A_SG_RSPBASELWR 0x34132#define A_SG_RSPBASEUPR 0x38133#define A_SG_FLTHRESHOLD 0x3c134 135#define S_FL_THRESHOLD 0136#define M_FL_THRESHOLD 0xffff137#define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)138#define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)139 140#define A_SG_RSPQUEUECREDIT 0x40141 142#define S_RESPQ_CREDIT 0143#define M_RESPQ_CREDIT 0x1ffff144#define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)145#define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)146 147#define A_SG_SLEEPING 0x48148 149#define S_SLEEPING 0150#define M_SLEEPING 0xffff151#define V_SLEEPING(x) ((x) << S_SLEEPING)152#define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)153 154#define A_SG_INTRTIMER 0x4c155 156#define S_INTERRUPT_TIMER_COUNT 0157#define M_INTERRUPT_TIMER_COUNT 0xffffff158#define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)159#define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)160 161#define A_SG_CMD0PTR 0x50162 163#define S_CMDQ0_POINTER 0164#define M_CMDQ0_POINTER 0xffff165#define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)166#define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)167 168#define S_CURRENT_GENERATION_BIT 16169#define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)170#define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U)171 172#define A_SG_CMD1PTR 0x54173 174#define S_CMDQ1_POINTER 0175#define M_CMDQ1_POINTER 0xffff176#define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)177#define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)178 179#define A_SG_FL0PTR 0x58180 181#define S_FL0_POINTER 0182#define M_FL0_POINTER 0xffff183#define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)184#define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)185 186#define A_SG_FL1PTR 0x5c187 188#define S_FL1_POINTER 0189#define M_FL1_POINTER 0xffff190#define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)191#define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)192 193#define A_SG_VERSION 0x6c194 195#define S_DAY 0196#define M_DAY 0x1f197#define V_DAY(x) ((x) << S_DAY)198#define G_DAY(x) (((x) >> S_DAY) & M_DAY)199 200#define S_MONTH 5201#define M_MONTH 0xf202#define V_MONTH(x) ((x) << S_MONTH)203#define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)204 205#define A_SG_CMD1SIZE 0xb0206 207#define S_CMDQ1_SIZE 0208#define M_CMDQ1_SIZE 0x1ffff209#define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)210#define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)211 212#define A_SG_FL1SIZE 0xb4213 214#define S_FL1_SIZE 0215#define M_FL1_SIZE 0x1ffff216#define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)217#define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)218 219#define A_SG_INT_ENABLE 0xb8220 221#define S_RESPQ_EXHAUSTED 0222#define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)223#define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)224 225#define S_RESPQ_OVERFLOW 1226#define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)227#define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)228 229#define S_FL_EXHAUSTED 2230#define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)231#define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)232 233#define S_PACKET_TOO_BIG 3234#define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)235#define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)236 237#define S_PACKET_MISMATCH 4238#define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)239#define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)240 241#define A_SG_INT_CAUSE 0xbc242#define A_SG_RESPACCUTIMER 0xc0243 244/* MC3 registers */245#define A_MC3_CFG 0x100246 247#define S_CLK_ENABLE 0248#define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)249#define F_CLK_ENABLE V_CLK_ENABLE(1U)250 251#define S_READY 1252#define V_READY(x) ((x) << S_READY)253#define F_READY V_READY(1U)254 255#define S_READ_TO_WRITE_DELAY 2256#define M_READ_TO_WRITE_DELAY 0x7257#define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)258#define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)259 260#define S_WRITE_TO_READ_DELAY 5261#define M_WRITE_TO_READ_DELAY 0x7262#define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)263#define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)264 265#define S_MC3_BANK_CYCLE 8266#define M_MC3_BANK_CYCLE 0xf267#define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)268#define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)269 270#define S_REFRESH_CYCLE 12271#define M_REFRESH_CYCLE 0xf272#define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)273#define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)274 275#define S_PRECHARGE_CYCLE 16276#define M_PRECHARGE_CYCLE 0x3277#define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)278#define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)279 280#define S_ACTIVE_TO_READ_WRITE_DELAY 18281#define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)282#define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U)283 284#define S_ACTIVE_TO_PRECHARGE_DELAY 19285#define M_ACTIVE_TO_PRECHARGE_DELAY 0x7286#define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)287#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)288 289#define S_WRITE_RECOVERY_DELAY 22290#define M_WRITE_RECOVERY_DELAY 0x3291#define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)292#define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)293 294#define S_DENSITY 24295#define M_DENSITY 0x3296#define V_DENSITY(x) ((x) << S_DENSITY)297#define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)298 299#define S_ORGANIZATION 26300#define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)301#define F_ORGANIZATION V_ORGANIZATION(1U)302 303#define S_BANKS 27304#define V_BANKS(x) ((x) << S_BANKS)305#define F_BANKS V_BANKS(1U)306 307#define S_UNREGISTERED 28308#define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)309#define F_UNREGISTERED V_UNREGISTERED(1U)310 311#define S_MC3_WIDTH 29312#define M_MC3_WIDTH 0x3313#define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)314#define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)315 316#define S_MC3_SLOW 31317#define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)318#define F_MC3_SLOW V_MC3_SLOW(1U)319 320#define A_MC3_MODE 0x104321 322#define S_MC3_MODE 0323#define M_MC3_MODE 0x3fff324#define V_MC3_MODE(x) ((x) << S_MC3_MODE)325#define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)326 327#define S_BUSY 31328#define V_BUSY(x) ((x) << S_BUSY)329#define F_BUSY V_BUSY(1U)330 331#define A_MC3_EXT_MODE 0x108332 333#define S_MC3_EXTENDED_MODE 0334#define M_MC3_EXTENDED_MODE 0x3fff335#define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)336#define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)337 338#define A_MC3_PRECHARG 0x10c339#define A_MC3_REFRESH 0x110340 341#define S_REFRESH_ENABLE 0342#define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)343#define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U)344 345#define S_REFRESH_DIVISOR 1346#define M_REFRESH_DIVISOR 0x3fff347#define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)348#define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)349 350#define A_MC3_STROBE 0x114351 352#define S_MASTER_DLL_RESET 0353#define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)354#define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U)355 356#define S_MASTER_DLL_TAP_COUNT 1357#define M_MASTER_DLL_TAP_COUNT 0xff358#define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)359#define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)360 361#define S_MASTER_DLL_LOCKED 9362#define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)363#define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U)364 365#define S_MASTER_DLL_MAX_TAP_COUNT 10366#define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)367#define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U)368 369#define S_MASTER_DLL_TAP_COUNT_OFFSET 11370#define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f371#define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)372#define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)373 374#define S_SLAVE_DLL_RESET 11375#define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)376#define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U)377 378#define S_SLAVE_DLL_DELTA 12379#define M_SLAVE_DLL_DELTA 0xf380#define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)381#define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)382 383#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17384#define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f385#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)386#define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)387 388#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23389#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)390#define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)391 392#define S_SLAVE_DELAY_LINE_TAP_COUNT 24393#define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f394#define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)395#define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)396 397#define A_MC3_ECC_CNTL 0x118398 399#define S_ECC_GENERATION_ENABLE 0400#define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)401#define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U)402 403#define S_ECC_CHECK_ENABLE 1404#define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)405#define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U)406 407#define S_CORRECTABLE_ERROR_COUNT 2408#define M_CORRECTABLE_ERROR_COUNT 0xff409#define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)410#define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)411 412#define S_UNCORRECTABLE_ERROR_COUNT 10413#define M_UNCORRECTABLE_ERROR_COUNT 0xff414#define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)415#define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)416 417#define A_MC3_CE_ADDR 0x11c418 419#define S_MC3_CE_ADDR 4420#define M_MC3_CE_ADDR 0xfffffff421#define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)422#define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)423 424#define A_MC3_CE_DATA0 0x120425#define A_MC3_CE_DATA1 0x124426#define A_MC3_CE_DATA2 0x128427#define A_MC3_CE_DATA3 0x12c428#define A_MC3_CE_DATA4 0x130429#define A_MC3_UE_ADDR 0x134430 431#define S_MC3_UE_ADDR 4432#define M_MC3_UE_ADDR 0xfffffff433#define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)434#define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)435 436#define A_MC3_UE_DATA0 0x138437#define A_MC3_UE_DATA1 0x13c438#define A_MC3_UE_DATA2 0x140439#define A_MC3_UE_DATA3 0x144440#define A_MC3_UE_DATA4 0x148441#define A_MC3_BD_ADDR 0x14c442#define A_MC3_BD_DATA0 0x150443#define A_MC3_BD_DATA1 0x154444#define A_MC3_BD_DATA2 0x158445#define A_MC3_BD_DATA3 0x15c446#define A_MC3_BD_DATA4 0x160447#define A_MC3_BD_OP 0x164448 449#define S_BACK_DOOR_OPERATION 0450#define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)451#define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U)452 453#define A_MC3_BIST_ADDR_BEG 0x168454#define A_MC3_BIST_ADDR_END 0x16c455#define A_MC3_BIST_DATA 0x170456#define A_MC3_BIST_OP 0x174457 458#define S_OP 0459#define V_OP(x) ((x) << S_OP)460#define F_OP V_OP(1U)461 462#define S_DATA_PATTERN 1463#define M_DATA_PATTERN 0x3464#define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)465#define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)466 467#define S_CONTINUOUS 3468#define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)469#define F_CONTINUOUS V_CONTINUOUS(1U)470 471#define A_MC3_INT_ENABLE 0x178472 473#define S_MC3_CORR_ERR 0474#define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)475#define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U)476 477#define S_MC3_UNCORR_ERR 1478#define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)479#define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U)480 481#define S_MC3_PARITY_ERR 2482#define M_MC3_PARITY_ERR 0xff483#define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)484#define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)485 486#define S_MC3_ADDR_ERR 10487#define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)488#define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U)489 490#define A_MC3_INT_CAUSE 0x17c491 492/* MC4 registers */493#define A_MC4_CFG 0x180494 495#define S_POWER_UP 0496#define V_POWER_UP(x) ((x) << S_POWER_UP)497#define F_POWER_UP V_POWER_UP(1U)498 499#define S_MC4_BANK_CYCLE 8500#define M_MC4_BANK_CYCLE 0x7501#define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)502#define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)503 504#define S_MC4_NARROW 24505#define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)506#define F_MC4_NARROW V_MC4_NARROW(1U)507 508#define S_MC4_SLOW 25509#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)510#define F_MC4_SLOW V_MC4_SLOW(1U)511 512#define S_MC4A_WIDTH 24513#define M_MC4A_WIDTH 0x3514#define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)515#define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)516 517#define S_MC4A_SLOW 26518#define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)519#define F_MC4A_SLOW V_MC4A_SLOW(1U)520 521#define A_MC4_MODE 0x184522 523#define S_MC4_MODE 0524#define M_MC4_MODE 0x7fff525#define V_MC4_MODE(x) ((x) << S_MC4_MODE)526#define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)527 528#define A_MC4_EXT_MODE 0x188529 530#define S_MC4_EXTENDED_MODE 0531#define M_MC4_EXTENDED_MODE 0x7fff532#define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)533#define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)534 535#define A_MC4_REFRESH 0x190536#define A_MC4_STROBE 0x194537#define A_MC4_ECC_CNTL 0x198538#define A_MC4_CE_ADDR 0x19c539 540#define S_MC4_CE_ADDR 4541#define M_MC4_CE_ADDR 0xffffff542#define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)543#define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)544 545#define A_MC4_CE_DATA0 0x1a0546#define A_MC4_CE_DATA1 0x1a4547#define A_MC4_CE_DATA2 0x1a8548#define A_MC4_CE_DATA3 0x1ac549#define A_MC4_CE_DATA4 0x1b0550#define A_MC4_UE_ADDR 0x1b4551 552#define S_MC4_UE_ADDR 4553#define M_MC4_UE_ADDR 0xffffff554#define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)555#define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)556 557#define A_MC4_UE_DATA0 0x1b8558#define A_MC4_UE_DATA1 0x1bc559#define A_MC4_UE_DATA2 0x1c0560#define A_MC4_UE_DATA3 0x1c4561#define A_MC4_UE_DATA4 0x1c8562#define A_MC4_BD_ADDR 0x1cc563 564#define S_MC4_BACK_DOOR_ADDR 0565#define M_MC4_BACK_DOOR_ADDR 0xfffffff566#define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)567#define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)568 569#define A_MC4_BD_DATA0 0x1d0570#define A_MC4_BD_DATA1 0x1d4571#define A_MC4_BD_DATA2 0x1d8572#define A_MC4_BD_DATA3 0x1dc573#define A_MC4_BD_DATA4 0x1e0574#define A_MC4_BD_OP 0x1e4575 576#define S_OPERATION 0577#define V_OPERATION(x) ((x) << S_OPERATION)578#define F_OPERATION V_OPERATION(1U)579 580#define A_MC4_BIST_ADDR_BEG 0x1e8581#define A_MC4_BIST_ADDR_END 0x1ec582#define A_MC4_BIST_DATA 0x1f0583#define A_MC4_BIST_OP 0x1f4584#define A_MC4_INT_ENABLE 0x1f8585 586#define S_MC4_CORR_ERR 0587#define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)588#define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U)589 590#define S_MC4_UNCORR_ERR 1591#define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)592#define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U)593 594#define S_MC4_ADDR_ERR 2595#define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)596#define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U)597 598#define A_MC4_INT_CAUSE 0x1fc599 600/* TPI registers */601#define A_TPI_ADDR 0x280602 603#define S_TPI_ADDRESS 0604#define M_TPI_ADDRESS 0xffffff605#define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)606#define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)607 608#define A_TPI_WR_DATA 0x284609#define A_TPI_RD_DATA 0x288610#define A_TPI_CSR 0x28c611 612#define S_TPIWR 0613#define V_TPIWR(x) ((x) << S_TPIWR)614#define F_TPIWR V_TPIWR(1U)615 616#define S_TPIRDY 1617#define V_TPIRDY(x) ((x) << S_TPIRDY)618#define F_TPIRDY V_TPIRDY(1U)619 620#define S_INT_DIR 31621#define V_INT_DIR(x) ((x) << S_INT_DIR)622#define F_INT_DIR V_INT_DIR(1U)623 624#define A_TPI_PAR 0x29c625 626#define S_TPIPAR 0627#define M_TPIPAR 0x7f628#define V_TPIPAR(x) ((x) << S_TPIPAR)629#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)630 631 632/* TP registers */633#define A_TP_IN_CONFIG 0x300634 635#define S_TP_IN_CSPI_TUNNEL 0636#define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)637#define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U)638 639#define S_TP_IN_CSPI_ETHERNET 1640#define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)641#define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U)642 643#define S_TP_IN_CSPI_CPL 3644#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)645#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)646 647#define S_TP_IN_CSPI_POS 4648#define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)649#define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U)650 651#define S_TP_IN_CSPI_CHECK_IP_CSUM 5652#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)653#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)654 655#define S_TP_IN_CSPI_CHECK_TCP_CSUM 6656#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)657#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)658 659#define S_TP_IN_ESPI_TUNNEL 7660#define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)661#define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U)662 663#define S_TP_IN_ESPI_ETHERNET 8664#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)665#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)666 667#define S_TP_IN_ESPI_CPL 10668#define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)669#define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U)670 671#define S_TP_IN_ESPI_POS 11672#define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)673#define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U)674 675#define S_TP_IN_ESPI_CHECK_IP_CSUM 12676#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)677#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)678 679#define S_TP_IN_ESPI_CHECK_TCP_CSUM 13680#define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)681#define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)682 683#define S_OFFLOAD_DISABLE 14684#define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)685#define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)686 687#define A_TP_OUT_CONFIG 0x304688 689#define S_TP_OUT_C_ETH 0690#define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)691#define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U)692 693#define S_TP_OUT_CSPI_CPL 2694#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)695#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)696 697#define S_TP_OUT_CSPI_POS 3698#define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)699#define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U)700 701#define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4702#define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)703#define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)704 705#define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5706#define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)707#define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)708 709#define S_TP_OUT_ESPI_ETHERNET 6710#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)711#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)712 713#define S_TP_OUT_ESPI_TAG_ETHERNET 7714#define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)715#define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U)716 717#define S_TP_OUT_ESPI_CPL 8718#define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)719#define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U)720 721#define S_TP_OUT_ESPI_POS 9722#define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)723#define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U)724 725#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10726#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)727#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)728 729#define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11730#define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)731#define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)732 733#define A_TP_GLOBAL_CONFIG 0x308734 735#define S_IP_TTL 0736#define M_IP_TTL 0xff737#define V_IP_TTL(x) ((x) << S_IP_TTL)738#define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)739 740#define S_TCAM_SERVER_REGION_USAGE 8741#define M_TCAM_SERVER_REGION_USAGE 0x3742#define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)743#define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)744 745#define S_QOS_MAPPING 10746#define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)747#define F_QOS_MAPPING V_QOS_MAPPING(1U)748 749#define S_TCP_CSUM 11750#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)751#define F_TCP_CSUM V_TCP_CSUM(1U)752 753#define S_UDP_CSUM 12754#define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)755#define F_UDP_CSUM V_UDP_CSUM(1U)756 757#define S_IP_CSUM 13758#define V_IP_CSUM(x) ((x) << S_IP_CSUM)759#define F_IP_CSUM V_IP_CSUM(1U)760 761#define S_IP_ID_SPLIT 14762#define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)763#define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U)764 765#define S_PATH_MTU 15766#define V_PATH_MTU(x) ((x) << S_PATH_MTU)767#define F_PATH_MTU V_PATH_MTU(1U)768 769#define S_5TUPLE_LOOKUP 17770#define M_5TUPLE_LOOKUP 0x3771#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)772#define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)773 774#define S_IP_FRAGMENT_DROP 19775#define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)776#define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U)777 778#define S_PING_DROP 20779#define V_PING_DROP(x) ((x) << S_PING_DROP)780#define F_PING_DROP V_PING_DROP(1U)781 782#define S_PROTECT_MODE 21783#define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)784#define F_PROTECT_MODE V_PROTECT_MODE(1U)785 786#define S_SYN_COOKIE_ALGORITHM 22787#define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)788#define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U)789 790#define S_ATTACK_FILTER 23791#define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)792#define F_ATTACK_FILTER V_ATTACK_FILTER(1U)793 794#define S_INTERFACE_TYPE 24795#define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)796#define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U)797 798#define S_DISABLE_RX_FLOW_CONTROL 25799#define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)800#define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U)801 802#define S_SYN_COOKIE_PARAMETER 26803#define M_SYN_COOKIE_PARAMETER 0x3f804#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)805#define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)806 807#define A_TP_GLOBAL_RX_CREDITS 0x30c808#define A_TP_CM_SIZE 0x310809#define A_TP_CM_MM_BASE 0x314810 811#define S_CM_MEMMGR_BASE 0812#define M_CM_MEMMGR_BASE 0xfffffff813#define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)814#define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)815 816#define A_TP_CM_TIMER_BASE 0x318817 818#define S_CM_TIMER_BASE 0819#define M_CM_TIMER_BASE 0xfffffff820#define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)821#define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)822 823#define A_TP_PM_SIZE 0x31c824#define A_TP_PM_TX_BASE 0x320825#define A_TP_PM_DEFRAG_BASE 0x324826#define A_TP_PM_RX_BASE 0x328827#define A_TP_PM_RX_PG_SIZE 0x32c828#define A_TP_PM_RX_MAX_PGS 0x330829#define A_TP_PM_TX_PG_SIZE 0x334830#define A_TP_PM_TX_MAX_PGS 0x338831#define A_TP_TCP_OPTIONS 0x340832 833#define S_TIMESTAMP 0834#define M_TIMESTAMP 0x3835#define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)836#define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)837 838#define S_WINDOW_SCALE 2839#define M_WINDOW_SCALE 0x3840#define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)841#define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)842 843#define S_SACK 4844#define M_SACK 0x3845#define V_SACK(x) ((x) << S_SACK)846#define G_SACK(x) (((x) >> S_SACK) & M_SACK)847 848#define S_ECN 6849#define M_ECN 0x3850#define V_ECN(x) ((x) << S_ECN)851#define G_ECN(x) (((x) >> S_ECN) & M_ECN)852 853#define S_SACK_ALGORITHM 8854#define M_SACK_ALGORITHM 0x3855#define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)856#define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)857 858#define S_MSS 10859#define V_MSS(x) ((x) << S_MSS)860#define F_MSS V_MSS(1U)861 862#define S_DEFAULT_PEER_MSS 16863#define M_DEFAULT_PEER_MSS 0xffff864#define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)865#define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)866 867#define A_TP_DACK_CONFIG 0x344868 869#define S_DACK_MODE 0870#define V_DACK_MODE(x) ((x) << S_DACK_MODE)871#define F_DACK_MODE V_DACK_MODE(1U)872 873#define S_DACK_AUTO_MGMT 1874#define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)875#define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U)876 877#define S_DACK_AUTO_CAREFUL 2878#define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)879#define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U)880 881#define S_DACK_MSS_SELECTOR 3882#define M_DACK_MSS_SELECTOR 0x3883#define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)884#define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)885 886#define S_DACK_BYTE_THRESHOLD 5887#define M_DACK_BYTE_THRESHOLD 0xfffff888#define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)889#define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)890 891#define A_TP_PC_CONFIG 0x348892 893#define S_TP_ACCESS_LATENCY 0894#define M_TP_ACCESS_LATENCY 0xf895#define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)896#define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)897 898#define S_HELD_FIN_DISABLE 4899#define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)900#define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U)901 902#define S_DDP_FC_ENABLE 5903#define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)904#define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U)905 906#define S_RDMA_ERR_ENABLE 6907#define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)908#define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U)909 910#define S_FAST_PDU_DELIVERY 7911#define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)912#define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U)913 914#define S_CLEAR_FIN 8915#define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)916#define F_CLEAR_FIN V_CLEAR_FIN(1U)917 918#define S_DIS_TX_FILL_WIN_PUSH 12919#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)920#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)921 922#define S_TP_PC_REV 30923#define M_TP_PC_REV 0x3924#define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)925#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)926 927#define A_TP_BACKOFF0 0x350928 929#define S_ELEMENT0 0930#define M_ELEMENT0 0xff931#define V_ELEMENT0(x) ((x) << S_ELEMENT0)932#define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)933 934#define S_ELEMENT1 8935#define M_ELEMENT1 0xff936#define V_ELEMENT1(x) ((x) << S_ELEMENT1)937#define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)938 939#define S_ELEMENT2 16940#define M_ELEMENT2 0xff941#define V_ELEMENT2(x) ((x) << S_ELEMENT2)942#define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)943 944#define S_ELEMENT3 24945#define M_ELEMENT3 0xff946#define V_ELEMENT3(x) ((x) << S_ELEMENT3)947#define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)948 949#define A_TP_BACKOFF1 0x354950#define A_TP_BACKOFF2 0x358951#define A_TP_BACKOFF3 0x35c952#define A_TP_PARA_REG0 0x360953 954#define S_VAR_MULT 0955#define M_VAR_MULT 0xf956#define V_VAR_MULT(x) ((x) << S_VAR_MULT)957#define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)958 959#define S_VAR_GAIN 4960#define M_VAR_GAIN 0xf961#define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)962#define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)963 964#define S_SRTT_GAIN 8965#define M_SRTT_GAIN 0xf966#define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)967#define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)968 969#define S_RTTVAR_INIT 12970#define M_RTTVAR_INIT 0xf971#define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)972#define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)973 974#define S_DUP_THRESH 20975#define M_DUP_THRESH 0xf976#define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)977#define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)978 979#define S_INIT_CONG_WIN 24980#define M_INIT_CONG_WIN 0x7981#define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)982#define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)983 984#define A_TP_PARA_REG1 0x364985 986#define S_INITIAL_SLOW_START_THRESHOLD 0987#define M_INITIAL_SLOW_START_THRESHOLD 0xffff988#define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)989#define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)990 991#define S_RECEIVE_BUFFER_SIZE 16992#define M_RECEIVE_BUFFER_SIZE 0xffff993#define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)994#define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)995 996#define A_TP_PARA_REG2 0x368997 998#define S_RX_COALESCE_SIZE 0999#define M_RX_COALESCE_SIZE 0xffff1000#define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)1001#define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)1002 1003#define S_MAX_RX_SIZE 161004#define M_MAX_RX_SIZE 0xffff1005#define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)1006#define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)1007 1008#define A_TP_PARA_REG3 0x36c1009 1010#define S_RX_COALESCING_PSH_DELIVER 01011#define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)1012#define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U)1013 1014#define S_RX_COALESCING_ENABLE 11015#define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)1016#define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U)1017 1018#define S_TAHOE_ENABLE 21019#define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)1020#define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U)1021 1022#define S_MAX_REORDER_FRAGMENTS 121023#define M_MAX_REORDER_FRAGMENTS 0x71024#define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)1025#define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)1026 1027#define A_TP_TIMER_RESOLUTION 0x3901028 1029#define S_DELAYED_ACK_TIMER_RESOLUTION 01030#define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f1031#define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)1032#define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)1033 1034#define S_GENERIC_TIMER_RESOLUTION 161035#define M_GENERIC_TIMER_RESOLUTION 0x3f1036#define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)1037#define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)1038 1039#define A_TP_2MSL 0x3941040 1041#define S_2MSL 01042#define M_2MSL 0x3fffffff1043#define V_2MSL(x) ((x) << S_2MSL)1044#define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)1045 1046#define A_TP_RXT_MIN 0x3981047 1048#define S_RETRANSMIT_TIMER_MIN 01049#define M_RETRANSMIT_TIMER_MIN 0xffff1050#define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)1051#define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)1052 1053#define A_TP_RXT_MAX 0x39c1054 1055#define S_RETRANSMIT_TIMER_MAX 01056#define M_RETRANSMIT_TIMER_MAX 0x3fffffff1057#define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)1058#define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)1059 1060#define A_TP_PERS_MIN 0x3a01061 1062#define S_PERSIST_TIMER_MIN 01063#define M_PERSIST_TIMER_MIN 0xffff1064#define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)1065#define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)1066 1067#define A_TP_PERS_MAX 0x3a41068 1069#define S_PERSIST_TIMER_MAX 01070#define M_PERSIST_TIMER_MAX 0x3fffffff1071#define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)1072#define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)1073 1074#define A_TP_KEEP_IDLE 0x3ac1075 1076#define S_KEEP_ALIVE_IDLE_TIME 01077#define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff1078#define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)1079#define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)1080 1081#define A_TP_KEEP_INTVL 0x3b01082 1083#define S_KEEP_ALIVE_INTERVAL_TIME 01084#define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff1085#define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)1086#define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)1087 1088#define A_TP_INIT_SRTT 0x3b41089 1090#define S_INITIAL_SRTT 01091#define M_INITIAL_SRTT 0xffff1092#define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)1093#define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)1094 1095#define A_TP_DACK_TIME 0x3b81096 1097#define S_DELAYED_ACK_TIME 01098#define M_DELAYED_ACK_TIME 0x7ff1099#define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)1100#define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)1101 1102#define A_TP_FINWAIT2_TIME 0x3bc1103 1104#define S_FINWAIT2_TIME 01105#define M_FINWAIT2_TIME 0x3fffffff1106#define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)1107#define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)1108 1109#define A_TP_FAST_FINWAIT2_TIME 0x3c01110 1111#define S_FAST_FINWAIT2_TIME 01112#define M_FAST_FINWAIT2_TIME 0x3fffffff1113#define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)1114#define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)1115 1116#define A_TP_SHIFT_CNT 0x3c41117 1118#define S_KEEPALIVE_MAX 01119#define M_KEEPALIVE_MAX 0xff1120#define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)1121#define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)1122 1123#define S_WINDOWPROBE_MAX 81124#define M_WINDOWPROBE_MAX 0xff1125#define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)1126#define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)1127 1128#define S_RETRANSMISSION_MAX 161129#define M_RETRANSMISSION_MAX 0xff1130#define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)1131#define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)1132 1133#define S_SYN_MAX 241134#define M_SYN_MAX 0xff1135#define V_SYN_MAX(x) ((x) << S_SYN_MAX)1136#define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)1137 1138#define A_TP_QOS_REG0 0x3e01139 1140#define S_L3_VALUE 01141#define M_L3_VALUE 0x3f1142#define V_L3_VALUE(x) ((x) << S_L3_VALUE)1143#define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)1144 1145#define A_TP_QOS_REG1 0x3e41146#define A_TP_QOS_REG2 0x3e81147#define A_TP_QOS_REG3 0x3ec1148#define A_TP_QOS_REG4 0x3f01149#define A_TP_QOS_REG5 0x3f41150#define A_TP_QOS_REG6 0x3f81151#define A_TP_QOS_REG7 0x3fc1152#define A_TP_MTU_REG0 0x4041153#define A_TP_MTU_REG1 0x4081154#define A_TP_MTU_REG2 0x40c1155#define A_TP_MTU_REG3 0x4101156#define A_TP_MTU_REG4 0x4141157#define A_TP_MTU_REG5 0x4181158#define A_TP_MTU_REG6 0x41c1159#define A_TP_MTU_REG7 0x4201160#define A_TP_RESET 0x44c1161 1162#define S_TP_RESET 01163#define V_TP_RESET(x) ((x) << S_TP_RESET)1164#define F_TP_RESET V_TP_RESET(1U)1165 1166#define S_CM_MEMMGR_INIT 11167#define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)1168#define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U)1169 1170#define A_TP_MIB_INDEX 0x4501171#define A_TP_MIB_DATA 0x4541172#define A_TP_SYNC_TIME_HI 0x4581173#define A_TP_SYNC_TIME_LO 0x45c1174#define A_TP_CM_MM_RX_FLST_BASE 0x4601175 1176#define S_CM_MEMMGR_RX_FREE_LIST_BASE 01177#define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff1178#define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)1179#define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)1180 1181#define A_TP_CM_MM_TX_FLST_BASE 0x4641182 1183#define S_CM_MEMMGR_TX_FREE_LIST_BASE 01184#define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff1185#define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)1186#define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)1187 1188#define A_TP_CM_MM_P_FLST_BASE 0x4681189 1190#define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 01191#define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff1192#define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)1193#define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)1194 1195#define A_TP_CM_MM_MAX_P 0x46c1196 1197#define S_CM_MEMMGR_MAX_PSTRUCT 01198#define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff1199#define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)1200#define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)1201 1202#define A_TP_INT_ENABLE 0x4701203 1204#define S_TX_FREE_LIST_EMPTY 01205#define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)1206#define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U)1207 1208#define S_RX_FREE_LIST_EMPTY 11209#define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)1210#define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U)1211 1212#define A_TP_INT_CAUSE 0x4741213#define A_TP_TIMER_SEPARATOR 0x4a41214 1215#define S_DISABLE_PAST_TIMER_INSERTION 01216#define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)1217#define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U)1218 1219#define S_MODULATION_TIMER_SEPARATOR 11220#define M_MODULATION_TIMER_SEPARATOR 0x7fff1221#define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)1222#define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)1223 1224#define S_GLOBAL_TIMER_SEPARATOR 161225#define M_GLOBAL_TIMER_SEPARATOR 0xffff1226#define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)1227#define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)1228 1229#define A_TP_CM_FC_MODE 0x4b01230#define A_TP_PC_CONGESTION_CNTL 0x4b41231#define A_TP_TX_DROP_CONFIG 0x4b81232 1233#define S_ENABLE_TX_DROP 311234#define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)1235#define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U)1236 1237#define S_ENABLE_TX_ERROR 301238#define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)1239#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)1240 1241#define S_DROP_TICKS_CNT 41242#define M_DROP_TICKS_CNT 0x3ffffff1243#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)1244#define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)1245 1246#define S_NUM_PKTS_DROPPED 01247#define M_NUM_PKTS_DROPPED 0xf1248#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)1249#define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)1250 1251#define A_TP_TX_DROP_COUNT 0x4bc1252 1253/* RAT registers */1254#define A_RAT_ROUTE_CONTROL 0x5801255 1256#define S_USE_ROUTE_TABLE 01257#define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)1258#define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U)1259 1260#define S_ENABLE_CSPI 11261#define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)1262#define F_ENABLE_CSPI V_ENABLE_CSPI(1U)1263 1264#define S_ENABLE_PCIX 21265#define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)1266#define F_ENABLE_PCIX V_ENABLE_PCIX(1U)1267 1268#define A_RAT_ROUTE_TABLE_INDEX 0x5841269 1270#define S_ROUTE_TABLE_INDEX 01271#define M_ROUTE_TABLE_INDEX 0xf1272#define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)1273#define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)1274 1275#define A_RAT_ROUTE_TABLE_DATA 0x5881276#define A_RAT_NO_ROUTE 0x58c1277 1278#define S_CPL_OPCODE 01279#define M_CPL_OPCODE 0xff1280#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)1281#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)1282 1283#define A_RAT_INTR_ENABLE 0x5901284 1285#define S_ZEROROUTEERROR 01286#define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)1287#define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U)1288 1289#define S_CSPIFRAMINGERROR 11290#define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)1291#define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U)1292 1293#define S_SGEFRAMINGERROR 21294#define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)1295#define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U)1296 1297#define S_TPFRAMINGERROR 31298#define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)1299#define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U)1300 1301#define A_RAT_INTR_CAUSE 0x5941302 1303/* CSPI registers */1304#define A_CSPI_RX_AE_WM 0x8101305#define A_CSPI_RX_AF_WM 0x8141306#define A_CSPI_CALENDAR_LEN 0x8181307 1308#define S_CALENDARLENGTH 01309#define M_CALENDARLENGTH 0xffff1310#define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)1311#define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)1312 1313#define A_CSPI_FIFO_STATUS_ENABLE 0x8201314 1315#define S_FIFOSTATUSENABLE 01316#define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)1317#define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U)1318 1319#define A_CSPI_MAXBURST1_MAXBURST2 0x8281320 1321#define S_MAXBURST1 01322#define M_MAXBURST1 0xffff1323#define V_MAXBURST1(x) ((x) << S_MAXBURST1)1324#define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)1325 1326#define S_MAXBURST2 161327#define M_MAXBURST2 0xffff1328#define V_MAXBURST2(x) ((x) << S_MAXBURST2)1329#define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)1330 1331#define A_CSPI_TRAIN 0x82c1332 1333#define S_CSPI_TRAIN_ALPHA 01334#define M_CSPI_TRAIN_ALPHA 0xffff1335#define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)1336#define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)1337 1338#define S_CSPI_TRAIN_DATA_MAXT 161339#define M_CSPI_TRAIN_DATA_MAXT 0xffff1340#define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)1341#define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)1342 1343#define A_CSPI_INTR_STATUS 0x8481344 1345#define S_DIP4ERR 01346#define V_DIP4ERR(x) ((x) << S_DIP4ERR)1347#define F_DIP4ERR V_DIP4ERR(1U)1348 1349#define S_RXDROP 11350#define V_RXDROP(x) ((x) << S_RXDROP)1351#define F_RXDROP V_RXDROP(1U)1352 1353#define S_TXDROP 21354#define V_TXDROP(x) ((x) << S_TXDROP)1355#define F_TXDROP V_TXDROP(1U)1356 1357#define S_RXOVERFLOW 31358#define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)1359#define F_RXOVERFLOW V_RXOVERFLOW(1U)1360 1361#define S_RAMPARITYERR 41362#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)1363#define F_RAMPARITYERR V_RAMPARITYERR(1U)1364 1365#define A_CSPI_INTR_ENABLE 0x84c1366 1367/* ESPI registers */1368#define A_ESPI_SCH_TOKEN0 0x8801369 1370#define S_SCHTOKEN0 01371#define M_SCHTOKEN0 0xffff1372#define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)1373#define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)1374 1375#define A_ESPI_SCH_TOKEN1 0x8841376 1377#define S_SCHTOKEN1 01378#define M_SCHTOKEN1 0xffff1379#define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)1380#define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)1381 1382#define A_ESPI_SCH_TOKEN2 0x8881383 1384#define S_SCHTOKEN2 01385#define M_SCHTOKEN2 0xffff1386#define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)1387#define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)1388 1389#define A_ESPI_SCH_TOKEN3 0x88c1390 1391#define S_SCHTOKEN3 01392#define M_SCHTOKEN3 0xffff1393#define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)1394#define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)1395 1396#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x8901397 1398#define S_ALMOSTEMPTY 01399#define M_ALMOSTEMPTY 0xffff1400#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)1401#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)1402 1403#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x8941404 1405#define S_ALMOSTFULL 01406#define M_ALMOSTFULL 0xffff1407#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)1408#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)1409 1410#define A_ESPI_CALENDAR_LENGTH 0x8981411#define A_PORT_CONFIG 0x89c1412 1413#define S_RX_NPORTS 01414#define M_RX_NPORTS 0xff1415#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)1416#define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)1417 1418#define S_TX_NPORTS 81419#define M_TX_NPORTS 0xff1420#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)1421#define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)1422 1423#define A_ESPI_FIFO_STATUS_ENABLE 0x8a01424 1425#define S_RXSTATUSENABLE 01426#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)1427#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)1428 1429#define S_TXDROPENABLE 11430#define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)1431#define F_TXDROPENABLE V_TXDROPENABLE(1U)1432 1433#define S_RXENDIANMODE 21434#define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)1435#define F_RXENDIANMODE V_RXENDIANMODE(1U)1436 1437#define S_TXENDIANMODE 31438#define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE)1439#define F_TXENDIANMODE V_TXENDIANMODE(1U)1440 1441#define S_INTEL1010MODE 41442#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)1443#define F_INTEL1010MODE V_INTEL1010MODE(1U)1444 1445#define A_ESPI_MAXBURST1_MAXBURST2 0x8a81446#define A_ESPI_TRAIN 0x8ac1447 1448#define S_MAXTRAINALPHA 01449#define M_MAXTRAINALPHA 0xffff1450#define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA)1451#define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA)1452 1453#define S_MAXTRAINDATA 161454#define M_MAXTRAINDATA 0xffff1455#define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA)1456#define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA)1457 1458#define A_RAM_STATUS 0x8b01459 1460#define S_RXFIFOPARITYERROR 01461#define M_RXFIFOPARITYERROR 0x3ff1462#define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR)1463#define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR)1464 1465#define S_TXFIFOPARITYERROR 101466#define M_TXFIFOPARITYERROR 0x3ff1467#define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR)1468#define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR)1469 1470#define S_RXFIFOOVERFLOW 201471#define M_RXFIFOOVERFLOW 0x3ff1472#define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)1473#define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW)1474 1475#define A_TX_DROP_COUNT0 0x8b41476 1477#define S_TXPORT0DROPCNT 01478#define M_TXPORT0DROPCNT 0xffff1479#define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT)1480#define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT)1481 1482#define S_TXPORT1DROPCNT 161483#define M_TXPORT1DROPCNT 0xffff1484#define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT)1485#define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT)1486 1487#define A_TX_DROP_COUNT1 0x8b81488 1489#define S_TXPORT2DROPCNT 01490#define M_TXPORT2DROPCNT 0xffff1491#define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT)1492#define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT)1493 1494#define S_TXPORT3DROPCNT 161495#define M_TXPORT3DROPCNT 0xffff1496#define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT)1497#define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT)1498 1499#define A_RX_DROP_COUNT0 0x8bc1500 1501#define S_RXPORT0DROPCNT 01502#define M_RXPORT0DROPCNT 0xffff1503#define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT)1504#define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT)1505 1506#define S_RXPORT1DROPCNT 161507#define M_RXPORT1DROPCNT 0xffff1508#define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT)1509#define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT)1510 1511#define A_RX_DROP_COUNT1 0x8c01512 1513#define S_RXPORT2DROPCNT 01514#define M_RXPORT2DROPCNT 0xffff1515#define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT)1516#define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT)1517 1518#define S_RXPORT3DROPCNT 161519#define M_RXPORT3DROPCNT 0xffff1520#define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT)1521#define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT)1522 1523#define A_DIP4_ERROR_COUNT 0x8c41524 1525#define S_DIP4ERRORCNT 01526#define M_DIP4ERRORCNT 0xfff1527#define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT)1528#define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT)1529 1530#define S_DIP4ERRORCNTSHADOW 121531#define M_DIP4ERRORCNTSHADOW 0xfff1532#define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW)1533#define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW)1534 1535#define S_TRICN_RX_TRAIN_ERR 241536#define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR)1537#define F_TRICN_RX_TRAIN_ERR V_TRICN_RX_TRAIN_ERR(1U)1538 1539#define S_TRICN_RX_TRAINING 251540#define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING)1541#define F_TRICN_RX_TRAINING V_TRICN_RX_TRAINING(1U)1542 1543#define S_TRICN_RX_TRAIN_OK 261544#define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK)1545#define F_TRICN_RX_TRAIN_OK V_TRICN_RX_TRAIN_OK(1U)1546 1547#define A_ESPI_INTR_STATUS 0x8c81548 1549#define S_DIP2PARITYERR 51550#define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)1551#define F_DIP2PARITYERR V_DIP2PARITYERR(1U)1552 1553#define A_ESPI_INTR_ENABLE 0x8cc1554#define A_RX_DROP_THRESHOLD 0x8d01555#define A_ESPI_RX_RESET 0x8ec1556 1557#define S_ESPI_RX_LNK_RST 01558#define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST)1559#define F_ESPI_RX_LNK_RST V_ESPI_RX_LNK_RST(1U)1560 1561#define S_ESPI_RX_CORE_RST 11562#define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST)1563#define F_ESPI_RX_CORE_RST V_ESPI_RX_CORE_RST(1U)1564 1565#define S_RX_CLK_STATUS 21566#define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS)1567#define F_RX_CLK_STATUS V_RX_CLK_STATUS(1U)1568 1569#define A_ESPI_MISC_CONTROL 0x8f01570 1571#define S_OUT_OF_SYNC_COUNT 01572#define M_OUT_OF_SYNC_COUNT 0xf1573#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)1574#define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT)1575 1576#define S_DIP2_COUNT_MODE_ENABLE 41577#define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE)1578#define F_DIP2_COUNT_MODE_ENABLE V_DIP2_COUNT_MODE_ENABLE(1U)1579 1580#define S_DIP2_PARITY_ERR_THRES 51581#define M_DIP2_PARITY_ERR_THRES 0xf1582#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)1583#define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES)1584 1585#define S_DIP4_THRES 91586#define M_DIP4_THRES 0xfff1587#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)1588#define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES)1589 1590#define S_DIP4_THRES_ENABLE 211591#define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE)1592#define F_DIP4_THRES_ENABLE V_DIP4_THRES_ENABLE(1U)1593 1594#define S_FORCE_DISABLE_STATUS 221595#define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS)1596#define F_FORCE_DISABLE_STATUS V_FORCE_DISABLE_STATUS(1U)1597 1598#define S_DYNAMIC_DESKEW 231599#define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW)1600#define F_DYNAMIC_DESKEW V_DYNAMIC_DESKEW(1U)1601 1602#define S_MONITORED_PORT_NUM 251603#define M_MONITORED_PORT_NUM 0x31604#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)1605#define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM)1606 1607#define S_MONITORED_DIRECTION 271608#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)1609#define F_MONITORED_DIRECTION V_MONITORED_DIRECTION(1U)1610 1611#define S_MONITORED_INTERFACE 281612#define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)1613#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U)1614 1615#define A_ESPI_DIP2_ERR_COUNT 0x8f41616 1617#define S_DIP2_ERR_CNT 01618#define M_DIP2_ERR_CNT 0xf1619#define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT)1620#define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT)1621 1622#define A_ESPI_CMD_ADDR 0x8f81623 1624#define S_WRITE_DATA 01625#define M_WRITE_DATA 0xff1626#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)1627#define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA)1628 1629#define S_REGISTER_OFFSET 81630#define M_REGISTER_OFFSET 0xf1631#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)1632#define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET)1633 1634#define S_CHANNEL_ADDR 121635#define M_CHANNEL_ADDR 0xf1636#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)1637#define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR)1638 1639#define S_MODULE_ADDR 161640#define M_MODULE_ADDR 0x31641#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)1642#define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR)1643 1644#define S_BUNDLE_ADDR 201645#define M_BUNDLE_ADDR 0x31646#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)1647#define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR)1648 1649#define S_SPI4_COMMAND 241650#define M_SPI4_COMMAND 0xff1651#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)1652#define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND)1653 1654#define A_ESPI_GOSTAT 0x8fc1655 1656#define S_READ_DATA 01657#define M_READ_DATA 0xff1658#define V_READ_DATA(x) ((x) << S_READ_DATA)1659#define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA)1660 1661#define S_ESPI_CMD_BUSY 81662#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)1663#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U)1664 1665#define S_ERROR_ACK 91666#define V_ERROR_ACK(x) ((x) << S_ERROR_ACK)1667#define F_ERROR_ACK V_ERROR_ACK(1U)1668 1669#define S_UNMAPPED_ERR 101670#define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR)1671#define F_UNMAPPED_ERR V_UNMAPPED_ERR(1U)1672 1673#define S_TRANSACTION_TIMER 161674#define M_TRANSACTION_TIMER 0xff1675#define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER)1676#define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER)1677 1678 1679/* ULP registers */1680#define A_ULP_ULIMIT 0x9801681#define A_ULP_TAGMASK 0x9841682#define A_ULP_HREG_INDEX 0x9881683#define A_ULP_HREG_DATA 0x98c1684#define A_ULP_INT_ENABLE 0x9901685#define A_ULP_INT_CAUSE 0x9941686 1687#define S_HREG_PAR_ERR 01688#define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR)1689#define F_HREG_PAR_ERR V_HREG_PAR_ERR(1U)1690 1691#define S_EGRS_DATA_PAR_ERR 11692#define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR)1693#define F_EGRS_DATA_PAR_ERR V_EGRS_DATA_PAR_ERR(1U)1694 1695#define S_INGRS_DATA_PAR_ERR 21696#define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR)1697#define F_INGRS_DATA_PAR_ERR V_INGRS_DATA_PAR_ERR(1U)1698 1699#define S_PM_INTR 31700#define V_PM_INTR(x) ((x) << S_PM_INTR)1701#define F_PM_INTR V_PM_INTR(1U)1702 1703#define S_PM_E2C_SYNC_ERR 41704#define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR)1705#define F_PM_E2C_SYNC_ERR V_PM_E2C_SYNC_ERR(1U)1706 1707#define S_PM_C2E_SYNC_ERR 51708#define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR)1709#define F_PM_C2E_SYNC_ERR V_PM_C2E_SYNC_ERR(1U)1710 1711#define S_PM_E2C_EMPTY_ERR 61712#define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR)1713#define F_PM_E2C_EMPTY_ERR V_PM_E2C_EMPTY_ERR(1U)1714 1715#define S_PM_C2E_EMPTY_ERR 71716#define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR)1717#define F_PM_C2E_EMPTY_ERR V_PM_C2E_EMPTY_ERR(1U)1718 1719#define S_PM_PAR_ERR 81720#define M_PM_PAR_ERR 0xffff1721#define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR)1722#define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR)1723 1724#define S_PM_E2C_WRT_FULL 241725#define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL)1726#define F_PM_E2C_WRT_FULL V_PM_E2C_WRT_FULL(1U)1727 1728#define S_PM_C2E_WRT_FULL 251729#define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL)1730#define F_PM_C2E_WRT_FULL V_PM_C2E_WRT_FULL(1U)1731 1732#define A_ULP_PIO_CTRL 0x9981733 1734/* PL registers */1735#define A_PL_ENABLE 0xa001736 1737#define S_PL_INTR_SGE_ERR 01738#define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)1739#define F_PL_INTR_SGE_ERR V_PL_INTR_SGE_ERR(1U)1740 1741#define S_PL_INTR_SGE_DATA 11742#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)1743#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U)1744 1745#define S_PL_INTR_MC3 21746#define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3)1747#define F_PL_INTR_MC3 V_PL_INTR_MC3(1U)1748 1749#define S_PL_INTR_MC4 31750#define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4)1751#define F_PL_INTR_MC4 V_PL_INTR_MC4(1U)1752 1753#define S_PL_INTR_MC5 41754#define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5)1755#define F_PL_INTR_MC5 V_PL_INTR_MC5(1U)1756 1757#define S_PL_INTR_RAT 51758#define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT)1759#define F_PL_INTR_RAT V_PL_INTR_RAT(1U)1760 1761#define S_PL_INTR_TP 61762#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)1763#define F_PL_INTR_TP V_PL_INTR_TP(1U)1764 1765#define S_PL_INTR_ULP 71766#define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP)1767#define F_PL_INTR_ULP V_PL_INTR_ULP(1U)1768 1769#define S_PL_INTR_ESPI 81770#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)1771#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U)1772 1773#define S_PL_INTR_CSPI 91774#define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI)1775#define F_PL_INTR_CSPI V_PL_INTR_CSPI(1U)1776 1777#define S_PL_INTR_PCIX 101778#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)1779#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U)1780 1781#define S_PL_INTR_EXT 111782#define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)1783#define F_PL_INTR_EXT V_PL_INTR_EXT(1U)1784 1785#define A_PL_CAUSE 0xa041786 1787/* MC5 registers */1788#define A_MC5_CONFIG 0xc041789 1790#define S_MODE 01791#define V_MODE(x) ((x) << S_MODE)1792#define F_MODE V_MODE(1U)1793 1794#define S_TCAM_RESET 11795#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)1796#define F_TCAM_RESET V_TCAM_RESET(1U)1797 1798#define S_TCAM_READY 21799#define V_TCAM_READY(x) ((x) << S_TCAM_READY)1800#define F_TCAM_READY V_TCAM_READY(1U)1801 1802#define S_DBGI_ENABLE 41803#define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE)1804#define F_DBGI_ENABLE V_DBGI_ENABLE(1U)1805 1806#define S_M_BUS_ENABLE 51807#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)1808#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U)1809 1810#define S_PARITY_ENABLE 61811#define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE)1812#define F_PARITY_ENABLE V_PARITY_ENABLE(1U)1813 1814#define S_SYN_ISSUE_MODE 71815#define M_SYN_ISSUE_MODE 0x31816#define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE)1817#define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE)1818 1819#define S_BUILD 161820#define V_BUILD(x) ((x) << S_BUILD)1821#define F_BUILD V_BUILD(1U)1822 1823#define S_COMPRESSION_ENABLE 171824#define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE)1825#define F_COMPRESSION_ENABLE V_COMPRESSION_ENABLE(1U)1826 1827#define S_NUM_LIP 181828#define M_NUM_LIP 0x3f1829#define V_NUM_LIP(x) ((x) << S_NUM_LIP)1830#define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP)1831 1832#define S_TCAM_PART_CNT 241833#define M_TCAM_PART_CNT 0x31834#define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT)1835#define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT)1836 1837#define S_TCAM_PART_TYPE 261838#define M_TCAM_PART_TYPE 0x31839#define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE)1840#define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE)1841 1842#define S_TCAM_PART_SIZE 281843#define M_TCAM_PART_SIZE 0x31844#define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE)1845#define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE)1846 1847#define S_TCAM_PART_TYPE_HI 301848#define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI)1849#define F_TCAM_PART_TYPE_HI V_TCAM_PART_TYPE_HI(1U)1850 1851#define A_MC5_SIZE 0xc081852 1853#define S_SIZE 01854#define M_SIZE 0x3fffff1855#define V_SIZE(x) ((x) << S_SIZE)1856#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)1857 1858#define A_MC5_ROUTING_TABLE_INDEX 0xc0c1859 1860#define S_START_OF_ROUTING_TABLE 01861#define M_START_OF_ROUTING_TABLE 0x3fffff1862#define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE)1863#define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE)1864 1865#define A_MC5_SERVER_INDEX 0xc141866 1867#define S_START_OF_SERVER_INDEX 01868#define M_START_OF_SERVER_INDEX 0x3fffff1869#define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX)1870#define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX)1871 1872#define A_MC5_LIP_RAM_ADDR 0xc181873 1874#define S_LOCAL_IP_RAM_ADDR 01875#define M_LOCAL_IP_RAM_ADDR 0x3f1876#define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR)1877#define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR)1878 1879#define S_RAM_WRITE_ENABLE 81880#define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE)1881#define F_RAM_WRITE_ENABLE V_RAM_WRITE_ENABLE(1U)1882 1883#define A_MC5_LIP_RAM_DATA 0xc1c1884#define A_MC5_RSP_LATENCY 0xc201885 1886#define S_SEARCH_RESPONSE_LATENCY 01887#define M_SEARCH_RESPONSE_LATENCY 0x1f1888#define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY)1889#define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)1890 1891#define S_LEARN_RESPONSE_LATENCY 81892#define M_LEARN_RESPONSE_LATENCY 0x1f1893#define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY)1894#define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY)1895 1896#define A_MC5_PARITY_LATENCY 0xc241897 1898#define S_SRCHLAT 01899#define M_SRCHLAT 0x1f1900#define V_SRCHLAT(x) ((x) << S_SRCHLAT)1901#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)1902 1903#define S_PARLAT 81904#define M_PARLAT 0x1f1905#define V_PARLAT(x) ((x) << S_PARLAT)1906#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)1907 1908#define A_MC5_WR_LRN_VERIFY 0xc281909 1910#define S_POVEREN 01911#define V_POVEREN(x) ((x) << S_POVEREN)1912#define F_POVEREN V_POVEREN(1U)1913 1914#define S_LRNVEREN 11915#define V_LRNVEREN(x) ((x) << S_LRNVEREN)1916#define F_LRNVEREN V_LRNVEREN(1U)1917 1918#define S_VWVEREN 21919#define V_VWVEREN(x) ((x) << S_VWVEREN)1920#define F_VWVEREN V_VWVEREN(1U)1921 1922#define A_MC5_PART_ID_INDEX 0xc2c1923 1924#define S_IDINDEX 01925#define M_IDINDEX 0xf1926#define V_IDINDEX(x) ((x) << S_IDINDEX)1927#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)1928 1929#define A_MC5_RESET_MAX 0xc301930 1931#define S_RSTMAX 01932#define M_RSTMAX 0x1ff1933#define V_RSTMAX(x) ((x) << S_RSTMAX)1934#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)1935 1936#define A_MC5_INT_ENABLE 0xc401937 1938#define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 01939#define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR)1940#define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U)1941 1942#define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR 11943#define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR)1944#define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U)1945 1946#define S_MC5_INT_HIT_IN_RT_REGION_ERR 21947#define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR)1948#define F_MC5_INT_HIT_IN_RT_REGION_ERR V_MC5_INT_HIT_IN_RT_REGION_ERR(1U)1949 1950#define S_MC5_INT_MISS_ERR 31951#define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR)1952#define F_MC5_INT_MISS_ERR V_MC5_INT_MISS_ERR(1U)1953 1954#define S_MC5_INT_LIP0_ERR 41955#define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR)1956#define F_MC5_INT_LIP0_ERR V_MC5_INT_LIP0_ERR(1U)1957 1958#define S_MC5_INT_LIP_MISS_ERR 51959#define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR)1960#define F_MC5_INT_LIP_MISS_ERR V_MC5_INT_LIP_MISS_ERR(1U)1961 1962#define S_MC5_INT_PARITY_ERR 61963#define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR)1964#define F_MC5_INT_PARITY_ERR V_MC5_INT_PARITY_ERR(1U)1965 1966#define S_MC5_INT_ACTIVE_REGION_FULL 71967#define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL)1968#define F_MC5_INT_ACTIVE_REGION_FULL V_MC5_INT_ACTIVE_REGION_FULL(1U)1969 1970#define S_MC5_INT_NFA_SRCH_ERR 81971#define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR)1972#define F_MC5_INT_NFA_SRCH_ERR V_MC5_INT_NFA_SRCH_ERR(1U)1973 1974#define S_MC5_INT_SYN_COOKIE 91975#define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE)1976#define F_MC5_INT_SYN_COOKIE V_MC5_INT_SYN_COOKIE(1U)1977 1978#define S_MC5_INT_SYN_COOKIE_BAD 101979#define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD)1980#define F_MC5_INT_SYN_COOKIE_BAD V_MC5_INT_SYN_COOKIE_BAD(1U)1981 1982#define S_MC5_INT_SYN_COOKIE_OFF 111983#define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF)1984#define F_MC5_INT_SYN_COOKIE_OFF V_MC5_INT_SYN_COOKIE_OFF(1U)1985 1986#define S_MC5_INT_UNKNOWN_CMD 151987#define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD)1988#define F_MC5_INT_UNKNOWN_CMD V_MC5_INT_UNKNOWN_CMD(1U)1989 1990#define S_MC5_INT_REQUESTQ_PARITY_ERR 161991#define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR)1992#define F_MC5_INT_REQUESTQ_PARITY_ERR V_MC5_INT_REQUESTQ_PARITY_ERR(1U)1993 1994#define S_MC5_INT_DISPATCHQ_PARITY_ERR 171995#define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR)1996#define F_MC5_INT_DISPATCHQ_PARITY_ERR V_MC5_INT_DISPATCHQ_PARITY_ERR(1U)1997 1998#define S_MC5_INT_DEL_ACT_EMPTY 181999#define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY)2000#define F_MC5_INT_DEL_ACT_EMPTY V_MC5_INT_DEL_ACT_EMPTY(1U)2001 2002#define A_MC5_INT_CAUSE 0xc442003#define A_MC5_INT_TID 0xc482004#define A_MC5_INT_PTID 0xc4c2005#define A_MC5_DBGI_CONFIG 0xc742006#define A_MC5_DBGI_REQ_CMD 0xc782007 2008#define S_CMDMODE 02009#define M_CMDMODE 0x72010#define V_CMDMODE(x) ((x) << S_CMDMODE)2011#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)2012 2013#define S_SADRSEL 42014#define V_SADRSEL(x) ((x) << S_SADRSEL)2015#define F_SADRSEL V_SADRSEL(1U)2016 2017#define S_WRITE_BURST_SIZE 222018#define M_WRITE_BURST_SIZE 0x3ff2019#define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE)2020#define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE)2021 2022#define A_MC5_DBGI_REQ_ADDR0 0xc7c2023#define A_MC5_DBGI_REQ_ADDR1 0xc802024#define A_MC5_DBGI_REQ_ADDR2 0xc842025#define A_MC5_DBGI_REQ_DATA0 0xc882026#define A_MC5_DBGI_REQ_DATA1 0xc8c2027#define A_MC5_DBGI_REQ_DATA2 0xc902028#define A_MC5_DBGI_REQ_DATA3 0xc942029#define A_MC5_DBGI_REQ_DATA4 0xc982030#define A_MC5_DBGI_REQ_MASK0 0xc9c2031#define A_MC5_DBGI_REQ_MASK1 0xca02032#define A_MC5_DBGI_REQ_MASK2 0xca42033#define A_MC5_DBGI_REQ_MASK3 0xca82034#define A_MC5_DBGI_REQ_MASK4 0xcac2035#define A_MC5_DBGI_RSP_STATUS 0xcb02036 2037#define S_DBGI_RSP_VALID 02038#define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID)2039#define F_DBGI_RSP_VALID V_DBGI_RSP_VALID(1U)2040 2041#define S_DBGI_RSP_HIT 12042#define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT)2043#define F_DBGI_RSP_HIT V_DBGI_RSP_HIT(1U)2044 2045#define S_DBGI_RSP_ERR 22046#define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR)2047#define F_DBGI_RSP_ERR V_DBGI_RSP_ERR(1U)2048 2049#define S_DBGI_RSP_ERR_REASON 82050#define M_DBGI_RSP_ERR_REASON 0x72051#define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON)2052#define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON)2053 2054#define A_MC5_DBGI_RSP_DATA0 0xcb42055#define A_MC5_DBGI_RSP_DATA1 0xcb82056#define A_MC5_DBGI_RSP_DATA2 0xcbc2057#define A_MC5_DBGI_RSP_DATA3 0xcc02058#define A_MC5_DBGI_RSP_DATA4 0xcc42059#define A_MC5_DBGI_RSP_LAST_CMD 0xcc82060#define A_MC5_POPEN_DATA_WR_CMD 0xccc2061#define A_MC5_POPEN_MASK_WR_CMD 0xcd02062#define A_MC5_AOPEN_SRCH_CMD 0xcd42063#define A_MC5_AOPEN_LRN_CMD 0xcd82064#define A_MC5_SYN_SRCH_CMD 0xcdc2065#define A_MC5_SYN_LRN_CMD 0xce02066#define A_MC5_ACK_SRCH_CMD 0xce42067#define A_MC5_ACK_LRN_CMD 0xce82068#define A_MC5_ILOOKUP_CMD 0xcec2069#define A_MC5_ELOOKUP_CMD 0xcf02070#define A_MC5_DATA_WRITE_CMD 0xcf42071#define A_MC5_DATA_READ_CMD 0xcf82072#define A_MC5_MASK_WRITE_CMD 0xcfc2073 2074/* PCICFG registers */2075#define A_PCICFG_PM_CSR 0x442076#define A_PCICFG_VPD_ADDR 0x4a2077 2078#define S_VPD_ADDR 02079#define M_VPD_ADDR 0x7fff2080#define V_VPD_ADDR(x) ((x) << S_VPD_ADDR)2081#define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR)2082 2083#define S_VPD_OP_FLAG 152084#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)2085#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U)2086 2087#define A_PCICFG_VPD_DATA 0x4c2088#define A_PCICFG_PCIX_CMD 0x602089#define A_PCICFG_INTR_ENABLE 0xf42090 2091#define S_MASTER_PARITY_ERR 02092#define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR)2093#define F_MASTER_PARITY_ERR V_MASTER_PARITY_ERR(1U)2094 2095#define S_SIG_TARGET_ABORT 12096#define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT)2097#define F_SIG_TARGET_ABORT V_SIG_TARGET_ABORT(1U)2098 2099#define S_RCV_TARGET_ABORT 22100#define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT)2101#define F_RCV_TARGET_ABORT V_RCV_TARGET_ABORT(1U)2102 2103#define S_RCV_MASTER_ABORT 32104#define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT)2105#define F_RCV_MASTER_ABORT V_RCV_MASTER_ABORT(1U)2106 2107#define S_SIG_SYS_ERR 42108#define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR)2109#define F_SIG_SYS_ERR V_SIG_SYS_ERR(1U)2110 2111#define S_DET_PARITY_ERR 52112#define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR)2113#define F_DET_PARITY_ERR V_DET_PARITY_ERR(1U)2114 2115#define S_PIO_PARITY_ERR 62116#define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR)2117#define F_PIO_PARITY_ERR V_PIO_PARITY_ERR(1U)2118 2119#define S_WF_PARITY_ERR 72120#define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR)2121#define F_WF_PARITY_ERR V_WF_PARITY_ERR(1U)2122 2123#define S_RF_PARITY_ERR 82124#define M_RF_PARITY_ERR 0x32125#define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR)2126#define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR)2127 2128#define S_CF_PARITY_ERR 102129#define M_CF_PARITY_ERR 0x32130#define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR)2131#define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR)2132 2133#define A_PCICFG_INTR_CAUSE 0xf82134#define A_PCICFG_MODE 0xfc2135 2136#define S_PCI_MODE_64BIT 02137#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)2138#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U)2139 2140#define S_PCI_MODE_66MHZ 12141#define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ)2142#define F_PCI_MODE_66MHZ V_PCI_MODE_66MHZ(1U)2143 2144#define S_PCI_MODE_PCIX_INITPAT 22145#define M_PCI_MODE_PCIX_INITPAT 0x72146#define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT)2147#define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT)2148 2149#define S_PCI_MODE_PCIX 52150#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)2151#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U)2152 2153#define S_PCI_MODE_CLK 62154#define M_PCI_MODE_CLK 0x32155#define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK)2156#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)2157 2158#endif /* _CXGB_REGS_H_ */2159