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1/* SPDX-License-Identifier: GPL-2.0-only */2/*****************************************************************************3 * *4 * File: suni1x10gexp_regs.h *5 * $Revision: 1.9 $ *6 * $Date: 2005/06/22 00:17:04 $ *7 * Description: *8 * PMC/SIERRA (pm3393) MAC-PHY functionality. *9 * part of the Chelsio 10Gb Ethernet Driver. *10 * *11 * *12 * http://www.chelsio.com *13 * *14 * Maintainers: maintainers@chelsio.com *15 * *16 * Authors: PMC/SIERRA *17 * *18 * History: *19 * *20 ****************************************************************************/21 22#ifndef _CXGB_SUNI1x10GEXP_REGS_H_23#define _CXGB_SUNI1x10GEXP_REGS_H_24 25/*26** Space allocated for each Exact Match Filter27** There are 8 filter configurations28*/29#define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x000330 31#define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )32 33/*34** Space allocated for VLAN-Id Filter35** There are 8 filter configurations36*/37#define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x000138 39#define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )40 41/*42** Space allocated for each MSTAT Counter43*/44#define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x000445 46#define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )47 48 49/******************************************************************************/50/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/51/******************************************************************************/52/* Refer to the Register Bit Masks bellow for the naming of each register and */53/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */54/******************************************************************************/55 56 57#define SUNI1x10GEXP_REG_IDENTIFICATION 0x000058#define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x000159#define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x000260#define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x000361#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x000462#define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x000563 64#define SUNI1x10GEXP_REG_MDIO_COMMAND 0x000665#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x000766#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x000867#define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x000968#define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A69#define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B70 71#define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C72#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D73#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E74#define SUNI1x10GEXP_REG_FREE 0x000F75 76#define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x001077#define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x001178 79#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x010080#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x010181#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x010282#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x010383#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x010484#define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x010785 86#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x204087#define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x204188#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x204289#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x204390#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x204591#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x204692#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x204793#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x204894#define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x204995#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))96#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))97#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))98#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId))99#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A100#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B101#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C102#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D103#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E104#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F105#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050106#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051107#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052108#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053109#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054110#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055111#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056112#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057113#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058114#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059115#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A116#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B117#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C118#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D119#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E120#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F121#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060122#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061123#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062124#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063125#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064126#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065127#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066128#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067129#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068130#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069131#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A132#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B133#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C134#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D135#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E136#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F137#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070138 139#define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081140#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084141#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085142#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086143#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087144#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088145#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089146#define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A147#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B148#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C149#define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092150 151#define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0152#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1153#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2154#define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3155#define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4156#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5157#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7158#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8159#define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9160#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA161#define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB162#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC163#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD164#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE165#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF166#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0167#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1168#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2169#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3170#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4171#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5172#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6173#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7174 175#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100176#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101177#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102178#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103179#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104180#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105181#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106182#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107183#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108184#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109185#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A186#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B187#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C188#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))189#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))190#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))191#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110192#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111193#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112194#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113195#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114196#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115197#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116198#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117199#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118200#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119201#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A202#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B203#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C204#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D205#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E206#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F207#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120208#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121209#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122210#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123211#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124212#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125213#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126214#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127215#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128216#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129217#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A218#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B219#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C220#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D221#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E222#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F223#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130224#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131225#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132226#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133227#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134228#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135229#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136230#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137231#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138232#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139233#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A234#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B235#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C236#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D237#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E238#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F239#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140240#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141241#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142242#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143243#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144244#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145245#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146246#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147247#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148248#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149249#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A250#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B251#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C252#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D253#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E254#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F255#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150256#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151257#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152258#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153259#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154260#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155261#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156262#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157263#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158264#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159265#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A266#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B267#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C268#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D269#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E270#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F271#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160272#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161273#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162274#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163275#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164276#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165277#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166278#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167279#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168280#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169281#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A282#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B283#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C284#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D285#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E286#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F287#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170288#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171289#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172290#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173291#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174292#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175293#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176294#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177295#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178296#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179297#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a298#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b299#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c300#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d301#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e302#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f303#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180304#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181305#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182306#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183307#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184308#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185309#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186310#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187311#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188312#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189313#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A314#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B315#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C316#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D317#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E318#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F319#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190320#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191321#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192322#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193323#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194324#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195325#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196326#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197327#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198328#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199329#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A330#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B331#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C332#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D333#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E334#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F335#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0336#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1337#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2338#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3339#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4340#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5341#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6342#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7343#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8344#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9345#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA346#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB347#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC348#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD349#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE350#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF351#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0352#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1353#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2354#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3355#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4356#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5357#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6358#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7359#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8360#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9361#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA362#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB363#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC364#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD365#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE366#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF367#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0368#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1369#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2370#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3371#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4372#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5373#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6374#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7375#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8376#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9377#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA378#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB379#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC380#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD381#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE382#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF383#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0384#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1385#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2386#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3387#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4388#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5389#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6390#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7391#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8392#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9393#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA394#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB395#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC396#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD397#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE398#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF399#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0400#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1401#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2402#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3403#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4404#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5405#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6406#define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51407 408#define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200409#define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201410#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209411#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A412#define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D413#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E414#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F415#define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210416#define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211417 418#define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240419#define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241420#define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242421#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243422#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244423#define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245424 425#define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280426#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282427#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283428#define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284429 430#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300431#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301432#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302433#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303434#define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304435#define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305436 437#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040438#define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041439#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042440#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043441#define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044442#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045443#define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046444#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047445#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048446#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049447#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D448#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E449#define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051450#define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052451 452#define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080453#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084454#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085455#define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086456 457#define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0458#define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1459#define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2460#define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3461#define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4462#define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5463#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6464#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7465#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8466#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9467#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA468#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB469#define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC470#define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD471#define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE472#define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF473#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0474#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1475#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2476#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3477 478 479#define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200480#define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201481#define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202482#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203483#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204484#define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205485#define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206486#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207487#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C488#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D489#define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210490 491#define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280492#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282493#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283494 495 496/*----------------------------------------*/497#define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480498 499/******************************************************************************/500/* -- End register offset definitions -- */501/******************************************************************************/502 503/******************************************************************************/504/** SUNI-1x10GE-XP REGISTER BIT MASKS **/505/******************************************************************************/506 507#define SUNI1x10GEXP_BITMSK_BITS_1 0x00001508#define SUNI1x10GEXP_BITMSK_BITS_2 0x00003509#define SUNI1x10GEXP_BITMSK_BITS_3 0x00007510#define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f511#define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f512#define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f513#define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f514#define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff515#define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff516#define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff517#define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff518#define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff519#define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff520#define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff521#define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff522#define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff523 524#define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15)525#define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14)526#define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13)527#define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12)528#define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11)529#define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10)530#define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9)531#define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8)532#define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7)533#define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)534#define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)535#define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)536#define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)537#define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)538#define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)539 540#define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)541 542 543 544/*----------------------------------------------------------------------------545 * Register 0x0001: S/UNI-1x10GE-XP Product Revision546 * Bit 3-0 REVISION547 *----------------------------------------------------------------------------*/548#define SUNI1x10GEXP_BITMSK_REVISION 0x000F549 550/*----------------------------------------------------------------------------551 * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control552 * Bit 2 XAUI_ARESETB553 * Bit 1 PL4_ARESETB554 * Bit 0 DRESETB555 *----------------------------------------------------------------------------*/556#define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004557#define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002558#define SUNI1x10GEXP_BITMSK_DRESETB 0x0001559 560/*----------------------------------------------------------------------------561 * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control562 * Bit 11 PL4IO_OUTCLKSEL563 * Bit 9 SYSPCSLB564 * Bit 8 LINEPCSLB565 * Bit 7 MSTAT_BYPASS566 * Bit 6 RXXG_BYPASS567 * Bit 5 TXXG_BYPASS568 * Bit 4 SOP_PAD_EN569 * Bit 1 LOS_INV570 * Bit 0 OVERRIDE_LOS571 *----------------------------------------------------------------------------*/572#define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800573#define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200574#define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100575#define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080576#define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040577#define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020578#define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010579#define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002580#define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001581 582/*----------------------------------------------------------------------------583 * Register 0x0004: S/UNI-1x10GE-XP Device Status584 * Bit 9 TOP_SXRA_EXPIRED585 * Bit 8 TOP_MDIO_BUSY586 * Bit 7 TOP_DTRB587 * Bit 6 TOP_EXPIRED588 * Bit 5 TOP_PAUSED589 * Bit 4 TOP_PL4_ID_DOOL590 * Bit 3 TOP_PL4_IS_DOOL591 * Bit 2 TOP_PL4_ID_ROOL592 * Bit 1 TOP_PL4_IS_ROOL593 * Bit 0 TOP_PL4_OUT_ROOL594 *----------------------------------------------------------------------------*/595#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200596#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100597#define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080598#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040599#define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020600#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010601#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008602#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004603#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002604#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001605 606/*----------------------------------------------------------------------------607 * Register 0x0005: Global Performance Update and Clock Monitors608 * Bit 15 TIP609 * Bit 8 XAUI_REF_CLKA610 * Bit 7 RXLANE3CLKA611 * Bit 6 RXLANE2CLKA612 * Bit 5 RXLANE1CLKA613 * Bit 4 RXLANE0CLKA614 * Bit 3 CSUCLKA615 * Bit 2 TDCLKA616 * Bit 1 RSCLKA617 * Bit 0 RDCLKA618 *----------------------------------------------------------------------------*/619#define SUNI1x10GEXP_BITMSK_TIP 0x8000620#define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100621#define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080622#define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040623#define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020624#define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010625#define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008626#define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004627#define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002628#define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001629 630/*----------------------------------------------------------------------------631 * Register 0x0006: MDIO Command632 * Bit 4 MDIO_RDINC633 * Bit 3 MDIO_RSTAT634 * Bit 2 MDIO_LCTLD635 * Bit 1 MDIO_LCTLA636 * Bit 0 MDIO_SPRE637 *----------------------------------------------------------------------------*/638#define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010639#define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008640#define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004641#define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002642#define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001643 644/*----------------------------------------------------------------------------645 * Register 0x0007: MDIO Interrupt Enable646 * Bit 0 MDIO_BUSY_EN647 *----------------------------------------------------------------------------*/648#define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001649 650/*----------------------------------------------------------------------------651 * Register 0x0008: MDIO Interrupt Status652 * Bit 0 MDIO_BUSYI653 *----------------------------------------------------------------------------*/654#define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001655 656/*----------------------------------------------------------------------------657 * Register 0x0009: MMD PHY Address658 * Bit 12-8 MDIO_DEVADR659 * Bit 4-0 MDIO_PRTADR660 *----------------------------------------------------------------------------*/661#define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00662#define SUNI1x10GEXP_BITOFF_MDIO_DEVADR 8663#define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F664#define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0665 666/*----------------------------------------------------------------------------667 * Register 0x000C: OAM Interface Control668 * Bit 6 MDO_OD_ENB669 * Bit 5 MDI_INV670 * Bit 4 MDI_SEL671 * Bit 3 RXOAMEN672 * Bit 2 RXOAMCLKEN673 * Bit 1 TXOAMEN674 * Bit 0 TXOAMCLKEN675 *----------------------------------------------------------------------------*/676#define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040677#define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020678#define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010679#define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008680#define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004681#define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002682#define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001683 684/*----------------------------------------------------------------------------685 * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status686 * Bit 15 TOP_PL4IO_INT687 * Bit 14 TOP_IRAM_INT688 * Bit 13 TOP_ERAM_INT689 * Bit 12 TOP_XAUI_INT690 * Bit 11 TOP_MSTAT_INT691 * Bit 10 TOP_RXXG_INT692 * Bit 9 TOP_TXXG_INT693 * Bit 8 TOP_XRF_INT694 * Bit 7 TOP_XTEF_INT695 * Bit 6 TOP_MDIO_BUSY_INT696 * Bit 5 TOP_RXOAM_INT697 * Bit 4 TOP_TXOAM_INT698 * Bit 3 TOP_IFLX_INT699 * Bit 2 TOP_EFLX_INT700 * Bit 1 TOP_PL4ODP_INT701 * Bit 0 TOP_PL4IDU_INT702 *----------------------------------------------------------------------------*/703#define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000704#define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000705#define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000706#define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000707#define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800708#define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400709#define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200710#define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100711#define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080712#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040713#define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020714#define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010715#define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008716#define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004717#define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002718#define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001719 720/*----------------------------------------------------------------------------721 * Register 0x000E:PM3393 Global interrupt enable722 * Bit 15 TOP_INTE723 *----------------------------------------------------------------------------*/724#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000725 726/*----------------------------------------------------------------------------727 * Register 0x0010: XTEF Miscellaneous Control728 * Bit 7 RF_VAL729 * Bit 6 RF_OVERRIDE730 * Bit 5 LF_VAL731 * Bit 4 LF_OVERRIDE732 *----------------------------------------------------------------------------*/733#define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080734#define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040735#define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020736#define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010737#define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0738 739/*----------------------------------------------------------------------------740 * Register 0x0011: XRF Miscellaneous Control741 * Bit 6-4 EN_IDLE_REP742 *----------------------------------------------------------------------------*/743#define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070744 745/*----------------------------------------------------------------------------746 * Register 0x0100: SERDES 3125 Configuration Register 1747 * Bit 10 RXEQB_3748 * Bit 8 RXEQB_2749 * Bit 6 RXEQB_1750 * Bit 4 RXEQB_0751 *----------------------------------------------------------------------------*/752#define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0753#define SUNI1x10GEXP_BITOFF_RXEQB_3 10754#define SUNI1x10GEXP_BITOFF_RXEQB_2 8755#define SUNI1x10GEXP_BITOFF_RXEQB_1 6756#define SUNI1x10GEXP_BITOFF_RXEQB_0 4757 758/*----------------------------------------------------------------------------759 * Register 0x0101: SERDES 3125 Configuration Register 2760 * Bit 12 YSEL761 * Bit 7 PRE_EMPH_3762 * Bit 6 PRE_EMPH_2763 * Bit 5 PRE_EMPH_1764 * Bit 4 PRE_EMPH_0765 *----------------------------------------------------------------------------*/766#define SUNI1x10GEXP_BITMSK_YSEL 0x1000767#define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0768#define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080769#define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040770#define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020771#define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010772 773/*----------------------------------------------------------------------------774 * Register 0x0102: SERDES 3125 Interrupt Enable Register775 * Bit 3 LASIE776 * Bit 2 SPLL_RAE777 * Bit 1 MPLL_RAE778 * Bit 0 PLL_LOCKE779 *----------------------------------------------------------------------------*/780#define SUNI1x10GEXP_BITMSK_LASIE 0x0008781#define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004782#define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002783#define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001784 785/*----------------------------------------------------------------------------786 * Register 0x0103: SERDES 3125 Interrupt Visibility Register787 * Bit 3 LASIV788 * Bit 2 SPLL_RAV789 * Bit 1 MPLL_RAV790 * Bit 0 PLL_LOCKV791 *----------------------------------------------------------------------------*/792#define SUNI1x10GEXP_BITMSK_LASIV 0x0008793#define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004794#define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002795#define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001796 797/*----------------------------------------------------------------------------798 * Register 0x0104: SERDES 3125 Interrupt Status Register799 * Bit 3 LASII800 * Bit 2 SPLL_RAI801 * Bit 1 MPLL_RAI802 * Bit 0 PLL_LOCKI803 *----------------------------------------------------------------------------*/804#define SUNI1x10GEXP_BITMSK_LASII 0x0008805#define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004806#define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002807#define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001808 809/*----------------------------------------------------------------------------810 * Register 0x0107: SERDES 3125 Test Configuration811 * Bit 12 DUALTX812 * Bit 10 HC_1813 * Bit 9 HC_0814 *----------------------------------------------------------------------------*/815#define SUNI1x10GEXP_BITMSK_DUALTX 0x1000816#define SUNI1x10GEXP_BITMSK_HC 0x0600817#define SUNI1x10GEXP_BITOFF_HC_0 9818 819/*----------------------------------------------------------------------------820 * Register 0x2040: RXXG Configuration 1821 * Bit 15 RXXG_RXEN822 * Bit 14 RXXG_ROCF823 * Bit 13 RXXG_PAD_STRIP824 * Bit 10 RXXG_PUREP825 * Bit 9 RXXG_LONGP826 * Bit 8 RXXG_PARF827 * Bit 7 RXXG_FLCHK828 * Bit 5 RXXG_PASS_CTRL829 * Bit 3 RXXG_CRC_STRIP830 * Bit 2-0 RXXG_MIFG831 *----------------------------------------------------------------------------*/832#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000833#define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000834#define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000835#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400836#define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200837#define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100838#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080839#define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020840#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008841 842/*----------------------------------------------------------------------------843 * Register 0x02041: RXXG Configuration 2844 * Bit 7-0 RXXG_HDRSIZE845 *----------------------------------------------------------------------------*/846#define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF847 848/*----------------------------------------------------------------------------849 * Register 0x2042: RXXG Configuration 3850 * Bit 15 RXXG_MIN_LERRE851 * Bit 14 RXXG_MAX_LERRE852 * Bit 12 RXXG_LINE_ERRE853 * Bit 10 RXXG_RX_OVRE854 * Bit 9 RXXG_ADR_FILTERE855 * Bit 8 RXXG_ERR_FILTERE856 * Bit 5 RXXG_PRMB_ERRE857 *----------------------------------------------------------------------------*/858#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000859#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000860#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000861#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400862#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200863#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100864#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020865 866/*----------------------------------------------------------------------------867 * Register 0x2043: RXXG Interrupt868 * Bit 15 RXXG_MIN_LERRI869 * Bit 14 RXXG_MAX_LERRI870 * Bit 12 RXXG_LINE_ERRI871 * Bit 10 RXXG_RX_OVRI872 * Bit 9 RXXG_ADR_FILTERI873 * Bit 8 RXXG_ERR_FILTERI874 * Bit 5 RXXG_PRMB_ERRE875 *----------------------------------------------------------------------------*/876#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000877#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000878#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000879#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400880#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200881#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100882#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020883 884/*----------------------------------------------------------------------------885 * Register 0x2049: RXXG Receive FIFO Threshold886 * Bit 2-0 RXXG_CUT_THRU887 *----------------------------------------------------------------------------*/888#define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007889#define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0890 891/*----------------------------------------------------------------------------892 * Register 0x2062H - 0x2069: RXXG Exact Match VID893 * Bit 11-0 RXXG_VID_MATCH894 *----------------------------------------------------------------------------*/895#define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF896#define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0897 898/*----------------------------------------------------------------------------899 * Register 0x206EH - 0x206F: RXXG Address Filter Control900 * Bit 3 RXXG_FORWARD_ENABLE901 * Bit 2 RXXG_VLAN_ENABLE902 * Bit 1 RXXG_SRC_ADDR903 * Bit 0 RXXG_MATCH_ENABLE904 *----------------------------------------------------------------------------*/905#define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008906#define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004907#define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002908#define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001909 910/*----------------------------------------------------------------------------911 * Register 0x2070: RXXG Address Filter Control 2912 * Bit 1 RXXG_PMODE913 * Bit 0 RXXG_MHASH_EN914 *----------------------------------------------------------------------------*/915#define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002916#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001917 918/*----------------------------------------------------------------------------919 * Register 0x2081: XRF Control Register 2920 * Bit 6 EN_PKT_GEN921 * Bit 4-2 PATT922 *----------------------------------------------------------------------------*/923#define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040924#define SUNI1x10GEXP_BITMSK_PATT 0x001C925#define SUNI1x10GEXP_BITOFF_PATT 2926 927/*----------------------------------------------------------------------------928 * Register 0x2088: XRF Interrupt Enable929 * Bit 12-9 LANE_HICERE930 * Bit 8-5 HS_SD_LANEE931 * Bit 4 ALIGN_STATUS_ERRE932 * Bit 3-0 LANE_SYNC_STAT_ERRE933 *----------------------------------------------------------------------------*/934#define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00935#define SUNI1x10GEXP_BITOFF_LANE_HICERE 9936#define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0937#define SUNI1x10GEXP_BITOFF_HS_SD_LANEE 5938#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010939#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F940#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0941 942/*----------------------------------------------------------------------------943 * Register 0x2089: XRF Interrupt Status944 * Bit 12-9 LANE_HICERI945 * Bit 8-5 HS_SD_LANEI946 * Bit 4 ALIGN_STATUS_ERRI947 * Bit 3-0 LANE_SYNC_STAT_ERRI948 *----------------------------------------------------------------------------*/949#define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00950#define SUNI1x10GEXP_BITOFF_LANE_HICERI 9951#define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0952#define SUNI1x10GEXP_BITOFF_HS_SD_LANEI 5953#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010954#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F955#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0956 957/*----------------------------------------------------------------------------958 * Register 0x208A: XRF Error Status959 * Bit 8-5 HS_SD_LANE960 * Bit 4 ALIGN_STATUS_ERR961 * Bit 3-0 LANE_SYNC_STAT_ERR962 *----------------------------------------------------------------------------*/963#define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100964#define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080965#define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040966#define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020967#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010968#define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008969#define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004970#define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002971#define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001972 973/*----------------------------------------------------------------------------974 * Register 0x208B: XRF Diagnostic Interrupt Enable975 * Bit 7-4 LANE_OVERRUNE976 * Bit 3-0 LANE_UNDERRUNE977 *----------------------------------------------------------------------------*/978#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0979#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE 4980#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F981#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0982 983/*----------------------------------------------------------------------------984 * Register 0x208C: XRF Diagnostic Interrupt Status985 * Bit 7-4 LANE_OVERRUNI986 * Bit 3-0 LANE_UNDERRUNI987 *----------------------------------------------------------------------------*/988#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0989#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI 4990#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F991#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0992 993/*----------------------------------------------------------------------------994 * Register 0x20C0: RXOAM Configuration995 * Bit 15 RXOAM_BUSY996 * Bit 14-12 RXOAM_F2_SEL997 * Bit 10-8 RXOAM_F1_SEL998 * Bit 7-6 RXOAM_FILTER_CTRL999 * Bit 5-0 RXOAM_PX_EN1000 *----------------------------------------------------------------------------*/1001#define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x80001002#define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x70001003#define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL 121004#define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x07001005#define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL 81006#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C01007#define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL 61008#define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F1009#define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 01010 1011/*----------------------------------------------------------------------------1012 * Register 0x20C1,0x20C2: RXOAM Filter Configuration1013 * Bit 15-8 RXOAM_FX_MASK1014 * Bit 7-0 RXOAM_FX_VAL1015 *----------------------------------------------------------------------------*/1016#define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF001017#define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK 81018#define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF1019#define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 01020 1021/*----------------------------------------------------------------------------1022 * Register 0x20C3: RXOAM Configuration Register 21023 * Bit 13 RXOAM_REC_BYTE_VAL1024 * Bit 11-10 RXOAM_BYPASS_MODE1025 * Bit 5-0 RXOAM_PX_CLEAR1026 *----------------------------------------------------------------------------*/1027#define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x20001028#define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C001029#define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE 101030#define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F1031#define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 01032 1033/*----------------------------------------------------------------------------1034 * Register 0x20C4: RXOAM HEC Configuration1035 * Bit 15-8 RXOAM_COSET1036 * Bit 2 RXOAM_HEC_ERR_PKT1037 * Bit 0 RXOAM_HEC_EN1038 *----------------------------------------------------------------------------*/1039#define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF001040#define SUNI1x10GEXP_BITOFF_RXOAM_COSET 81041#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x00041042#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x00011043 1044/*----------------------------------------------------------------------------1045 * Register 0x20C7: RXOAM Interrupt Enable1046 * Bit 10 RXOAM_FILTER_THRSHE1047 * Bit 9 RXOAM_OAM_ERRE1048 * Bit 8 RXOAM_HECE_THRSHE1049 * Bit 7 RXOAM_SOPE1050 * Bit 6 RXOAM_RFE1051 * Bit 5 RXOAM_LFE1052 * Bit 4 RXOAM_DV_ERRE1053 * Bit 3 RXOAM_DATA_INVALIDE1054 * Bit 2 RXOAM_FILTER_DROPE1055 * Bit 1 RXOAM_HECE1056 * Bit 0 RXOAM_OFLE1057 *----------------------------------------------------------------------------*/1058#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x04001059#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x02001060#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x01001061#define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x00801062#define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x00401063#define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x00201064#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x00101065#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x00081066#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x00041067#define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x00021068#define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x00011069 1070/*----------------------------------------------------------------------------1071 * Register 0x20C8: RXOAM Interrupt Status1072 * Bit 10 RXOAM_FILTER_THRSHI1073 * Bit 9 RXOAM_OAM_ERRI1074 * Bit 8 RXOAM_HECE_THRSHI1075 * Bit 7 RXOAM_SOPI1076 * Bit 6 RXOAM_RFI1077 * Bit 5 RXOAM_LFI1078 * Bit 4 RXOAM_DV_ERRI1079 * Bit 3 RXOAM_DATA_INVALIDI1080 * Bit 2 RXOAM_FILTER_DROPI1081 * Bit 1 RXOAM_HECI1082 * Bit 0 RXOAM_OFLI1083 *----------------------------------------------------------------------------*/1084#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x04001085#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x02001086#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x01001087#define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x00801088#define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x00401089#define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x00201090#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x00101091#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x00081092#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x00041093#define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x00021094#define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x00011095 1096/*----------------------------------------------------------------------------1097 * Register 0x20C9: RXOAM Status1098 * Bit 10 RXOAM_FILTER_THRSHV1099 * Bit 8 RXOAM_HECE_THRSHV1100 * Bit 6 RXOAM_RFV1101 * Bit 5 RXOAM_LFV1102 *----------------------------------------------------------------------------*/1103#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x04001104#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x01001105#define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x00401106#define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x00201107 1108/*----------------------------------------------------------------------------1109 * Register 0x2100: MSTAT Control1110 * Bit 2 MSTAT_WRITE1111 * Bit 1 MSTAT_CLEAR1112 * Bit 0 MSTAT_SNAP1113 *----------------------------------------------------------------------------*/1114#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x00041115#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x00021116#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x00011117 1118/*----------------------------------------------------------------------------1119 * Register 0x2109: MSTAT Counter Write Address1120 * Bit 5-0 MSTAT_WRITE_ADDRESS1121 *----------------------------------------------------------------------------*/1122#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F1123#define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 01124 1125/*----------------------------------------------------------------------------1126 * Register 0x2200: IFLX Global Configuration Register1127 * Bit 15 IFLX_IRCU_ENABLE1128 * Bit 14 IFLX_IDSWT_ENABLE1129 * Bit 13-0 IFLX_IFD_CNT1130 *----------------------------------------------------------------------------*/1131#define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x80001132#define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x40001133#define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF1134#define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 01135 1136/*----------------------------------------------------------------------------1137 * Register 0x2209: IFLX FIFO Overflow Enable1138 * Bit 0 IFLX_OVFE1139 *----------------------------------------------------------------------------*/1140#define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x00011141 1142/*----------------------------------------------------------------------------1143 * Register 0x220A: IFLX FIFO Overflow Interrupt1144 * Bit 0 IFLX_OVFI1145 *----------------------------------------------------------------------------*/1146#define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x00011147 1148/*----------------------------------------------------------------------------1149 * Register 0x220D: IFLX Indirect Channel Address1150 * Bit 15 IFLX_BUSY1151 * Bit 14 IFLX_RWB1152 *----------------------------------------------------------------------------*/1153#define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x80001154#define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x40001155 1156/*----------------------------------------------------------------------------1157 * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision1158 * Bit 9-0 IFLX_LOLIM1159 *----------------------------------------------------------------------------*/1160#define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF1161#define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 01162 1163/*----------------------------------------------------------------------------1164 * Register 0x220F: IFLX Indirect Logical FIFO High Limit1165 * Bit 9-0 IFLX_HILIM1166 *----------------------------------------------------------------------------*/1167#define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF1168#define SUNI1x10GEXP_BITOFF_IFLX_HILIM 01169 1170/*----------------------------------------------------------------------------1171 * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit1172 * Bit 15 IFLX_FULL1173 * Bit 14 IFLX_AFULL1174 * Bit 13-0 IFLX_AFTH1175 *----------------------------------------------------------------------------*/1176#define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x80001177#define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x40001178#define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF1179#define SUNI1x10GEXP_BITOFF_IFLX_AFTH 01180 1181/*----------------------------------------------------------------------------1182 * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit1183 * Bit 15 IFLX_EMPTY1184 * Bit 14 IFLX_AEMPTY1185 * Bit 13-0 IFLX_AETH1186 *----------------------------------------------------------------------------*/1187#define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x80001188#define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x40001189#define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF1190#define SUNI1x10GEXP_BITOFF_IFLX_AETH 01191 1192/*----------------------------------------------------------------------------1193 * Register 0x2240: PL4MOS Configuration Register1194 * Bit 3 PL4MOS_RE_INIT1195 * Bit 2 PL4MOS_EN1196 * Bit 1 PL4MOS_NO_STATUS1197 *----------------------------------------------------------------------------*/1198#define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x00081199#define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x00041200#define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x00021201 1202/*----------------------------------------------------------------------------1203 * Register 0x2243: PL4MOS MaxBurst1 Register1204 * Bit 11-0 PL4MOS_MAX_BURST11205 *----------------------------------------------------------------------------*/1206#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF1207#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 01208 1209/*----------------------------------------------------------------------------1210 * Register 0x2244: PL4MOS MaxBurst2 Register1211 * Bit 11-0 PL4MOS_MAX_BURST21212 *----------------------------------------------------------------------------*/1213#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF1214#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 01215 1216/*----------------------------------------------------------------------------1217 * Register 0x2245: PL4MOS Transfer Size Register1218 * Bit 7-0 PL4MOS_MAX_TRANSFER1219 *----------------------------------------------------------------------------*/1220#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF1221#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 01222 1223/*----------------------------------------------------------------------------1224 * Register 0x2280: PL4ODP Configuration1225 * Bit 15-12 PL4ODP_REPEAT_T1226 * Bit 8 PL4ODP_SOP_RULE1227 * Bit 1 PL4ODP_EN_PORTS1228 * Bit 0 PL4ODP_EN_DFWD1229 *----------------------------------------------------------------------------*/1230#define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF0001231#define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T 121232#define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x01001233#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x00021234#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x00011235 1236/*----------------------------------------------------------------------------1237 * Register 0x2282: PL4ODP Interrupt Mask1238 * Bit 0 PL4ODP_OUT_DISE1239 *----------------------------------------------------------------------------*/1240#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x00011241 1242 1243 1244#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x00801245#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x00401246#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x00081247#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x00041248#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x00021249 1250 1251/*----------------------------------------------------------------------------1252 * Register 0x2283: PL4ODP Interrupt1253 * Bit 0 PL4ODP_OUT_DISI1254 *----------------------------------------------------------------------------*/1255#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x00011256 1257 1258 1259#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x00801260#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x00401261#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x00081262#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x00041263#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x00021264 1265/*----------------------------------------------------------------------------1266 * Register 0x2300: PL4IO Lock Detect Status1267 * Bit 15 PL4IO_OUT_ROOLV1268 * Bit 12 PL4IO_IS_ROOLV1269 * Bit 11 PL4IO_DIP2_ERRV1270 * Bit 8 PL4IO_ID_ROOLV1271 * Bit 4 PL4IO_IS_DOOLV1272 * Bit 0 PL4IO_ID_DOOLV1273 *----------------------------------------------------------------------------*/1274#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x80001275#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x10001276#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x08001277#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x01001278#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x00101279#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x00011280 1281/*----------------------------------------------------------------------------1282 * Register 0x2301: PL4IO Lock Detect Change1283 * Bit 15 PL4IO_OUT_ROOLI1284 * Bit 12 PL4IO_IS_ROOLI1285 * Bit 11 PL4IO_DIP2_ERRI1286 * Bit 8 PL4IO_ID_ROOLI1287 * Bit 4 PL4IO_IS_DOOLI1288 * Bit 0 PL4IO_ID_DOOLI1289 *----------------------------------------------------------------------------*/1290#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x80001291#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x10001292#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x08001293#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x01001294#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x00101295#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x00011296 1297/*----------------------------------------------------------------------------1298 * Register 0x2302: PL4IO Lock Detect Mask1299 * Bit 15 PL4IO_OUT_ROOLE1300 * Bit 12 PL4IO_IS_ROOLE1301 * Bit 11 PL4IO_DIP2_ERRE1302 * Bit 8 PL4IO_ID_ROOLE1303 * Bit 4 PL4IO_IS_DOOLE1304 * Bit 0 PL4IO_ID_DOOLE1305 *----------------------------------------------------------------------------*/1306#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x80001307#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x10001308#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x08001309#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x01001310#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x00101311#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x00011312 1313/*----------------------------------------------------------------------------1314 * Register 0x2303: PL4IO Lock Detect Limits1315 * Bit 15-8 PL4IO_REF_LIMIT1316 * Bit 7-0 PL4IO_TRAN_LIMIT1317 *----------------------------------------------------------------------------*/1318#define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF001319#define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT 81320#define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF1321#define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 01322 1323/*----------------------------------------------------------------------------1324 * Register 0x2304: PL4IO Calendar Repetitions1325 * Bit 15-8 PL4IO_IN_MUL1326 * Bit 7-0 PL4IO_OUT_MUL1327 *----------------------------------------------------------------------------*/1328#define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF001329#define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL 81330#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF1331#define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 01332 1333/*----------------------------------------------------------------------------1334 * Register 0x2305: PL4IO Configuration1335 * Bit 15 PL4IO_DIP2_ERR_CHK1336 * Bit 11 PL4IO_ODAT_DIS1337 * Bit 10 PL4IO_TRAIN_DIS1338 * Bit 9 PL4IO_OSTAT_DIS1339 * Bit 8 PL4IO_ISTAT_DIS1340 * Bit 7 PL4IO_NO_ISTAT1341 * Bit 6 PL4IO_STAT_OUTSEL1342 * Bit 5 PL4IO_INSEL1343 * Bit 4 PL4IO_DLSEL1344 * Bit 1-0 PL4IO_OUTSEL1345 *----------------------------------------------------------------------------*/1346#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x80001347#define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x08001348#define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x04001349#define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x02001350#define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x01001351#define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x00801352#define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x00401353#define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x00201354#define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x00101355#define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x00031356#define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 01357 1358/*----------------------------------------------------------------------------1359 * Register 0x3040: TXXG Configuration Register 11360 * Bit 15 TXXG_TXEN01361 * Bit 13 TXXG_HOSTPAUSE1362 * Bit 12-7 TXXG_IPGT1363 * Bit 5 TXXG_32BIT_ALIGN1364 * Bit 4 TXXG_CRCEN1365 * Bit 3 TXXG_FCTX1366 * Bit 2 TXXG_FCRX1367 * Bit 1 TXXG_PADEN1368 * Bit 0 TXXG_SPRE1369 *----------------------------------------------------------------------------*/1370#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x80001371#define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x20001372#define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F801373#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 71374#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x00201375#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x00101376#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x00081377#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x00041378#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x00021379#define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x00011380 1381/*----------------------------------------------------------------------------1382 * Register 0x3041: TXXG Configuration Register 21383 * Bit 7-0 TXXG_HDRSIZE1384 *----------------------------------------------------------------------------*/1385#define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF1386 1387/*----------------------------------------------------------------------------1388 * Register 0x3042: TXXG Configuration Register 31389 * Bit 15 TXXG_FIFO_ERRE1390 * Bit 14 TXXG_FIFO_UDRE1391 * Bit 13 TXXG_MAX_LERRE1392 * Bit 12 TXXG_MIN_LERRE1393 * Bit 11 TXXG_XFERE1394 *----------------------------------------------------------------------------*/1395#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x80001396#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x40001397#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x20001398#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x10001399#define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x08001400 1401/*----------------------------------------------------------------------------1402 * Register 0x3043: TXXG Interrupt1403 * Bit 15 TXXG_FIFO_ERRI1404 * Bit 14 TXXG_FIFO_UDRI1405 * Bit 13 TXXG_MAX_LERRI1406 * Bit 12 TXXG_MIN_LERRI1407 * Bit 11 TXXG_XFERI1408 *----------------------------------------------------------------------------*/1409#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x80001410#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x40001411#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x20001412#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x10001413#define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x08001414 1415/*----------------------------------------------------------------------------1416 * Register 0x3044: TXXG Status Register1417 * Bit 1 TXXG_TXACTIVE1418 * Bit 0 TXXG_PAUSED1419 *----------------------------------------------------------------------------*/1420#define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x00021421#define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x00011422 1423/*----------------------------------------------------------------------------1424 * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register1425 * Bit 7-0 TXXG_TX_MINFR1426 *----------------------------------------------------------------------------*/1427#define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF1428#define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 01429 1430/*----------------------------------------------------------------------------1431 * Register 0x3052: TXXG Pause Quantum Value Configuration Register1432 * Bit 7-0 TXXG_FC_PAUSE_QNTM1433 *----------------------------------------------------------------------------*/1434#define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF1435#define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 01436 1437/*----------------------------------------------------------------------------1438 * Register 0x3080: XTEF Control1439 * Bit 3-0 XTEF_FORCE_PARITY_ERR1440 *----------------------------------------------------------------------------*/1441#define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F1442#define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 01443 1444/*----------------------------------------------------------------------------1445 * Register 0x3084: XTEF Interrupt Event Register1446 * Bit 0 XTEF_LOST_SYNCI1447 *----------------------------------------------------------------------------*/1448#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x00011449 1450/*----------------------------------------------------------------------------1451 * Register 0x3085: XTEF Interrupt Enable Register1452 * Bit 0 XTEF_LOST_SYNCE1453 *----------------------------------------------------------------------------*/1454#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x00011455 1456/*----------------------------------------------------------------------------1457 * Register 0x3086: XTEF Visibility Register1458 * Bit 0 XTEF_LOST_SYNCV1459 *----------------------------------------------------------------------------*/1460#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x00011461 1462/*----------------------------------------------------------------------------1463 * Register 0x30C0: TXOAM OAM Configuration1464 * Bit 15 TXOAM_HEC_EN1465 * Bit 14 TXOAM_EMPTYCODE_EN1466 * Bit 13 TXOAM_FORCE_IDLE1467 * Bit 12 TXOAM_IGNORE_IDLE1468 * Bit 11-6 TXOAM_PX_OVERWRITE1469 * Bit 5-0 TXOAM_PX_SEL1470 *----------------------------------------------------------------------------*/1471#define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x80001472#define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x40001473#define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x20001474#define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x10001475#define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC01476#define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE 61477#define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F1478#define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 01479 1480/*----------------------------------------------------------------------------1481 * Register 0x30C1: TXOAM Mini-Packet Rate Configuration1482 * Bit 15 TXOAM_MINIDIS1483 * Bit 14 TXOAM_BUSY1484 * Bit 13 TXOAM_TRANS_EN1485 * Bit 10-0 TXOAM_MINIRATE1486 *----------------------------------------------------------------------------*/1487#define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x80001488#define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x40001489#define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x20001490#define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF1491 1492/*----------------------------------------------------------------------------1493 * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration1494 * Bit 13-10 TXOAM_FTHRESH1495 * Bit 9-6 TXOAM_MINIPOST1496 * Bit 5-0 TXOAM_MINIPRE1497 *----------------------------------------------------------------------------*/1498#define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C001499#define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH 101500#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C01501#define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST 61502#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F1503 1504/*----------------------------------------------------------------------------1505 * Register 0x30C6: TXOAM Interrupt Enable1506 * Bit 2 TXOAM_SOP_ERRE1507 * Bit 1 TXOAM_OFLE1508 * Bit 0 TXOAM_ERRE1509 *----------------------------------------------------------------------------*/1510#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x00041511#define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x00021512#define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x00011513 1514/*----------------------------------------------------------------------------1515 * Register 0x30C7: TXOAM Interrupt Status1516 * Bit 2 TXOAM_SOP_ERRI1517 * Bit 1 TXOAM_OFLI1518 * Bit 0 TXOAM_ERRI1519 *----------------------------------------------------------------------------*/1520#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x00041521#define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x00021522#define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x00011523 1524/*----------------------------------------------------------------------------1525 * Register 0x30CF: TXOAM Coset1526 * Bit 7-0 TXOAM_COSET1527 *----------------------------------------------------------------------------*/1528#define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF1529 1530/*----------------------------------------------------------------------------1531 * Register 0x3200: EFLX Global Configuration1532 * Bit 15 EFLX_ERCU_EN1533 * Bit 7 EFLX_EN_EDSWT1534 *----------------------------------------------------------------------------*/1535#define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x80001536#define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x00801537 1538/*----------------------------------------------------------------------------1539 * Register 0x3201: EFLX ERCU Global Status1540 * Bit 13 EFLX_OVF_ERR1541 *----------------------------------------------------------------------------*/1542#define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x20001543 1544/*----------------------------------------------------------------------------1545 * Register 0x3202: EFLX Indirect Channel Address1546 * Bit 15 EFLX_BUSY1547 * Bit 14 EFLX_RDWRB1548 *----------------------------------------------------------------------------*/1549#define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x80001550#define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x40001551 1552/*----------------------------------------------------------------------------1553 * Register 0x3203: EFLX Indirect Logical FIFO Low Limit1554 *----------------------------------------------------------------------------*/1555#define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF1556#define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 01557 1558/*----------------------------------------------------------------------------1559 * Register 0x3204: EFLX Indirect Logical FIFO High Limit1560 *----------------------------------------------------------------------------*/1561#define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF1562#define SUNI1x10GEXP_BITOFF_EFLX_HILIM 01563 1564/*----------------------------------------------------------------------------1565 * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit1566 * Bit 15 EFLX_FULL1567 * Bit 14 EFLX_AFULL1568 * Bit 13-0 EFLX_AFTH1569 *----------------------------------------------------------------------------*/1570#define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x80001571#define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x40001572#define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF1573#define SUNI1x10GEXP_BITOFF_EFLX_AFTH 01574 1575/*----------------------------------------------------------------------------1576 * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit1577 * Bit 15 EFLX_EMPTY1578 * Bit 14 EFLX_AEMPTY1579 * Bit 13-0 EFLX_AETH1580 *----------------------------------------------------------------------------*/1581#define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x80001582#define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x40001583#define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF1584#define SUNI1x10GEXP_BITOFF_EFLX_AETH 01585 1586/*----------------------------------------------------------------------------1587 * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold1588 *----------------------------------------------------------------------------*/1589#define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF1590#define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 01591 1592/*----------------------------------------------------------------------------1593 * Register 0x320C: EFLX FIFO Overflow Error Enable1594 * Bit 0 EFLX_OVFE1595 *----------------------------------------------------------------------------*/1596#define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x00011597 1598/*----------------------------------------------------------------------------1599 * Register 0x320D: EFLX FIFO Overflow Error Indication1600 * Bit 0 EFLX_OVFI1601 *----------------------------------------------------------------------------*/1602#define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x00011603 1604/*----------------------------------------------------------------------------1605 * Register 0x3210: EFLX Channel Provision1606 * Bit 0 EFLX_PROV1607 *----------------------------------------------------------------------------*/1608#define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x00011609 1610/*----------------------------------------------------------------------------1611 * Register 0x3280: PL4IDU Configuration1612 * Bit 2 PL4IDU_SYNCH_ON_TRAIN1613 * Bit 1 PL4IDU_EN_PORTS1614 * Bit 0 PL4IDU_EN_DFWD1615 *----------------------------------------------------------------------------*/1616#define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x00041617#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x00021618#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x00011619 1620/*----------------------------------------------------------------------------1621 * Register 0x3282: PL4IDU Interrupt Mask1622 * Bit 1 PL4IDU_DIP4E1623 *----------------------------------------------------------------------------*/1624#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x00021625 1626/*----------------------------------------------------------------------------1627 * Register 0x3283: PL4IDU Interrupt1628 * Bit 1 PL4IDU_DIP4I1629 *----------------------------------------------------------------------------*/1630#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x00021631 1632#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */1633