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1/*2 * This file is part of the Chelsio T4 Ethernet driver for Linux.3 *4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.5 *6 * This software is available to you under a choice of one of two7 * licenses. You may choose to be licensed under the terms of the GNU8 * General Public License (GPL) Version 2, available from the file9 * COPYING in the main directory of this source tree, or the10 * OpenIB.org BSD license below:11 *12 * Redistribution and use in source and binary forms, with or13 * without modification, are permitted provided that the following14 * conditions are met:15 *16 * - Redistributions of source code must retain the above17 * copyright notice, this list of conditions and the following18 * disclaimer.19 *20 * - Redistributions in binary form must reproduce the above21 * copyright notice, this list of conditions and the following22 * disclaimer in the documentation and/or other materials23 * provided with the distribution.24 *25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE32 * SOFTWARE.33 */34 35#ifndef __T4_HW_H36#define __T4_HW_H37 38#include <linux/types.h>39 40enum {41 NCHAN = 4, /* # of HW channels */42 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */43 EEPROMSIZE = 17408,/* Serial EEPROM physical size */44 EEPROMVSIZE = 32768,/* Serial EEPROM virtual address space size */45 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */46 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */47 T6_RSS_NENTRIES = 4096, /* # of entries in RSS mapping table */48 TCB_SIZE = 128, /* TCB size */49 NMTUS = 16, /* size of MTU table */50 NCCTRL_WIN = 32, /* # of congestion control windows */51 NTX_SCHED = 8, /* # of HW Tx scheduling queues */52 PM_NSTATS = 5, /* # of PM stats */53 T6_PM_NSTATS = 7, /* # of PM stats in T6 */54 MBOX_LEN = 64, /* mailbox size in bytes */55 TRACE_LEN = 112, /* length of trace data and mask */56 FILTER_OPT_LEN = 36, /* filter tuple width for optional components */57};58 59enum {60 CIM_NUM_IBQ = 6, /* # of CIM IBQs */61 CIM_NUM_OBQ = 6, /* # of CIM OBQs */62 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */63 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */64 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */65 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */66 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */67 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */68 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */69 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */70};71 72/* SGE context types */73enum ctxt_type {74 CTXT_EGRESS,75 CTXT_INGRESS,76 CTXT_FLM,77 CTXT_CNM,78};79 80enum {81 SF_PAGE_SIZE = 256, /* serial flash page size */82 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */83};84 85enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */86 87enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */88 89enum {90 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */91 SGE_CTXT_SIZE = 24, /* size of SGE context */92 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */93 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */94 SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */95 SGE_MAX_IQ_SIZE = 65520,96 97 SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */98 SGE_TIMER_UPD_CIDX = 7, /* update cidx only */99 100 SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */101 102 SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */103 SGE_INTRDST_IQ = 1, /* destination is an ingress queue */104 105 SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */106 SGE_UPDATEDEL_INTR = 1, /* interrupt */107 SGE_UPDATEDEL_STPG = 2, /* status page */108 SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */109 110 SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */111 SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */112 SGE_HOSTFCMODE_STPG = 2, /* sent to status page */113 SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */114 115 SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */116 SGE_FETCHBURSTMIN_32B = 1,117 SGE_FETCHBURSTMIN_64B = 2,118 SGE_FETCHBURSTMIN_128B = 3,119 120 SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */121 SGE_FETCHBURSTMAX_128B = 1,122 SGE_FETCHBURSTMAX_256B = 2,123 SGE_FETCHBURSTMAX_512B = 3,124 125 SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */126 SGE_CIDXFLUSHTHRESH_2 = 1,127 SGE_CIDXFLUSHTHRESH_4 = 2,128 SGE_CIDXFLUSHTHRESH_8 = 3,129 SGE_CIDXFLUSHTHRESH_16 = 4,130 SGE_CIDXFLUSHTHRESH_32 = 5,131 SGE_CIDXFLUSHTHRESH_64 = 6,132 SGE_CIDXFLUSHTHRESH_128 = 7,133 134 SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */135};136 137/* PCI-e memory window access */138enum pcie_memwin {139 MEMWIN_NIC = 0,140 MEMWIN_RSVD1 = 1,141 MEMWIN_RSVD2 = 2,142 MEMWIN_RDMA = 3,143 MEMWIN_RSVD4 = 4,144 MEMWIN_FOISCSI = 5,145 MEMWIN_CSIOSTOR = 6,146 MEMWIN_RSVD7 = 7,147};148 149struct sge_qstat { /* data written to SGE queue status entries */150 __be32 qid;151 __be16 cidx;152 __be16 pidx;153};154 155/*156 * Structure for last 128 bits of response descriptors157 */158struct rsp_ctrl {159 __be32 hdrbuflen_pidx;160 __be32 pldbuflen_qid;161 union {162 u8 type_gen;163 __be64 last_flit;164 };165};166 167#define RSPD_NEWBUF_S 31168#define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S)169#define RSPD_NEWBUF_F RSPD_NEWBUF_V(1U)170 171#define RSPD_LEN_S 0172#define RSPD_LEN_M 0x7fffffff173#define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M)174 175#define RSPD_QID_S RSPD_LEN_S176#define RSPD_QID_M RSPD_LEN_M177#define RSPD_QID_G(x) RSPD_LEN_G(x)178 179#define RSPD_GEN_S 7180 181#define RSPD_TYPE_S 4182#define RSPD_TYPE_M 0x3183#define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M)184 185/* Rx queue interrupt deferral fields: counter enable and timer index */186#define QINTR_CNT_EN_S 0187#define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S)188#define QINTR_CNT_EN_F QINTR_CNT_EN_V(1U)189 190#define QINTR_TIMER_IDX_S 1191#define QINTR_TIMER_IDX_M 0x7192#define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S)193#define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M)194 195/*196 * Flash layout.197 */198#define FLASH_START(start) ((start) * SF_SEC_SIZE)199#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)200 201enum {202 /*203 * Various Expansion-ROM boot images, etc.204 */205 FLASH_EXP_ROM_START_SEC = 0,206 FLASH_EXP_ROM_NSECS = 6,207 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),208 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),209 210 /*211 * iSCSI Boot Firmware Table (iBFT) and other driver-related212 * parameters ...213 */214 FLASH_IBFT_START_SEC = 6,215 FLASH_IBFT_NSECS = 1,216 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),217 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),218 219 /*220 * Boot configuration data.221 */222 FLASH_BOOTCFG_START_SEC = 7,223 FLASH_BOOTCFG_NSECS = 1,224 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),225 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),226 227 /*228 * Location of firmware image in FLASH.229 */230 FLASH_FW_START_SEC = 8,231 FLASH_FW_NSECS = 16,232 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),233 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),234 235 /* Location of bootstrap firmware image in FLASH.236 */237 FLASH_FWBOOTSTRAP_START_SEC = 27,238 FLASH_FWBOOTSTRAP_NSECS = 1,239 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),240 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),241 242 /*243 * iSCSI persistent/crash information.244 */245 FLASH_ISCSI_CRASH_START_SEC = 29,246 FLASH_ISCSI_CRASH_NSECS = 1,247 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),248 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),249 250 /*251 * FCoE persistent/crash information.252 */253 FLASH_FCOE_CRASH_START_SEC = 30,254 FLASH_FCOE_CRASH_NSECS = 1,255 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),256 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),257 258 /*259 * Location of Firmware Configuration File in FLASH. Since the FPGA260 * "FLASH" is smaller we need to store the Configuration File in a261 * different location -- which will overlap the end of the firmware262 * image if firmware ever gets that large ...263 */264 FLASH_CFG_START_SEC = 31,265 FLASH_CFG_NSECS = 1,266 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),267 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),268 269 /* We don't support FLASH devices which can't support the full270 * standard set of sections which we need for normal271 * operations.272 */273 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,274 275 FLASH_FPGA_CFG_START_SEC = 15,276 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),277 278 /*279 * Sectors 32-63 are reserved for FLASH failover.280 */281};282 283#undef FLASH_START284#undef FLASH_MAX_SIZE285 286#define SGE_TIMESTAMP_S 0287#define SGE_TIMESTAMP_M 0xfffffffffffffffULL288#define SGE_TIMESTAMP_V(x) ((__u64)(x) << SGE_TIMESTAMP_S)289#define SGE_TIMESTAMP_G(x) (((__u64)(x) >> SGE_TIMESTAMP_S) & SGE_TIMESTAMP_M)290 291#define I2C_DEV_ADDR_A0 0xa0292#define I2C_DEV_ADDR_A2 0xa2293#define I2C_PAGE_SIZE 0x100294#define SFP_DIAG_TYPE_ADDR 0x5c295#define SFP_DIAG_TYPE_LEN 0x1296#define SFP_DIAG_ADDRMODE BIT(2)297#define SFP_DIAG_IMPLEMENTED BIT(6)298#define SFF_8472_COMP_ADDR 0x5e299#define SFF_8472_COMP_LEN 0x1300#define SFF_REV_ADDR 0x1301#define SFF_REV_LEN 0x1302 303#endif /* __T4_HW_H */304