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1/*2 * This file is part of the Chelsio T4 Ethernet driver for Linux.3 *4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.5 *6 * This software is available to you under a choice of one of two7 * licenses. You may choose to be licensed under the terms of the GNU8 * General Public License (GPL) Version 2, available from the file9 * COPYING in the main directory of this source tree, or the10 * OpenIB.org BSD license below:11 *12 * Redistribution and use in source and binary forms, with or13 * without modification, are permitted provided that the following14 * conditions are met:15 *16 * - Redistributions of source code must retain the above17 * copyright notice, this list of conditions and the following18 * disclaimer.19 *20 * - Redistributions in binary form must reproduce the above21 * copyright notice, this list of conditions and the following22 * disclaimer in the documentation and/or other materials23 * provided with the distribution.24 *25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE32 * SOFTWARE.33 */34 35#ifndef __T4_REGS_H36#define __T4_REGS_H37 38#define MYPF_BASE 0x1b00039#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))40 41#define PF0_BASE 0x1e00042#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))43 44#define PF_STRIDE 0x40045#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)46#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))47 48#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 449#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 1650 51#define MYPORT_BASE 0x1c00052#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))53 54#define PORT0_BASE 0x2000055#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))56 57#define PORT_STRIDE 0x200058#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)59#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))60 61#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)62#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)63 64#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)65#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)66#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)67#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)68 69#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)70 71#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 1772#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 1773 74#define SGE_PF_KDOORBELL_A 0x075 76#define QID_S 1577#define QID_V(x) ((x) << QID_S)78 79#define DBPRIO_S 1480#define DBPRIO_V(x) ((x) << DBPRIO_S)81#define DBPRIO_F DBPRIO_V(1U)82 83#define PIDX_S 084#define PIDX_V(x) ((x) << PIDX_S)85 86#define SGE_VF_KDOORBELL_A 0x087 88#define DBTYPE_S 1389#define DBTYPE_V(x) ((x) << DBTYPE_S)90#define DBTYPE_F DBTYPE_V(1U)91 92#define PIDX_T5_S 093#define PIDX_T5_M 0x1fffU94#define PIDX_T5_V(x) ((x) << PIDX_T5_S)95#define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)96 97#define SGE_PF_GTS_A 0x498 99#define INGRESSQID_S 16100#define INGRESSQID_V(x) ((x) << INGRESSQID_S)101 102#define TIMERREG_S 13103#define TIMERREG_V(x) ((x) << TIMERREG_S)104 105#define SEINTARM_S 12106#define SEINTARM_V(x) ((x) << SEINTARM_S)107 108#define CIDXINC_S 0109#define CIDXINC_M 0xfffU110#define CIDXINC_V(x) ((x) << CIDXINC_S)111 112#define SGE_CONTROL_A 0x1008113#define SGE_CONTROL2_A 0x1124114 115#define RXPKTCPLMODE_S 18116#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)117#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)118 119#define EGRSTATUSPAGESIZE_S 17120#define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)121#define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U)122 123#define PKTSHIFT_S 10124#define PKTSHIFT_M 0x7U125#define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)126#define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)127 128#define INGPCIEBOUNDARY_S 7129#define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)130 131#define INGPADBOUNDARY_S 4132#define INGPADBOUNDARY_M 0x7U133#define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)134#define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)135 136#define EGRPCIEBOUNDARY_S 1137#define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)138 139#define INGPACKBOUNDARY_S 16140#define INGPACKBOUNDARY_M 0x7U141#define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S)142#define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \143 & INGPACKBOUNDARY_M)144 145#define VFIFO_ENABLE_S 10146#define VFIFO_ENABLE_V(x) ((x) << VFIFO_ENABLE_S)147#define VFIFO_ENABLE_F VFIFO_ENABLE_V(1U)148 149#define SGE_DBVFIFO_BADDR_A 0x1138150 151#define DBVFIFO_SIZE_S 6152#define DBVFIFO_SIZE_M 0xfffU153#define DBVFIFO_SIZE_G(x) (((x) >> DBVFIFO_SIZE_S) & DBVFIFO_SIZE_M)154 155#define T6_DBVFIFO_SIZE_S 0156#define T6_DBVFIFO_SIZE_M 0x1fffU157#define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M)158 159#define SGE_CTXT_CMD_A 0x11fc160 161#define BUSY_S 31162#define BUSY_V(x) ((x) << BUSY_S)163#define BUSY_F BUSY_V(1U)164 165#define CTXTTYPE_S 24166#define CTXTTYPE_M 0x3U167#define CTXTTYPE_V(x) ((x) << CTXTTYPE_S)168 169#define CTXTQID_S 0170#define CTXTQID_M 0x1ffffU171#define CTXTQID_V(x) ((x) << CTXTQID_S)172 173#define SGE_CTXT_DATA0_A 0x1200174#define SGE_CTXT_DATA5_A 0x1214175 176#define GLOBALENABLE_S 0177#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)178#define GLOBALENABLE_F GLOBALENABLE_V(1U)179 180#define SGE_HOST_PAGE_SIZE_A 0x100c181 182#define HOSTPAGESIZEPF7_S 28183#define HOSTPAGESIZEPF7_M 0xfU184#define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)185#define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)186 187#define HOSTPAGESIZEPF6_S 24188#define HOSTPAGESIZEPF6_M 0xfU189#define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)190#define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)191 192#define HOSTPAGESIZEPF5_S 20193#define HOSTPAGESIZEPF5_M 0xfU194#define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)195#define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)196 197#define HOSTPAGESIZEPF4_S 16198#define HOSTPAGESIZEPF4_M 0xfU199#define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)200#define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)201 202#define HOSTPAGESIZEPF3_S 12203#define HOSTPAGESIZEPF3_M 0xfU204#define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)205#define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)206 207#define HOSTPAGESIZEPF2_S 8208#define HOSTPAGESIZEPF2_M 0xfU209#define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)210#define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)211 212#define HOSTPAGESIZEPF1_S 4213#define HOSTPAGESIZEPF1_M 0xfU214#define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)215#define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)216 217#define HOSTPAGESIZEPF0_S 0218#define HOSTPAGESIZEPF0_M 0xfU219#define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)220#define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)221 222#define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010223#define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014224 225#define QUEUESPERPAGEPF1_S 4226 227#define QUEUESPERPAGEPF0_S 0228#define QUEUESPERPAGEPF0_M 0xfU229#define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)230#define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)231 232#define SGE_INT_CAUSE1_A 0x1024233#define SGE_INT_CAUSE2_A 0x1030234#define SGE_INT_CAUSE3_A 0x103c235 236#define ERR_FLM_DBP_S 31237#define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)238#define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U)239 240#define ERR_FLM_IDMA1_S 30241#define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)242#define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U)243 244#define ERR_FLM_IDMA0_S 29245#define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)246#define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U)247 248#define ERR_FLM_HINT_S 28249#define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)250#define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U)251 252#define ERR_PCIE_ERROR3_S 27253#define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)254#define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U)255 256#define ERR_PCIE_ERROR2_S 26257#define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)258#define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U)259 260#define ERR_PCIE_ERROR1_S 25261#define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)262#define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U)263 264#define ERR_PCIE_ERROR0_S 24265#define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)266#define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U)267 268#define ERR_CPL_EXCEED_IQE_SIZE_S 22269#define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)270#define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U)271 272#define ERR_INVALID_CIDX_INC_S 21273#define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)274#define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U)275 276#define ERR_CPL_OPCODE_0_S 19277#define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)278#define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U)279 280#define ERR_DROPPED_DB_S 18281#define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)282#define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U)283 284#define ERR_DATA_CPL_ON_HIGH_QID1_S 17285#define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)286#define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U)287 288#define ERR_DATA_CPL_ON_HIGH_QID0_S 16289#define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)290#define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U)291 292#define ERR_BAD_DB_PIDX3_S 15293#define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)294#define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U)295 296#define ERR_BAD_DB_PIDX2_S 14297#define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)298#define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U)299 300#define ERR_BAD_DB_PIDX1_S 13301#define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)302#define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U)303 304#define ERR_BAD_DB_PIDX0_S 12305#define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)306#define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U)307 308#define ERR_ING_CTXT_PRIO_S 10309#define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)310#define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U)311 312#define ERR_EGR_CTXT_PRIO_S 9313#define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)314#define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U)315 316#define DBFIFO_HP_INT_S 8317#define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)318#define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U)319 320#define DBFIFO_LP_INT_S 7321#define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)322#define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U)323 324#define INGRESS_SIZE_ERR_S 5325#define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)326#define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U)327 328#define EGRESS_SIZE_ERR_S 4329#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)330#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)331 332#define SGE_INT_ENABLE3_A 0x1040333#define SGE_FL_BUFFER_SIZE0_A 0x1044334#define SGE_FL_BUFFER_SIZE1_A 0x1048335#define SGE_FL_BUFFER_SIZE2_A 0x104c336#define SGE_FL_BUFFER_SIZE3_A 0x1050337#define SGE_FL_BUFFER_SIZE4_A 0x1054338#define SGE_FL_BUFFER_SIZE5_A 0x1058339#define SGE_FL_BUFFER_SIZE6_A 0x105c340#define SGE_FL_BUFFER_SIZE7_A 0x1060341#define SGE_FL_BUFFER_SIZE8_A 0x1064342 343#define SGE_IMSG_CTXT_BADDR_A 0x1088344#define SGE_FLM_CACHE_BADDR_A 0x108c345#define SGE_FLM_CFG_A 0x1090346 347#define NOHDR_S 18348#define NOHDR_V(x) ((x) << NOHDR_S)349#define NOHDR_F NOHDR_V(1U)350 351#define HDRSTARTFLQ_S 11352#define HDRSTARTFLQ_M 0x7U353#define HDRSTARTFLQ_G(x) (((x) >> HDRSTARTFLQ_S) & HDRSTARTFLQ_M)354 355#define SGE_INGRESS_RX_THRESHOLD_A 0x10a0356 357#define THRESHOLD_0_S 24358#define THRESHOLD_0_M 0x3fU359#define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)360#define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)361 362#define THRESHOLD_1_S 16363#define THRESHOLD_1_M 0x3fU364#define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)365#define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)366 367#define THRESHOLD_2_S 8368#define THRESHOLD_2_M 0x3fU369#define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)370#define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)371 372#define THRESHOLD_3_S 0373#define THRESHOLD_3_M 0x3fU374#define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)375#define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)376 377#define SGE_CONM_CTRL_A 0x1094378 379#define EGRTHRESHOLD_S 8380#define EGRTHRESHOLD_M 0x3fU381#define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)382#define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)383 384#define EGRTHRESHOLDPACKING_S 14385#define EGRTHRESHOLDPACKING_M 0x3fU386#define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)387#define EGRTHRESHOLDPACKING_G(x) \388 (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)389 390#define T6_EGRTHRESHOLDPACKING_S 16391#define T6_EGRTHRESHOLDPACKING_M 0xffU392#define T6_EGRTHRESHOLDPACKING_G(x) \393 (((x) >> T6_EGRTHRESHOLDPACKING_S) & T6_EGRTHRESHOLDPACKING_M)394 395#define SGE_TIMESTAMP_LO_A 0x1098396#define SGE_TIMESTAMP_HI_A 0x109c397 398#define TSOP_S 28399#define TSOP_M 0x3U400#define TSOP_V(x) ((x) << TSOP_S)401#define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)402 403#define TSVAL_S 0404#define TSVAL_M 0xfffffffU405#define TSVAL_V(x) ((x) << TSVAL_S)406#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)407 408#define SGE_DBFIFO_STATUS_A 0x10a4409#define SGE_DBVFIFO_SIZE_A 0x113c410 411#define HP_INT_THRESH_S 28412#define HP_INT_THRESH_M 0xfU413#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)414 415#define LP_INT_THRESH_S 12416#define LP_INT_THRESH_M 0xfU417#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)418 419#define SGE_DOORBELL_CONTROL_A 0x10a8420 421#define NOCOALESCE_S 26422#define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)423#define NOCOALESCE_F NOCOALESCE_V(1U)424 425#define ENABLE_DROP_S 13426#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)427#define ENABLE_DROP_F ENABLE_DROP_V(1U)428 429#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8430 431#define TIMERVALUE0_S 16432#define TIMERVALUE0_M 0xffffU433#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)434#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)435 436#define TIMERVALUE1_S 0437#define TIMERVALUE1_M 0xffffU438#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)439#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)440 441#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc442 443#define TIMERVALUE2_S 16444#define TIMERVALUE2_M 0xffffU445#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)446#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)447 448#define TIMERVALUE3_S 0449#define TIMERVALUE3_M 0xffffU450#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)451#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)452 453#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0454 455#define TIMERVALUE4_S 16456#define TIMERVALUE4_M 0xffffU457#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)458#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)459 460#define TIMERVALUE5_S 0461#define TIMERVALUE5_M 0xffffU462#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)463#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)464 465#define SGE_DEBUG_INDEX_A 0x10cc466#define SGE_DEBUG_DATA_HIGH_A 0x10d0467#define SGE_DEBUG_DATA_LOW_A 0x10d4468 469#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8470#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc471#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8472 473#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4474#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8475 476#define SGE_ERROR_STATS_A 0x1100477 478#define UNCAPTURED_ERROR_S 18479#define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S)480#define UNCAPTURED_ERROR_F UNCAPTURED_ERROR_V(1U)481 482#define ERROR_QID_VALID_S 17483#define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S)484#define ERROR_QID_VALID_F ERROR_QID_VALID_V(1U)485 486#define ERROR_QID_S 0487#define ERROR_QID_M 0x1ffffU488#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)489 490#define SGE_INT_CAUSE5_A 0x110c491 492#define ERR_T_RXCRC_S 31493#define ERR_T_RXCRC_V(x) ((x) << ERR_T_RXCRC_S)494#define ERR_T_RXCRC_F ERR_T_RXCRC_V(1U)495 496#define HP_INT_THRESH_S 28497#define HP_INT_THRESH_M 0xfU498#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)499 500#define HP_COUNT_S 16501#define HP_COUNT_M 0x7ffU502#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)503 504#define LP_INT_THRESH_S 12505#define LP_INT_THRESH_M 0xfU506#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)507 508#define LP_COUNT_S 0509#define LP_COUNT_M 0x7ffU510#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)511 512#define LP_INT_THRESH_T5_S 18513#define LP_INT_THRESH_T5_M 0xfffU514#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)515 516#define LP_COUNT_T5_S 0517#define LP_COUNT_T5_M 0x3ffffU518#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)519 520#define SGE_DOORBELL_CONTROL_A 0x10a8521 522#define SGE_STAT_TOTAL_A 0x10e4523#define SGE_STAT_MATCH_A 0x10e8524#define SGE_STAT_CFG_A 0x10ec525 526#define STATMODE_S 2527#define STATMODE_V(x) ((x) << STATMODE_S)528 529#define STATSOURCE_T5_S 9530#define STATSOURCE_T5_M 0xfU531#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)532#define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M)533 534#define T6_STATMODE_S 0535#define T6_STATMODE_V(x) ((x) << T6_STATMODE_S)536 537#define SGE_DBFIFO_STATUS2_A 0x1118538 539#define HP_INT_THRESH_T5_S 10540#define HP_INT_THRESH_T5_M 0xfU541#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)542 543#define HP_COUNT_T5_S 0544#define HP_COUNT_T5_M 0x3ffU545#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)546 547#define ENABLE_DROP_S 13548#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)549#define ENABLE_DROP_F ENABLE_DROP_V(1U)550 551#define DROPPED_DB_S 0552#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)553#define DROPPED_DB_F DROPPED_DB_V(1U)554 555#define SGE_CTXT_CMD_A 0x11fc556#define SGE_DBQ_CTXT_BADDR_A 0x1084557 558/* registers for module PCIE */559#define PCIE_PF_CFG_A 0x40560 561#define AIVEC_S 4562#define AIVEC_M 0x3ffU563#define AIVEC_V(x) ((x) << AIVEC_S)564 565#define PCIE_PF_CLI_A 0x44566 567#define PCIE_PF_EXPROM_OFST_A 0x4c568#define OFFSET_S 10569#define OFFSET_M 0x3fffU570#define OFFSET_G(x) (((x) >> OFFSET_S) & OFFSET_M)571 572#define PCIE_INT_CAUSE_A 0x3004573 574#define UNXSPLCPLERR_S 29575#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)576#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)577 578#define PCIEPINT_S 28579#define PCIEPINT_V(x) ((x) << PCIEPINT_S)580#define PCIEPINT_F PCIEPINT_V(1U)581 582#define PCIESINT_S 27583#define PCIESINT_V(x) ((x) << PCIESINT_S)584#define PCIESINT_F PCIESINT_V(1U)585 586#define RPLPERR_S 26587#define RPLPERR_V(x) ((x) << RPLPERR_S)588#define RPLPERR_F RPLPERR_V(1U)589 590#define RXWRPERR_S 25591#define RXWRPERR_V(x) ((x) << RXWRPERR_S)592#define RXWRPERR_F RXWRPERR_V(1U)593 594#define RXCPLPERR_S 24595#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)596#define RXCPLPERR_F RXCPLPERR_V(1U)597 598#define PIOTAGPERR_S 23599#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)600#define PIOTAGPERR_F PIOTAGPERR_V(1U)601 602#define MATAGPERR_S 22603#define MATAGPERR_V(x) ((x) << MATAGPERR_S)604#define MATAGPERR_F MATAGPERR_V(1U)605 606#define INTXCLRPERR_S 21607#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)608#define INTXCLRPERR_F INTXCLRPERR_V(1U)609 610#define FIDPERR_S 20611#define FIDPERR_V(x) ((x) << FIDPERR_S)612#define FIDPERR_F FIDPERR_V(1U)613 614#define CFGSNPPERR_S 19615#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)616#define CFGSNPPERR_F CFGSNPPERR_V(1U)617 618#define HRSPPERR_S 18619#define HRSPPERR_V(x) ((x) << HRSPPERR_S)620#define HRSPPERR_F HRSPPERR_V(1U)621 622#define HREQPERR_S 17623#define HREQPERR_V(x) ((x) << HREQPERR_S)624#define HREQPERR_F HREQPERR_V(1U)625 626#define HCNTPERR_S 16627#define HCNTPERR_V(x) ((x) << HCNTPERR_S)628#define HCNTPERR_F HCNTPERR_V(1U)629 630#define DRSPPERR_S 15631#define DRSPPERR_V(x) ((x) << DRSPPERR_S)632#define DRSPPERR_F DRSPPERR_V(1U)633 634#define DREQPERR_S 14635#define DREQPERR_V(x) ((x) << DREQPERR_S)636#define DREQPERR_F DREQPERR_V(1U)637 638#define DCNTPERR_S 13639#define DCNTPERR_V(x) ((x) << DCNTPERR_S)640#define DCNTPERR_F DCNTPERR_V(1U)641 642#define CRSPPERR_S 12643#define CRSPPERR_V(x) ((x) << CRSPPERR_S)644#define CRSPPERR_F CRSPPERR_V(1U)645 646#define CREQPERR_S 11647#define CREQPERR_V(x) ((x) << CREQPERR_S)648#define CREQPERR_F CREQPERR_V(1U)649 650#define CCNTPERR_S 10651#define CCNTPERR_V(x) ((x) << CCNTPERR_S)652#define CCNTPERR_F CCNTPERR_V(1U)653 654#define TARTAGPERR_S 9655#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)656#define TARTAGPERR_F TARTAGPERR_V(1U)657 658#define PIOREQPERR_S 8659#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)660#define PIOREQPERR_F PIOREQPERR_V(1U)661 662#define PIOCPLPERR_S 7663#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)664#define PIOCPLPERR_F PIOCPLPERR_V(1U)665 666#define MSIXDIPERR_S 6667#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)668#define MSIXDIPERR_F MSIXDIPERR_V(1U)669 670#define MSIXDATAPERR_S 5671#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)672#define MSIXDATAPERR_F MSIXDATAPERR_V(1U)673 674#define MSIXADDRHPERR_S 4675#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)676#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)677 678#define MSIXADDRLPERR_S 3679#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)680#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)681 682#define MSIDATAPERR_S 2683#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)684#define MSIDATAPERR_F MSIDATAPERR_V(1U)685 686#define MSIADDRHPERR_S 1687#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)688#define MSIADDRHPERR_F MSIADDRHPERR_V(1U)689 690#define MSIADDRLPERR_S 0691#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)692#define MSIADDRLPERR_F MSIADDRLPERR_V(1U)693 694#define READRSPERR_S 29695#define READRSPERR_V(x) ((x) << READRSPERR_S)696#define READRSPERR_F READRSPERR_V(1U)697 698#define TRGT1GRPPERR_S 28699#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)700#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)701 702#define IPSOTPERR_S 27703#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)704#define IPSOTPERR_F IPSOTPERR_V(1U)705 706#define IPRETRYPERR_S 26707#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)708#define IPRETRYPERR_F IPRETRYPERR_V(1U)709 710#define IPRXDATAGRPPERR_S 25711#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)712#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)713 714#define IPRXHDRGRPPERR_S 24715#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)716#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)717 718#define MAGRPPERR_S 22719#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)720#define MAGRPPERR_F MAGRPPERR_V(1U)721 722#define VFIDPERR_S 21723#define VFIDPERR_V(x) ((x) << VFIDPERR_S)724#define VFIDPERR_F VFIDPERR_V(1U)725 726#define HREQWRPERR_S 16727#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)728#define HREQWRPERR_F HREQWRPERR_V(1U)729 730#define DREQWRPERR_S 13731#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)732#define DREQWRPERR_F DREQWRPERR_V(1U)733 734#define CREQRDPERR_S 11735#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)736#define CREQRDPERR_F CREQRDPERR_V(1U)737 738#define MSTTAGQPERR_S 10739#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)740#define MSTTAGQPERR_F MSTTAGQPERR_V(1U)741 742#define PIOREQGRPPERR_S 8743#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)744#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)745 746#define PIOCPLGRPPERR_S 7747#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)748#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)749 750#define MSIXSTIPERR_S 2751#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)752#define MSIXSTIPERR_F MSIXSTIPERR_V(1U)753 754#define MSTTIMEOUTPERR_S 1755#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)756#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)757 758#define MSTGRPPERR_S 0759#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)760#define MSTGRPPERR_F MSTGRPPERR_V(1U)761 762#define PCIE_NONFAT_ERR_A 0x3010763#define PCIE_CFG_SPACE_REQ_A 0x3060764#define PCIE_CFG_SPACE_DATA_A 0x3064765#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068766 767#define PCIEOFST_S 10768#define PCIEOFST_M 0x3fffffU769#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)770 771#define BIR_S 8772#define BIR_M 0x3U773#define BIR_V(x) ((x) << BIR_S)774#define BIR_G(x) (((x) >> BIR_S) & BIR_M)775 776#define WINDOW_S 0777#define WINDOW_M 0xffU778#define WINDOW_V(x) ((x) << WINDOW_S)779#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)780 781#define PCIE_MEM_ACCESS_OFFSET_A 0x306c782 783#define ENABLE_S 30784#define ENABLE_V(x) ((x) << ENABLE_S)785#define ENABLE_F ENABLE_V(1U)786 787#define LOCALCFG_S 28788#define LOCALCFG_V(x) ((x) << LOCALCFG_S)789#define LOCALCFG_F LOCALCFG_V(1U)790 791#define FUNCTION_S 12792#define FUNCTION_V(x) ((x) << FUNCTION_S)793 794#define REGISTER_S 0795#define REGISTER_V(x) ((x) << REGISTER_S)796 797#define T6_ENABLE_S 31798#define T6_ENABLE_V(x) ((x) << T6_ENABLE_S)799#define T6_ENABLE_F T6_ENABLE_V(1U)800 801#define PFNUM_S 0802#define PFNUM_V(x) ((x) << PFNUM_S)803 804#define PCIE_FW_A 0x30b8805#define PCIE_FW_PF_A 0x30bc806 807#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908808 809#define RNPP_S 31810#define RNPP_V(x) ((x) << RNPP_S)811#define RNPP_F RNPP_V(1U)812 813#define RPCP_S 29814#define RPCP_V(x) ((x) << RPCP_S)815#define RPCP_F RPCP_V(1U)816 817#define RCIP_S 27818#define RCIP_V(x) ((x) << RCIP_S)819#define RCIP_F RCIP_V(1U)820 821#define RCCP_S 26822#define RCCP_V(x) ((x) << RCCP_S)823#define RCCP_F RCCP_V(1U)824 825#define RFTP_S 23826#define RFTP_V(x) ((x) << RFTP_S)827#define RFTP_F RFTP_V(1U)828 829#define PTRP_S 20830#define PTRP_V(x) ((x) << PTRP_S)831#define PTRP_F PTRP_V(1U)832 833#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4834 835#define TPCP_S 30836#define TPCP_V(x) ((x) << TPCP_S)837#define TPCP_F TPCP_V(1U)838 839#define TNPP_S 29840#define TNPP_V(x) ((x) << TNPP_S)841#define TNPP_F TNPP_V(1U)842 843#define TFTP_S 28844#define TFTP_V(x) ((x) << TFTP_S)845#define TFTP_F TFTP_V(1U)846 847#define TCAP_S 27848#define TCAP_V(x) ((x) << TCAP_S)849#define TCAP_F TCAP_V(1U)850 851#define TCIP_S 26852#define TCIP_V(x) ((x) << TCIP_S)853#define TCIP_F TCIP_V(1U)854 855#define RCAP_S 25856#define RCAP_V(x) ((x) << RCAP_S)857#define RCAP_F RCAP_V(1U)858 859#define PLUP_S 23860#define PLUP_V(x) ((x) << PLUP_S)861#define PLUP_F PLUP_V(1U)862 863#define PLDN_S 22864#define PLDN_V(x) ((x) << PLDN_S)865#define PLDN_F PLDN_V(1U)866 867#define OTDD_S 21868#define OTDD_V(x) ((x) << OTDD_S)869#define OTDD_F OTDD_V(1U)870 871#define GTRP_S 20872#define GTRP_V(x) ((x) << GTRP_S)873#define GTRP_F GTRP_V(1U)874 875#define RDPE_S 18876#define RDPE_V(x) ((x) << RDPE_S)877#define RDPE_F RDPE_V(1U)878 879#define TDCE_S 17880#define TDCE_V(x) ((x) << TDCE_S)881#define TDCE_F TDCE_V(1U)882 883#define TDUE_S 16884#define TDUE_V(x) ((x) << TDUE_S)885#define TDUE_F TDUE_V(1U)886 887/* SPARE2 register contains 32-bit value at offset 0x6 in Serial INIT888 * Configuration flashed on EEPROM. This value corresponds to 32-bit889 * Serial Configuration Version information.890 */891#define PCIE_STATIC_SPARE2_A 0x5bfc892 893/* registers for module MC */894#define MC_INT_CAUSE_A 0x7518895#define MC_P_INT_CAUSE_A 0x41318896 897#define ECC_UE_INT_CAUSE_S 2898#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)899#define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U)900 901#define ECC_CE_INT_CAUSE_S 1902#define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)903#define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U)904 905#define PERR_INT_CAUSE_S 0906#define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)907#define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U)908 909#define DBG_GPIO_EN_A 0x6010910#define XGMAC_PORT_CFG_A 0x1000911#define MAC_PORT_CFG_A 0x800912 913#define SIGNAL_DET_S 14914#define SIGNAL_DET_V(x) ((x) << SIGNAL_DET_S)915#define SIGNAL_DET_F SIGNAL_DET_V(1U)916 917#define MC_ECC_STATUS_A 0x751c918#define MC_P_ECC_STATUS_A 0x4131c919 920#define ECC_CECNT_S 16921#define ECC_CECNT_M 0xffffU922#define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)923#define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)924 925#define ECC_UECNT_S 0926#define ECC_UECNT_M 0xffffU927#define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)928#define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)929 930#define MC_BIST_CMD_A 0x7600931 932#define START_BIST_S 31933#define START_BIST_V(x) ((x) << START_BIST_S)934#define START_BIST_F START_BIST_V(1U)935 936#define BIST_CMD_GAP_S 8937#define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)938 939#define BIST_OPCODE_S 0940#define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)941 942#define MC_BIST_CMD_ADDR_A 0x7604943#define MC_BIST_CMD_LEN_A 0x7608944#define MC_BIST_DATA_PATTERN_A 0x760c945 946#define MC_BIST_STATUS_RDATA_A 0x7688947 948/* registers for module MA */949#define MA_EDRAM0_BAR_A 0x77c0950 951#define EDRAM0_BASE_S 16952#define EDRAM0_BASE_M 0xfffU953#define EDRAM0_BASE_G(x) (((x) >> EDRAM0_BASE_S) & EDRAM0_BASE_M)954 955#define EDRAM0_SIZE_S 0956#define EDRAM0_SIZE_M 0xfffU957#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)958#define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)959 960#define MA_EDRAM1_BAR_A 0x77c4961 962#define EDRAM1_BASE_S 16963#define EDRAM1_BASE_M 0xfffU964#define EDRAM1_BASE_G(x) (((x) >> EDRAM1_BASE_S) & EDRAM1_BASE_M)965 966#define EDRAM1_SIZE_S 0967#define EDRAM1_SIZE_M 0xfffU968#define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)969#define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)970 971#define MA_EXT_MEMORY_BAR_A 0x77c8972 973#define EXT_MEM_BASE_S 16974#define EXT_MEM_BASE_M 0xfffU975#define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S)976#define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M)977 978#define EXT_MEM_SIZE_S 0979#define EXT_MEM_SIZE_M 0xfffU980#define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)981#define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)982 983#define MA_EXT_MEMORY1_BAR_A 0x7808984 985#define HMA_MUX_S 5986#define HMA_MUX_V(x) ((x) << HMA_MUX_S)987#define HMA_MUX_F HMA_MUX_V(1U)988 989#define EXT_MEM1_BASE_S 16990#define EXT_MEM1_BASE_M 0xfffU991#define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)992 993#define EXT_MEM1_SIZE_S 0994#define EXT_MEM1_SIZE_M 0xfffU995#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)996#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)997 998#define MA_EXT_MEMORY0_BAR_A 0x77c8999 1000#define EXT_MEM0_BASE_S 161001#define EXT_MEM0_BASE_M 0xfffU1002#define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M)1003 1004#define EXT_MEM0_SIZE_S 01005#define EXT_MEM0_SIZE_M 0xfffU1006#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)1007#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)1008 1009#define MA_TARGET_MEM_ENABLE_A 0x77d81010 1011#define EXT_MEM_ENABLE_S 21012#define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)1013#define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)1014 1015#define EDRAM1_ENABLE_S 11016#define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)1017#define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)1018 1019#define EDRAM0_ENABLE_S 01020#define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)1021#define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)1022 1023#define EXT_MEM1_ENABLE_S 41024#define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)1025#define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)1026 1027#define EXT_MEM0_ENABLE_S 21028#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)1029#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)1030 1031#define MA_INT_CAUSE_A 0x77e01032 1033#define MEM_PERR_INT_CAUSE_S 11034#define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)1035#define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U)1036 1037#define MEM_WRAP_INT_CAUSE_S 01038#define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)1039#define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U)1040 1041#define MA_INT_WRAP_STATUS_A 0x77e41042 1043#define MEM_WRAP_ADDRESS_S 41044#define MEM_WRAP_ADDRESS_M 0xfffffffU1045#define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)1046 1047#define MEM_WRAP_CLIENT_NUM_S 01048#define MEM_WRAP_CLIENT_NUM_M 0xfU1049#define MEM_WRAP_CLIENT_NUM_G(x) \1050 (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)1051 1052#define MA_PARITY_ERROR_STATUS_A 0x77f41053#define MA_PARITY_ERROR_STATUS1_A 0x77f41054#define MA_PARITY_ERROR_STATUS2_A 0x78041055 1056/* registers for module EDC_0 */1057#define EDC_0_BASE_ADDR 0x79001058 1059#define EDC_BIST_CMD_A 0x79041060#define EDC_BIST_CMD_ADDR_A 0x79081061#define EDC_BIST_CMD_LEN_A 0x790c1062#define EDC_BIST_DATA_PATTERN_A 0x79101063#define EDC_BIST_STATUS_RDATA_A 0x79281064#define EDC_INT_CAUSE_A 0x79781065 1066#define ECC_UE_PAR_S 51067#define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)1068#define ECC_UE_PAR_F ECC_UE_PAR_V(1U)1069 1070#define ECC_CE_PAR_S 41071#define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)1072#define ECC_CE_PAR_F ECC_CE_PAR_V(1U)1073 1074#define PERR_PAR_CAUSE_S 31075#define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)1076#define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U)1077 1078#define EDC_ECC_STATUS_A 0x797c1079 1080/* registers for module EDC_1 */1081#define EDC_1_BASE_ADDR 0x79801082 1083/* registers for module CIM */1084#define CIM_BOOT_CFG_A 0x7b001085#define CIM_SDRAM_BASE_ADDR_A 0x7b141086#define CIM_SDRAM_ADDR_SIZE_A 0x7b181087#define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c1088#define CIM_EXTMEM2_ADDR_SIZE_A 0x7b201089#define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x2901090 1091#define BOOTADDR_M 0xffffff00U1092 1093#define UPCRST_S 01094#define UPCRST_V(x) ((x) << UPCRST_S)1095#define UPCRST_F UPCRST_V(1U)1096 1097#define CIM_PF_MAILBOX_DATA_A 0x2401098#define CIM_PF_MAILBOX_CTRL_A 0x2801099 1100#define MBMSGVALID_S 31101#define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)1102#define MBMSGVALID_F MBMSGVALID_V(1U)1103 1104#define MBINTREQ_S 21105#define MBINTREQ_V(x) ((x) << MBINTREQ_S)1106#define MBINTREQ_F MBINTREQ_V(1U)1107 1108#define MBOWNER_S 01109#define MBOWNER_M 0x3U1110#define MBOWNER_V(x) ((x) << MBOWNER_S)1111#define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)1112 1113#define CIM_PF_HOST_INT_ENABLE_A 0x2881114 1115#define MBMSGRDYINTEN_S 191116#define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)1117#define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U)1118 1119#define CIM_PF_HOST_INT_CAUSE_A 0x28c1120 1121#define MBMSGRDYINT_S 191122#define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)1123#define MBMSGRDYINT_F MBMSGRDYINT_V(1U)1124 1125#define CIM_HOST_INT_CAUSE_A 0x7b2c1126 1127#define TIEQOUTPARERRINT_S 201128#define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)1129#define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U)1130 1131#define TIEQINPARERRINT_S 191132#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)1133#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)1134 1135#define TIMER0INT_S 21136#define TIMER0INT_V(x) ((x) << TIMER0INT_S)1137#define TIMER0INT_F TIMER0INT_V(1U)1138 1139#define PREFDROPINT_S 11140#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)1141#define PREFDROPINT_F PREFDROPINT_V(1U)1142 1143#define UPACCNONZERO_S 01144#define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)1145#define UPACCNONZERO_F UPACCNONZERO_V(1U)1146 1147#define MBHOSTPARERR_S 181148#define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)1149#define MBHOSTPARERR_F MBHOSTPARERR_V(1U)1150 1151#define MBUPPARERR_S 171152#define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)1153#define MBUPPARERR_F MBUPPARERR_V(1U)1154 1155#define IBQTP0PARERR_S 161156#define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)1157#define IBQTP0PARERR_F IBQTP0PARERR_V(1U)1158 1159#define IBQTP1PARERR_S 151160#define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)1161#define IBQTP1PARERR_F IBQTP1PARERR_V(1U)1162 1163#define IBQULPPARERR_S 141164#define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)1165#define IBQULPPARERR_F IBQULPPARERR_V(1U)1166 1167#define IBQSGELOPARERR_S 131168#define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)1169#define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U)1170 1171#define IBQSGEHIPARERR_S 121172#define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)1173#define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U)1174 1175#define IBQNCSIPARERR_S 111176#define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)1177#define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U)1178 1179#define OBQULP0PARERR_S 101180#define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)1181#define OBQULP0PARERR_F OBQULP0PARERR_V(1U)1182 1183#define OBQULP1PARERR_S 91184#define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)1185#define OBQULP1PARERR_F OBQULP1PARERR_V(1U)1186 1187#define OBQULP2PARERR_S 81188#define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)1189#define OBQULP2PARERR_F OBQULP2PARERR_V(1U)1190 1191#define OBQULP3PARERR_S 71192#define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)1193#define OBQULP3PARERR_F OBQULP3PARERR_V(1U)1194 1195#define OBQSGEPARERR_S 61196#define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)1197#define OBQSGEPARERR_F OBQSGEPARERR_V(1U)1198 1199#define OBQNCSIPARERR_S 51200#define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)1201#define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U)1202 1203#define CIM_HOST_UPACC_INT_CAUSE_A 0x7b341204 1205#define EEPROMWRINT_S 301206#define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)1207#define EEPROMWRINT_F EEPROMWRINT_V(1U)1208 1209#define TIMEOUTMAINT_S 291210#define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)1211#define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U)1212 1213#define TIMEOUTINT_S 281214#define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)1215#define TIMEOUTINT_F TIMEOUTINT_V(1U)1216 1217#define RSPOVRLOOKUPINT_S 271218#define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)1219#define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U)1220 1221#define REQOVRLOOKUPINT_S 261222#define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)1223#define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U)1224 1225#define BLKWRPLINT_S 251226#define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)1227#define BLKWRPLINT_F BLKWRPLINT_V(1U)1228 1229#define BLKRDPLINT_S 241230#define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)1231#define BLKRDPLINT_F BLKRDPLINT_V(1U)1232 1233#define SGLWRPLINT_S 231234#define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)1235#define SGLWRPLINT_F SGLWRPLINT_V(1U)1236 1237#define SGLRDPLINT_S 221238#define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)1239#define SGLRDPLINT_F SGLRDPLINT_V(1U)1240 1241#define BLKWRCTLINT_S 211242#define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)1243#define BLKWRCTLINT_F BLKWRCTLINT_V(1U)1244 1245#define BLKRDCTLINT_S 201246#define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)1247#define BLKRDCTLINT_F BLKRDCTLINT_V(1U)1248 1249#define SGLWRCTLINT_S 191250#define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)1251#define SGLWRCTLINT_F SGLWRCTLINT_V(1U)1252 1253#define SGLRDCTLINT_S 181254#define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)1255#define SGLRDCTLINT_F SGLRDCTLINT_V(1U)1256 1257#define BLKWREEPROMINT_S 171258#define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)1259#define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U)1260 1261#define BLKRDEEPROMINT_S 161262#define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)1263#define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U)1264 1265#define SGLWREEPROMINT_S 151266#define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)1267#define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U)1268 1269#define SGLRDEEPROMINT_S 141270#define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)1271#define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U)1272 1273#define BLKWRFLASHINT_S 131274#define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)1275#define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U)1276 1277#define BLKRDFLASHINT_S 121278#define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)1279#define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U)1280 1281#define SGLWRFLASHINT_S 111282#define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)1283#define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U)1284 1285#define SGLRDFLASHINT_S 101286#define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)1287#define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U)1288 1289#define BLKWRBOOTINT_S 91290#define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)1291#define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U)1292 1293#define BLKRDBOOTINT_S 81294#define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)1295#define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U)1296 1297#define SGLWRBOOTINT_S 71298#define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)1299#define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U)1300 1301#define SGLRDBOOTINT_S 61302#define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)1303#define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U)1304 1305#define ILLWRBEINT_S 51306#define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)1307#define ILLWRBEINT_F ILLWRBEINT_V(1U)1308 1309#define ILLRDBEINT_S 41310#define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)1311#define ILLRDBEINT_F ILLRDBEINT_V(1U)1312 1313#define ILLRDINT_S 31314#define ILLRDINT_V(x) ((x) << ILLRDINT_S)1315#define ILLRDINT_F ILLRDINT_V(1U)1316 1317#define ILLWRINT_S 21318#define ILLWRINT_V(x) ((x) << ILLWRINT_S)1319#define ILLWRINT_F ILLWRINT_V(1U)1320 1321#define ILLTRANSINT_S 11322#define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)1323#define ILLTRANSINT_F ILLTRANSINT_V(1U)1324 1325#define RSVDSPACEINT_S 01326#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)1327#define RSVDSPACEINT_F RSVDSPACEINT_V(1U)1328 1329/* registers for module TP */1330#define DBGLAWHLF_S 231331#define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)1332#define DBGLAWHLF_F DBGLAWHLF_V(1U)1333 1334#define DBGLAWPTR_S 161335#define DBGLAWPTR_M 0x7fU1336#define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M)1337 1338#define DBGLAENABLE_S 121339#define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S)1340#define DBGLAENABLE_F DBGLAENABLE_V(1U)1341 1342#define DBGLARPTR_S 01343#define DBGLARPTR_M 0x7fU1344#define DBGLARPTR_V(x) ((x) << DBGLARPTR_S)1345 1346#define CRXPKTENC_S 31347#define CRXPKTENC_V(x) ((x) << CRXPKTENC_S)1348#define CRXPKTENC_F CRXPKTENC_V(1U)1349 1350#define TP_DBG_LA_DATAL_A 0x7ed81351#define TP_DBG_LA_CONFIG_A 0x7ed41352#define TP_OUT_CONFIG_A 0x7d041353#define TP_GLOBAL_CONFIG_A 0x7d081354 1355#define ACTIVEFILTERCOUNTS_S 221356#define ACTIVEFILTERCOUNTS_V(x) ((x) << ACTIVEFILTERCOUNTS_S)1357#define ACTIVEFILTERCOUNTS_F ACTIVEFILTERCOUNTS_V(1U)1358 1359#define TP_CMM_TCB_BASE_A 0x7d101360#define TP_CMM_MM_BASE_A 0x7d141361#define TP_CMM_TIMER_BASE_A 0x7d181362#define TP_PMM_TX_BASE_A 0x7d201363#define TP_PMM_RX_BASE_A 0x7d281364#define TP_PMM_RX_PAGE_SIZE_A 0x7d2c1365#define TP_PMM_RX_MAX_PAGE_A 0x7d301366#define TP_PMM_TX_PAGE_SIZE_A 0x7d341367#define TP_PMM_TX_MAX_PAGE_A 0x7d381368#define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c1369 1370#define PMRXNUMCHN_S 311371#define PMRXNUMCHN_V(x) ((x) << PMRXNUMCHN_S)1372#define PMRXNUMCHN_F PMRXNUMCHN_V(1U)1373 1374#define PMTXNUMCHN_S 301375#define PMTXNUMCHN_M 0x3U1376#define PMTXNUMCHN_G(x) (((x) >> PMTXNUMCHN_S) & PMTXNUMCHN_M)1377 1378#define PMTXMAXPAGE_S 01379#define PMTXMAXPAGE_M 0x1fffffU1380#define PMTXMAXPAGE_G(x) (((x) >> PMTXMAXPAGE_S) & PMTXMAXPAGE_M)1381 1382#define PMRXMAXPAGE_S 01383#define PMRXMAXPAGE_M 0x1fffffU1384#define PMRXMAXPAGE_G(x) (((x) >> PMRXMAXPAGE_S) & PMRXMAXPAGE_M)1385 1386#define DBGLAMODE_S 141387#define DBGLAMODE_M 0x3U1388#define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M)1389 1390#define FIVETUPLELOOKUP_S 171391#define FIVETUPLELOOKUP_M 0x3U1392#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)1393#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)1394 1395#define TP_PARA_REG2_A 0x7d681396 1397#define MAXRXDATA_S 161398#define MAXRXDATA_M 0xffffU1399#define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)1400 1401#define TP_TIMER_RESOLUTION_A 0x7d901402 1403#define TIMERRESOLUTION_S 161404#define TIMERRESOLUTION_M 0xffU1405#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)1406 1407#define TIMESTAMPRESOLUTION_S 81408#define TIMESTAMPRESOLUTION_M 0xffU1409#define TIMESTAMPRESOLUTION_G(x) \1410 (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)1411 1412#define DELAYEDACKRESOLUTION_S 01413#define DELAYEDACKRESOLUTION_M 0xffU1414#define DELAYEDACKRESOLUTION_G(x) \1415 (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)1416 1417#define TP_SHIFT_CNT_A 0x7dc01418#define TP_RXT_MIN_A 0x7d981419#define TP_RXT_MAX_A 0x7d9c1420#define TP_PERS_MIN_A 0x7da01421#define TP_PERS_MAX_A 0x7da41422#define TP_KEEP_IDLE_A 0x7da81423#define TP_KEEP_INTVL_A 0x7dac1424#define TP_INIT_SRTT_A 0x7db01425#define TP_DACK_TIMER_A 0x7db41426#define TP_FINWAIT2_TIMER_A 0x7db81427 1428#define INITSRTT_S 01429#define INITSRTT_M 0xffffU1430#define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)1431 1432#define PERSMAX_S 01433#define PERSMAX_M 0x3fffffffU1434#define PERSMAX_V(x) ((x) << PERSMAX_S)1435#define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)1436 1437#define SYNSHIFTMAX_S 241438#define SYNSHIFTMAX_M 0xffU1439#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)1440#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)1441 1442#define RXTSHIFTMAXR1_S 201443#define RXTSHIFTMAXR1_M 0xfU1444#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)1445#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)1446 1447#define RXTSHIFTMAXR2_S 161448#define RXTSHIFTMAXR2_M 0xfU1449#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)1450#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)1451 1452#define PERSHIFTBACKOFFMAX_S 121453#define PERSHIFTBACKOFFMAX_M 0xfU1454#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)1455#define PERSHIFTBACKOFFMAX_G(x) \1456 (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)1457 1458#define PERSHIFTMAX_S 81459#define PERSHIFTMAX_M 0xfU1460#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)1461#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)1462 1463#define KEEPALIVEMAXR1_S 41464#define KEEPALIVEMAXR1_M 0xfU1465#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)1466#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)1467 1468#define KEEPALIVEMAXR2_S 01469#define KEEPALIVEMAXR2_M 0xfU1470#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)1471#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)1472 1473#define ROWINDEX_S 161474#define ROWINDEX_V(x) ((x) << ROWINDEX_S)1475 1476#define TP_CCTRL_TABLE_A 0x7ddc1477#define TP_PACE_TABLE_A 0x7dd81478#define TP_MTU_TABLE_A 0x7de41479 1480#define MTUINDEX_S 241481#define MTUINDEX_V(x) ((x) << MTUINDEX_S)1482 1483#define MTUWIDTH_S 161484#define MTUWIDTH_M 0xfU1485#define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)1486#define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)1487 1488#define MTUVALUE_S 01489#define MTUVALUE_M 0x3fffU1490#define MTUVALUE_V(x) ((x) << MTUVALUE_S)1491#define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)1492 1493#define TP_RSS_LKP_TABLE_A 0x7dec1494#define TP_CMM_MM_RX_FLST_BASE_A 0x7e601495#define TP_CMM_MM_TX_FLST_BASE_A 0x7e641496#define TP_CMM_MM_PS_FLST_BASE_A 0x7e681497 1498#define LKPTBLROWVLD_S 311499#define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)1500#define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U)1501 1502#define LKPTBLQUEUE1_S 101503#define LKPTBLQUEUE1_M 0x3ffU1504#define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)1505 1506#define LKPTBLQUEUE0_S 01507#define LKPTBLQUEUE0_M 0x3ffU1508#define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)1509 1510#define TP_TM_PIO_ADDR_A 0x7e181511#define TP_TM_PIO_DATA_A 0x7e1c1512#define TP_MOD_CONFIG_A 0x7e241513 1514#define TIMERMODE_S 81515#define TIMERMODE_M 0xffU1516#define TIMERMODE_G(x) (((x) >> TIMERMODE_S) & TIMERMODE_M)1517 1518#define TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A 0x31519#define TP_TX_MOD_Q1_Q0_RATE_LIMIT_A 0x81520 1521#define TP_PIO_ADDR_A 0x7e401522#define TP_PIO_DATA_A 0x7e441523#define TP_MIB_INDEX_A 0x7e501524#define TP_MIB_DATA_A 0x7e541525#define TP_INT_CAUSE_A 0x7e741526 1527#define TP_FLM_FREE_PS_CNT_A 0x7e801528#define TP_FLM_FREE_RX_CNT_A 0x7e841529 1530#define FREEPSTRUCTCOUNT_S 01531#define FREEPSTRUCTCOUNT_M 0x1fffffU1532#define FREEPSTRUCTCOUNT_G(x) (((x) >> FREEPSTRUCTCOUNT_S) & FREEPSTRUCTCOUNT_M)1533 1534#define FREERXPAGECOUNT_S 01535#define FREERXPAGECOUNT_M 0x1fffffU1536#define FREERXPAGECOUNT_V(x) ((x) << FREERXPAGECOUNT_S)1537#define FREERXPAGECOUNT_G(x) (((x) >> FREERXPAGECOUNT_S) & FREERXPAGECOUNT_M)1538 1539#define TP_FLM_FREE_TX_CNT_A 0x7e881540 1541#define FREETXPAGECOUNT_S 01542#define FREETXPAGECOUNT_M 0x1fffffU1543#define FREETXPAGECOUNT_V(x) ((x) << FREETXPAGECOUNT_S)1544#define FREETXPAGECOUNT_G(x) (((x) >> FREETXPAGECOUNT_S) & FREETXPAGECOUNT_M)1545 1546#define FLMTXFLSTEMPTY_S 301547#define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)1548#define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U)1549 1550#define TP_TX_ORATE_A 0x7ebc1551 1552#define OFDRATE3_S 241553#define OFDRATE3_M 0xffU1554#define OFDRATE3_G(x) (((x) >> OFDRATE3_S) & OFDRATE3_M)1555 1556#define OFDRATE2_S 161557#define OFDRATE2_M 0xffU1558#define OFDRATE2_G(x) (((x) >> OFDRATE2_S) & OFDRATE2_M)1559 1560#define OFDRATE1_S 81561#define OFDRATE1_M 0xffU1562#define OFDRATE1_G(x) (((x) >> OFDRATE1_S) & OFDRATE1_M)1563 1564#define OFDRATE0_S 01565#define OFDRATE0_M 0xffU1566#define OFDRATE0_G(x) (((x) >> OFDRATE0_S) & OFDRATE0_M)1567 1568#define TP_TX_TRATE_A 0x7ed01569 1570#define TNLRATE3_S 241571#define TNLRATE3_M 0xffU1572#define TNLRATE3_G(x) (((x) >> TNLRATE3_S) & TNLRATE3_M)1573 1574#define TNLRATE2_S 161575#define TNLRATE2_M 0xffU1576#define TNLRATE2_G(x) (((x) >> TNLRATE2_S) & TNLRATE2_M)1577 1578#define TNLRATE1_S 81579#define TNLRATE1_M 0xffU1580#define TNLRATE1_G(x) (((x) >> TNLRATE1_S) & TNLRATE1_M)1581 1582#define TNLRATE0_S 01583#define TNLRATE0_M 0xffU1584#define TNLRATE0_G(x) (((x) >> TNLRATE0_S) & TNLRATE0_M)1585 1586#define TP_VLAN_PRI_MAP_A 0x1401587 1588#define FRAGMENTATION_S 91589#define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)1590#define FRAGMENTATION_F FRAGMENTATION_V(1U)1591 1592#define MPSHITTYPE_S 81593#define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)1594#define MPSHITTYPE_F MPSHITTYPE_V(1U)1595 1596#define MACMATCH_S 71597#define MACMATCH_V(x) ((x) << MACMATCH_S)1598#define MACMATCH_F MACMATCH_V(1U)1599 1600#define ETHERTYPE_S 61601#define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)1602#define ETHERTYPE_F ETHERTYPE_V(1U)1603 1604#define PROTOCOL_S 51605#define PROTOCOL_V(x) ((x) << PROTOCOL_S)1606#define PROTOCOL_F PROTOCOL_V(1U)1607 1608#define TOS_S 41609#define TOS_V(x) ((x) << TOS_S)1610#define TOS_F TOS_V(1U)1611 1612#define VLAN_S 31613#define VLAN_V(x) ((x) << VLAN_S)1614#define VLAN_F VLAN_V(1U)1615 1616#define VNIC_ID_S 21617#define VNIC_ID_V(x) ((x) << VNIC_ID_S)1618#define VNIC_ID_F VNIC_ID_V(1U)1619 1620#define PORT_S 11621#define PORT_V(x) ((x) << PORT_S)1622#define PORT_F PORT_V(1U)1623 1624#define FCOE_S 01625#define FCOE_V(x) ((x) << FCOE_S)1626#define FCOE_F FCOE_V(1U)1627 1628#define FILTERMODE_S 151629#define FILTERMODE_V(x) ((x) << FILTERMODE_S)1630#define FILTERMODE_F FILTERMODE_V(1U)1631 1632#define FCOEMASK_S 141633#define FCOEMASK_V(x) ((x) << FCOEMASK_S)1634#define FCOEMASK_F FCOEMASK_V(1U)1635 1636#define TP_INGRESS_CONFIG_A 0x1411637 1638#define VNIC_S 111639#define VNIC_V(x) ((x) << VNIC_S)1640#define VNIC_F VNIC_V(1U)1641 1642#define USE_ENC_IDX_S 131643#define USE_ENC_IDX_V(x) ((x) << USE_ENC_IDX_S)1644#define USE_ENC_IDX_F USE_ENC_IDX_V(1U)1645 1646#define CSUM_HAS_PSEUDO_HDR_S 101647#define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)1648#define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U)1649 1650#define TP_MIB_MAC_IN_ERR_0_A 0x01651#define TP_MIB_HDR_IN_ERR_0_A 0x41652#define TP_MIB_TCP_IN_ERR_0_A 0x81653#define TP_MIB_TCP_OUT_RST_A 0xc1654#define TP_MIB_TCP_IN_SEG_HI_A 0x101655#define TP_MIB_TCP_IN_SEG_LO_A 0x111656#define TP_MIB_TCP_OUT_SEG_HI_A 0x121657#define TP_MIB_TCP_OUT_SEG_LO_A 0x131658#define TP_MIB_TCP_RXT_SEG_HI_A 0x141659#define TP_MIB_TCP_RXT_SEG_LO_A 0x151660#define TP_MIB_TNL_CNG_DROP_0_A 0x181661#define TP_MIB_OFD_CHN_DROP_0_A 0x1c1662#define TP_MIB_TCP_V6IN_ERR_0_A 0x281663#define TP_MIB_TCP_V6OUT_RST_A 0x2c1664#define TP_MIB_OFD_ARP_DROP_A 0x361665#define TP_MIB_CPL_IN_REQ_0_A 0x381666#define TP_MIB_CPL_OUT_RSP_0_A 0x3c1667#define TP_MIB_TNL_DROP_0_A 0x441668#define TP_MIB_FCOE_DDP_0_A 0x481669#define TP_MIB_FCOE_DROP_0_A 0x4c1670#define TP_MIB_FCOE_BYTE_0_HI_A 0x501671#define TP_MIB_OFD_VLN_DROP_0_A 0x581672#define TP_MIB_USM_PKTS_A 0x5c1673#define TP_MIB_RQE_DFR_PKT_A 0x641674 1675#define ULP_TX_INT_CAUSE_A 0x8dcc1676#define ULP_TX_TPT_LLIMIT_A 0x8dd41677#define ULP_TX_TPT_ULIMIT_A 0x8dd81678#define ULP_TX_PBL_LLIMIT_A 0x8ddc1679#define ULP_TX_PBL_ULIMIT_A 0x8de01680#define ULP_TX_ERR_TABLE_BASE_A 0x8e041681 1682#define PBL_BOUND_ERR_CH3_S 311683#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)1684#define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U)1685 1686#define PBL_BOUND_ERR_CH2_S 301687#define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)1688#define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U)1689 1690#define PBL_BOUND_ERR_CH1_S 291691#define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)1692#define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U)1693 1694#define PBL_BOUND_ERR_CH0_S 281695#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)1696#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)1697 1698#define PM_RX_INT_CAUSE_A 0x8fdc1699#define PM_RX_STAT_CONFIG_A 0x8fc81700#define PM_RX_STAT_COUNT_A 0x8fcc1701#define PM_RX_STAT_LSB_A 0x8fd01702#define PM_RX_DBG_CTRL_A 0x8fd01703#define PM_RX_DBG_DATA_A 0x8fd41704#define PM_RX_DBG_STAT_MSB_A 0x100131705 1706#define PMRX_FRAMING_ERROR_F 0x003ffff0U1707 1708#define ZERO_E_CMD_ERROR_S 221709#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)1710#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)1711 1712#define OCSPI_PAR_ERROR_S 31713#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)1714#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)1715 1716#define DB_OPTIONS_PAR_ERROR_S 21717#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)1718#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)1719 1720#define IESPI_PAR_ERROR_S 11721#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)1722#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)1723 1724#define ULP_TX_LA_RDPTR_0_A 0x8ec01725#define ULP_TX_LA_RDDATA_0_A 0x8ec41726#define ULP_TX_LA_WRPTR_0_A 0x8ec81727#define ULP_TX_ASIC_DEBUG_CTRL_A 0x8f701728 1729#define ULP_TX_ASIC_DEBUG_0_A 0x8f741730#define ULP_TX_ASIC_DEBUG_1_A 0x8f781731#define ULP_TX_ASIC_DEBUG_2_A 0x8f7c1732#define ULP_TX_ASIC_DEBUG_3_A 0x8f801733#define ULP_TX_ASIC_DEBUG_4_A 0x8f841734 1735/* registers for module PM_RX */1736#define PM_RX_BASE_ADDR 0x8fc01737 1738#define PMRX_E_PCMD_PAR_ERROR_S 01739#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)1740#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)1741 1742#define PM_TX_INT_CAUSE_A 0x8ffc1743#define PM_TX_STAT_CONFIG_A 0x8fe81744#define PM_TX_STAT_COUNT_A 0x8fec1745#define PM_TX_STAT_LSB_A 0x8ff01746#define PM_TX_DBG_CTRL_A 0x8ff01747#define PM_TX_DBG_DATA_A 0x8ff41748#define PM_TX_DBG_STAT_MSB_A 0x1001a1749 1750#define PCMD_LEN_OVFL0_S 311751#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)1752#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)1753 1754#define PCMD_LEN_OVFL1_S 301755#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)1756#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)1757 1758#define PCMD_LEN_OVFL2_S 291759#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)1760#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)1761 1762#define ZERO_C_CMD_ERROR_S 281763#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)1764#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)1765 1766#define PMTX_FRAMING_ERROR_F 0x0ffffff0U1767 1768#define OESPI_PAR_ERROR_S 31769#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)1770#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)1771 1772#define ICSPI_PAR_ERROR_S 11773#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)1774#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)1775 1776#define PMTX_C_PCMD_PAR_ERROR_S 01777#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)1778#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)1779 1780#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x4001781#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x4041782#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x4081783#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c1784#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x4101785#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x4141786#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x4181787#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c1788#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x4201789#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x4241790#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x4281791#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c1792#define MPS_PORT_STAT_TX_PORT_64B_L 0x4301793#define MPS_PORT_STAT_TX_PORT_64B_H 0x4341794#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x4381795#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c1796#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x4401797#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x4441798#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x4481799#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c1800#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x4501801#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x4541802#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x4581803#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c1804#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x4601805#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x4641806#define MPS_PORT_STAT_TX_PORT_DROP_L 0x4681807#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c1808#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x4701809#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x4741810#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x4781811#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c1812#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x4801813#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x4841814#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x4881815#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c1816#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x4901817#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x4941818#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x4981819#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c1820#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a01821#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a41822#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a81823#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac1824#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b01825#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b41826#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c01827#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c41828#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c81829#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc1830#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d01831#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d41832#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d81833#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc1834#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e01835#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e41836#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e81837#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec1838#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f01839#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f41840#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f81841#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc1842#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x5001843#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x5041844#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x5081845#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c1846#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x5101847#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x5141848#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x5181849#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c1850#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x5201851#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x5241852#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x5281853#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x5281854#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x5401855#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x5441856#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x5481857#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c1858#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x5501859#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x5541860#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x5581861#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c1862#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x5601863#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x5641864#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x5681865#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c1866#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x5701867#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x5741868#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x5781869#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c1870#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x5801871#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x5841872#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x5881873#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c1874#define MPS_PORT_STAT_RX_PORT_64B_L 0x5901875#define MPS_PORT_STAT_RX_PORT_64B_H 0x5941876#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x5981877#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c1878#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a01879#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a41880#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a81881#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac1882#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b01883#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b41884#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b81885#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc1886#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c01887#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c41888#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c81889#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc1890#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d01891#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d41892#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d81893#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc1894#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e01895#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e41896#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e81897#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec1898#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f01899#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f41900#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f81901#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc1902#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x6001903#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x6041904#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x6081905#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c1906#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x6101907#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x6141908#define MAC_PORT_MAGIC_MACID_LO 0x8241909#define MAC_PORT_MAGIC_MACID_HI 0x8281910#define MAC_PORT_TX_TS_VAL_LO 0x9281911#define MAC_PORT_TX_TS_VAL_HI 0x92c1912 1913#define MAC_PORT_EPIO_DATA0_A 0x8c01914#define MAC_PORT_EPIO_DATA1_A 0x8c41915#define MAC_PORT_EPIO_DATA2_A 0x8c81916#define MAC_PORT_EPIO_DATA3_A 0x8cc1917#define MAC_PORT_EPIO_OP_A 0x8d01918 1919#define MAC_PORT_CFG2_A 0x8181920 1921#define MAC_PORT_PTP_SUM_LO_A 0x9901922#define MAC_PORT_PTP_SUM_HI_A 0x9941923 1924#define MPS_CMN_CTL_A 0x90001925 1926#define COUNTPAUSEMCRX_S 51927#define COUNTPAUSEMCRX_V(x) ((x) << COUNTPAUSEMCRX_S)1928#define COUNTPAUSEMCRX_F COUNTPAUSEMCRX_V(1U)1929 1930#define COUNTPAUSESTATRX_S 41931#define COUNTPAUSESTATRX_V(x) ((x) << COUNTPAUSESTATRX_S)1932#define COUNTPAUSESTATRX_F COUNTPAUSESTATRX_V(1U)1933 1934#define COUNTPAUSEMCTX_S 31935#define COUNTPAUSEMCTX_V(x) ((x) << COUNTPAUSEMCTX_S)1936#define COUNTPAUSEMCTX_F COUNTPAUSEMCTX_V(1U)1937 1938#define COUNTPAUSESTATTX_S 21939#define COUNTPAUSESTATTX_V(x) ((x) << COUNTPAUSESTATTX_S)1940#define COUNTPAUSESTATTX_F COUNTPAUSESTATTX_V(1U)1941 1942#define NUMPORTS_S 01943#define NUMPORTS_M 0x3U1944#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)1945 1946#define MPS_INT_CAUSE_A 0x90081947#define MPS_TX_INT_CAUSE_A 0x94081948#define MPS_STAT_CTL_A 0x96001949 1950#define FRMERR_S 151951#define FRMERR_V(x) ((x) << FRMERR_S)1952#define FRMERR_F FRMERR_V(1U)1953 1954#define SECNTERR_S 141955#define SECNTERR_V(x) ((x) << SECNTERR_S)1956#define SECNTERR_F SECNTERR_V(1U)1957 1958#define BUBBLE_S 131959#define BUBBLE_V(x) ((x) << BUBBLE_S)1960#define BUBBLE_F BUBBLE_V(1U)1961 1962#define TXDESCFIFO_S 91963#define TXDESCFIFO_M 0xfU1964#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)1965 1966#define TXDATAFIFO_S 51967#define TXDATAFIFO_M 0xfU1968#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)1969 1970#define NCSIFIFO_S 41971#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)1972#define NCSIFIFO_F NCSIFIFO_V(1U)1973 1974#define TPFIFO_S 01975#define TPFIFO_M 0xfU1976#define TPFIFO_V(x) ((x) << TPFIFO_S)1977 1978#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x96141979#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x96201980#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c1981 1982#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x96401983#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x96441984#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x96481985#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c1986#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x96501987#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x96541988#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x96581989#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c1990#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x96601991#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x96641992#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x96681993#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c1994#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x96701995#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x96741996#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x96781997#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c1998#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x96801999#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x96842000#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x96882001#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c2002#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x96902003#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x96942004#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x96982005#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c2006#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a02007#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a42008#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a82009#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac2010#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b02011#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b42012#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b82013#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc2014 2015#define MPS_TRC_CFG_A 0x98002016 2017#define TRCFIFOEMPTY_S 42018#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)2019#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)2020 2021#define TRCIGNOREDROPINPUT_S 32022#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)2023#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)2024 2025#define TRCKEEPDUPLICATES_S 22026#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)2027#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)2028 2029#define TRCEN_S 12030#define TRCEN_V(x) ((x) << TRCEN_S)2031#define TRCEN_F TRCEN_V(1U)2032 2033#define TRCMULTIFILTER_S 02034#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)2035#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)2036 2037#define MPS_TRC_RSS_CONTROL_A 0x98082038#define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff42039#define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc2040#define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa0042041#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c2042 2043#define RSSCONTROL_S 162044#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)2045 2046#define QUEUENUMBER_S 02047#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)2048 2049#define TFINVERTMATCH_S 242050#define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)2051#define TFINVERTMATCH_F TFINVERTMATCH_V(1U)2052 2053#define TFEN_S 222054#define TFEN_V(x) ((x) << TFEN_S)2055#define TFEN_F TFEN_V(1U)2056 2057#define TFPORT_S 182058#define TFPORT_M 0xfU2059#define TFPORT_V(x) ((x) << TFPORT_S)2060#define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)2061 2062#define TFLENGTH_S 82063#define TFLENGTH_M 0x1fU2064#define TFLENGTH_V(x) ((x) << TFLENGTH_S)2065#define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)2066 2067#define TFOFFSET_S 02068#define TFOFFSET_M 0x1fU2069#define TFOFFSET_V(x) ((x) << TFOFFSET_S)2070#define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)2071 2072#define T5_TFINVERTMATCH_S 252073#define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)2074#define T5_TFINVERTMATCH_F T5_TFINVERTMATCH_V(1U)2075 2076#define T5_TFEN_S 232077#define T5_TFEN_V(x) ((x) << T5_TFEN_S)2078#define T5_TFEN_F T5_TFEN_V(1U)2079 2080#define T5_TFPORT_S 182081#define T5_TFPORT_M 0x1fU2082#define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)2083#define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)2084 2085#define MPS_TRC_FILTER_MATCH_CTL_A_A 0x98102086#define MPS_TRC_FILTER_MATCH_CTL_B_A 0x98202087 2088#define TFMINPKTSIZE_S 162089#define TFMINPKTSIZE_M 0x1ffU2090#define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)2091#define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)2092 2093#define TFCAPTUREMAX_S 02094#define TFCAPTUREMAX_M 0x3fffU2095#define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)2096#define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)2097 2098#define MPS_TRC_FILTER0_MATCH_A 0x9c002099#define MPS_TRC_FILTER0_DONT_CARE_A 0x9c802100#define MPS_TRC_FILTER1_MATCH_A 0x9d002101 2102#define TP_RSS_CONFIG_A 0x7df02103 2104#define TNL4TUPENIPV6_S 312105#define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)2106#define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U)2107 2108#define TNL2TUPENIPV6_S 302109#define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)2110#define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U)2111 2112#define TNL4TUPENIPV4_S 292113#define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)2114#define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U)2115 2116#define TNL2TUPENIPV4_S 282117#define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)2118#define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U)2119 2120#define TNLTCPSEL_S 272121#define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)2122#define TNLTCPSEL_F TNLTCPSEL_V(1U)2123 2124#define TNLIP6SEL_S 262125#define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)2126#define TNLIP6SEL_F TNLIP6SEL_V(1U)2127 2128#define TNLVRTSEL_S 252129#define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)2130#define TNLVRTSEL_F TNLVRTSEL_V(1U)2131 2132#define TNLMAPEN_S 242133#define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)2134#define TNLMAPEN_F TNLMAPEN_V(1U)2135 2136#define OFDHASHSAVE_S 192137#define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)2138#define OFDHASHSAVE_F OFDHASHSAVE_V(1U)2139 2140#define OFDVRTSEL_S 182141#define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)2142#define OFDVRTSEL_F OFDVRTSEL_V(1U)2143 2144#define OFDMAPEN_S 172145#define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)2146#define OFDMAPEN_F OFDMAPEN_V(1U)2147 2148#define OFDLKPEN_S 162149#define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)2150#define OFDLKPEN_F OFDLKPEN_V(1U)2151 2152#define SYN4TUPENIPV6_S 152153#define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)2154#define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U)2155 2156#define SYN2TUPENIPV6_S 142157#define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)2158#define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U)2159 2160#define SYN4TUPENIPV4_S 132161#define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)2162#define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U)2163 2164#define SYN2TUPENIPV4_S 122165#define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)2166#define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U)2167 2168#define SYNIP6SEL_S 112169#define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)2170#define SYNIP6SEL_F SYNIP6SEL_V(1U)2171 2172#define SYNVRTSEL_S 102173#define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)2174#define SYNVRTSEL_F SYNVRTSEL_V(1U)2175 2176#define SYNMAPEN_S 92177#define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)2178#define SYNMAPEN_F SYNMAPEN_V(1U)2179 2180#define SYNLKPEN_S 82181#define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)2182#define SYNLKPEN_F SYNLKPEN_V(1U)2183 2184#define CHANNELENABLE_S 72185#define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)2186#define CHANNELENABLE_F CHANNELENABLE_V(1U)2187 2188#define PORTENABLE_S 62189#define PORTENABLE_V(x) ((x) << PORTENABLE_S)2190#define PORTENABLE_F PORTENABLE_V(1U)2191 2192#define TNLALLLOOKUP_S 52193#define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)2194#define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U)2195 2196#define VIRTENABLE_S 42197#define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)2198#define VIRTENABLE_F VIRTENABLE_V(1U)2199 2200#define CONGESTIONENABLE_S 32201#define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)2202#define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U)2203 2204#define HASHTOEPLITZ_S 22205#define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)2206#define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U)2207 2208#define UDPENABLE_S 12209#define UDPENABLE_V(x) ((x) << UDPENABLE_S)2210#define UDPENABLE_F UDPENABLE_V(1U)2211 2212#define DISABLE_S 02213#define DISABLE_V(x) ((x) << DISABLE_S)2214#define DISABLE_F DISABLE_V(1U)2215 2216#define TP_RSS_CONFIG_TNL_A 0x7df42217 2218#define MASKSIZE_S 282219#define MASKSIZE_M 0xfU2220#define MASKSIZE_V(x) ((x) << MASKSIZE_S)2221#define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)2222 2223#define MASKFILTER_S 162224#define MASKFILTER_M 0x7ffU2225#define MASKFILTER_V(x) ((x) << MASKFILTER_S)2226#define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)2227 2228#define USEWIRECH_S 02229#define USEWIRECH_V(x) ((x) << USEWIRECH_S)2230#define USEWIRECH_F USEWIRECH_V(1U)2231 2232#define HASHALL_S 22233#define HASHALL_V(x) ((x) << HASHALL_S)2234#define HASHALL_F HASHALL_V(1U)2235 2236#define HASHETH_S 12237#define HASHETH_V(x) ((x) << HASHETH_S)2238#define HASHETH_F HASHETH_V(1U)2239 2240#define TP_RSS_CONFIG_OFD_A 0x7df82241 2242#define RRCPLMAPEN_S 202243#define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)2244#define RRCPLMAPEN_F RRCPLMAPEN_V(1U)2245 2246#define RRCPLQUEWIDTH_S 162247#define RRCPLQUEWIDTH_M 0xfU2248#define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)2249#define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)2250 2251#define TP_RSS_CONFIG_SYN_A 0x7dfc2252#define TP_RSS_CONFIG_VRT_A 0x7e002253 2254#define VFRDRG_S 252255#define VFRDRG_V(x) ((x) << VFRDRG_S)2256#define VFRDRG_F VFRDRG_V(1U)2257 2258#define VFRDEN_S 242259#define VFRDEN_V(x) ((x) << VFRDEN_S)2260#define VFRDEN_F VFRDEN_V(1U)2261 2262#define VFPERREN_S 232263#define VFPERREN_V(x) ((x) << VFPERREN_S)2264#define VFPERREN_F VFPERREN_V(1U)2265 2266#define KEYPERREN_S 222267#define KEYPERREN_V(x) ((x) << KEYPERREN_S)2268#define KEYPERREN_F KEYPERREN_V(1U)2269 2270#define DISABLEVLAN_S 212271#define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)2272#define DISABLEVLAN_F DISABLEVLAN_V(1U)2273 2274#define ENABLEUP0_S 202275#define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)2276#define ENABLEUP0_F ENABLEUP0_V(1U)2277 2278#define HASHDELAY_S 162279#define HASHDELAY_M 0xfU2280#define HASHDELAY_V(x) ((x) << HASHDELAY_S)2281#define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)2282 2283#define VFWRADDR_S 82284#define VFWRADDR_M 0x7fU2285#define VFWRADDR_V(x) ((x) << VFWRADDR_S)2286#define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)2287 2288#define KEYMODE_S 62289#define KEYMODE_M 0x3U2290#define KEYMODE_V(x) ((x) << KEYMODE_S)2291#define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)2292 2293#define VFWREN_S 52294#define VFWREN_V(x) ((x) << VFWREN_S)2295#define VFWREN_F VFWREN_V(1U)2296 2297#define KEYWREN_S 42298#define KEYWREN_V(x) ((x) << KEYWREN_S)2299#define KEYWREN_F KEYWREN_V(1U)2300 2301#define KEYWRADDR_S 02302#define KEYWRADDR_M 0xfU2303#define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)2304#define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)2305 2306#define KEYWRADDRX_S 302307#define KEYWRADDRX_M 0x3U2308#define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)2309#define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)2310 2311#define KEYEXTEND_S 262312#define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)2313#define KEYEXTEND_F KEYEXTEND_V(1U)2314 2315#define LKPIDXSIZE_S 242316#define LKPIDXSIZE_M 0x3U2317#define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)2318#define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)2319 2320#define TP_RSS_VFL_CONFIG_A 0x3a2321#define TP_RSS_VFH_CONFIG_A 0x3b2322 2323#define ENABLEUDPHASH_S 312324#define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)2325#define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U)2326 2327#define VFUPEN_S 302328#define VFUPEN_V(x) ((x) << VFUPEN_S)2329#define VFUPEN_F VFUPEN_V(1U)2330 2331#define VFVLNEX_S 282332#define VFVLNEX_V(x) ((x) << VFVLNEX_S)2333#define VFVLNEX_F VFVLNEX_V(1U)2334 2335#define VFPRTEN_S 272336#define VFPRTEN_V(x) ((x) << VFPRTEN_S)2337#define VFPRTEN_F VFPRTEN_V(1U)2338 2339#define VFCHNEN_S 262340#define VFCHNEN_V(x) ((x) << VFCHNEN_S)2341#define VFCHNEN_F VFCHNEN_V(1U)2342 2343#define DEFAULTQUEUE_S 162344#define DEFAULTQUEUE_M 0x3ffU2345#define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)2346 2347#define VFIP6TWOTUPEN_S 62348#define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)2349#define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U)2350 2351#define VFIP4FOURTUPEN_S 52352#define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)2353#define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U)2354 2355#define VFIP4TWOTUPEN_S 42356#define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)2357#define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U)2358 2359#define KEYINDEX_S 02360#define KEYINDEX_M 0xfU2361#define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)2362 2363#define MAPENABLE_S 312364#define MAPENABLE_V(x) ((x) << MAPENABLE_S)2365#define MAPENABLE_F MAPENABLE_V(1U)2366 2367#define CHNENABLE_S 302368#define CHNENABLE_V(x) ((x) << CHNENABLE_S)2369#define CHNENABLE_F CHNENABLE_V(1U)2370 2371#define LE_DB_DBGI_CONFIG_A 0x19cf02372 2373#define DBGICMDBUSY_S 32374#define DBGICMDBUSY_V(x) ((x) << DBGICMDBUSY_S)2375#define DBGICMDBUSY_F DBGICMDBUSY_V(1U)2376 2377#define DBGICMDSTRT_S 22378#define DBGICMDSTRT_V(x) ((x) << DBGICMDSTRT_S)2379#define DBGICMDSTRT_F DBGICMDSTRT_V(1U)2380 2381#define DBGICMDMODE_S 02382#define DBGICMDMODE_M 0x3U2383#define DBGICMDMODE_V(x) ((x) << DBGICMDMODE_S)2384 2385#define LE_DB_DBGI_REQ_TCAM_CMD_A 0x19cf42386 2387#define DBGICMD_S 202388#define DBGICMD_M 0xfU2389#define DBGICMD_V(x) ((x) << DBGICMD_S)2390 2391#define DBGITID_S 02392#define DBGITID_M 0xfffffU2393#define DBGITID_V(x) ((x) << DBGITID_S)2394 2395#define LE_DB_DBGI_REQ_DATA_A 0x19d002396#define LE_DB_DBGI_RSP_STATUS_A 0x19d942397 2398#define LE_DB_DBGI_RSP_DATA_A 0x19da02399 2400#define PRTENABLE_S 292401#define PRTENABLE_V(x) ((x) << PRTENABLE_S)2402#define PRTENABLE_F PRTENABLE_V(1U)2403 2404#define UDPFOURTUPEN_S 282405#define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)2406#define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U)2407 2408#define IP6FOURTUPEN_S 272409#define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)2410#define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U)2411 2412#define IP6TWOTUPEN_S 262413#define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)2414#define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U)2415 2416#define IP4FOURTUPEN_S 252417#define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)2418#define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U)2419 2420#define IP4TWOTUPEN_S 242421#define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)2422#define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U)2423 2424#define IVFWIDTH_S 202425#define IVFWIDTH_M 0xfU2426#define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)2427#define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)2428 2429#define CH1DEFAULTQUEUE_S 102430#define CH1DEFAULTQUEUE_M 0x3ffU2431#define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)2432#define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)2433 2434#define CH0DEFAULTQUEUE_S 02435#define CH0DEFAULTQUEUE_M 0x3ffU2436#define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)2437#define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)2438 2439#define VFLKPIDX_S 82440#define VFLKPIDX_M 0xffU2441#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)2442 2443#define T6_VFWRADDR_S 82444#define T6_VFWRADDR_M 0xffU2445#define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)2446#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)2447 2448#define TP_RSS_CONFIG_CNG_A 0x7e042449#define TP_RSS_SECRET_KEY0_A 0x402450#define TP_RSS_PF0_CONFIG_A 0x302451#define TP_RSS_PF_MAP_A 0x382452#define TP_RSS_PF_MSK_A 0x392453 2454#define PF1LKPIDX_S 32455 2456#define PF0LKPIDX_M 0x7U2457 2458#define PF1MSKSIZE_S 42459#define PF1MSKSIZE_M 0xfU2460 2461#define CHNCOUNT3_S 312462#define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)2463#define CHNCOUNT3_F CHNCOUNT3_V(1U)2464 2465#define CHNCOUNT2_S 302466#define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)2467#define CHNCOUNT2_F CHNCOUNT2_V(1U)2468 2469#define CHNCOUNT1_S 292470#define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)2471#define CHNCOUNT1_F CHNCOUNT1_V(1U)2472 2473#define CHNCOUNT0_S 282474#define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)2475#define CHNCOUNT0_F CHNCOUNT0_V(1U)2476 2477#define CHNUNDFLOW3_S 272478#define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)2479#define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U)2480 2481#define CHNUNDFLOW2_S 262482#define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)2483#define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U)2484 2485#define CHNUNDFLOW1_S 252486#define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)2487#define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U)2488 2489#define CHNUNDFLOW0_S 242490#define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)2491#define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U)2492 2493#define RSTCHN3_S 192494#define RSTCHN3_V(x) ((x) << RSTCHN3_S)2495#define RSTCHN3_F RSTCHN3_V(1U)2496 2497#define RSTCHN2_S 182498#define RSTCHN2_V(x) ((x) << RSTCHN2_S)2499#define RSTCHN2_F RSTCHN2_V(1U)2500 2501#define RSTCHN1_S 172502#define RSTCHN1_V(x) ((x) << RSTCHN1_S)2503#define RSTCHN1_F RSTCHN1_V(1U)2504 2505#define RSTCHN0_S 162506#define RSTCHN0_V(x) ((x) << RSTCHN0_S)2507#define RSTCHN0_F RSTCHN0_V(1U)2508 2509#define UPDVLD_S 152510#define UPDVLD_V(x) ((x) << UPDVLD_S)2511#define UPDVLD_F UPDVLD_V(1U)2512 2513#define XOFF_S 142514#define XOFF_V(x) ((x) << XOFF_S)2515#define XOFF_F XOFF_V(1U)2516 2517#define UPDCHN3_S 132518#define UPDCHN3_V(x) ((x) << UPDCHN3_S)2519#define UPDCHN3_F UPDCHN3_V(1U)2520 2521#define UPDCHN2_S 122522#define UPDCHN2_V(x) ((x) << UPDCHN2_S)2523#define UPDCHN2_F UPDCHN2_V(1U)2524 2525#define UPDCHN1_S 112526#define UPDCHN1_V(x) ((x) << UPDCHN1_S)2527#define UPDCHN1_F UPDCHN1_V(1U)2528 2529#define UPDCHN0_S 102530#define UPDCHN0_V(x) ((x) << UPDCHN0_S)2531#define UPDCHN0_F UPDCHN0_V(1U)2532 2533#define QUEUE_S 02534#define QUEUE_M 0x3ffU2535#define QUEUE_V(x) ((x) << QUEUE_S)2536#define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)2537 2538#define MPS_TRC_INT_CAUSE_A 0x985c2539 2540#define MISCPERR_S 82541#define MISCPERR_V(x) ((x) << MISCPERR_S)2542#define MISCPERR_F MISCPERR_V(1U)2543 2544#define PKTFIFO_S 42545#define PKTFIFO_M 0xfU2546#define PKTFIFO_V(x) ((x) << PKTFIFO_S)2547 2548#define FILTMEM_S 02549#define FILTMEM_M 0xfU2550#define FILTMEM_V(x) ((x) << FILTMEM_S)2551 2552#define MPS_CLS_INT_CAUSE_A 0xd0282553 2554#define HASHSRAM_S 22555#define HASHSRAM_V(x) ((x) << HASHSRAM_S)2556#define HASHSRAM_F HASHSRAM_V(1U)2557 2558#define MATCHTCAM_S 12559#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)2560#define MATCHTCAM_F MATCHTCAM_V(1U)2561 2562#define MATCHSRAM_S 02563#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)2564#define MATCHSRAM_F MATCHSRAM_V(1U)2565 2566#define MPS_RX_PG_RSV0_A 0x110102567#define MPS_RX_PG_RSV4_A 0x110202568#define MPS_RX_PERR_INT_CAUSE_A 0x110742569#define MPS_RX_MAC_BG_PG_CNT0_A 0x112082570#define MPS_RX_LPBK_BG_PG_CNT0_A 0x112182571 2572#define MPS_RX_VXLAN_TYPE_A 0x112342573 2574#define VXLAN_EN_S 162575#define VXLAN_EN_V(x) ((x) << VXLAN_EN_S)2576#define VXLAN_EN_F VXLAN_EN_V(1U)2577 2578#define VXLAN_S 02579#define VXLAN_M 0xffffU2580#define VXLAN_V(x) ((x) << VXLAN_S)2581#define VXLAN_G(x) (((x) >> VXLAN_S) & VXLAN_M)2582 2583#define MPS_RX_GENEVE_TYPE_A 0x112382584 2585#define GENEVE_EN_S 162586#define GENEVE_EN_V(x) ((x) << GENEVE_EN_S)2587#define GENEVE_EN_F GENEVE_EN_V(1U)2588 2589#define GENEVE_S 02590#define GENEVE_M 0xffffU2591#define GENEVE_V(x) ((x) << GENEVE_S)2592#define GENEVE_G(x) (((x) >> GENEVE_S) & GENEVE_M)2593 2594#define MPS_CLS_TCAM_Y_L_A 0xf0002595#define MPS_CLS_TCAM_DATA0_A 0xf0002596#define MPS_CLS_TCAM_DATA1_A 0xf0042597 2598#define CTLREQID_S 302599#define CTLREQID_V(x) ((x) << CTLREQID_S)2600 2601#define MPS_VF_RPLCT_MAP0_A 0x1111c2602#define MPS_VF_RPLCT_MAP1_A 0x111202603#define MPS_VF_RPLCT_MAP2_A 0x111242604#define MPS_VF_RPLCT_MAP3_A 0x111282605#define MPS_VF_RPLCT_MAP4_A 0x113002606#define MPS_VF_RPLCT_MAP5_A 0x113042607#define MPS_VF_RPLCT_MAP6_A 0x113082608#define MPS_VF_RPLCT_MAP7_A 0x1130c2609 2610#define VIDL_S 162611#define VIDL_M 0xffffU2612#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)2613 2614#define DATALKPTYPE_S 102615#define DATALKPTYPE_M 0x3U2616#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)2617 2618#define DATAPORTNUM_S 122619#define DATAPORTNUM_M 0xfU2620#define DATAPORTNUM_V(x) ((x) << DATAPORTNUM_S)2621#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)2622 2623#define DATALKPTYPE_S 102624#define DATALKPTYPE_M 0x3U2625#define DATALKPTYPE_V(x) ((x) << DATALKPTYPE_S)2626#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)2627 2628#define DATADIPHIT_S 82629#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)2630#define DATADIPHIT_F DATADIPHIT_V(1U)2631 2632#define DATAVIDH2_S 72633#define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)2634#define DATAVIDH2_F DATAVIDH2_V(1U)2635 2636#define DATAVIDH1_S 02637#define DATAVIDH1_M 0x7fU2638#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)2639 2640#define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf0202641#define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf0242642#define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf0282643 2644#define USED_S 162645#define USED_M 0x7ffU2646#define USED_G(x) (((x) >> USED_S) & USED_M)2647 2648#define ALLOC_S 02649#define ALLOC_M 0x7ffU2650#define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)2651 2652#define T5_USED_S 162653#define T5_USED_M 0xfffU2654#define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)2655 2656#define T5_ALLOC_S 02657#define T5_ALLOC_M 0xfffU2658#define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)2659 2660#define DMACH_S 02661#define DMACH_M 0xffffU2662#define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)2663 2664#define MPS_CLS_TCAM_X_L_A 0xf0082665#define MPS_CLS_TCAM_DATA2_CTL_A 0xf0082666 2667#define CTLCMDTYPE_S 312668#define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)2669#define CTLCMDTYPE_F CTLCMDTYPE_V(1U)2670 2671#define CTLTCAMSEL_S 252672#define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)2673 2674#define CTLTCAMINDEX_S 172675#define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)2676 2677#define CTLXYBITSEL_S 162678#define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)2679 2680#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)2681#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 5122682 2683#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)2684#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 5122685 2686#define MPS_CLS_SRAM_L_A 0xe0002687 2688#define T6_MULTILISTEN0_S 262689 2690#define T6_SRAM_PRIO3_S 232691#define T6_SRAM_PRIO3_M 0x7U2692#define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)2693 2694#define T6_SRAM_PRIO2_S 202695#define T6_SRAM_PRIO2_M 0x7U2696#define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)2697 2698#define T6_SRAM_PRIO1_S 172699#define T6_SRAM_PRIO1_M 0x7U2700#define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)2701 2702#define T6_SRAM_PRIO0_S 142703#define T6_SRAM_PRIO0_M 0x7U2704#define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)2705 2706#define T6_SRAM_VLD_S 132707#define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)2708#define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U)2709 2710#define T6_REPLICATE_S 122711#define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)2712#define T6_REPLICATE_F T6_REPLICATE_V(1U)2713 2714#define T6_PF_S 92715#define T6_PF_M 0x7U2716#define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)2717 2718#define T6_VF_VALID_S 82719#define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)2720#define T6_VF_VALID_F T6_VF_VALID_V(1U)2721 2722#define T6_VF_S 02723#define T6_VF_M 0xffU2724#define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)2725 2726#define MPS_CLS_SRAM_H_A 0xe0042727 2728#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)2729#define NUM_MPS_CLS_SRAM_L_INSTANCES 3362730 2731#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)2732#define NUM_MPS_CLS_SRAM_H_INSTANCES 3362733 2734#define MULTILISTEN0_S 252735 2736#define REPLICATE_S 112737#define REPLICATE_V(x) ((x) << REPLICATE_S)2738#define REPLICATE_F REPLICATE_V(1U)2739 2740#define PF_S 82741#define PF_M 0x7U2742#define PF_G(x) (((x) >> PF_S) & PF_M)2743 2744#define VF_VALID_S 72745#define VF_VALID_V(x) ((x) << VF_VALID_S)2746#define VF_VALID_F VF_VALID_V(1U)2747 2748#define VF_S 02749#define VF_M 0x7fU2750#define VF_G(x) (((x) >> VF_S) & VF_M)2751 2752#define SRAM_PRIO3_S 222753#define SRAM_PRIO3_M 0x7U2754#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)2755 2756#define SRAM_PRIO2_S 192757#define SRAM_PRIO2_M 0x7U2758#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)2759 2760#define SRAM_PRIO1_S 162761#define SRAM_PRIO1_M 0x7U2762#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)2763 2764#define SRAM_PRIO0_S 132765#define SRAM_PRIO0_M 0x7U2766#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)2767 2768#define SRAM_VLD_S 122769#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)2770#define SRAM_VLD_F SRAM_VLD_V(1U)2771 2772#define PORTMAP_S 02773#define PORTMAP_M 0xfU2774#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)2775 2776#define CPL_INTR_CAUSE_A 0x190542777 2778#define CIM_OP_MAP_PERR_S 52779#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)2780#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)2781 2782#define CIM_OVFL_ERROR_S 42783#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)2784#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)2785 2786#define TP_FRAMING_ERROR_S 32787#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)2788#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)2789 2790#define SGE_FRAMING_ERROR_S 22791#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)2792#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)2793 2794#define CIM_FRAMING_ERROR_S 12795#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)2796#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)2797 2798#define ZERO_SWITCH_ERROR_S 02799#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)2800#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)2801 2802#define SMB_INT_CAUSE_A 0x190902803 2804#define MSTTXFIFOPARINT_S 212805#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)2806#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)2807 2808#define MSTRXFIFOPARINT_S 202809#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)2810#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)2811 2812#define SLVFIFOPARINT_S 192813#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)2814#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)2815 2816#define ULP_RX_INT_CAUSE_A 0x191582817#define ULP_RX_ISCSI_LLIMIT_A 0x1915c2818#define ULP_RX_ISCSI_ULIMIT_A 0x191602819#define ULP_RX_ISCSI_TAGMASK_A 0x191642820#define ULP_RX_ISCSI_PSZ_A 0x191682821#define ULP_RX_TDDP_LLIMIT_A 0x1916c2822#define ULP_RX_TDDP_ULIMIT_A 0x191702823#define ULP_RX_STAG_LLIMIT_A 0x1917c2824#define ULP_RX_STAG_ULIMIT_A 0x191802825#define ULP_RX_RQ_LLIMIT_A 0x191842826#define ULP_RX_RQ_ULIMIT_A 0x191882827#define ULP_RX_PBL_LLIMIT_A 0x1918c2828#define ULP_RX_PBL_ULIMIT_A 0x191902829#define ULP_RX_CTX_BASE_A 0x191942830#define ULP_RX_RQUDP_LLIMIT_A 0x191a42831#define ULP_RX_RQUDP_ULIMIT_A 0x191a82832#define ULP_RX_LA_CTL_A 0x1923c2833#define ULP_RX_LA_RDPTR_A 0x192402834#define ULP_RX_LA_RDDATA_A 0x192442835#define ULP_RX_LA_WRPTR_A 0x192482836#define ULP_RX_TLS_KEY_LLIMIT_A 0x192ac2837#define ULP_RX_TLS_KEY_ULIMIT_A 0x192b02838 2839#define HPZ3_S 242840#define HPZ3_V(x) ((x) << HPZ3_S)2841 2842#define HPZ2_S 162843#define HPZ2_V(x) ((x) << HPZ2_S)2844 2845#define HPZ1_S 82846#define HPZ1_V(x) ((x) << HPZ1_S)2847 2848#define HPZ0_S 02849#define HPZ0_V(x) ((x) << HPZ0_S)2850 2851#define ULP_RX_TDDP_PSZ_A 0x191782852 2853/* registers for module SF */2854#define SF_DATA_A 0x193f82855#define SF_OP_A 0x193fc2856 2857#define SF_BUSY_S 312858#define SF_BUSY_V(x) ((x) << SF_BUSY_S)2859#define SF_BUSY_F SF_BUSY_V(1U)2860 2861#define SF_LOCK_S 42862#define SF_LOCK_V(x) ((x) << SF_LOCK_S)2863#define SF_LOCK_F SF_LOCK_V(1U)2864 2865#define SF_CONT_S 32866#define SF_CONT_V(x) ((x) << SF_CONT_S)2867#define SF_CONT_F SF_CONT_V(1U)2868 2869#define BYTECNT_S 12870#define BYTECNT_V(x) ((x) << BYTECNT_S)2871 2872#define OP_S 02873#define OP_V(x) ((x) << OP_S)2874#define OP_F OP_V(1U)2875 2876#define PL_PF_INT_CAUSE_A 0x3c02877 2878#define PFSW_S 32879#define PFSW_V(x) ((x) << PFSW_S)2880#define PFSW_F PFSW_V(1U)2881 2882#define PFCIM_S 12883#define PFCIM_V(x) ((x) << PFCIM_S)2884#define PFCIM_F PFCIM_V(1U)2885 2886#define PL_PF_INT_ENABLE_A 0x3c42887#define PL_PF_CTL_A 0x3c82888 2889#define PL_WHOAMI_A 0x194002890 2891#define SOURCEPF_S 82892#define SOURCEPF_M 0x7U2893#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)2894 2895#define T6_SOURCEPF_S 92896#define T6_SOURCEPF_M 0x7U2897#define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)2898 2899#define PL_INT_CAUSE_A 0x1940c2900 2901#define ULP_TX_S 272902#define ULP_TX_V(x) ((x) << ULP_TX_S)2903#define ULP_TX_F ULP_TX_V(1U)2904 2905#define SGE_S 262906#define SGE_V(x) ((x) << SGE_S)2907#define SGE_F SGE_V(1U)2908 2909#define CPL_SWITCH_S 242910#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)2911#define CPL_SWITCH_F CPL_SWITCH_V(1U)2912 2913#define ULP_RX_S 232914#define ULP_RX_V(x) ((x) << ULP_RX_S)2915#define ULP_RX_F ULP_RX_V(1U)2916 2917#define PM_RX_S 222918#define PM_RX_V(x) ((x) << PM_RX_S)2919#define PM_RX_F PM_RX_V(1U)2920 2921#define PM_TX_S 212922#define PM_TX_V(x) ((x) << PM_TX_S)2923#define PM_TX_F PM_TX_V(1U)2924 2925#define MA_S 202926#define MA_V(x) ((x) << MA_S)2927#define MA_F MA_V(1U)2928 2929#define TP_S 192930#define TP_V(x) ((x) << TP_S)2931#define TP_F TP_V(1U)2932 2933#define LE_S 182934#define LE_V(x) ((x) << LE_S)2935#define LE_F LE_V(1U)2936 2937#define EDC1_S 172938#define EDC1_V(x) ((x) << EDC1_S)2939#define EDC1_F EDC1_V(1U)2940 2941#define EDC0_S 162942#define EDC0_V(x) ((x) << EDC0_S)2943#define EDC0_F EDC0_V(1U)2944 2945#define MC_S 152946#define MC_V(x) ((x) << MC_S)2947#define MC_F MC_V(1U)2948 2949#define PCIE_S 142950#define PCIE_V(x) ((x) << PCIE_S)2951#define PCIE_F PCIE_V(1U)2952 2953#define XGMAC_KR1_S 122954#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)2955#define XGMAC_KR1_F XGMAC_KR1_V(1U)2956 2957#define XGMAC_KR0_S 112958#define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)2959#define XGMAC_KR0_F XGMAC_KR0_V(1U)2960 2961#define XGMAC1_S 102962#define XGMAC1_V(x) ((x) << XGMAC1_S)2963#define XGMAC1_F XGMAC1_V(1U)2964 2965#define XGMAC0_S 92966#define XGMAC0_V(x) ((x) << XGMAC0_S)2967#define XGMAC0_F XGMAC0_V(1U)2968 2969#define SMB_S 82970#define SMB_V(x) ((x) << SMB_S)2971#define SMB_F SMB_V(1U)2972 2973#define SF_S 72974#define SF_V(x) ((x) << SF_S)2975#define SF_F SF_V(1U)2976 2977#define PL_S 62978#define PL_V(x) ((x) << PL_S)2979#define PL_F PL_V(1U)2980 2981#define NCSI_S 52982#define NCSI_V(x) ((x) << NCSI_S)2983#define NCSI_F NCSI_V(1U)2984 2985#define MPS_S 42986#define MPS_V(x) ((x) << MPS_S)2987#define MPS_F MPS_V(1U)2988 2989#define CIM_S 02990#define CIM_V(x) ((x) << CIM_S)2991#define CIM_F CIM_V(1U)2992 2993#define MC1_S 312994#define MC1_V(x) ((x) << MC1_S)2995#define MC1_F MC1_V(1U)2996 2997#define PL_INT_ENABLE_A 0x194102998#define PL_INT_MAP0_A 0x194142999#define PL_RST_A 0x194283000 3001#define PIORST_S 13002#define PIORST_V(x) ((x) << PIORST_S)3003#define PIORST_F PIORST_V(1U)3004 3005#define PIORSTMODE_S 03006#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)3007#define PIORSTMODE_F PIORSTMODE_V(1U)3008 3009#define PL_PL_INT_CAUSE_A 0x194303010 3011#define FATALPERR_S 43012#define FATALPERR_V(x) ((x) << FATALPERR_S)3013#define FATALPERR_F FATALPERR_V(1U)3014 3015#define PERRVFID_S 03016#define PERRVFID_V(x) ((x) << PERRVFID_S)3017#define PERRVFID_F PERRVFID_V(1U)3018 3019#define PL_REV_A 0x1943c3020 3021#define REV_S 03022#define REV_M 0xfU3023#define REV_V(x) ((x) << REV_S)3024#define REV_G(x) (((x) >> REV_S) & REV_M)3025 3026#define HASHTBLMEMCRCERR_S 273027#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)3028#define HASHTBLMEMCRCERR_F HASHTBLMEMCRCERR_V(1U)3029 3030#define CMDTIDERR_S 223031#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)3032#define CMDTIDERR_F CMDTIDERR_V(1U)3033 3034#define T6_UNKNOWNCMD_S 33035#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)3036#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)3037 3038#define T6_LIP0_S 23039#define T6_LIP0_V(x) ((x) << T6_LIP0_S)3040#define T6_LIP0_F T6_LIP0_V(1U)3041 3042#define T6_LIPMISS_S 13043#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)3044#define T6_LIPMISS_F T6_LIPMISS_V(1U)3045 3046#define LE_DB_CONFIG_A 0x19c043047#define LE_DB_ROUTING_TABLE_INDEX_A 0x19c103048#define LE_DB_ACTIVE_TABLE_START_INDEX_A 0x19c103049#define LE_DB_FILTER_TABLE_INDEX_A 0x19c143050#define LE_DB_SERVER_INDEX_A 0x19c183051#define LE_DB_SRVR_START_INDEX_A 0x19c183052#define LE_DB_CLIP_TABLE_INDEX_A 0x19c1c3053#define LE_DB_ACT_CNT_IPV4_A 0x19c203054#define LE_DB_ACT_CNT_IPV6_A 0x19c243055#define LE_DB_HASH_CONFIG_A 0x19c283056 3057#define HASHTIDSIZE_S 163058#define HASHTIDSIZE_M 0x3fU3059#define HASHTIDSIZE_G(x) (((x) >> HASHTIDSIZE_S) & HASHTIDSIZE_M)3060 3061#define HASHTBLSIZE_S 33062#define HASHTBLSIZE_M 0x1ffffU3063#define HASHTBLSIZE_G(x) (((x) >> HASHTBLSIZE_S) & HASHTBLSIZE_M)3064 3065#define LE_DB_HASH_TID_BASE_A 0x19c303066#define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c303067#define LE_DB_INT_CAUSE_A 0x19c3c3068#define LE_DB_CLCAM_TID_BASE_A 0x19df43069#define LE_DB_TID_HASHBASE_A 0x19df83070#define T6_LE_DB_HASH_TID_BASE_A 0x19df83071 3072#define HASHEN_S 203073#define HASHEN_V(x) ((x) << HASHEN_S)3074#define HASHEN_F HASHEN_V(1U)3075 3076#define ASLIPCOMPEN_S 173077#define ASLIPCOMPEN_V(x) ((x) << ASLIPCOMPEN_S)3078#define ASLIPCOMPEN_F ASLIPCOMPEN_V(1U)3079 3080#define REQQPARERR_S 163081#define REQQPARERR_V(x) ((x) << REQQPARERR_S)3082#define REQQPARERR_F REQQPARERR_V(1U)3083 3084#define UNKNOWNCMD_S 153085#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)3086#define UNKNOWNCMD_F UNKNOWNCMD_V(1U)3087 3088#define PARITYERR_S 63089#define PARITYERR_V(x) ((x) << PARITYERR_S)3090#define PARITYERR_F PARITYERR_V(1U)3091 3092#define LIPMISS_S 53093#define LIPMISS_V(x) ((x) << LIPMISS_S)3094#define LIPMISS_F LIPMISS_V(1U)3095 3096#define LIP0_S 43097#define LIP0_V(x) ((x) << LIP0_S)3098#define LIP0_F LIP0_V(1U)3099 3100#define BASEADDR_S 33101#define BASEADDR_M 0x1fffffffU3102#define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M)3103 3104#define TCAMINTPERR_S 133105#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)3106#define TCAMINTPERR_F TCAMINTPERR_V(1U)3107 3108#define SSRAMINTPERR_S 103109#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)3110#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)3111 3112#define LE_DB_RSP_CODE_0_A 0x19c743113 3114#define TCAM_ACTV_HIT_S 03115#define TCAM_ACTV_HIT_M 0x1fU3116#define TCAM_ACTV_HIT_V(x) ((x) << TCAM_ACTV_HIT_S)3117#define TCAM_ACTV_HIT_G(x) (((x) >> TCAM_ACTV_HIT_S) & TCAM_ACTV_HIT_M)3118 3119#define LE_DB_RSP_CODE_1_A 0x19c783120 3121#define HASH_ACTV_HIT_S 253122#define HASH_ACTV_HIT_M 0x1fU3123#define HASH_ACTV_HIT_V(x) ((x) << HASH_ACTV_HIT_S)3124#define HASH_ACTV_HIT_G(x) (((x) >> HASH_ACTV_HIT_S) & HASH_ACTV_HIT_M)3125 3126#define LE_3_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eac3127#define LE_4_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eb03128 3129#define NCSI_INT_CAUSE_A 0x1a0d83130 3131#define CIM_DM_PRTY_ERR_S 83132#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)3133#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)3134 3135#define MPS_DM_PRTY_ERR_S 73136#define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)3137#define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U)3138 3139#define TXFIFO_PRTY_ERR_S 13140#define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)3141#define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U)3142 3143#define RXFIFO_PRTY_ERR_S 03144#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)3145#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)3146 3147#define XGMAC_PORT_CFG2_A 0x10183148 3149#define PATEN_S 183150#define PATEN_V(x) ((x) << PATEN_S)3151#define PATEN_F PATEN_V(1U)3152 3153#define MAGICEN_S 173154#define MAGICEN_V(x) ((x) << MAGICEN_S)3155#define MAGICEN_F MAGICEN_V(1U)3156 3157#define XGMAC_PORT_MAGIC_MACID_LO 0x10243158#define XGMAC_PORT_MAGIC_MACID_HI 0x10283159 3160#define XGMAC_PORT_EPIO_DATA0_A 0x10c03161#define XGMAC_PORT_EPIO_DATA1_A 0x10c43162#define XGMAC_PORT_EPIO_DATA2_A 0x10c83163#define XGMAC_PORT_EPIO_DATA3_A 0x10cc3164#define XGMAC_PORT_EPIO_OP_A 0x10d03165 3166#define EPIOWR_S 83167#define EPIOWR_V(x) ((x) << EPIOWR_S)3168#define EPIOWR_F EPIOWR_V(1U)3169 3170#define ADDRESS_S 03171#define ADDRESS_V(x) ((x) << ADDRESS_S)3172 3173#define MAC_PORT_INT_CAUSE_A 0x8dc3174#define XGMAC_PORT_INT_CAUSE_A 0x10dc3175 3176#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e283177 3178#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e303179#define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e343180 3181#define TX_MOD_QUEUE_REQ_MAP_S 03182#define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)3183 3184#define TX_MODQ_WEIGHT3_S 243185#define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)3186 3187#define TX_MODQ_WEIGHT2_S 163188#define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)3189 3190#define TX_MODQ_WEIGHT1_S 83191#define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)3192 3193#define TX_MODQ_WEIGHT0_S 03194#define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)3195 3196#define TP_TX_SCHED_HDR_A 0x233197#define TP_TX_SCHED_FIFO_A 0x243198#define TP_TX_SCHED_PCMD_A 0x253199 3200#define NUM_MPS_CLS_SRAM_L_INSTANCES 3363201#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 5123202 3203#define T5_PORT0_BASE 0x300003204#define T5_PORT_STRIDE 0x40003205#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)3206#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))3207 3208#define MC_0_BASE_ADDR 0x400003209#define MC_1_BASE_ADDR 0x480003210#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)3211#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)3212 3213#define MC_P_BIST_CMD_A 0x414003214#define MC_P_BIST_CMD_ADDR_A 0x414043215#define MC_P_BIST_CMD_LEN_A 0x414083216#define MC_P_BIST_DATA_PATTERN_A 0x4140c3217#define MC_P_BIST_STATUS_RDATA_A 0x414883218 3219#define EDC_T50_BASE_ADDR 0x500003220 3221#define EDC_H_BIST_CMD_A 0x500043222#define EDC_H_BIST_CMD_ADDR_A 0x500083223#define EDC_H_BIST_CMD_LEN_A 0x5000c3224#define EDC_H_BIST_DATA_PATTERN_A 0x500103225#define EDC_H_BIST_STATUS_RDATA_A 0x500283226 3227#define EDC_H_ECC_ERR_ADDR_A 0x500843228#define EDC_T51_BASE_ADDR 0x508003229 3230#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)3231#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)3232 3233#define PL_VF_REV_A 0x43234#define PL_VF_WHOAMI_A 0x03235#define PL_VF_REVISION_A 0x83236 3237/* registers for module CIM */3238#define CIM_HOST_ACC_CTRL_A 0x7b503239#define CIM_HOST_ACC_DATA_A 0x7b543240#define UP_UP_DBG_LA_CFG_A 0x1403241#define UP_UP_DBG_LA_DATA_A 0x1443242 3243#define HOSTBUSY_S 173244#define HOSTBUSY_V(x) ((x) << HOSTBUSY_S)3245#define HOSTBUSY_F HOSTBUSY_V(1U)3246 3247#define HOSTWRITE_S 163248#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)3249#define HOSTWRITE_F HOSTWRITE_V(1U)3250 3251#define CIM_IBQ_DBG_CFG_A 0x7b603252 3253#define IBQDBGADDR_S 163254#define IBQDBGADDR_M 0xfffU3255#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)3256#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)3257 3258#define IBQDBGBUSY_S 13259#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)3260#define IBQDBGBUSY_F IBQDBGBUSY_V(1U)3261 3262#define IBQDBGEN_S 03263#define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)3264#define IBQDBGEN_F IBQDBGEN_V(1U)3265 3266#define CIM_OBQ_DBG_CFG_A 0x7b643267 3268#define OBQDBGADDR_S 163269#define OBQDBGADDR_M 0xfffU3270#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)3271#define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)3272 3273#define OBQDBGBUSY_S 13274#define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)3275#define OBQDBGBUSY_F OBQDBGBUSY_V(1U)3276 3277#define OBQDBGEN_S 03278#define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)3279#define OBQDBGEN_F OBQDBGEN_V(1U)3280 3281#define CIM_IBQ_DBG_DATA_A 0x7b683282#define CIM_OBQ_DBG_DATA_A 0x7b6c3283#define CIM_DEBUGCFG_A 0x7b703284#define CIM_DEBUGSTS_A 0x7b743285 3286#define POLADBGRDPTR_S 233287#define POLADBGRDPTR_M 0x1ffU3288#define POLADBGRDPTR_V(x) ((x) << POLADBGRDPTR_S)3289 3290#define POLADBGWRPTR_S 163291#define POLADBGWRPTR_M 0x1ffU3292#define POLADBGWRPTR_G(x) (((x) >> POLADBGWRPTR_S) & POLADBGWRPTR_M)3293 3294#define PILADBGRDPTR_S 143295#define PILADBGRDPTR_M 0x1ffU3296#define PILADBGRDPTR_V(x) ((x) << PILADBGRDPTR_S)3297 3298#define PILADBGWRPTR_S 03299#define PILADBGWRPTR_M 0x1ffU3300#define PILADBGWRPTR_G(x) (((x) >> PILADBGWRPTR_S) & PILADBGWRPTR_M)3301 3302#define LADBGEN_S 123303#define LADBGEN_V(x) ((x) << LADBGEN_S)3304#define LADBGEN_F LADBGEN_V(1U)3305 3306#define CIM_PO_LA_DEBUGDATA_A 0x7b783307#define CIM_PI_LA_DEBUGDATA_A 0x7b7c3308#define CIM_PO_LA_MADEBUGDATA_A 0x7b803309#define CIM_PI_LA_MADEBUGDATA_A 0x7b843310 3311#define UPDBGLARDEN_S 13312#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)3313#define UPDBGLARDEN_F UPDBGLARDEN_V(1U)3314 3315#define UPDBGLAEN_S 03316#define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S)3317#define UPDBGLAEN_F UPDBGLAEN_V(1U)3318 3319#define UPDBGLARDPTR_S 23320#define UPDBGLARDPTR_M 0xfffU3321#define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S)3322 3323#define UPDBGLAWRPTR_S 163324#define UPDBGLAWRPTR_M 0xfffU3325#define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)3326 3327#define UPDBGLACAPTPCONLY_S 303328#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)3329#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)3330 3331#define CIM_QUEUE_CONFIG_REF_A 0x7b483332#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c3333 3334#define CIMQSIZE_S 243335#define CIMQSIZE_M 0x3fU3336#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)3337 3338#define CIMQBASE_S 163339#define CIMQBASE_M 0x3fU3340#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)3341 3342#define QUEFULLTHRSH_S 03343#define QUEFULLTHRSH_M 0x1ffU3344#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)3345 3346#define UP_IBQ_0_RDADDR_A 0x103347#define UP_IBQ_0_SHADOW_RDADDR_A 0x2803348#define UP_OBQ_0_REALADDR_A 0x1043349#define UP_OBQ_0_SHADOW_REALADDR_A 0x3943350 3351#define IBQRDADDR_S 03352#define IBQRDADDR_M 0x1fffU3353#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)3354 3355#define IBQWRADDR_S 03356#define IBQWRADDR_M 0x1fffU3357#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)3358 3359#define QUERDADDR_S 03360#define QUERDADDR_M 0x7fffU3361#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)3362 3363#define QUEREMFLITS_S 03364#define QUEREMFLITS_M 0x7ffU3365#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)3366 3367#define QUEEOPCNT_S 163368#define QUEEOPCNT_M 0xfffU3369#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)3370 3371#define QUESOPCNT_S 03372#define QUESOPCNT_M 0xfffU3373#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)3374 3375#define OBQSELECT_S 43376#define OBQSELECT_V(x) ((x) << OBQSELECT_S)3377#define OBQSELECT_F OBQSELECT_V(1U)3378 3379#define IBQSELECT_S 33380#define IBQSELECT_V(x) ((x) << IBQSELECT_S)3381#define IBQSELECT_F IBQSELECT_V(1U)3382 3383#define QUENUMSELECT_S 03384#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)3385 3386#endif /* __T4_REGS_H */3387