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1/*2 * This file is part of the Chelsio T4 Ethernet driver for Linux.3 *4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.5 *6 * This software is available to you under a choice of one of two7 * licenses. You may choose to be licensed under the terms of the GNU8 * General Public License (GPL) Version 2, available from the file9 * COPYING in the main directory of this source tree, or the10 * OpenIB.org BSD license below:11 *12 * Redistribution and use in source and binary forms, with or13 * without modification, are permitted provided that the following14 * conditions are met:15 *16 * - Redistributions of source code must retain the above17 * copyright notice, this list of conditions and the following18 * disclaimer.19 *20 * - Redistributions in binary form must reproduce the above21 * copyright notice, this list of conditions and the following22 * disclaimer in the documentation and/or other materials23 * provided with the distribution.24 *25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE32 * SOFTWARE.33 */34 35#ifndef __T4_VALUES_H__36#define __T4_VALUES_H__37 38/* This file contains definitions for various T4 register value hardware39 * constants. The types of values encoded here are predominantly those for40 * register fields which control "modal" behavior. For the most part, we do41 * not include definitions for register fields which are simple numeric42 * metrics, etc.43 */44 45/* SGE register field values.46 */47 48/* CONTROL1 register */49#define RXPKTCPLMODE_SPLIT_X 150 51#define INGPCIEBOUNDARY_SHIFT_X 552#define INGPCIEBOUNDARY_32B_X 053 54#define INGPADBOUNDARY_SHIFT_X 555 56#define T6_INGPADBOUNDARY_SHIFT_X 357#define T6_INGPADBOUNDARY_8B_X 058#define T6_INGPADBOUNDARY_32B_X 259 60#define INGPADBOUNDARY_32B_X 061 62/* CONTROL2 register */63#define INGPACKBOUNDARY_SHIFT_X 564#define INGPACKBOUNDARY_16B_X 065#define INGPACKBOUNDARY_64B_X 166 67/* GTS register */68#define SGE_TIMERREGS 669#define TIMERREG_COUNTER0_X 070 71#define FETCHBURSTMIN_64B_X 272#define FETCHBURSTMIN_128B_X 373 74/* T6 and later use a single-bit encoding for FetchBurstMin */75#define FETCHBURSTMIN_64B_T6_X 076#define FETCHBURSTMIN_128B_T6_X 177 78#define FETCHBURSTMAX_256B_X 279#define FETCHBURSTMAX_512B_X 380 81#define HOSTFCMODE_INGRESS_QUEUE_X 182#define HOSTFCMODE_STATUS_PAGE_X 283 84#define CIDXFLUSHTHRESH_32_X 585#define CIDXFLUSHTHRESH_128_X 786 87#define UPDATEDELIVERY_INTERRUPT_X 188 89#define RSPD_TYPE_FLBUF_X 090#define RSPD_TYPE_CPL_X 191#define RSPD_TYPE_INTR_X 292 93/* Congestion Manager Definitions.94 */95#define CONMCTXT_CNGTPMODE_S 1996#define CONMCTXT_CNGTPMODE_V(x) ((x) << CONMCTXT_CNGTPMODE_S)97#define CONMCTXT_CNGCHMAP_S 098#define CONMCTXT_CNGCHMAP_V(x) ((x) << CONMCTXT_CNGCHMAP_S)99#define CONMCTXT_CNGTPMODE_CHANNEL_X 2100#define CONMCTXT_CNGTPMODE_QUEUE_X 1101 102/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.103 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at104 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit105 * (IDXSIZE_UNIT_X) Gather Buffer interface at offset 64. For Ingress Queues,106 * we have a Going To Sleep register at offsets 8x+4.107 *108 * As noted above, we have many instances of the Simple Doorbell and Going To109 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a110 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to111 * avoid buffering of the writes to the Simple Doorbell and we want to use a112 * non-contiguous offset for the Going To Sleep writes in order to avoid113 * possible combining between them.114 */115#define SGE_UDB_SIZE 128116#define SGE_UDB_KDOORBELL 8117#define SGE_UDB_GTS 20118#define SGE_UDB_WCDOORBELL 64119 120/* CIM register field values.121 */122#define X_MBOWNER_FW 1123#define X_MBOWNER_PL 2124 125/* PCI-E definitions */126#define WINDOW_SHIFT_X 10127#define PCIEOFST_SHIFT_X 10128 129/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the130 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP131 * selects for a particular field being present. These fields, when present132 * in the Compressed Filter Tuple, have the following widths in bits.133 */134#define FT_FCOE_W 1135#define FT_PORT_W 3136#define FT_VNIC_ID_W 17137#define FT_VLAN_W 17138#define FT_TOS_W 8139#define FT_PROTOCOL_W 8140#define FT_ETHERTYPE_W 16141#define FT_MACMATCH_W 9142#define FT_MPSHITTYPE_W 3143#define FT_FRAGMENTATION_W 1144 145/* Some of the Compressed Filter Tuple fields have internal structure. These146 * bit shifts/masks describe those structures. All shifts are relative to the147 * base position of the fields within the Compressed Filter Tuple148 */149#define FT_VLAN_VLD_S 16150#define FT_VLAN_VLD_V(x) ((x) << FT_VLAN_VLD_S)151#define FT_VLAN_VLD_F FT_VLAN_VLD_V(1U)152 153#define FT_VNID_ID_VF_S 0154#define FT_VNID_ID_VF_V(x) ((x) << FT_VNID_ID_VF_S)155 156#define FT_VNID_ID_PF_S 7157#define FT_VNID_ID_PF_V(x) ((x) << FT_VNID_ID_PF_S)158 159#define FT_VNID_ID_VLD_S 16160#define FT_VNID_ID_VLD_V(x) ((x) << FT_VNID_ID_VLD_S)161 162#endif /* __T4_VALUES_H__ */163