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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.4 * Copyright 2007 Nuova Systems, Inc. All rights reserved.5 */6 7#ifndef _CQ_ENET_DESC_H_8#define _CQ_ENET_DESC_H_9 10#include "cq_desc.h"11 12/* Ethernet completion queue descriptor: 16B */13struct cq_enet_wq_desc {14 __le16 completed_index;15 __le16 q_number;16 u8 reserved[11];17 u8 type_color;18};19 20static inline void cq_enet_wq_desc_dec(struct cq_enet_wq_desc *desc,21 u8 *type, u8 *color, u16 *q_number, u16 *completed_index)22{23 cq_desc_dec((struct cq_desc *)desc, type,24 color, q_number, completed_index);25}26 27/* Completion queue descriptor: Ethernet receive queue, 16B */28struct cq_enet_rq_desc {29 __le16 completed_index_flags;30 __le16 q_number_rss_type_flags;31 __le32 rss_hash;32 __le16 bytes_written_flags;33 __le16 vlan;34 __le16 checksum_fcoe;35 u8 flags;36 u8 type_color;37};38 39#define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)40#define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)41#define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)42#define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15)43 44#define CQ_ENET_RQ_DESC_RSS_TYPE_BITS 445#define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \46 ((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1)47#define CQ_ENET_RQ_DESC_RSS_TYPE_NONE 048#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4 149#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4 250#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6 351#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6 452#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX 553#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX 654 55#define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC (0x1 << 14)56 57#define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS 1458#define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \59 ((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)60#define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14)61#define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15)62 63#define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS 1264#define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_MASK \65 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS) - 1)66#define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK (0x1 << 12)67#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS 368#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_MASK \69 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS) - 1)70#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_SHIFT 1371 72#define CQ_ENET_RQ_DESC_FCOE_SOF_BITS 873#define CQ_ENET_RQ_DESC_FCOE_SOF_MASK \74 ((1 << CQ_ENET_RQ_DESC_FCOE_SOF_BITS) - 1)75#define CQ_ENET_RQ_DESC_FCOE_EOF_BITS 876#define CQ_ENET_RQ_DESC_FCOE_EOF_MASK \77 ((1 << CQ_ENET_RQ_DESC_FCOE_EOF_BITS) - 1)78#define CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT 879 80#define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK (0x1 << 0)81#define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK (0x1 << 0)82#define CQ_ENET_RQ_DESC_FLAGS_UDP (0x1 << 1)83#define CQ_ENET_RQ_DESC_FCOE_ENC_ERROR (0x1 << 1)84#define CQ_ENET_RQ_DESC_FLAGS_TCP (0x1 << 2)85#define CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK (0x1 << 3)86#define CQ_ENET_RQ_DESC_FLAGS_IPV6 (0x1 << 4)87#define CQ_ENET_RQ_DESC_FLAGS_IPV4 (0x1 << 5)88#define CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT (0x1 << 6)89#define CQ_ENET_RQ_DESC_FLAGS_FCS_OK (0x1 << 7)90 91static inline void cq_enet_rq_desc_dec(struct cq_enet_rq_desc *desc,92 u8 *type, u8 *color, u16 *q_number, u16 *completed_index,93 u8 *ingress_port, u8 *fcoe, u8 *eop, u8 *sop, u8 *rss_type,94 u8 *csum_not_calc, u32 *rss_hash, u16 *bytes_written, u8 *packet_error,95 u8 *vlan_stripped, u16 *vlan_tci, u16 *checksum, u8 *fcoe_sof,96 u8 *fcoe_fc_crc_ok, u8 *fcoe_enc_error, u8 *fcoe_eof,97 u8 *tcp_udp_csum_ok, u8 *udp, u8 *tcp, u8 *ipv4_csum_ok,98 u8 *ipv6, u8 *ipv4, u8 *ipv4_fragment, u8 *fcs_ok)99{100 u16 completed_index_flags;101 u16 q_number_rss_type_flags;102 u16 bytes_written_flags;103 104 cq_desc_dec((struct cq_desc *)desc, type,105 color, q_number, completed_index);106 107 completed_index_flags = le16_to_cpu(desc->completed_index_flags);108 q_number_rss_type_flags =109 le16_to_cpu(desc->q_number_rss_type_flags);110 bytes_written_flags = le16_to_cpu(desc->bytes_written_flags);111 112 *ingress_port = (completed_index_flags &113 CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT) ? 1 : 0;114 *fcoe = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_FCOE) ?115 1 : 0;116 *eop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_EOP) ?117 1 : 0;118 *sop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_SOP) ?119 1 : 0;120 121 *rss_type = (u8)((q_number_rss_type_flags >> CQ_DESC_Q_NUM_BITS) &122 CQ_ENET_RQ_DESC_RSS_TYPE_MASK);123 *csum_not_calc = (q_number_rss_type_flags &124 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ? 1 : 0;125 126 *rss_hash = le32_to_cpu(desc->rss_hash);127 128 *bytes_written = bytes_written_flags &129 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;130 *packet_error = (bytes_written_flags &131 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ? 1 : 0;132 *vlan_stripped = (bytes_written_flags &133 CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) ? 1 : 0;134 135 /*136 * Tag Control Information(16) = user_priority(3) + cfi(1) + vlan(12)137 */138 *vlan_tci = le16_to_cpu(desc->vlan);139 140 if (*fcoe) {141 *fcoe_sof = (u8)(le16_to_cpu(desc->checksum_fcoe) &142 CQ_ENET_RQ_DESC_FCOE_SOF_MASK);143 *fcoe_fc_crc_ok = (desc->flags &144 CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK) ? 1 : 0;145 *fcoe_enc_error = (desc->flags &146 CQ_ENET_RQ_DESC_FCOE_ENC_ERROR) ? 1 : 0;147 *fcoe_eof = (u8)((le16_to_cpu(desc->checksum_fcoe) >>148 CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT) &149 CQ_ENET_RQ_DESC_FCOE_EOF_MASK);150 *checksum = 0;151 } else {152 *fcoe_sof = 0;153 *fcoe_fc_crc_ok = 0;154 *fcoe_enc_error = 0;155 *fcoe_eof = 0;156 *checksum = le16_to_cpu(desc->checksum_fcoe);157 }158 159 *tcp_udp_csum_ok =160 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ? 1 : 0;161 *udp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_UDP) ? 1 : 0;162 *tcp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP) ? 1 : 0;163 *ipv4_csum_ok =164 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ? 1 : 0;165 *ipv6 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV6) ? 1 : 0;166 *ipv4 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4) ? 1 : 0;167 *ipv4_fragment =168 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT) ? 1 : 0;169 *fcs_ok = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_FCS_OK) ? 1 : 0;170}171 172#endif /* _CQ_ENET_DESC_H_ */173