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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.4 * Copyright 2007 Nuova Systems, Inc. All rights reserved.5 */6 7#ifndef _ENIC_H_8#define _ENIC_H_9 10#include "vnic_enet.h"11#include "vnic_dev.h"12#include "vnic_wq.h"13#include "vnic_rq.h"14#include "vnic_cq.h"15#include "vnic_intr.h"16#include "vnic_stats.h"17#include "vnic_nic.h"18#include "vnic_rss.h"19#include <linux/irq.h>20 21#define DRV_NAME "enic"22#define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver"23 24#define ENIC_BARS_MAX 625 26#define ENIC_WQ_MAX 827#define ENIC_RQ_MAX 828#define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX)29#define ENIC_INTR_MAX (ENIC_CQ_MAX + 2)30 31#define ENIC_WQ_NAPI_BUDGET 25632 33#define ENIC_AIC_LARGE_PKT_DIFF 334 35struct enic_msix_entry {36 int requested;37 char devname[IFNAMSIZ + 8];38 irqreturn_t (*isr)(int, void *);39 void *devid;40 cpumask_var_t affinity_mask;41};42 43/* Store only the lower range. Higher range is given by fw. */44struct enic_intr_mod_range {45 u32 small_pkt_range_start;46 u32 large_pkt_range_start;47};48 49struct enic_intr_mod_table {50 u32 rx_rate;51 u32 range_percent;52};53 54#define ENIC_MAX_LINK_SPEEDS 355#define ENIC_LINK_SPEED_10G 1000056#define ENIC_LINK_SPEED_4G 400057#define ENIC_LINK_40G_INDEX 258#define ENIC_LINK_10G_INDEX 159#define ENIC_LINK_4G_INDEX 060#define ENIC_RX_COALESCE_RANGE_END 12561#define ENIC_AIC_TS_BREAK 10062 63struct enic_rx_coal {64 u32 small_pkt_range_start;65 u32 large_pkt_range_start;66 u32 range_end;67 u32 use_adaptive_rx_coalesce;68};69 70/* priv_flags */71#define ENIC_SRIOV_ENABLED (1 << 0)72 73/* enic port profile set flags */74#define ENIC_PORT_REQUEST_APPLIED (1 << 0)75#define ENIC_SET_REQUEST (1 << 1)76#define ENIC_SET_NAME (1 << 2)77#define ENIC_SET_INSTANCE (1 << 3)78#define ENIC_SET_HOST (1 << 4)79 80struct enic_port_profile {81 u32 set;82 u8 request;83 char name[PORT_PROFILE_MAX];84 u8 instance_uuid[PORT_UUID_MAX];85 u8 host_uuid[PORT_UUID_MAX];86 u8 vf_mac[ETH_ALEN];87 u8 mac_addr[ETH_ALEN];88};89 90/* enic_rfs_fltr_node - rfs filter node in hash table91 * @@keys: IPv4 5 tuple92 * @flow_id: flow_id of clsf filter provided by kernel93 * @fltr_id: filter id of clsf filter returned by adaptor94 * @rq_id: desired rq index95 * @node: hlist_node96 */97struct enic_rfs_fltr_node {98 struct flow_keys keys;99 u32 flow_id;100 u16 fltr_id;101 u16 rq_id;102 struct hlist_node node;103};104 105/* enic_rfs_flw_tbl - rfs flow table106 * @max: Maximum number of filters vNIC supports107 * @free: Number of free filters available108 * @toclean: hash table index to clean next109 * @ht_head: hash table list head110 * @lock: spin lock111 * @rfs_may_expire: timer function for enic_rps_may_expire_flow112 */113struct enic_rfs_flw_tbl {114 u16 max;115 int free;116 117#define ENIC_RFS_FLW_BITSHIFT (10)118#define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1)119 u16 toclean:ENIC_RFS_FLW_BITSHIFT;120 struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT];121 spinlock_t lock;122 struct timer_list rfs_may_expire;123};124 125struct vxlan_offload {126 u16 vxlan_udp_port_number;127 u8 patch_level;128 u8 flags;129};130 131struct enic_wq_stats {132 u64 packets; /* pkts queued for Tx */133 u64 stopped; /* Tx ring almost full, queue stopped */134 u64 wake; /* Tx ring no longer full, queue woken up*/135 u64 tso; /* non-encap tso pkt */136 u64 encap_tso; /* encap tso pkt */137 u64 encap_csum; /* encap HW csum */138 u64 csum_partial; /* skb->ip_summed = CHECKSUM_PARTIAL */139 u64 csum_none; /* HW csum not required */140 u64 bytes; /* bytes queued for Tx */141 u64 add_vlan; /* HW adds vlan tag */142 u64 cq_work; /* Tx completions processed */143 u64 cq_bytes; /* Tx bytes processed */144 u64 null_pkt; /* skb length <= 0 */145 u64 skb_linear_fail; /* linearize failures */146 u64 desc_full_awake; /* TX ring full while queue awake */147};148 149struct enic_rq_stats {150 u64 packets; /* pkts received */151 u64 bytes; /* bytes received */152 u64 l4_rss_hash; /* hashed on l4 */153 u64 l3_rss_hash; /* hashed on l3 */154 u64 csum_unnecessary; /* HW verified csum */155 u64 csum_unnecessary_encap; /* HW verified csum on encap packet */156 u64 vlan_stripped; /* HW stripped vlan */157 u64 napi_complete; /* napi complete intr reenabled */158 u64 napi_repoll; /* napi poll again */159 u64 bad_fcs; /* bad pkts */160 u64 pkt_truncated; /* truncated pkts */161 u64 no_skb; /* out of skbs */162 u64 desc_skip; /* Rx pkt went into later buffer */163};164 165/* Per-instance private data structure */166struct enic {167 struct net_device *netdev;168 struct pci_dev *pdev;169 struct vnic_enet_config config;170 struct vnic_dev_bar bar[ENIC_BARS_MAX];171 struct vnic_dev *vdev;172 struct timer_list notify_timer;173 struct work_struct reset;174 struct work_struct tx_hang_reset;175 struct work_struct change_mtu_work;176 struct msix_entry msix_entry[ENIC_INTR_MAX];177 struct enic_msix_entry msix[ENIC_INTR_MAX];178 u32 msg_enable;179 spinlock_t devcmd_lock;180 u8 mac_addr[ETH_ALEN];181 unsigned int flags;182 unsigned int priv_flags;183 unsigned int mc_count;184 unsigned int uc_count;185 u32 port_mtu;186 struct enic_rx_coal rx_coalesce_setting;187 u32 rx_coalesce_usecs;188 u32 tx_coalesce_usecs;189#ifdef CONFIG_PCI_IOV190 u16 num_vfs;191#endif192 spinlock_t enic_api_lock;193 bool enic_api_busy;194 struct enic_port_profile *pp;195 196 /* work queue cache line section */197 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX];198 spinlock_t wq_lock[ENIC_WQ_MAX];199 struct enic_wq_stats wq_stats[ENIC_WQ_MAX];200 unsigned int wq_count;201 u16 loop_enable;202 u16 loop_tag;203 204 /* receive queue cache line section */205 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX];206 struct enic_rq_stats rq_stats[ENIC_RQ_MAX];207 unsigned int rq_count;208 struct vxlan_offload vxlan;209 struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX];210 211 /* interrupt resource cache line section */212 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];213 unsigned int intr_count;214 u32 __iomem *legacy_pba; /* memory-mapped */215 216 /* completion queue cache line section */217 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];218 unsigned int cq_count;219 struct enic_rfs_flw_tbl rfs_h;220 u32 rx_copybreak;221 u8 rss_key[ENIC_RSS_LEN];222 struct vnic_gen_stats gen_stats;223};224 225static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev)226{227 struct enic *enic = vdev->priv;228 229 return enic->netdev;230}231 232/* wrappers function for kernel log233 */234#define vdev_err(vdev, fmt, ...) \235 dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)236#define vdev_warn(vdev, fmt, ...) \237 dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)238#define vdev_info(vdev, fmt, ...) \239 dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)240 241#define vdev_neterr(vdev, fmt, ...) \242 netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)243#define vdev_netwarn(vdev, fmt, ...) \244 netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)245#define vdev_netinfo(vdev, fmt, ...) \246 netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)247 248static inline struct device *enic_get_dev(struct enic *enic)249{250 return &(enic->pdev->dev);251}252 253static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq)254{255 return rq;256}257 258static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)259{260 return enic->rq_count + wq;261}262 263static inline unsigned int enic_msix_rq_intr(struct enic *enic,264 unsigned int rq)265{266 return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset;267}268 269static inline unsigned int enic_msix_wq_intr(struct enic *enic,270 unsigned int wq)271{272 return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset;273}274 275static inline unsigned int enic_msix_err_intr(struct enic *enic)276{277 return enic->rq_count + enic->wq_count;278}279 280#define ENIC_LEGACY_IO_INTR 0281#define ENIC_LEGACY_ERR_INTR 1282#define ENIC_LEGACY_NOTIFY_INTR 2283 284static inline unsigned int enic_msix_notify_intr(struct enic *enic)285{286 return enic->rq_count + enic->wq_count + 1;287}288 289static inline bool enic_is_err_intr(struct enic *enic, int intr)290{291 switch (vnic_dev_get_intr_mode(enic->vdev)) {292 case VNIC_DEV_INTR_MODE_INTX:293 return intr == ENIC_LEGACY_ERR_INTR;294 case VNIC_DEV_INTR_MODE_MSIX:295 return intr == enic_msix_err_intr(enic);296 case VNIC_DEV_INTR_MODE_MSI:297 default:298 return false;299 }300}301 302static inline bool enic_is_notify_intr(struct enic *enic, int intr)303{304 switch (vnic_dev_get_intr_mode(enic->vdev)) {305 case VNIC_DEV_INTR_MODE_INTX:306 return intr == ENIC_LEGACY_NOTIFY_INTR;307 case VNIC_DEV_INTR_MODE_MSIX:308 return intr == enic_msix_notify_intr(enic);309 case VNIC_DEV_INTR_MODE_MSI:310 default:311 return false;312 }313}314 315static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr)316{317 if (unlikely(dma_mapping_error(&enic->pdev->dev, dma_addr))) {318 net_warn_ratelimited("%s: PCI dma mapping failed!\n",319 enic->netdev->name);320 enic->gen_stats.dma_map_error++;321 322 return -ENOMEM;323 }324 325 return 0;326}327 328void enic_reset_addr_lists(struct enic *enic);329int enic_sriov_enabled(struct enic *enic);330int enic_is_valid_vf(struct enic *enic, int vf);331int enic_is_dynamic(struct enic *enic);332void enic_set_ethtool_ops(struct net_device *netdev);333int __enic_set_rsskey(struct enic *enic);334 335#endif /* _ENIC_H_ */336