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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.4 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.5 */6 7#ifndef _ENIC_RES_H_8#define _ENIC_RES_H_9 10#include "wq_enet_desc.h"11#include "rq_enet_desc.h"12#include "vnic_wq.h"13#include "vnic_rq.h"14 15#define ENIC_MIN_WQ_DESCS		6416#define ENIC_MAX_WQ_DESCS		409617#define ENIC_MIN_RQ_DESCS		6418#define ENIC_MAX_RQ_DESCS		409619 20#define ENIC_MIN_MTU			ETH_MIN_MTU21#define ENIC_MAX_MTU			900022 23#define ENIC_MULTICAST_PERFECT_FILTERS	3224#define ENIC_UNICAST_PERFECT_FILTERS	3225 26#define ENIC_NON_TSO_MAX_DESC		1627 28#define ENIC_SETTING(enic, f) ((enic->config.flags & VENETF_##f) ? 1 : 0)29 30static inline void enic_queue_wq_desc_ex(struct vnic_wq *wq,31	void *os_buf, dma_addr_t dma_addr, unsigned int len,32	unsigned int mss_or_csum_offset, unsigned int hdr_len,33	int vlan_tag_insert, unsigned int vlan_tag,34	int offload_mode, int cq_entry, int sop, int eop, int loopback)35{36	struct wq_enet_desc *desc = vnic_wq_next_desc(wq);37	u8 desc_skip_cnt = 1;38	u8 compressed_send = 0;39	u64 wrid = 0;40 41	wq_enet_desc_enc(desc,42		(u64)dma_addr | VNIC_PADDR_TARGET,43		(u16)len,44		(u16)mss_or_csum_offset,45		(u16)hdr_len, (u8)offload_mode,46		(u8)eop, (u8)cq_entry,47		0, /* fcoe_encap */48		(u8)vlan_tag_insert,49		(u16)vlan_tag,50		(u8)loopback);51 52	vnic_wq_post(wq, os_buf, dma_addr, len, sop, eop, desc_skip_cnt,53			(u8)cq_entry, compressed_send, wrid);54}55 56static inline void enic_queue_wq_desc_cont(struct vnic_wq *wq,57	void *os_buf, dma_addr_t dma_addr, unsigned int len,58	int eop, int loopback)59{60	enic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,61		0, 0, 0, 0, 0,62		eop, 0 /* !SOP */, eop, loopback);63}64 65static inline void enic_queue_wq_desc(struct vnic_wq *wq, void *os_buf,66	dma_addr_t dma_addr, unsigned int len, int vlan_tag_insert,67	unsigned int vlan_tag, int eop, int loopback)68{69	enic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,70		0, 0, vlan_tag_insert, vlan_tag,71		WQ_ENET_OFFLOAD_MODE_CSUM,72		eop, 1 /* SOP */, eop, loopback);73}74 75static inline void enic_queue_wq_desc_csum(struct vnic_wq *wq,76	void *os_buf, dma_addr_t dma_addr, unsigned int len,77	int ip_csum, int tcpudp_csum, int vlan_tag_insert,78	unsigned int vlan_tag, int eop, int loopback)79{80	enic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,81		(ip_csum ? 1 : 0) + (tcpudp_csum ? 2 : 0),82		0, vlan_tag_insert, vlan_tag,83		WQ_ENET_OFFLOAD_MODE_CSUM,84		eop, 1 /* SOP */, eop, loopback);85}86 87static inline void enic_queue_wq_desc_csum_l4(struct vnic_wq *wq,88	void *os_buf, dma_addr_t dma_addr, unsigned int len,89	unsigned int csum_offset, unsigned int hdr_len,90	int vlan_tag_insert, unsigned int vlan_tag, int eop, int loopback)91{92	enic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,93		csum_offset, hdr_len, vlan_tag_insert, vlan_tag,94		WQ_ENET_OFFLOAD_MODE_CSUM_L4,95		eop, 1 /* SOP */, eop, loopback);96}97 98static inline void enic_queue_wq_desc_tso(struct vnic_wq *wq,99	void *os_buf, dma_addr_t dma_addr, unsigned int len,100	unsigned int mss, unsigned int hdr_len, int vlan_tag_insert,101	unsigned int vlan_tag, int eop, int loopback)102{103	enic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,104		mss, hdr_len, vlan_tag_insert, vlan_tag,105		WQ_ENET_OFFLOAD_MODE_TSO,106		eop, 1 /* SOP */, eop, loopback);107}108 109static inline void enic_queue_rq_desc(struct vnic_rq *rq,110	void *os_buf, unsigned int os_buf_index,111	dma_addr_t dma_addr, unsigned int len)112{113	struct rq_enet_desc *desc = vnic_rq_next_desc(rq);114	u64 wrid = 0;115	u8 type = os_buf_index ?116		RQ_ENET_TYPE_NOT_SOP : RQ_ENET_TYPE_ONLY_SOP;117 118	rq_enet_desc_enc(desc,119		(u64)dma_addr | VNIC_PADDR_TARGET,120		type, (u16)len);121 122	vnic_rq_post(rq, os_buf, os_buf_index, dma_addr, len, wrid);123}124 125struct enic;126 127int enic_get_vnic_config(struct enic *);128int enic_add_vlan(struct enic *enic, u16 vlanid);129int enic_del_vlan(struct enic *enic, u16 vlanid);130int enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,131	u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,132	u8 ig_vlan_strip_en);133int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len);134int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len);135void enic_get_res_counts(struct enic *enic);136void enic_init_vnic_resources(struct enic *enic);137int enic_alloc_vnic_resources(struct enic *);138void enic_free_vnic_resources(struct enic *);139 140#endif /* _ENIC_RES_H_ */141