249 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (C) 2021 Gerhard Engleder <gerhard@engleder-embedded.com> */3 4/* Hardware definition of TSNEP and EtherCAT MAC device */5 6#ifndef _TSNEP_HW_H7#define _TSNEP_HW_H8 9#include <linux/types.h>10 11/* type */12#define ECM_TYPE 0x000013#define ECM_REVISION_MASK 0x000000FF14#define ECM_REVISION_SHIFT 015#define ECM_VERSION_MASK 0x0000FF0016#define ECM_VERSION_SHIFT 817#define ECM_QUEUE_COUNT_MASK 0x0007000018#define ECM_QUEUE_COUNT_SHIFT 1619#define ECM_GATE_CONTROL 0x0200000020 21/* system time */22#define ECM_SYSTEM_TIME_LOW 0x000823#define ECM_SYSTEM_TIME_HIGH 0x000C24 25/* clock */26#define ECM_CLOCK_RATE 0x001027#define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF28#define ECM_CLOCK_RATE_OFFSET_SIGN 0x8000000029 30/* interrupt */31#define ECM_INT_ENABLE 0x001832#define ECM_INT_ACTIVE 0x001C33#define ECM_INT_ACKNOWLEDGE 0x001C34#define ECM_INT_LINK 0x0000002035#define ECM_INT_TX_0 0x0000010036#define ECM_INT_RX_0 0x0000020037#define ECM_INT_TXRX_SHIFT 238#define ECM_INT_ALL 0x7FFFFFFF39#define ECM_INT_DISABLE 0x8000000040 41/* reset */42#define ECM_RESET 0x002043#define ECM_RESET_COMMON 0x0000000144#define ECM_RESET_CHANNEL 0x0000010045#define ECM_RESET_TXRX 0x0001000046 47/* counter */48#define ECM_COUNTER_LOW 0x002849#define ECM_COUNTER_HIGH 0x002C50 51/* interrupt delay */52#define ECM_INT_DELAY 0x003053#define ECM_INT_DELAY_MASK 0xF054#define ECM_INT_DELAY_SHIFT 455#define ECM_INT_DELAY_BASE_US 1656#define ECM_INT_DELAY_OFFSET 157 58/* control and status */59#define ECM_STATUS 0x008060#define ECM_LINK_MODE_OFF 0x0100000061#define ECM_LINK_MODE_100 0x0200000062#define ECM_LINK_MODE_1000 0x0400000063#define ECM_NO_LINK 0x0100000064#define ECM_LINK_MODE_MASK 0x0600000065 66/* management data */67#define ECM_MD_CONTROL 0x008468#define ECM_MD_STATUS 0x008469#define ECM_MD_PREAMBLE 0x0000000170#define ECM_MD_READ 0x0000000471#define ECM_MD_WRITE 0x0000000272#define ECM_MD_ADDR_MASK 0x000000F873#define ECM_MD_ADDR_SHIFT 374#define ECM_MD_PHY_ADDR_MASK 0x00001F0075#define ECM_MD_PHY_ADDR_SHIFT 876#define ECM_MD_BUSY 0x0000000177#define ECM_MD_DATA_MASK 0xFFFF000078#define ECM_MD_DATA_SHIFT 1679 80/* statistic */81#define ECM_STAT 0x00B082#define ECM_STAT_RX_ERR_MASK 0x000000FF83#define ECM_STAT_RX_ERR_SHIFT 084#define ECM_STAT_INV_FRM_MASK 0x0000FF0085#define ECM_STAT_INV_FRM_SHIFT 886#define ECM_STAT_FWD_RX_ERR_MASK 0x00FF000087#define ECM_STAT_FWD_RX_ERR_SHIFT 1688 89/* tsnep */90#define TSNEP_MAC_SIZE 0x400091#define TSNEP_QUEUE_SIZE 0x100092#define TSNEP_QUEUE(n) ({ typeof(n) __n = (n); \93 (__n) == 0 ? \94 0 : \95 TSNEP_MAC_SIZE + TSNEP_QUEUE_SIZE * ((__n) - 1); })96#define TSNEP_MAX_QUEUES 897#define TSNEP_MAX_FRAME_SIZE (2 * 1024) /* hardware supports actually 16k */98#define TSNEP_DESC_SIZE 25699#define TSNEP_DESC_OFFSET 128100 101/* tsnep register */102#define TSNEP_INFO 0x0100103#define TSNEP_INFO_TX_TIME 0x00010000104#define TSNEP_CONTROL 0x0108105#define TSNEP_CONTROL_TX_RESET 0x00000001106#define TSNEP_CONTROL_TX_ENABLE 0x00000002107#define TSNEP_CONTROL_TX_DMA_ERROR 0x00000010108#define TSNEP_CONTROL_TX_DESC_ERROR 0x00000020109#define TSNEP_CONTROL_RX_RESET 0x00000100110#define TSNEP_CONTROL_RX_ENABLE 0x00000200111#define TSNEP_CONTROL_RX_DISABLE 0x00000400112#define TSNEP_CONTROL_RX_DMA_ERROR 0x00001000113#define TSNEP_CONTROL_RX_DESC_ERROR 0x00002000114#define TSNEP_TX_DESC_ADDR_LOW 0x0140115#define TSNEP_TX_DESC_ADDR_HIGH 0x0144116#define TSNEP_RX_DESC_ADDR_LOW 0x0180117#define TSNEP_RX_DESC_ADDR_HIGH 0x0184118#define TSNEP_RESET_OWNER_COUNTER 0x01119#define TSNEP_RX_STATISTIC 0x0190120#define TSNEP_RX_STATISTIC_NO_DESC_MASK 0x000000FF121#define TSNEP_RX_STATISTIC_NO_DESC_SHIFT 0122#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_MASK 0x0000FF00123#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_SHIFT 8124#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_MASK 0x00FF0000125#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_SHIFT 16126#define TSNEP_RX_STATISTIC_INVALID_FRAME_MASK 0xFF000000127#define TSNEP_RX_STATISTIC_INVALID_FRAME_SHIFT 24128#define TSNEP_RX_STATISTIC_NO_DESC 0x0190129#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL 0x0191130#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW 0x0192131#define TSNEP_RX_STATISTIC_INVALID_FRAME 0x0193132#define TSNEP_MAC_ADDRESS_LOW 0x0800133#define TSNEP_MAC_ADDRESS_HIGH 0x0804134#define TSNEP_RX_FILTER 0x0806135#define TSNEP_RX_FILTER_ACCEPT_ALL_MULTICASTS 0x0001136#define TSNEP_RX_FILTER_ACCEPT_ALL_UNICASTS 0x0002137#define TSNEP_GC 0x0808138#define TSNEP_GC_ENABLE_A 0x00000002139#define TSNEP_GC_ENABLE_B 0x00000004140#define TSNEP_GC_DISABLE 0x00000008141#define TSNEP_GC_ENABLE_TIMEOUT 0x00000010142#define TSNEP_GC_ACTIVE_A 0x00000002143#define TSNEP_GC_ACTIVE_B 0x00000004144#define TSNEP_GC_CHANGE_AB 0x00000008145#define TSNEP_GC_TIMEOUT_ACTIVE 0x00000010146#define TSNEP_GC_TIMEOUT_SIGNAL 0x00000020147#define TSNEP_GC_LIST_ERROR 0x00000080148#define TSNEP_GC_OPEN 0x00FF0000149#define TSNEP_GC_OPEN_SHIFT 16150#define TSNEP_GC_NEXT_OPEN 0xFF000000151#define TSNEP_GC_NEXT_OPEN_SHIFT 24152#define TSNEP_GC_TIMEOUT 131072153#define TSNEP_GC_TIME 0x080C154#define TSNEP_GC_CHANGE 0x0810155#define TSNEP_GCL_A 0x2000156#define TSNEP_GCL_B 0x2800157#define TSNEP_GCL_SIZE SZ_2K158#define TSNEP_RX_ASSIGN 0x0840159#define TSNEP_RX_ASSIGN_ACTIVE 0x00000001160#define TSNEP_RX_ASSIGN_QUEUE_MASK 0x00000006161#define TSNEP_RX_ASSIGN_QUEUE_SHIFT 1162#define TSNEP_RX_ASSIGN_OFFSET 1163#define TSNEP_RX_ASSIGN_ETHER_TYPE 0x0880164#define TSNEP_RX_ASSIGN_ETHER_TYPE_OFFSET 2165#define TSNEP_RX_ASSIGN_ETHER_TYPE_COUNT 2166 167/* tsnep gate control list operation */168struct tsnep_gcl_operation {169 u32 properties;170 u32 interval;171};172 173#define TSNEP_GCL_COUNT (TSNEP_GCL_SIZE / sizeof(struct tsnep_gcl_operation))174#define TSNEP_GCL_MASK 0x000000FF175#define TSNEP_GCL_INSERT 0x20000000176#define TSNEP_GCL_CHANGE 0x40000000177#define TSNEP_GCL_LAST 0x80000000178#define TSNEP_GCL_MIN_INTERVAL 32179 180/* tsnep TX/RX descriptor */181#define TSNEP_DESC_SIZE 256182#define TSNEP_DESC_SIZE_DATA_AFTER 2048183#define TSNEP_DESC_OFFSET 128184#define TSNEP_DESC_SIZE_DATA_AFTER_INLINE (64 - sizeof(struct tsnep_tx_desc) + \185 sizeof_field(struct tsnep_tx_desc, tx))186#define TSNEP_DESC_OWNER_COUNTER_MASK 0xC0000000187#define TSNEP_DESC_OWNER_COUNTER_SHIFT 30188#define TSNEP_DESC_LENGTH_MASK 0x00003FFF189#define TSNEP_DESC_INTERRUPT_FLAG 0x00040000190#define TSNEP_DESC_EXTENDED_WRITEBACK_FLAG 0x00080000191#define TSNEP_DESC_NO_LINK_FLAG 0x01000000192 193/* tsnep TX descriptor */194struct tsnep_tx_desc {195 __le32 properties;196 __le32 more_properties;197 __le32 reserved[2];198 __le64 next;199 __le64 tx;200};201 202#define TSNEP_TX_DESC_OWNER_MASK 0xE0000000203#define TSNEP_TX_DESC_OWNER_USER_FLAG 0x20000000204#define TSNEP_TX_DESC_LAST_FRAGMENT_FLAG 0x00010000205#define TSNEP_TX_DESC_DATA_AFTER_DESC_FLAG 0x00020000206 207/* tsnep TX descriptor writeback */208struct tsnep_tx_desc_wb {209 __le32 properties;210 __le32 reserved1;211 __le64 counter;212 __le64 timestamp;213 __le32 dma_delay;214 __le32 reserved2;215};216 217#define TSNEP_TX_DESC_UNDERRUN_ERROR_FLAG 0x00010000218#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_MASK 0x0000FFFC219#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_SHIFT 2220#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_MASK 0xFFFC0000221#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_SHIFT 18222#define TSNEP_TX_DESC_DMA_DELAY_NS 64223 224/* tsnep RX descriptor */225struct tsnep_rx_desc {226 __le32 properties;227 __le32 reserved[3];228 __le64 next;229 __le64 rx;230};231 232#define TSNEP_RX_DESC_BUFFER_SIZE_MASK 0x00003FFC233 234/* tsnep RX descriptor writeback */235struct tsnep_rx_desc_wb {236 __le32 properties;237 __le32 reserved[7];238};239 240/* tsnep RX inline meta */241struct tsnep_rx_inline {242 __le64 counter;243 __le64 timestamp;244};245 246#define TSNEP_RX_INLINE_METADATA_SIZE (sizeof(struct tsnep_rx_inline))247 248#endif /* _TSNEP_HW_H */249