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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright(c) 2015 EZchip Technologies.4 */5 6#ifndef _NPS_ENET_H7#define _NPS_ENET_H8 9/* default values */10#define NPS_ENET_NAPI_POLL_WEIGHT 0x211#define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF12#define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x713#define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x514#define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC15#define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x716#define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x317#define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x1418#define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC19#define NPS_ENET_ENABLE 120#define NPS_ENET_DISABLE 021 22/* register definitions */23#define NPS_ENET_REG_TX_CTL 0x80024#define NPS_ENET_REG_TX_BUF 0x80825#define NPS_ENET_REG_RX_CTL 0x81026#define NPS_ENET_REG_RX_BUF 0x81827#define NPS_ENET_REG_BUF_INT_ENABLE 0x8C028#define NPS_ENET_REG_GE_MAC_CFG_0 0x100029#define NPS_ENET_REG_GE_MAC_CFG_1 0x100430#define NPS_ENET_REG_GE_MAC_CFG_2 0x100831#define NPS_ENET_REG_GE_MAC_CFG_3 0x100C32#define NPS_ENET_REG_GE_RST 0x140033#define NPS_ENET_REG_PHASE_FIFO_CTL 0x140434 35/* Tx control register masks and shifts */36#define TX_CTL_NT_MASK 0x7FF37#define TX_CTL_NT_SHIFT 038#define TX_CTL_ET_MASK 0x400039#define TX_CTL_ET_SHIFT 1440#define TX_CTL_CT_MASK 0x800041#define TX_CTL_CT_SHIFT 1542 43/* Rx control register masks and shifts */44#define RX_CTL_NR_MASK 0x7FF45#define RX_CTL_NR_SHIFT 046#define RX_CTL_CRC_MASK 0x200047#define RX_CTL_CRC_SHIFT 1348#define RX_CTL_ER_MASK 0x400049#define RX_CTL_ER_SHIFT 1450#define RX_CTL_CR_MASK 0x800051#define RX_CTL_CR_SHIFT 1552 53/* Interrupt enable for data buffer events register masks and shifts */54#define RX_RDY_MASK 0x155#define RX_RDY_SHIFT 056#define TX_DONE_MASK 0x257#define TX_DONE_SHIFT 158 59/* Gbps Eth MAC Configuration 0 register masks and shifts */60#define CFG_0_RX_EN_MASK 0x161#define CFG_0_RX_EN_SHIFT 062#define CFG_0_TX_EN_MASK 0x263#define CFG_0_TX_EN_SHIFT 164#define CFG_0_TX_FC_EN_MASK 0x465#define CFG_0_TX_FC_EN_SHIFT 266#define CFG_0_TX_PAD_EN_MASK 0x867#define CFG_0_TX_PAD_EN_SHIFT 368#define CFG_0_TX_CRC_EN_MASK 0x1069#define CFG_0_TX_CRC_EN_SHIFT 470#define CFG_0_RX_FC_EN_MASK 0x2071#define CFG_0_RX_FC_EN_SHIFT 572#define CFG_0_RX_CRC_STRIP_MASK 0x4073#define CFG_0_RX_CRC_STRIP_SHIFT 674#define CFG_0_RX_CRC_IGNORE_MASK 0x8075#define CFG_0_RX_CRC_IGNORE_SHIFT 776#define CFG_0_RX_LENGTH_CHECK_EN_MASK 0x10077#define CFG_0_RX_LENGTH_CHECK_EN_SHIFT 878#define CFG_0_TX_FC_RETR_MASK 0xE0079#define CFG_0_TX_FC_RETR_SHIFT 980#define CFG_0_RX_IFG_MASK 0xF00081#define CFG_0_RX_IFG_SHIFT 1282#define CFG_0_TX_IFG_MASK 0x3F000083#define CFG_0_TX_IFG_SHIFT 1684#define CFG_0_RX_PR_CHECK_EN_MASK 0x40000085#define CFG_0_RX_PR_CHECK_EN_SHIFT 2286#define CFG_0_NIB_MODE_MASK 0x80000087#define CFG_0_NIB_MODE_SHIFT 2388#define CFG_0_TX_IFG_NIB_MASK 0xF00000089#define CFG_0_TX_IFG_NIB_SHIFT 2490#define CFG_0_TX_PR_LEN_MASK 0xF000000091#define CFG_0_TX_PR_LEN_SHIFT 2892 93/* Gbps Eth MAC Configuration 1 register masks and shifts */94#define CFG_1_OCTET_0_MASK 0x000000FF95#define CFG_1_OCTET_0_SHIFT 096#define CFG_1_OCTET_1_MASK 0x0000FF0097#define CFG_1_OCTET_1_SHIFT 898#define CFG_1_OCTET_2_MASK 0x00FF000099#define CFG_1_OCTET_2_SHIFT 16100#define CFG_1_OCTET_3_MASK 0xFF000000101#define CFG_1_OCTET_3_SHIFT 24102 103/* Gbps Eth MAC Configuration 2 register masks and shifts */104#define CFG_2_OCTET_4_MASK 0x000000FF105#define CFG_2_OCTET_4_SHIFT 0106#define CFG_2_OCTET_5_MASK 0x0000FF00107#define CFG_2_OCTET_5_SHIFT 8108#define CFG_2_DISK_MC_MASK 0x00100000109#define CFG_2_DISK_MC_SHIFT 20110#define CFG_2_DISK_BC_MASK 0x00200000111#define CFG_2_DISK_BC_SHIFT 21112#define CFG_2_DISK_DA_MASK 0x00400000113#define CFG_2_DISK_DA_SHIFT 22114#define CFG_2_STAT_EN_MASK 0x3000000115#define CFG_2_STAT_EN_SHIFT 24116#define CFG_2_TRANSMIT_FLUSH_EN_MASK 0x80000000117#define CFG_2_TRANSMIT_FLUSH_EN_SHIFT 31118 119/* Gbps Eth MAC Configuration 3 register masks and shifts */120#define CFG_3_TM_HD_MODE_MASK 0x1121#define CFG_3_TM_HD_MODE_SHIFT 0122#define CFG_3_RX_CBFC_EN_MASK 0x2123#define CFG_3_RX_CBFC_EN_SHIFT 1124#define CFG_3_RX_CBFC_REDIR_EN_MASK 0x4125#define CFG_3_RX_CBFC_REDIR_EN_SHIFT 2126#define CFG_3_REDIRECT_CBFC_SEL_MASK 0x18127#define CFG_3_REDIRECT_CBFC_SEL_SHIFT 3128#define CFG_3_CF_DROP_MASK 0x20129#define CFG_3_CF_DROP_SHIFT 5130#define CFG_3_CF_TIMEOUT_MASK 0x3C0131#define CFG_3_CF_TIMEOUT_SHIFT 6132#define CFG_3_RX_IFG_TH_MASK 0x7C00133#define CFG_3_RX_IFG_TH_SHIFT 10134#define CFG_3_TX_CBFC_EN_MASK 0x8000135#define CFG_3_TX_CBFC_EN_SHIFT 15136#define CFG_3_MAX_LEN_MASK 0x3FFF0000137#define CFG_3_MAX_LEN_SHIFT 16138#define CFG_3_EXT_OOB_CBFC_SEL_MASK 0xC0000000139#define CFG_3_EXT_OOB_CBFC_SEL_SHIFT 30140 141/* GE MAC, PCS reset control register masks and shifts */142#define RST_SPCS_MASK 0x1143#define RST_SPCS_SHIFT 0144#define RST_GMAC_0_MASK 0x100145#define RST_GMAC_0_SHIFT 8146 147/* Tx phase sync FIFO control register masks and shifts */148#define PHASE_FIFO_CTL_RST_MASK 0x1149#define PHASE_FIFO_CTL_RST_SHIFT 0150#define PHASE_FIFO_CTL_INIT_MASK 0x2151#define PHASE_FIFO_CTL_INIT_SHIFT 1152 153/**154 * struct nps_enet_priv - Storage of ENET's private information.155 * @regs_base: Base address of ENET memory-mapped control registers.156 * @irq: For RX/TX IRQ number.157 * @tx_skb: socket buffer of sent frame.158 * @napi: Structure for NAPI.159 */160struct nps_enet_priv {161 void __iomem *regs_base;162 s32 irq;163 struct sk_buff *tx_skb;164 struct napi_struct napi;165 u32 ge_mac_cfg_2_value;166 u32 ge_mac_cfg_3_value;167};168 169/**170 * nps_enet_reg_set - Sets ENET register with provided value.171 * @priv: Pointer to EZchip ENET private data structure.172 * @reg: Register offset from base address.173 * @value: Value to set in register.174 */175static inline void nps_enet_reg_set(struct nps_enet_priv *priv,176 s32 reg, s32 value)177{178 iowrite32be(value, priv->regs_base + reg);179}180 181/**182 * nps_enet_reg_get - Gets value of specified ENET register.183 * @priv: Pointer to EZchip ENET private data structure.184 * @reg: Register offset from base address.185 *186 * returns: Value of requested register.187 */188static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg)189{190 return ioread32be(priv->regs_base + reg);191}192 193#endif /* _NPS_ENET_H */194