1433 lines · c
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)2/* Copyright 2017-2019 NXP */3 4#include <linux/unaligned.h>5#include <linux/mdio.h>6#include <linux/module.h>7#include <linux/fsl/enetc_mdio.h>8#include <linux/of_platform.h>9#include <linux/of_mdio.h>10#include <linux/of_net.h>11#include <linux/pcs-lynx.h>12#include "enetc_ierb.h"13#include "enetc_pf.h"14 15#define ENETC_DRV_NAME_STR "ENETC PF driver"16 17static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)18{19 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));20 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));21 22 put_unaligned_le32(upper, addr);23 put_unaligned_le16(lower, addr + 4);24}25 26static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,27 const u8 *addr)28{29 u32 upper = get_unaligned_le32(addr);30 u16 lower = get_unaligned_le16(addr + 4);31 32 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));33 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));34}35 36static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)37{38 struct enetc_ndev_priv *priv = netdev_priv(ndev);39 struct sockaddr *saddr = addr;40 41 if (!is_valid_ether_addr(saddr->sa_data))42 return -EADDRNOTAVAIL;43 44 eth_hw_addr_set(ndev, saddr->sa_data);45 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);46 47 return 0;48}49 50static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)51{52 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);53 54 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);55 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);56}57 58static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)59{60 pf->vlan_promisc_simap |= BIT(si_idx);61 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);62}63 64static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)65{66 pf->vlan_promisc_simap &= ~BIT(si_idx);67 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);68}69 70static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)71{72 u32 val = 0;73 74 if (vlan)75 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;76 77 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);78}79 80static int enetc_mac_addr_hash_idx(const u8 *addr)81{82 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;83 u64 mask = 0;84 int res = 0;85 int i;86 87 for (i = 0; i < 8; i++)88 mask |= BIT_ULL(i * 6);89 90 for (i = 0; i < 6; i++)91 res |= (hweight64(fold & (mask << i)) & 0x1) << i;92 93 return res;94}95 96static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)97{98 filter->mac_addr_cnt = 0;99 100 bitmap_zero(filter->mac_hash_table,101 ENETC_MADDR_HASH_TBL_SZ);102}103 104static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,105 const unsigned char *addr)106{107 /* add exact match addr */108 ether_addr_copy(filter->mac_addr, addr);109 filter->mac_addr_cnt++;110}111 112static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,113 const unsigned char *addr)114{115 int idx = enetc_mac_addr_hash_idx(addr);116 117 /* add hash table entry */118 __set_bit(idx, filter->mac_hash_table);119 filter->mac_addr_cnt++;120}121 122static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)123{124 bool err = si->errata & ENETC_ERR_UCMCSWP;125 126 if (type == UC) {127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);128 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);129 } else { /* MC */130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);131 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);132 }133}134 135static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,136 unsigned long hash)137{138 bool err = si->errata & ENETC_ERR_UCMCSWP;139 140 if (type == UC) {141 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),142 lower_32_bits(hash));143 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),144 upper_32_bits(hash));145 } else { /* MC */146 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),147 lower_32_bits(hash));148 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),149 upper_32_bits(hash));150 }151}152 153static void enetc_sync_mac_filters(struct enetc_pf *pf)154{155 struct enetc_mac_filter *f = pf->mac_filter;156 struct enetc_si *si = pf->si;157 int i, pos;158 159 pos = EMETC_MAC_ADDR_FILT_RES;160 161 for (i = 0; i < MADDR_TYPE; i++, f++) {162 bool em = (f->mac_addr_cnt == 1) && (i == UC);163 bool clear = !f->mac_addr_cnt;164 165 if (clear) {166 if (i == UC)167 enetc_clear_mac_flt_entry(si, pos);168 169 enetc_clear_mac_ht_flt(si, 0, i);170 continue;171 }172 173 /* exact match filter */174 if (em) {175 int err;176 177 enetc_clear_mac_ht_flt(si, 0, UC);178 179 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,180 BIT(0));181 if (!err)182 continue;183 184 /* fallback to HT filtering */185 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",186 err);187 }188 189 /* hash table filter, clear EM filter for UC entries */190 if (i == UC)191 enetc_clear_mac_flt_entry(si, pos);192 193 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);194 }195}196 197static void enetc_pf_set_rx_mode(struct net_device *ndev)198{199 struct enetc_ndev_priv *priv = netdev_priv(ndev);200 struct enetc_pf *pf = enetc_si_priv(priv->si);201 struct enetc_hw *hw = &priv->si->hw;202 bool uprom = false, mprom = false;203 struct enetc_mac_filter *filter;204 struct netdev_hw_addr *ha;205 u32 psipmr = 0;206 bool em;207 208 if (ndev->flags & IFF_PROMISC) {209 /* enable promisc mode for SI0 (PF) */210 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);211 uprom = true;212 mprom = true;213 } else if (ndev->flags & IFF_ALLMULTI) {214 /* enable multi cast promisc mode for SI0 (PF) */215 psipmr = ENETC_PSIPMR_SET_MP(0);216 mprom = true;217 }218 219 /* first 2 filter entries belong to PF */220 if (!uprom) {221 /* Update unicast filters */222 filter = &pf->mac_filter[UC];223 enetc_reset_mac_addr_filter(filter);224 225 em = (netdev_uc_count(ndev) == 1);226 netdev_for_each_uc_addr(ha, ndev) {227 if (em) {228 enetc_add_mac_addr_em_filter(filter, ha->addr);229 break;230 }231 232 enetc_add_mac_addr_ht_filter(filter, ha->addr);233 }234 }235 236 if (!mprom) {237 /* Update multicast filters */238 filter = &pf->mac_filter[MC];239 enetc_reset_mac_addr_filter(filter);240 241 netdev_for_each_mc_addr(ha, ndev) {242 if (!is_multicast_ether_addr(ha->addr))243 continue;244 245 enetc_add_mac_addr_ht_filter(filter, ha->addr);246 }247 }248 249 if (!uprom || !mprom)250 /* update PF entries */251 enetc_sync_mac_filters(pf);252 253 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &254 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));255 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);256}257 258static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,259 unsigned long hash)260{261 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));262 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));263}264 265static int enetc_vid_hash_idx(unsigned int vid)266{267 int res = 0;268 int i;269 270 for (i = 0; i < 6; i++)271 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;272 273 return res;274}275 276static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)277{278 int i;279 280 if (rehash) {281 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);282 283 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {284 int hidx = enetc_vid_hash_idx(i);285 286 __set_bit(hidx, pf->vlan_ht_filter);287 }288 }289 290 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);291}292 293static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)294{295 struct enetc_ndev_priv *priv = netdev_priv(ndev);296 struct enetc_pf *pf = enetc_si_priv(priv->si);297 int idx;298 299 __set_bit(vid, pf->active_vlans);300 301 idx = enetc_vid_hash_idx(vid);302 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))303 enetc_sync_vlan_ht_filter(pf, false);304 305 return 0;306}307 308static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)309{310 struct enetc_ndev_priv *priv = netdev_priv(ndev);311 struct enetc_pf *pf = enetc_si_priv(priv->si);312 313 __clear_bit(vid, pf->active_vlans);314 enetc_sync_vlan_ht_filter(pf, true);315 316 return 0;317}318 319static void enetc_set_loopback(struct net_device *ndev, bool en)320{321 struct enetc_ndev_priv *priv = netdev_priv(ndev);322 struct enetc_si *si = priv->si;323 u32 reg;324 325 reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);326 if (reg & ENETC_PM0_IFM_RG) {327 /* RGMII mode */328 reg = (reg & ~ENETC_PM0_IFM_RLP) |329 (en ? ENETC_PM0_IFM_RLP : 0);330 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);331 } else {332 /* assume SGMII mode */333 reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);334 reg = (reg & ~ENETC_PM0_CMD_XGLP) |335 (en ? ENETC_PM0_CMD_XGLP : 0);336 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |337 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);338 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);339 }340}341 342static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)343{344 struct enetc_ndev_priv *priv = netdev_priv(ndev);345 struct enetc_pf *pf = enetc_si_priv(priv->si);346 struct enetc_vf_state *vf_state;347 348 if (vf >= pf->total_vfs)349 return -EINVAL;350 351 if (!is_valid_ether_addr(mac))352 return -EADDRNOTAVAIL;353 354 vf_state = &pf->vf_state[vf];355 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;356 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);357 return 0;358}359 360static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,361 u8 qos, __be16 proto)362{363 struct enetc_ndev_priv *priv = netdev_priv(ndev);364 struct enetc_pf *pf = enetc_si_priv(priv->si);365 366 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)367 return -EOPNOTSUPP;368 369 if (vf >= pf->total_vfs)370 return -EINVAL;371 372 if (proto != htons(ETH_P_8021Q))373 /* only C-tags supported for now */374 return -EPROTONOSUPPORT;375 376 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);377 return 0;378}379 380static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)381{382 struct enetc_ndev_priv *priv = netdev_priv(ndev);383 struct enetc_pf *pf = enetc_si_priv(priv->si);384 u32 cfgr;385 386 if (vf >= pf->total_vfs)387 return -EINVAL;388 389 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));390 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);391 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);392 393 return 0;394}395 396static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,397 int si)398{399 struct device *dev = &pf->si->pdev->dev;400 struct enetc_hw *hw = &pf->si->hw;401 u8 mac_addr[ETH_ALEN] = { 0 };402 int err;403 404 /* (1) try to get the MAC address from the device tree */405 if (np) {406 err = of_get_mac_address(np, mac_addr);407 if (err == -EPROBE_DEFER)408 return err;409 }410 411 /* (2) bootloader supplied MAC address */412 if (is_zero_ether_addr(mac_addr))413 enetc_pf_get_primary_mac_addr(hw, si, mac_addr);414 415 /* (3) choose a random one */416 if (is_zero_ether_addr(mac_addr)) {417 eth_random_addr(mac_addr);418 dev_info(dev, "no MAC address specified for SI%d, using %pM\n",419 si, mac_addr);420 }421 422 enetc_pf_set_primary_mac_addr(hw, si, mac_addr);423 424 return 0;425}426 427static int enetc_setup_mac_addresses(struct device_node *np,428 struct enetc_pf *pf)429{430 int err, i;431 432 /* The PF might take its MAC from the device tree */433 err = enetc_setup_mac_address(np, pf, 0);434 if (err)435 return err;436 437 for (i = 0; i < pf->total_vfs; i++) {438 err = enetc_setup_mac_address(NULL, pf, i + 1);439 if (err)440 return err;441 }442 443 return 0;444}445 446static void enetc_port_assign_rfs_entries(struct enetc_si *si)447{448 struct enetc_pf *pf = enetc_si_priv(si);449 struct enetc_hw *hw = &si->hw;450 int num_entries, vf_entries, i;451 u32 val;452 453 /* split RFS entries between functions */454 val = enetc_port_rd(hw, ENETC_PRFSCAPR);455 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);456 vf_entries = num_entries / (pf->total_vfs + 1);457 458 for (i = 0; i < pf->total_vfs; i++)459 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),461 num_entries - vf_entries * pf->total_vfs);462 463 /* enable RFS on port */464 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);465}466 467static void enetc_port_si_configure(struct enetc_si *si)468{469 struct enetc_pf *pf = enetc_si_priv(si);470 struct enetc_hw *hw = &si->hw;471 int num_rings, i;472 u32 val;473 474 val = enetc_port_rd(hw, ENETC_PCAPR0);475 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));476 477 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);478 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);479 480 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {481 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);482 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);483 484 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",485 num_rings, ENETC_PF_NUM_RINGS);486 487 num_rings = 0;488 }489 490 /* Add default one-time settings for SI0 (PF) */491 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);492 493 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);494 495 if (num_rings)496 num_rings -= ENETC_PF_NUM_RINGS;497 498 /* Configure the SIs for each available VF */499 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);500 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;501 502 if (num_rings) {503 num_rings /= pf->total_vfs;504 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);505 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);506 }507 508 for (i = 0; i < pf->total_vfs; i++)509 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);510 511 /* Port level VLAN settings */512 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);513 enetc_port_wr(hw, ENETC_PVCLCTR, val);514 /* use outer tag for VLAN filtering */515 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);516}517 518void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)519{520 int tc;521 522 for (tc = 0; tc < 8; tc++) {523 u32 val = ENETC_MAC_MAXFRM_SIZE;524 525 if (max_sdu[tc])526 val = max_sdu[tc] + VLAN_ETH_HLEN;527 528 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);529 }530}531 532void enetc_reset_ptcmsdur(struct enetc_hw *hw)533{534 int tc;535 536 for (tc = 0; tc < 8; tc++)537 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);538}539 540static void enetc_configure_port_mac(struct enetc_si *si)541{542 struct enetc_hw *hw = &si->hw;543 544 enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,545 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));546 547 enetc_reset_ptcmsdur(hw);548 549 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |550 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);551 552 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high553 * and may lead to RX lock-up under traffic. Set it to 1 instead,554 * as recommended by the hardware team.555 */556 enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);557}558 559static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)560{561 u32 val;562 563 if (phy_interface_mode_is_rgmii(phy_mode)) {564 val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);565 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);566 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;567 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);568 }569 570 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {571 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;572 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);573 }574}575 576static void enetc_mac_enable(struct enetc_si *si, bool en)577{578 u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);579 580 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);581 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;582 583 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);584}585 586static void enetc_configure_port(struct enetc_pf *pf)587{588 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];589 struct enetc_hw *hw = &pf->si->hw;590 591 enetc_configure_port_mac(pf->si);592 593 enetc_port_si_configure(pf->si);594 595 /* set up hash key */596 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);597 enetc_set_rss_key(hw, hash_key);598 599 /* split up RFS entries */600 enetc_port_assign_rfs_entries(pf->si);601 602 /* enforce VLAN promisc mode for all SIs */603 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;604 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);605 606 enetc_port_wr(hw, ENETC_PSIPMR, 0);607 608 /* enable port */609 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);610}611 612/* Messaging */613static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,614 int vf_id)615{616 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];617 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];618 struct enetc_msg_cmd_set_primary_mac *cmd;619 struct device *dev = &pf->si->pdev->dev;620 u16 cmd_id;621 char *addr;622 623 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;624 cmd_id = cmd->header.id;625 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)626 return ENETC_MSG_CMD_STATUS_FAIL;627 628 addr = cmd->mac.sa_data;629 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)630 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",631 vf_id);632 else633 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);634 635 return ENETC_MSG_CMD_STATUS_OK;636}637 638void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)639{640 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];641 struct device *dev = &pf->si->pdev->dev;642 struct enetc_msg_cmd_header *cmd_hdr;643 u16 cmd_type;644 645 *status = ENETC_MSG_CMD_STATUS_OK;646 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;647 cmd_type = cmd_hdr->type;648 649 switch (cmd_type) {650 case ENETC_MSG_CMD_MNG_MAC:651 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);652 break;653 default:654 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",655 cmd_type);656 }657}658 659#ifdef CONFIG_PCI_IOV660static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)661{662 struct enetc_si *si = pci_get_drvdata(pdev);663 struct enetc_pf *pf = enetc_si_priv(si);664 int err;665 666 if (!num_vfs) {667 enetc_msg_psi_free(pf);668 pf->num_vfs = 0;669 pci_disable_sriov(pdev);670 } else {671 pf->num_vfs = num_vfs;672 673 err = enetc_msg_psi_init(pf);674 if (err) {675 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);676 goto err_msg_psi;677 }678 679 err = pci_enable_sriov(pdev, num_vfs);680 if (err) {681 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);682 goto err_en_sriov;683 }684 }685 686 return num_vfs;687 688err_en_sriov:689 enetc_msg_psi_free(pf);690err_msg_psi:691 pf->num_vfs = 0;692 693 return err;694}695#else696#define enetc_sriov_configure(pdev, num_vfs) (void)0697#endif698 699static int enetc_pf_set_features(struct net_device *ndev,700 netdev_features_t features)701{702 netdev_features_t changed = ndev->features ^ features;703 struct enetc_ndev_priv *priv = netdev_priv(ndev);704 int err;705 706 if (changed & NETIF_F_HW_TC) {707 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));708 if (err)709 return err;710 }711 712 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {713 struct enetc_pf *pf = enetc_si_priv(priv->si);714 715 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))716 enetc_disable_si_vlan_promisc(pf, 0);717 else718 enetc_enable_si_vlan_promisc(pf, 0);719 }720 721 if (changed & NETIF_F_LOOPBACK)722 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));723 724 enetc_set_features(ndev, features);725 726 return 0;727}728 729static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,730 void *type_data)731{732 switch (type) {733 case TC_QUERY_CAPS:734 return enetc_qos_query_caps(ndev, type_data);735 case TC_SETUP_QDISC_MQPRIO:736 return enetc_setup_tc_mqprio(ndev, type_data);737 case TC_SETUP_QDISC_TAPRIO:738 return enetc_setup_tc_taprio(ndev, type_data);739 case TC_SETUP_QDISC_CBS:740 return enetc_setup_tc_cbs(ndev, type_data);741 case TC_SETUP_QDISC_ETF:742 return enetc_setup_tc_txtime(ndev, type_data);743 case TC_SETUP_BLOCK:744 return enetc_setup_tc_psfp(ndev, type_data);745 default:746 return -EOPNOTSUPP;747 }748}749 750static const struct net_device_ops enetc_ndev_ops = {751 .ndo_open = enetc_open,752 .ndo_stop = enetc_close,753 .ndo_start_xmit = enetc_xmit,754 .ndo_get_stats = enetc_get_stats,755 .ndo_set_mac_address = enetc_pf_set_mac_addr,756 .ndo_set_rx_mode = enetc_pf_set_rx_mode,757 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,758 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,759 .ndo_set_vf_mac = enetc_pf_set_vf_mac,760 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,761 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,762 .ndo_set_features = enetc_pf_set_features,763 .ndo_eth_ioctl = enetc_ioctl,764 .ndo_setup_tc = enetc_pf_setup_tc,765 .ndo_bpf = enetc_setup_bpf,766 .ndo_xdp_xmit = enetc_xdp_xmit,767};768 769static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,770 const struct net_device_ops *ndev_ops)771{772 struct enetc_ndev_priv *priv = netdev_priv(ndev);773 774 SET_NETDEV_DEV(ndev, &si->pdev->dev);775 priv->ndev = ndev;776 priv->si = si;777 priv->dev = &si->pdev->dev;778 si->ndev = ndev;779 780 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;781 ndev->netdev_ops = ndev_ops;782 enetc_set_ethtool_ops(ndev);783 ndev->watchdog_timeo = 5 * HZ;784 ndev->max_mtu = ENETC_MAX_MTU;785 786 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |787 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |788 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK |789 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;790 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |791 NETIF_F_HW_VLAN_CTAG_TX |792 NETIF_F_HW_VLAN_CTAG_RX |793 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;794 ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM |795 NETIF_F_TSO | NETIF_F_TSO6;796 797 if (si->num_rss)798 ndev->hw_features |= NETIF_F_RXHASH;799 800 ndev->priv_flags |= IFF_UNICAST_FLT;801 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |802 NETDEV_XDP_ACT_NDO_XMIT | NETDEV_XDP_ACT_RX_SG |803 NETDEV_XDP_ACT_NDO_XMIT_SG;804 805 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {806 priv->active_offloads |= ENETC_F_QCI;807 ndev->features |= NETIF_F_HW_TC;808 ndev->hw_features |= NETIF_F_HW_TC;809 }810 811 /* pick up primary MAC address from SI */812 enetc_load_primary_mac_addr(&si->hw, ndev);813}814 815static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)816{817 struct device *dev = &pf->si->pdev->dev;818 struct enetc_mdio_priv *mdio_priv;819 struct mii_bus *bus;820 int err;821 822 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));823 if (!bus)824 return -ENOMEM;825 826 bus->name = "Freescale ENETC MDIO Bus";827 bus->read = enetc_mdio_read_c22;828 bus->write = enetc_mdio_write_c22;829 bus->read_c45 = enetc_mdio_read_c45;830 bus->write_c45 = enetc_mdio_write_c45;831 bus->parent = dev;832 mdio_priv = bus->priv;833 mdio_priv->hw = &pf->si->hw;834 mdio_priv->mdio_base = ENETC_EMDIO_BASE;835 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));836 837 err = of_mdiobus_register(bus, np);838 if (err)839 return dev_err_probe(dev, err, "cannot register MDIO bus\n");840 841 pf->mdio = bus;842 843 return 0;844}845 846static void enetc_mdio_remove(struct enetc_pf *pf)847{848 if (pf->mdio)849 mdiobus_unregister(pf->mdio);850}851 852static int enetc_imdio_create(struct enetc_pf *pf)853{854 struct device *dev = &pf->si->pdev->dev;855 struct enetc_mdio_priv *mdio_priv;856 struct phylink_pcs *phylink_pcs;857 struct mii_bus *bus;858 int err;859 860 bus = mdiobus_alloc_size(sizeof(*mdio_priv));861 if (!bus)862 return -ENOMEM;863 864 bus->name = "Freescale ENETC internal MDIO Bus";865 bus->read = enetc_mdio_read_c22;866 bus->write = enetc_mdio_write_c22;867 bus->read_c45 = enetc_mdio_read_c45;868 bus->write_c45 = enetc_mdio_write_c45;869 bus->parent = dev;870 bus->phy_mask = ~0;871 mdio_priv = bus->priv;872 mdio_priv->hw = &pf->si->hw;873 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;874 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));875 876 err = mdiobus_register(bus);877 if (err) {878 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);879 goto free_mdio_bus;880 }881 882 phylink_pcs = lynx_pcs_create_mdiodev(bus, 0);883 if (IS_ERR(phylink_pcs)) {884 err = PTR_ERR(phylink_pcs);885 dev_err(dev, "cannot create lynx pcs (%d)\n", err);886 goto unregister_mdiobus;887 }888 889 pf->imdio = bus;890 pf->pcs = phylink_pcs;891 892 return 0;893 894unregister_mdiobus:895 mdiobus_unregister(bus);896free_mdio_bus:897 mdiobus_free(bus);898 return err;899}900 901static void enetc_imdio_remove(struct enetc_pf *pf)902{903 if (pf->pcs)904 lynx_pcs_destroy(pf->pcs);905 if (pf->imdio) {906 mdiobus_unregister(pf->imdio);907 mdiobus_free(pf->imdio);908 }909}910 911static bool enetc_port_has_pcs(struct enetc_pf *pf)912{913 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||914 pf->if_mode == PHY_INTERFACE_MODE_1000BASEX ||915 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||916 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);917}918 919static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)920{921 struct device_node *mdio_np;922 int err;923 924 mdio_np = of_get_child_by_name(node, "mdio");925 if (mdio_np) {926 err = enetc_mdio_probe(pf, mdio_np);927 928 of_node_put(mdio_np);929 if (err)930 return err;931 }932 933 if (enetc_port_has_pcs(pf)) {934 err = enetc_imdio_create(pf);935 if (err) {936 enetc_mdio_remove(pf);937 return err;938 }939 }940 941 return 0;942}943 944static void enetc_mdiobus_destroy(struct enetc_pf *pf)945{946 enetc_mdio_remove(pf);947 enetc_imdio_remove(pf);948}949 950static struct phylink_pcs *951enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)952{953 struct enetc_pf *pf = phylink_to_enetc_pf(config);954 955 return pf->pcs;956}957 958static void enetc_pl_mac_config(struct phylink_config *config,959 unsigned int mode,960 const struct phylink_link_state *state)961{962 struct enetc_pf *pf = phylink_to_enetc_pf(config);963 964 enetc_mac_config(pf->si, state->interface);965}966 967static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)968{969 u32 old_val, val;970 971 old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);972 973 if (speed == SPEED_1000) {974 val &= ~ENETC_PM0_IFM_SSP_MASK;975 val |= ENETC_PM0_IFM_SSP_1000;976 } else if (speed == SPEED_100) {977 val &= ~ENETC_PM0_IFM_SSP_MASK;978 val |= ENETC_PM0_IFM_SSP_100;979 } else if (speed == SPEED_10) {980 val &= ~ENETC_PM0_IFM_SSP_MASK;981 val |= ENETC_PM0_IFM_SSP_10;982 }983 984 if (duplex == DUPLEX_FULL)985 val |= ENETC_PM0_IFM_FULL_DPX;986 else987 val &= ~ENETC_PM0_IFM_FULL_DPX;988 989 if (val == old_val)990 return;991 992 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);993}994 995static void enetc_pl_mac_link_up(struct phylink_config *config,996 struct phy_device *phy, unsigned int mode,997 phy_interface_t interface, int speed,998 int duplex, bool tx_pause, bool rx_pause)999{1000 struct enetc_pf *pf = phylink_to_enetc_pf(config);1001 u32 pause_off_thresh = 0, pause_on_thresh = 0;1002 u32 init_quanta = 0, refresh_quanta = 0;1003 struct enetc_hw *hw = &pf->si->hw;1004 struct enetc_si *si = pf->si;1005 struct enetc_ndev_priv *priv;1006 u32 rbmr, cmd_cfg;1007 int idx;1008 1009 priv = netdev_priv(pf->si->ndev);1010 1011 if (pf->si->hw_features & ENETC_SI_F_QBV)1012 enetc_sched_speed_set(priv, speed);1013 1014 if (!phylink_autoneg_inband(mode) &&1015 phy_interface_mode_is_rgmii(interface))1016 enetc_force_rgmii_mac(si, speed, duplex);1017 1018 /* Flow control */1019 for (idx = 0; idx < priv->num_rx_rings; idx++) {1020 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);1021 1022 if (tx_pause)1023 rbmr |= ENETC_RBMR_CM;1024 else1025 rbmr &= ~ENETC_RBMR_CM;1026 1027 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);1028 }1029 1030 if (tx_pause) {1031 /* When the port first enters congestion, send a PAUSE request1032 * with the maximum number of quanta. When the port exits1033 * congestion, it will automatically send a PAUSE frame with1034 * zero quanta.1035 */1036 init_quanta = 0xffff;1037 1038 /* Also, set up the refresh timer to send follow-up PAUSE1039 * frames at half the quanta value, in case the congestion1040 * condition persists.1041 */1042 refresh_quanta = 0xffff / 2;1043 1044 /* Start emitting PAUSE frames when 3 large frames (or more1045 * smaller frames) have accumulated in the FIFO waiting to be1046 * DMAed to the RX ring.1047 */1048 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;1049 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;1050 }1051 1052 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);1053 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);1054 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);1055 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);1056 1057 cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);1058 1059 if (rx_pause)1060 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;1061 else1062 cmd_cfg |= ENETC_PM0_PAUSE_IGN;1063 1064 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);1065 1066 enetc_mac_enable(si, true);1067 1068 if (si->hw_features & ENETC_SI_F_QBU)1069 enetc_mm_link_state_update(priv, true);1070}1071 1072static void enetc_pl_mac_link_down(struct phylink_config *config,1073 unsigned int mode,1074 phy_interface_t interface)1075{1076 struct enetc_pf *pf = phylink_to_enetc_pf(config);1077 struct enetc_si *si = pf->si;1078 struct enetc_ndev_priv *priv;1079 1080 priv = netdev_priv(si->ndev);1081 1082 if (si->hw_features & ENETC_SI_F_QBU)1083 enetc_mm_link_state_update(priv, false);1084 1085 enetc_mac_enable(si, false);1086}1087 1088static const struct phylink_mac_ops enetc_mac_phylink_ops = {1089 .mac_select_pcs = enetc_pl_mac_select_pcs,1090 .mac_config = enetc_pl_mac_config,1091 .mac_link_up = enetc_pl_mac_link_up,1092 .mac_link_down = enetc_pl_mac_link_down,1093};1094 1095static int enetc_phylink_create(struct enetc_ndev_priv *priv,1096 struct device_node *node)1097{1098 struct enetc_pf *pf = enetc_si_priv(priv->si);1099 struct phylink *phylink;1100 int err;1101 1102 pf->phylink_config.dev = &priv->ndev->dev;1103 pf->phylink_config.type = PHYLINK_NETDEV;1104 pf->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |1105 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;1106 1107 __set_bit(PHY_INTERFACE_MODE_INTERNAL,1108 pf->phylink_config.supported_interfaces);1109 __set_bit(PHY_INTERFACE_MODE_SGMII,1110 pf->phylink_config.supported_interfaces);1111 __set_bit(PHY_INTERFACE_MODE_1000BASEX,1112 pf->phylink_config.supported_interfaces);1113 __set_bit(PHY_INTERFACE_MODE_2500BASEX,1114 pf->phylink_config.supported_interfaces);1115 __set_bit(PHY_INTERFACE_MODE_USXGMII,1116 pf->phylink_config.supported_interfaces);1117 phy_interface_set_rgmii(pf->phylink_config.supported_interfaces);1118 1119 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),1120 pf->if_mode, &enetc_mac_phylink_ops);1121 if (IS_ERR(phylink)) {1122 err = PTR_ERR(phylink);1123 return err;1124 }1125 1126 priv->phylink = phylink;1127 1128 return 0;1129}1130 1131static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)1132{1133 phylink_destroy(priv->phylink);1134}1135 1136/* Initialize the entire shared memory for the flow steering entries1137 * of this port (PF + VFs)1138 */1139static int enetc_init_port_rfs_memory(struct enetc_si *si)1140{1141 struct enetc_cmd_rfse rfse = {0};1142 struct enetc_hw *hw = &si->hw;1143 int num_rfs, i, err = 0;1144 u32 val;1145 1146 val = enetc_port_rd(hw, ENETC_PRFSCAPR);1147 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);1148 1149 for (i = 0; i < num_rfs; i++) {1150 err = enetc_set_fs_entry(si, &rfse, i);1151 if (err)1152 break;1153 }1154 1155 return err;1156}1157 1158static int enetc_init_port_rss_memory(struct enetc_si *si)1159{1160 struct enetc_hw *hw = &si->hw;1161 int num_rss, err;1162 int *rss_table;1163 u32 val;1164 1165 val = enetc_port_rd(hw, ENETC_PRSSCAPR);1166 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);1167 if (!num_rss)1168 return 0;1169 1170 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);1171 if (!rss_table)1172 return -ENOMEM;1173 1174 err = enetc_set_rss_table(si, rss_table, num_rss);1175 1176 kfree(rss_table);1177 1178 return err;1179}1180 1181static int enetc_pf_register_with_ierb(struct pci_dev *pdev)1182{1183 struct platform_device *ierb_pdev;1184 struct device_node *ierb_node;1185 1186 ierb_node = of_find_compatible_node(NULL, NULL,1187 "fsl,ls1028a-enetc-ierb");1188 if (!ierb_node || !of_device_is_available(ierb_node))1189 return -ENODEV;1190 1191 ierb_pdev = of_find_device_by_node(ierb_node);1192 of_node_put(ierb_node);1193 1194 if (!ierb_pdev)1195 return -EPROBE_DEFER;1196 1197 return enetc_ierb_register_pf(ierb_pdev, pdev);1198}1199 1200static struct enetc_si *enetc_psi_create(struct pci_dev *pdev)1201{1202 struct enetc_si *si;1203 int err;1204 1205 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf));1206 if (err) {1207 dev_err_probe(&pdev->dev, err, "PCI probing failed\n");1208 goto out;1209 }1210 1211 si = pci_get_drvdata(pdev);1212 if (!si->hw.port || !si->hw.global) {1213 err = -ENODEV;1214 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");1215 goto out_pci_remove;1216 }1217 1218 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,1219 &si->cbd_ring);1220 if (err)1221 goto out_pci_remove;1222 1223 err = enetc_init_port_rfs_memory(si);1224 if (err) {1225 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");1226 goto out_teardown_cbdr;1227 }1228 1229 err = enetc_init_port_rss_memory(si);1230 if (err) {1231 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");1232 goto out_teardown_cbdr;1233 }1234 1235 return si;1236 1237out_teardown_cbdr:1238 enetc_teardown_cbdr(&si->cbd_ring);1239out_pci_remove:1240 enetc_pci_remove(pdev);1241out:1242 return ERR_PTR(err);1243}1244 1245static void enetc_psi_destroy(struct pci_dev *pdev)1246{1247 struct enetc_si *si = pci_get_drvdata(pdev);1248 1249 enetc_teardown_cbdr(&si->cbd_ring);1250 enetc_pci_remove(pdev);1251}1252 1253static int enetc_pf_probe(struct pci_dev *pdev,1254 const struct pci_device_id *ent)1255{1256 struct device_node *node = pdev->dev.of_node;1257 struct enetc_ndev_priv *priv;1258 struct net_device *ndev;1259 struct enetc_si *si;1260 struct enetc_pf *pf;1261 int err;1262 1263 err = enetc_pf_register_with_ierb(pdev);1264 if (err == -EPROBE_DEFER)1265 return err;1266 if (err)1267 dev_warn(&pdev->dev,1268 "Could not register with IERB driver: %pe, please update the device tree\n",1269 ERR_PTR(err));1270 1271 si = enetc_psi_create(pdev);1272 if (IS_ERR(si)) {1273 err = PTR_ERR(si);1274 goto err_psi_create;1275 }1276 1277 pf = enetc_si_priv(si);1278 pf->si = si;1279 pf->total_vfs = pci_sriov_get_totalvfs(pdev);1280 if (pf->total_vfs) {1281 pf->vf_state = kcalloc(pf->total_vfs, sizeof(struct enetc_vf_state),1282 GFP_KERNEL);1283 if (!pf->vf_state)1284 goto err_alloc_vf_state;1285 }1286 1287 err = enetc_setup_mac_addresses(node, pf);1288 if (err)1289 goto err_setup_mac_addresses;1290 1291 enetc_configure_port(pf);1292 1293 enetc_get_si_caps(si);1294 1295 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);1296 if (!ndev) {1297 err = -ENOMEM;1298 dev_err(&pdev->dev, "netdev creation failed\n");1299 goto err_alloc_netdev;1300 }1301 1302 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);1303 1304 priv = netdev_priv(ndev);1305 1306 mutex_init(&priv->mm_lock);1307 1308 enetc_init_si_rings_params(priv);1309 1310 err = enetc_alloc_si_resources(priv);1311 if (err) {1312 dev_err(&pdev->dev, "SI resource alloc failed\n");1313 goto err_alloc_si_res;1314 }1315 1316 err = enetc_configure_si(priv);1317 if (err) {1318 dev_err(&pdev->dev, "Failed to configure SI\n");1319 goto err_config_si;1320 }1321 1322 err = enetc_alloc_msix(priv);1323 if (err) {1324 dev_err(&pdev->dev, "MSIX alloc failed\n");1325 goto err_alloc_msix;1326 }1327 1328 err = of_get_phy_mode(node, &pf->if_mode);1329 if (err) {1330 dev_err(&pdev->dev, "Failed to read PHY mode\n");1331 goto err_phy_mode;1332 }1333 1334 err = enetc_mdiobus_create(pf, node);1335 if (err)1336 goto err_mdiobus_create;1337 1338 err = enetc_phylink_create(priv, node);1339 if (err)1340 goto err_phylink_create;1341 1342 err = register_netdev(ndev);1343 if (err)1344 goto err_reg_netdev;1345 1346 return 0;1347 1348err_reg_netdev:1349 enetc_phylink_destroy(priv);1350err_phylink_create:1351 enetc_mdiobus_destroy(pf);1352err_mdiobus_create:1353err_phy_mode:1354 enetc_free_msix(priv);1355err_config_si:1356err_alloc_msix:1357 enetc_free_si_resources(priv);1358err_alloc_si_res:1359 si->ndev = NULL;1360 free_netdev(ndev);1361err_alloc_netdev:1362err_setup_mac_addresses:1363 kfree(pf->vf_state);1364err_alloc_vf_state:1365 enetc_psi_destroy(pdev);1366err_psi_create:1367 return err;1368}1369 1370static void enetc_pf_remove(struct pci_dev *pdev)1371{1372 struct enetc_si *si = pci_get_drvdata(pdev);1373 struct enetc_pf *pf = enetc_si_priv(si);1374 struct enetc_ndev_priv *priv;1375 1376 priv = netdev_priv(si->ndev);1377 1378 if (pf->num_vfs)1379 enetc_sriov_configure(pdev, 0);1380 1381 unregister_netdev(si->ndev);1382 1383 enetc_phylink_destroy(priv);1384 enetc_mdiobus_destroy(pf);1385 1386 enetc_free_msix(priv);1387 1388 enetc_free_si_resources(priv);1389 1390 free_netdev(si->ndev);1391 kfree(pf->vf_state);1392 1393 enetc_psi_destroy(pdev);1394}1395 1396static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev)1397{1398 struct device_node *node = pdev->dev.of_node;1399 struct enetc_si *si;1400 1401 /* Only apply quirk for disabled functions. For the ones1402 * that are enabled, enetc_pf_probe() will apply it.1403 */1404 if (node && of_device_is_available(node))1405 return;1406 1407 si = enetc_psi_create(pdev);1408 if (!IS_ERR(si))1409 enetc_psi_destroy(pdev);1410}1411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF,1412 enetc_fixup_clear_rss_rfs);1413 1414static const struct pci_device_id enetc_pf_id_table[] = {1415 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },1416 { 0, } /* End of table. */1417};1418MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);1419 1420static struct pci_driver enetc_pf_driver = {1421 .name = KBUILD_MODNAME,1422 .id_table = enetc_pf_id_table,1423 .probe = enetc_pf_probe,1424 .remove = enetc_pf_remove,1425#ifdef CONFIG_PCI_IOV1426 .sriov_configure = enetc_sriov_configure,1427#endif1428};1429module_pci_driver(enetc_pf_driver);1430 1431MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);1432MODULE_LICENSE("Dual BSD/GPL");1433