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1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later2/*3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.4 */5 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt7 8#include "fman_memac.h"9#include "fman.h"10#include "mac.h"11 12#include <linux/slab.h>13#include <linux/io.h>14#include <linux/pcs-lynx.h>15#include <linux/phy.h>16#include <linux/phy_fixed.h>17#include <linux/phy/phy.h>18#include <linux/of_mdio.h>19 20/* Num of additional exact match MAC adr regs */21#define MEMAC_NUM_OF_PADDRS 722 23/* Control and Configuration Register (COMMAND_CONFIG) */24#define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */25#define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */26#define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */27#define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */28#define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */29#define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */30#define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */31#define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */32#define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */33#define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */34#define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */35#define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */36 37/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */38#define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF000039#define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF40#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x0040000041#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x0010000042#define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x0000001943#define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x0000002044#define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x0000006045 46#define GET_TX_EMPTY_DEFAULT_VALUE(_val) \47do { \48 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \49 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \50 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\51 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\52} while (0)53 54/* Interface Mode Register (IF_MODE) */55 56#define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */57#define IF_MODE_10G 0x00000000 /* 30-31 10G interface */58#define IF_MODE_MII 0x00000001 /* 30-31 MII interface */59#define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */60#define IF_MODE_RGMII 0x0000000461#define IF_MODE_RGMII_AUTO 0x0000800062#define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */63#define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */64#define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */65#define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */66#define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */67#define IF_MODE_HD 0x00000040 /* Half duplex operation */68 69/* Hash table Control Register (HASHTABLE_CTRL) */70#define HASH_CTRL_MCAST_EN 0x0000010071/* 26-31 Hash table address code */72#define HASH_CTRL_ADDR_MASK 0x0000003F73/* MAC mcast indication */74#define GROUP_ADDRESS 0x0000010000000000LL75#define HASH_TABLE_SIZE 64 /* Hash tbl size */76 77/* Interrupt Mask Register (IMASK) */78#define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */79#define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */80#define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */81#define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */82 83#define MEMAC_ALL_ERRS_IMASK \84 ((u32)(MEMAC_IMASK_TSECC_ER | \85 MEMAC_IMASK_TECC_ER | \86 MEMAC_IMASK_RECC_ER | \87 MEMAC_IMASK_MGI))88 89#define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */90#define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */91#define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */92#define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */93#define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/94#define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */95#define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */96#define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */97#define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */98#define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */99#define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */100#define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */101#define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */102#define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */103#define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */104#define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */105#define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */106 107#define DEFAULT_PAUSE_QUANTA 0xf000108#define DEFAULT_FRAME_LENGTH 0x600109#define DEFAULT_TX_IPG_LENGTH 12110 111#define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF112#define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000113#define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF114#define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000115 116struct mac_addr {117 /* Lower 32 bits of 48-bit MAC address */118 u32 mac_addr_l;119 /* Upper 16 bits of 48-bit MAC address */120 u32 mac_addr_u;121};122 123/* memory map */124struct memac_regs {125 u32 res0000[2]; /* General Control and Status */126 u32 command_config; /* 0x008 Ctrl and cfg */127 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */128 u32 maxfrm; /* 0x014 Max frame length */129 u32 res0018[1];130 u32 rx_fifo_sections; /* Receive FIFO configuration reg */131 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */132 u32 res0024[2];133 u32 hashtable_ctrl; /* 0x02C Hash table control */134 u32 res0030[4];135 u32 ievent; /* 0x040 Interrupt event */136 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */137 u32 res0048;138 u32 imask; /* 0x04C Interrupt mask */139 u32 res0050;140 u32 pause_quanta[4]; /* 0x054 Pause quanta */141 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */142 u32 rx_pause_status; /* 0x074 Receive pause status */143 u32 res0078[2];144 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */145 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */146 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */147 u32 res00c0[8];148 u32 statn_config; /* 0x0E0 Statistics configuration */149 u32 res00e4[7];150 /* Rx Statistics Counter */151 u32 reoct_l;152 u32 reoct_u;153 u32 roct_l;154 u32 roct_u;155 u32 raln_l;156 u32 raln_u;157 u32 rxpf_l;158 u32 rxpf_u;159 u32 rfrm_l;160 u32 rfrm_u;161 u32 rfcs_l;162 u32 rfcs_u;163 u32 rvlan_l;164 u32 rvlan_u;165 u32 rerr_l;166 u32 rerr_u;167 u32 ruca_l;168 u32 ruca_u;169 u32 rmca_l;170 u32 rmca_u;171 u32 rbca_l;172 u32 rbca_u;173 u32 rdrp_l;174 u32 rdrp_u;175 u32 rpkt_l;176 u32 rpkt_u;177 u32 rund_l;178 u32 rund_u;179 u32 r64_l;180 u32 r64_u;181 u32 r127_l;182 u32 r127_u;183 u32 r255_l;184 u32 r255_u;185 u32 r511_l;186 u32 r511_u;187 u32 r1023_l;188 u32 r1023_u;189 u32 r1518_l;190 u32 r1518_u;191 u32 r1519x_l;192 u32 r1519x_u;193 u32 rovr_l;194 u32 rovr_u;195 u32 rjbr_l;196 u32 rjbr_u;197 u32 rfrg_l;198 u32 rfrg_u;199 u32 rcnp_l;200 u32 rcnp_u;201 u32 rdrntp_l;202 u32 rdrntp_u;203 u32 res01d0[12];204 /* Tx Statistics Counter */205 u32 teoct_l;206 u32 teoct_u;207 u32 toct_l;208 u32 toct_u;209 u32 res0210[2];210 u32 txpf_l;211 u32 txpf_u;212 u32 tfrm_l;213 u32 tfrm_u;214 u32 tfcs_l;215 u32 tfcs_u;216 u32 tvlan_l;217 u32 tvlan_u;218 u32 terr_l;219 u32 terr_u;220 u32 tuca_l;221 u32 tuca_u;222 u32 tmca_l;223 u32 tmca_u;224 u32 tbca_l;225 u32 tbca_u;226 u32 res0258[2];227 u32 tpkt_l;228 u32 tpkt_u;229 u32 tund_l;230 u32 tund_u;231 u32 t64_l;232 u32 t64_u;233 u32 t127_l;234 u32 t127_u;235 u32 t255_l;236 u32 t255_u;237 u32 t511_l;238 u32 t511_u;239 u32 t1023_l;240 u32 t1023_u;241 u32 t1518_l;242 u32 t1518_u;243 u32 t1519x_l;244 u32 t1519x_u;245 u32 res02a8[6];246 u32 tcnp_l;247 u32 tcnp_u;248 u32 res02c8[14];249 /* Line Interface Control */250 u32 if_mode; /* 0x300 Interface Mode Control */251 u32 if_status; /* 0x304 Interface Status */252 u32 res0308[14];253 /* HiGig/2 */254 u32 hg_config; /* 0x340 Control and cfg */255 u32 res0344[3];256 u32 hg_pause_quanta; /* 0x350 Pause quanta */257 u32 res0354[3];258 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */259 u32 res0364[3];260 u32 hgrx_pause_status; /* 0x370 Receive pause status */261 u32 hg_fifos_status; /* 0x374 fifos status */262 u32 rhm; /* 0x378 rx messages counter */263 u32 thm; /* 0x37C tx messages counter */264};265 266struct memac_cfg {267 bool reset_on_init;268 bool pause_ignore;269 bool promiscuous_mode_enable;270 u16 max_frame_length;271 u16 pause_quanta;272 u32 tx_ipg_length;273};274 275struct fman_mac {276 /* Pointer to MAC memory mapped registers */277 struct memac_regs __iomem *regs;278 /* MAC address of device */279 u64 addr;280 struct mac_device *dev_id; /* device cookie used by the exception cbs */281 fman_mac_exception_cb *exception_cb;282 fman_mac_exception_cb *event_cb;283 /* Pointer to driver's global address hash table */284 struct eth_hash_t *multicast_addr_hash;285 /* Pointer to driver's individual address hash table */286 struct eth_hash_t *unicast_addr_hash;287 u8 mac_id;288 u32 exceptions;289 struct memac_cfg *memac_drv_param;290 void *fm;291 struct fman_rev_info fm_rev_info;292 struct phy *serdes;293 struct phylink_pcs *sgmii_pcs;294 struct phylink_pcs *qsgmii_pcs;295 struct phylink_pcs *xfi_pcs;296 bool allmulti_enabled;297 bool rgmii_no_half_duplex;298};299 300static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,301 u8 paddr_num)302{303 u32 tmp0, tmp1;304 305 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);306 tmp1 = (u32)(adr[4] | adr[5] << 8);307 308 if (paddr_num == 0) {309 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l);310 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u);311 } else {312 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l);313 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u);314 }315}316 317static int reset(struct memac_regs __iomem *regs)318{319 u32 tmp;320 int count;321 322 tmp = ioread32be(®s->command_config);323 324 tmp |= CMD_CFG_SW_RESET;325 326 iowrite32be(tmp, ®s->command_config);327 328 count = 100;329 do {330 udelay(1);331 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) &&332 --count);333 334 if (count == 0)335 return -EBUSY;336 337 return 0;338}339 340static void set_exception(struct memac_regs __iomem *regs, u32 val,341 bool enable)342{343 u32 tmp;344 345 tmp = ioread32be(®s->imask);346 if (enable)347 tmp |= val;348 else349 tmp &= ~val;350 351 iowrite32be(tmp, ®s->imask);352}353 354static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,355 u32 exceptions)356{357 u32 tmp;358 359 /* Config */360 tmp = 0;361 if (cfg->promiscuous_mode_enable)362 tmp |= CMD_CFG_PROMIS_EN;363 if (cfg->pause_ignore)364 tmp |= CMD_CFG_PAUSE_IGNORE;365 366 /* Payload length check disable */367 tmp |= CMD_CFG_NO_LEN_CHK;368 /* Enable padding of frames in transmit direction */369 tmp |= CMD_CFG_TX_PAD_EN;370 371 tmp |= CMD_CFG_CRC_FWD;372 373 iowrite32be(tmp, ®s->command_config);374 375 /* Max Frame Length */376 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm);377 378 /* Pause Time */379 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]);380 iowrite32be((u32)0, ®s->pause_thresh[0]);381 382 /* clear all pending events and set-up interrupts */383 iowrite32be(0xffffffff, ®s->ievent);384 set_exception(regs, exceptions, true);385 386 return 0;387}388 389static void set_dflts(struct memac_cfg *cfg)390{391 cfg->reset_on_init = false;392 cfg->promiscuous_mode_enable = false;393 cfg->pause_ignore = false;394 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;395 cfg->max_frame_length = DEFAULT_FRAME_LENGTH;396 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;397}398 399static u32 get_mac_addr_hash_code(u64 eth_addr)400{401 u64 mask1, mask2;402 u32 xor_val = 0;403 u8 i, j;404 405 for (i = 0; i < 6; i++) {406 mask1 = eth_addr & (u64)0x01;407 eth_addr >>= 1;408 409 for (j = 0; j < 7; j++) {410 mask2 = eth_addr & (u64)0x01;411 mask1 ^= mask2;412 eth_addr >>= 1;413 }414 415 xor_val |= (mask1 << (5 - i));416 }417 418 return xor_val;419}420 421static int check_init_parameters(struct fman_mac *memac)422{423 if (!memac->exception_cb) {424 pr_err("Uninitialized exception handler\n");425 return -EINVAL;426 }427 if (!memac->event_cb) {428 pr_warn("Uninitialize event handler\n");429 return -EINVAL;430 }431 432 return 0;433}434 435static int get_exception_flag(enum fman_mac_exceptions exception)436{437 u32 bit_mask;438 439 switch (exception) {440 case FM_MAC_EX_10G_TX_ECC_ER:441 bit_mask = MEMAC_IMASK_TECC_ER;442 break;443 case FM_MAC_EX_10G_RX_ECC_ER:444 bit_mask = MEMAC_IMASK_RECC_ER;445 break;446 case FM_MAC_EX_TS_FIFO_ECC_ERR:447 bit_mask = MEMAC_IMASK_TSECC_ER;448 break;449 case FM_MAC_EX_MAGIC_PACKET_INDICATION:450 bit_mask = MEMAC_IMASK_MGI;451 break;452 default:453 bit_mask = 0;454 break;455 }456 457 return bit_mask;458}459 460static void memac_err_exception(void *handle)461{462 struct fman_mac *memac = (struct fman_mac *)handle;463 struct memac_regs __iomem *regs = memac->regs;464 u32 event, imask;465 466 event = ioread32be(®s->ievent);467 imask = ioread32be(®s->imask);468 469 /* Imask include both error and notification/event bits.470 * Leaving only error bits enabled by imask.471 * The imask error bits are shifted by 16 bits offset from472 * their corresponding location in the ievent - hence the >> 16473 */474 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);475 476 iowrite32be(event, ®s->ievent);477 478 if (event & MEMAC_IEVNT_TS_ECC_ER)479 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR);480 if (event & MEMAC_IEVNT_TX_ECC_ER)481 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER);482 if (event & MEMAC_IEVNT_RX_ECC_ER)483 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER);484}485 486static void memac_exception(void *handle)487{488 struct fman_mac *memac = (struct fman_mac *)handle;489 struct memac_regs __iomem *regs = memac->regs;490 u32 event, imask;491 492 event = ioread32be(®s->ievent);493 imask = ioread32be(®s->imask);494 495 /* Imask include both error and notification/event bits.496 * Leaving only error bits enabled by imask.497 * The imask error bits are shifted by 16 bits offset from498 * their corresponding location in the ievent - hence the >> 16499 */500 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);501 502 iowrite32be(event, ®s->ievent);503 504 if (event & MEMAC_IEVNT_MGI)505 memac->exception_cb(memac->dev_id,506 FM_MAC_EX_MAGIC_PACKET_INDICATION);507}508 509static void free_init_resources(struct fman_mac *memac)510{511 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,512 FMAN_INTR_TYPE_ERR);513 514 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,515 FMAN_INTR_TYPE_NORMAL);516 517 /* release the driver's group hash table */518 free_hash_table(memac->multicast_addr_hash);519 memac->multicast_addr_hash = NULL;520 521 /* release the driver's individual hash table */522 free_hash_table(memac->unicast_addr_hash);523 memac->unicast_addr_hash = NULL;524}525 526static int memac_enable(struct fman_mac *memac)527{528 int ret;529 530 ret = phy_init(memac->serdes);531 if (ret) {532 dev_err(memac->dev_id->dev,533 "could not initialize serdes: %pe\n", ERR_PTR(ret));534 return ret;535 }536 537 ret = phy_power_on(memac->serdes);538 if (ret) {539 dev_err(memac->dev_id->dev,540 "could not power on serdes: %pe\n", ERR_PTR(ret));541 phy_exit(memac->serdes);542 }543 544 return ret;545}546 547static void memac_disable(struct fman_mac *memac)548{549 phy_power_off(memac->serdes);550 phy_exit(memac->serdes);551}552 553static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)554{555 struct memac_regs __iomem *regs = memac->regs;556 u32 tmp;557 558 tmp = ioread32be(®s->command_config);559 if (new_val)560 tmp |= CMD_CFG_PROMIS_EN;561 else562 tmp &= ~CMD_CFG_PROMIS_EN;563 564 iowrite32be(tmp, ®s->command_config);565 566 return 0;567}568 569static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,570 u16 pause_time, u16 thresh_time)571{572 struct memac_regs __iomem *regs = memac->regs;573 u32 tmp;574 575 tmp = ioread32be(®s->tx_fifo_sections);576 577 GET_TX_EMPTY_DEFAULT_VALUE(tmp);578 iowrite32be(tmp, ®s->tx_fifo_sections);579 580 tmp = ioread32be(®s->command_config);581 tmp &= ~CMD_CFG_PFC_MODE;582 583 iowrite32be(tmp, ®s->command_config);584 585 tmp = ioread32be(®s->pause_quanta[priority / 2]);586 if (priority % 2)587 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT;588 else589 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT;590 tmp |= ((u32)pause_time << (16 * (priority % 2)));591 iowrite32be(tmp, ®s->pause_quanta[priority / 2]);592 593 tmp = ioread32be(®s->pause_thresh[priority / 2]);594 if (priority % 2)595 tmp &= CLXY_PAUSE_THRESH_CLX_QTH;596 else597 tmp &= CLXY_PAUSE_THRESH_CLY_QTH;598 tmp |= ((u32)thresh_time << (16 * (priority % 2)));599 iowrite32be(tmp, ®s->pause_thresh[priority / 2]);600 601 return 0;602}603 604static int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en)605{606 struct memac_regs __iomem *regs = memac->regs;607 u32 tmp;608 609 tmp = ioread32be(®s->command_config);610 if (en)611 tmp &= ~CMD_CFG_PAUSE_IGNORE;612 else613 tmp |= CMD_CFG_PAUSE_IGNORE;614 615 iowrite32be(tmp, ®s->command_config);616 617 return 0;618}619 620static unsigned long memac_get_caps(struct phylink_config *config,621 phy_interface_t interface)622{623 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;624 unsigned long caps = config->mac_capabilities;625 626 if (phy_interface_mode_is_rgmii(interface) &&627 memac->rgmii_no_half_duplex)628 caps &= ~(MAC_10HD | MAC_100HD);629 630 return caps;631}632 633/**634 * memac_if_mode() - Convert an interface mode into an IF_MODE config635 * @interface: A phy interface mode636 *637 * Return: A configuration word, suitable for programming into the lower bits638 * of %IF_MODE.639 */640static u32 memac_if_mode(phy_interface_t interface)641{642 switch (interface) {643 case PHY_INTERFACE_MODE_MII:644 return IF_MODE_MII;645 case PHY_INTERFACE_MODE_RGMII:646 case PHY_INTERFACE_MODE_RGMII_ID:647 case PHY_INTERFACE_MODE_RGMII_RXID:648 case PHY_INTERFACE_MODE_RGMII_TXID:649 return IF_MODE_GMII | IF_MODE_RGMII;650 case PHY_INTERFACE_MODE_SGMII:651 case PHY_INTERFACE_MODE_1000BASEX:652 case PHY_INTERFACE_MODE_QSGMII:653 return IF_MODE_GMII;654 case PHY_INTERFACE_MODE_10GBASER:655 return IF_MODE_10G;656 default:657 WARN_ON_ONCE(1);658 return 0;659 }660}661 662static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,663 phy_interface_t iface)664{665 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;666 667 switch (iface) {668 case PHY_INTERFACE_MODE_SGMII:669 case PHY_INTERFACE_MODE_1000BASEX:670 return memac->sgmii_pcs;671 case PHY_INTERFACE_MODE_QSGMII:672 return memac->qsgmii_pcs;673 case PHY_INTERFACE_MODE_10GBASER:674 return memac->xfi_pcs;675 default:676 return NULL;677 }678}679 680static int memac_prepare(struct phylink_config *config, unsigned int mode,681 phy_interface_t iface)682{683 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;684 685 switch (iface) {686 case PHY_INTERFACE_MODE_SGMII:687 case PHY_INTERFACE_MODE_1000BASEX:688 case PHY_INTERFACE_MODE_QSGMII:689 case PHY_INTERFACE_MODE_10GBASER:690 return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,691 iface);692 default:693 return 0;694 }695}696 697static void memac_mac_config(struct phylink_config *config, unsigned int mode,698 const struct phylink_link_state *state)699{700 struct mac_device *mac_dev = fman_config_to_mac(config);701 struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;702 u32 tmp = ioread32be(®s->if_mode);703 704 tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);705 tmp |= memac_if_mode(state->interface);706 if (phylink_autoneg_inband(mode))707 tmp |= IF_MODE_RGMII_AUTO;708 iowrite32be(tmp, ®s->if_mode);709}710 711static void memac_link_up(struct phylink_config *config, struct phy_device *phy,712 unsigned int mode, phy_interface_t interface,713 int speed, int duplex, bool tx_pause, bool rx_pause)714{715 struct mac_device *mac_dev = fman_config_to_mac(config);716 struct fman_mac *memac = mac_dev->fman_mac;717 struct memac_regs __iomem *regs = memac->regs;718 u32 tmp = memac_if_mode(interface);719 u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :720 FSL_FM_PAUSE_TIME_DISABLE;721 722 memac_set_tx_pause_frames(memac, 0, pause_time, 0);723 memac_accept_rx_pause_frames(memac, rx_pause);724 725 if (duplex == DUPLEX_HALF)726 tmp |= IF_MODE_HD;727 728 switch (speed) {729 case SPEED_1000:730 tmp |= IF_MODE_RGMII_1000;731 break;732 case SPEED_100:733 tmp |= IF_MODE_RGMII_100;734 break;735 case SPEED_10:736 tmp |= IF_MODE_RGMII_10;737 break;738 }739 iowrite32be(tmp, ®s->if_mode);740 741 /* TODO: EEE? */742 743 if (speed == SPEED_10000) {744 if (memac->fm_rev_info.major == 6 &&745 memac->fm_rev_info.minor == 4)746 tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;747 else748 tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;749 tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;750 } else {751 tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |752 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;753 }754 iowrite32be(tmp, ®s->tx_fifo_sections);755 756 mac_dev->update_speed(mac_dev, speed);757 758 tmp = ioread32be(®s->command_config);759 tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;760 iowrite32be(tmp, ®s->command_config);761}762 763static void memac_link_down(struct phylink_config *config, unsigned int mode,764 phy_interface_t interface)765{766 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;767 struct memac_regs __iomem *regs = memac->regs;768 u32 tmp;769 770 /* TODO: graceful */771 tmp = ioread32be(®s->command_config);772 tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);773 iowrite32be(tmp, ®s->command_config);774}775 776static const struct phylink_mac_ops memac_mac_ops = {777 .mac_get_caps = memac_get_caps,778 .mac_select_pcs = memac_select_pcs,779 .mac_prepare = memac_prepare,780 .mac_config = memac_mac_config,781 .mac_link_up = memac_link_up,782 .mac_link_down = memac_link_down,783};784 785static int memac_modify_mac_address(struct fman_mac *memac,786 const enet_addr_t *enet_addr)787{788 add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);789 790 return 0;791}792 793static int memac_add_hash_mac_address(struct fman_mac *memac,794 enet_addr_t *eth_addr)795{796 struct memac_regs __iomem *regs = memac->regs;797 struct eth_hash_entry *hash_entry;798 u32 hash;799 u64 addr;800 801 addr = ENET_ADDR_TO_UINT64(*eth_addr);802 803 if (!(addr & GROUP_ADDRESS)) {804 /* Unicast addresses not supported in hash */805 pr_err("Unicast Address\n");806 return -EINVAL;807 }808 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;809 810 /* Create element to be added to the driver hash table */811 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);812 if (!hash_entry)813 return -ENOMEM;814 hash_entry->addr = addr;815 INIT_LIST_HEAD(&hash_entry->node);816 817 list_add_tail(&hash_entry->node,818 &memac->multicast_addr_hash->lsts[hash]);819 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);820 821 return 0;822}823 824static int memac_set_allmulti(struct fman_mac *memac, bool enable)825{826 u32 entry;827 struct memac_regs __iomem *regs = memac->regs;828 829 if (enable) {830 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)831 iowrite32be(entry | HASH_CTRL_MCAST_EN,832 ®s->hashtable_ctrl);833 } else {834 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)835 iowrite32be(entry & ~HASH_CTRL_MCAST_EN,836 ®s->hashtable_ctrl);837 }838 839 memac->allmulti_enabled = enable;840 841 return 0;842}843 844static int memac_set_tstamp(struct fman_mac *memac, bool enable)845{846 return 0; /* Always enabled. */847}848 849static int memac_del_hash_mac_address(struct fman_mac *memac,850 enet_addr_t *eth_addr)851{852 struct memac_regs __iomem *regs = memac->regs;853 struct eth_hash_entry *hash_entry = NULL;854 struct list_head *pos;855 u32 hash;856 u64 addr;857 858 addr = ENET_ADDR_TO_UINT64(*eth_addr);859 860 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;861 862 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) {863 hash_entry = ETH_HASH_ENTRY_OBJ(pos);864 if (hash_entry && hash_entry->addr == addr) {865 list_del_init(&hash_entry->node);866 kfree(hash_entry);867 break;868 }869 }870 871 if (!memac->allmulti_enabled) {872 if (list_empty(&memac->multicast_addr_hash->lsts[hash]))873 iowrite32be(hash & ~HASH_CTRL_MCAST_EN,874 ®s->hashtable_ctrl);875 }876 877 return 0;878}879 880static int memac_set_exception(struct fman_mac *memac,881 enum fman_mac_exceptions exception, bool enable)882{883 u32 bit_mask = 0;884 885 bit_mask = get_exception_flag(exception);886 if (bit_mask) {887 if (enable)888 memac->exceptions |= bit_mask;889 else890 memac->exceptions &= ~bit_mask;891 } else {892 pr_err("Undefined exception\n");893 return -EINVAL;894 }895 set_exception(memac->regs, bit_mask, enable);896 897 return 0;898}899 900static int memac_init(struct fman_mac *memac)901{902 struct memac_cfg *memac_drv_param;903 enet_addr_t eth_addr;904 int err;905 u32 reg32 = 0;906 907 err = check_init_parameters(memac);908 if (err)909 return err;910 911 memac_drv_param = memac->memac_drv_param;912 913 /* First, reset the MAC if desired. */914 if (memac_drv_param->reset_on_init) {915 err = reset(memac->regs);916 if (err) {917 pr_err("mEMAC reset failed\n");918 return err;919 }920 }921 922 /* MAC Address */923 if (memac->addr != 0) {924 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr);925 add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);926 }927 928 init(memac->regs, memac->memac_drv_param, memac->exceptions);929 930 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround931 * Exists only in FMan 6.0 and 6.3.932 */933 if ((memac->fm_rev_info.major == 6) &&934 ((memac->fm_rev_info.minor == 0) ||935 (memac->fm_rev_info.minor == 3))) {936 /* MAC strips CRC from received frames - this workaround937 * should decrease the likelihood of bug appearance938 */939 reg32 = ioread32be(&memac->regs->command_config);940 reg32 &= ~CMD_CFG_CRC_FWD;941 iowrite32be(reg32, &memac->regs->command_config);942 }943 944 /* Max Frame Length */945 err = fman_set_mac_max_frame(memac->fm, memac->mac_id,946 memac_drv_param->max_frame_length);947 if (err) {948 pr_err("settings Mac max frame length is FAILED\n");949 return err;950 }951 952 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);953 if (!memac->multicast_addr_hash) {954 free_init_resources(memac);955 pr_err("allocation hash table is FAILED\n");956 return -ENOMEM;957 }958 959 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);960 if (!memac->unicast_addr_hash) {961 free_init_resources(memac);962 pr_err("allocation hash table is FAILED\n");963 return -ENOMEM;964 }965 966 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,967 FMAN_INTR_TYPE_ERR, memac_err_exception, memac);968 969 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,970 FMAN_INTR_TYPE_NORMAL, memac_exception, memac);971 972 return 0;973}974 975static void pcs_put(struct phylink_pcs *pcs)976{977 if (IS_ERR_OR_NULL(pcs))978 return;979 980 lynx_pcs_destroy(pcs);981}982 983static int memac_free(struct fman_mac *memac)984{985 free_init_resources(memac);986 987 pcs_put(memac->sgmii_pcs);988 pcs_put(memac->qsgmii_pcs);989 pcs_put(memac->xfi_pcs);990 kfree(memac->memac_drv_param);991 kfree(memac);992 993 return 0;994}995 996static struct fman_mac *memac_config(struct mac_device *mac_dev,997 struct fman_mac_params *params)998{999 struct fman_mac *memac;1000 struct memac_cfg *memac_drv_param;1001 1002 /* allocate memory for the m_emac data structure */1003 memac = kzalloc(sizeof(*memac), GFP_KERNEL);1004 if (!memac)1005 return NULL;1006 1007 /* allocate memory for the m_emac driver parameters data structure */1008 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL);1009 if (!memac_drv_param) {1010 memac_free(memac);1011 return NULL;1012 }1013 1014 /* Plant parameter structure pointer */1015 memac->memac_drv_param = memac_drv_param;1016 1017 set_dflts(memac_drv_param);1018 1019 memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);1020 1021 memac->regs = mac_dev->vaddr;1022 memac->mac_id = params->mac_id;1023 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |1024 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);1025 memac->exception_cb = params->exception_cb;1026 memac->event_cb = params->event_cb;1027 memac->dev_id = mac_dev;1028 memac->fm = params->fm;1029 1030 /* Save FMan revision */1031 fman_get_revision(memac->fm, &memac->fm_rev_info);1032 1033 return memac;1034}1035 1036static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,1037 int index)1038{1039 struct device_node *node;1040 struct phylink_pcs *pcs;1041 1042 node = of_parse_phandle(mac_node, "pcsphy-handle", index);1043 if (!node)1044 return ERR_PTR(-ENODEV);1045 1046 pcs = lynx_pcs_create_fwnode(of_fwnode_handle(node));1047 of_node_put(node);1048 1049 return pcs;1050}1051 1052static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)1053{1054 /* If there's no serdes device, assume that it's been configured for1055 * whatever the default interface mode is.1056 */1057 if (!mac_dev->fman_mac->serdes)1058 return mac_dev->phy_if == iface;1059 /* Otherwise, ask the serdes */1060 return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,1061 iface, NULL);1062}1063 1064int memac_initialization(struct mac_device *mac_dev,1065 struct device_node *mac_node,1066 struct fman_mac_params *params)1067{1068 int err;1069 struct phylink_pcs *pcs;1070 struct fman_mac *memac;1071 unsigned long capabilities;1072 unsigned long *supported;1073 1074 /* The internal connection to the serdes is XGMII, but this isn't1075 * really correct for the phy mode (which is the external connection).1076 * However, this is how all older device trees say that they want1077 * 10GBASE-R (aka XFI), so just convert it for them.1078 */1079 if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)1080 mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;1081 1082 mac_dev->phylink_ops = &memac_mac_ops;1083 mac_dev->set_promisc = memac_set_promiscuous;1084 mac_dev->change_addr = memac_modify_mac_address;1085 mac_dev->add_hash_mac_addr = memac_add_hash_mac_address;1086 mac_dev->remove_hash_mac_addr = memac_del_hash_mac_address;1087 mac_dev->set_exception = memac_set_exception;1088 mac_dev->set_allmulti = memac_set_allmulti;1089 mac_dev->set_tstamp = memac_set_tstamp;1090 mac_dev->set_multi = fman_set_multi;1091 mac_dev->enable = memac_enable;1092 mac_dev->disable = memac_disable;1093 1094 mac_dev->fman_mac = memac_config(mac_dev, params);1095 if (!mac_dev->fman_mac)1096 return -EINVAL;1097 1098 memac = mac_dev->fman_mac;1099 memac->memac_drv_param->max_frame_length = fman_get_max_frm();1100 memac->memac_drv_param->reset_on_init = true;1101 1102 err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");1103 if (err >= 0) {1104 memac->xfi_pcs = memac_pcs_create(mac_node, err);1105 if (IS_ERR(memac->xfi_pcs)) {1106 err = PTR_ERR(memac->xfi_pcs);1107 dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");1108 goto _return_fm_mac_free;1109 }1110 } else if (err != -EINVAL && err != -ENODATA) {1111 goto _return_fm_mac_free;1112 }1113 1114 err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");1115 if (err >= 0) {1116 memac->qsgmii_pcs = memac_pcs_create(mac_node, err);1117 if (IS_ERR(memac->qsgmii_pcs)) {1118 err = PTR_ERR(memac->qsgmii_pcs);1119 dev_err_probe(mac_dev->dev, err,1120 "missing qsgmii pcs\n");1121 goto _return_fm_mac_free;1122 }1123 } else if (err != -EINVAL && err != -ENODATA) {1124 goto _return_fm_mac_free;1125 }1126 1127 /* For compatibility, if pcs-handle-names is missing, we assume this1128 * phy is the first one in pcsphy-handle1129 */1130 err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");1131 if (err == -EINVAL || err == -ENODATA)1132 pcs = memac_pcs_create(mac_node, 0);1133 else if (err < 0)1134 goto _return_fm_mac_free;1135 else1136 pcs = memac_pcs_create(mac_node, err);1137 1138 if (IS_ERR(pcs)) {1139 err = PTR_ERR(pcs);1140 dev_err_probe(mac_dev->dev, err, "missing pcs\n");1141 goto _return_fm_mac_free;1142 }1143 1144 /* If err is set here, it means that pcs-handle-names was missing above1145 * (and therefore that xfi_pcs cannot be set). If we are defaulting to1146 * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.1147 */1148 if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_10GBASER)1149 memac->xfi_pcs = pcs;1150 else1151 memac->sgmii_pcs = pcs;1152 1153 memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,1154 "serdes");1155 if (!memac->serdes) {1156 dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");1157 } else if (IS_ERR(memac->serdes)) {1158 err = PTR_ERR(memac->serdes);1159 goto _return_fm_mac_free;1160 }1161 1162 /* TODO: The following interface modes are supported by (some) hardware1163 * but not by this driver:1164 * - 1000BASE-KX1165 * - 10GBASE-KR1166 * - XAUI/HiGig1167 */1168 supported = mac_dev->phylink_config.supported_interfaces;1169 1170 /* Note that half duplex is only supported on 10/100M interfaces. */1171 1172 if (memac->sgmii_pcs &&1173 (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||1174 memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {1175 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);1176 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);1177 }1178 1179 if (memac->sgmii_pcs &&1180 memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))1181 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);1182 1183 if (memac->qsgmii_pcs &&1184 memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))1185 __set_bit(PHY_INTERFACE_MODE_QSGMII, supported);1186 else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)1187 dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");1188 1189 if (memac->xfi_pcs &&1190 memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {1191 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);1192 } else {1193 /* From what I can tell, no 10g macs support RGMII. */1194 phy_interface_set_rgmii(supported);1195 __set_bit(PHY_INTERFACE_MODE_MII, supported);1196 }1197 1198 capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;1199 capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;1200 1201 /* These SoCs don't support half duplex at all; there's no different1202 * FMan version or compatible, so we just have to check the machine1203 * compatible instead1204 */1205 if (of_machine_is_compatible("fsl,ls1043a") ||1206 of_machine_is_compatible("fsl,ls1046a") ||1207 of_machine_is_compatible("fsl,B4QDS"))1208 capabilities &= ~(MAC_10HD | MAC_100HD);1209 1210 mac_dev->phylink_config.mac_capabilities = capabilities;1211 1212 /* The T2080 and T4240 don't support half duplex RGMII. There is no1213 * other way to identify these SoCs, so just use the machine1214 * compatible.1215 */1216 if (of_machine_is_compatible("fsl,T2080QDS") ||1217 of_machine_is_compatible("fsl,T2080RDB") ||1218 of_machine_is_compatible("fsl,T2081QDS") ||1219 of_machine_is_compatible("fsl,T4240QDS") ||1220 of_machine_is_compatible("fsl,T4240RDB"))1221 memac->rgmii_no_half_duplex = true;1222 1223 /* Most boards should use MLO_AN_INBAND, but existing boards don't have1224 * a managed property. Default to MLO_AN_INBAND rather than MLO_AN_PHY.1225 * Phylink will allow this to be overriden by a fixed link. We need to1226 * be careful and not enable this if we are using MII or RGMII, since1227 * those configurations modes don't use in-band autonegotiation.1228 */1229 if (!of_property_read_bool(mac_node, "managed") &&1230 mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&1231 !phy_interface_mode_is_rgmii(mac_dev->phy_if))1232 mac_dev->phylink_config.default_an_inband = true;1233 1234 err = memac_init(mac_dev->fman_mac);1235 if (err < 0)1236 goto _return_fm_mac_free;1237 1238 dev_info(mac_dev->dev, "FMan MEMAC\n");1239 1240 return 0;1241 1242_return_fm_mac_free:1243 memac_free(mac_dev->fman_mac);1244 return err;1245}1246