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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT)2 * Google virtual Ethernet (gve) driver3 *4 * Copyright (C) 2015-2021 Google, Inc.5 */6 7#ifndef _GVE_DQO_H_8#define _GVE_DQO_H_9 10#include "gve_adminq.h"11 12#define GVE_ITR_ENABLE_BIT_DQO BIT(0)13#define GVE_ITR_CLEAR_PBA_BIT_DQO BIT(1)14#define GVE_ITR_NO_UPDATE_DQO (3 << 3)15 16#define GVE_ITR_INTERVAL_DQO_SHIFT 517#define GVE_ITR_INTERVAL_DQO_MASK ((1 << 12) - 1)18 19#define GVE_TX_IRQ_RATELIMIT_US_DQO 5020#define GVE_RX_IRQ_RATELIMIT_US_DQO 2021#define GVE_MAX_ITR_INTERVAL_DQO (GVE_ITR_INTERVAL_DQO_MASK * 2)22 23/* Timeout in seconds to wait for a reinjection completion after receiving24 * its corresponding miss completion.25 */26#define GVE_REINJECT_COMPL_TIMEOUT 127 28/* Timeout in seconds to deallocate the completion tag for a packet that was29 * prematurely freed for not receiving a valid completion. This should be large30 * enough to rule out the possibility of receiving the corresponding valid31 * completion after this interval.32 */33#define GVE_DEALLOCATE_COMPL_TIMEOUT 6034 35netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev);36netdev_features_t gve_features_check_dqo(struct sk_buff *skb,37 struct net_device *dev,38 netdev_features_t features);39bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean);40int gve_rx_poll_dqo(struct gve_notify_block *block, int budget);41int gve_tx_alloc_rings_dqo(struct gve_priv *priv,42 struct gve_tx_alloc_rings_cfg *cfg);43void gve_tx_free_rings_dqo(struct gve_priv *priv,44 struct gve_tx_alloc_rings_cfg *cfg);45void gve_tx_start_ring_dqo(struct gve_priv *priv, int idx);46void gve_tx_stop_ring_dqo(struct gve_priv *priv, int idx);47int gve_rx_alloc_ring_dqo(struct gve_priv *priv,48 struct gve_rx_alloc_rings_cfg *cfg,49 struct gve_rx_ring *rx,50 int idx);51void gve_rx_free_ring_dqo(struct gve_priv *priv, struct gve_rx_ring *rx,52 struct gve_rx_alloc_rings_cfg *cfg);53int gve_rx_alloc_rings_dqo(struct gve_priv *priv,54 struct gve_rx_alloc_rings_cfg *cfg);55void gve_rx_free_rings_dqo(struct gve_priv *priv,56 struct gve_rx_alloc_rings_cfg *cfg);57void gve_rx_start_ring_dqo(struct gve_priv *priv, int idx);58void gve_rx_stop_ring_dqo(struct gve_priv *priv, int idx);59int gve_clean_tx_done_dqo(struct gve_priv *priv, struct gve_tx_ring *tx,60 struct napi_struct *napi);61void gve_rx_post_buffers_dqo(struct gve_rx_ring *rx);62void gve_rx_write_doorbell_dqo(const struct gve_priv *priv, int queue_idx);63 64static inline void65gve_tx_put_doorbell_dqo(const struct gve_priv *priv,66 const struct gve_queue_resources *q_resources, u32 val)67{68 u64 index;69 70 index = be32_to_cpu(q_resources->db_index);71 iowrite32(val, &priv->db_bar2[index]);72}73 74/* Builds register value to write to DQO IRQ doorbell to enable with specified75 * ITR interval.76 */77static inline u32 gve_setup_itr_interval_dqo(u32 interval_us)78{79 u32 result = GVE_ITR_ENABLE_BIT_DQO;80 81 /* Interval has 2us granularity. */82 interval_us >>= 1;83 84 interval_us &= GVE_ITR_INTERVAL_DQO_MASK;85 result |= (interval_us << GVE_ITR_INTERVAL_DQO_SHIFT);86 87 return result;88}89 90static inline void91gve_write_irq_doorbell_dqo(const struct gve_priv *priv,92 const struct gve_notify_block *block, u32 val)93{94 u32 index = be32_to_cpu(*block->irq_db_index);95 96 iowrite32(val, &priv->db_bar2[index]);97}98 99/* Sets interrupt throttling interval and enables interrupt100 * by writing to IRQ doorbell.101 */102static inline void103gve_set_itr_coalesce_usecs_dqo(struct gve_priv *priv,104 struct gve_notify_block *block,105 u32 usecs)106{107 gve_write_irq_doorbell_dqo(priv, block,108 gve_setup_itr_interval_dqo(usecs));109}110 111int gve_napi_poll_dqo(struct napi_struct *napi, int budget);112#endif /* _GVE_DQO_H_ */113