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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright (c) 2014-2015 Hisilicon Limited.4 */5 6#include <linux/cdev.h>7#include <linux/module.h>8#include <linux/kernel.h>9#include <linux/init.h>10#include <linux/netdevice.h>11#include <linux/etherdevice.h>12#include <asm/cacheflush.h>13#include <linux/platform_device.h>14#include <linux/spinlock.h>15 16#include "hns_dsaf_main.h"17#include "hns_dsaf_ppe.h"18#include "hns_dsaf_rcb.h"19 20#define RCB_COMMON_REG_OFFSET 0x8000021#define TX_RING 022#define RX_RING 123 24#define RCB_RESET_WAIT_TIMES 3025#define RCB_RESET_TRY_TIMES 1026 27/* Because default mtu is 1500, rcb buffer size is set to 2048 enough */28#define RCB_DEFAULT_BUFFER_SIZE 204829 30/**31 *hns_rcb_wait_fbd_clean - clean fbd32 *@qs: ring struct pointer array33 *@q_num: num of array34 *@flag: tx or rx flag35 */36void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag)37{38 int i, wait_cnt;39 u32 fbd_num;40 41 for (wait_cnt = i = 0; i < q_num; wait_cnt++) {42 usleep_range(200, 300);43 fbd_num = 0;44 if (flag & RCB_INT_FLAG_TX)45 fbd_num += dsaf_read_dev(qs[i],46 RCB_RING_TX_RING_FBDNUM_REG);47 if (flag & RCB_INT_FLAG_RX)48 fbd_num += dsaf_read_dev(qs[i],49 RCB_RING_RX_RING_FBDNUM_REG);50 if (!fbd_num)51 i++;52 if (wait_cnt >= 10000)53 break;54 }55 56 if (i < q_num)57 dev_err(qs[i]->handle->owner_dev,58 "queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num);59}60 61int hns_rcb_wait_tx_ring_clean(struct hnae_queue *qs)62{63 u32 head, tail;64 int wait_cnt;65 66 tail = dsaf_read_dev(&qs->tx_ring, RCB_REG_TAIL);67 wait_cnt = 0;68 while (wait_cnt++ < HNS_MAX_WAIT_CNT) {69 head = dsaf_read_dev(&qs->tx_ring, RCB_REG_HEAD);70 if (tail == head)71 break;72 73 usleep_range(100, 200);74 }75 76 if (wait_cnt >= HNS_MAX_WAIT_CNT) {77 dev_err(qs->dev->dev, "rcb wait timeout, head not equal to tail.\n");78 return -EBUSY;79 }80 81 return 0;82}83 84/**85 *hns_rcb_reset_ring_hw - ring reset86 *@q: ring struct pointer87 */88void hns_rcb_reset_ring_hw(struct hnae_queue *q)89{90 u32 wait_cnt;91 u32 try_cnt = 0;92 u32 could_ret;93 94 u32 tx_fbd_num;95 96 while (try_cnt++ < RCB_RESET_TRY_TIMES) {97 usleep_range(100, 200);98 tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG);99 if (tx_fbd_num)100 continue;101 102 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);103 104 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);105 106 msleep(20);107 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);108 109 wait_cnt = 0;110 while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) {111 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);112 113 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);114 115 msleep(20);116 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);117 118 wait_cnt++;119 }120 121 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);122 123 if (could_ret)124 break;125 }126 127 if (try_cnt >= RCB_RESET_TRY_TIMES)128 dev_err(q->dev->dev, "port%d reset ring fail\n",129 hns_ae_get_vf_cb(q->handle)->port_index);130}131 132/**133 *hns_rcb_int_ctrl_hw - rcb irq enable control134 *@q: hnae queue struct pointer135 *@flag:ring flag tx or rx136 *@mask:mask137 */138void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)139{140 u32 int_mask_en = !!mask;141 142 if (flag & RCB_INT_FLAG_TX) {143 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);144 dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG,145 int_mask_en);146 }147 148 if (flag & RCB_INT_FLAG_RX) {149 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);150 dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG,151 int_mask_en);152 }153}154 155void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag)156{157 if (flag & RCB_INT_FLAG_TX) {158 dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1);159 dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, 1);160 }161 162 if (flag & RCB_INT_FLAG_RX) {163 dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, 1);164 dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, 1);165 }166}167 168void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)169{170 u32 int_mask_en = !!mask;171 172 if (flag & RCB_INT_FLAG_TX)173 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);174 175 if (flag & RCB_INT_FLAG_RX)176 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);177}178 179void hns_rcbv2_int_clr_hw(struct hnae_queue *q, u32 flag)180{181 if (flag & RCB_INT_FLAG_TX)182 dsaf_write_dev(q, RCBV2_TX_RING_INT_STS_REG, 1);183 184 if (flag & RCB_INT_FLAG_RX)185 dsaf_write_dev(q, RCBV2_RX_RING_INT_STS_REG, 1);186}187 188/**189 *hns_rcb_ring_enable_hw - enable ring190 *@q: rcb ring191 *@val: value to write192 */193void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val)194{195 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);196}197 198void hns_rcb_start(struct hnae_queue *q, u32 val)199{200 hns_rcb_ring_enable_hw(q, val);201}202 203/**204 *hns_rcb_common_init_commit_hw - make rcb common init completed205 *@rcb_common: rcb common device206 */207void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common)208{209 wmb(); /* Sync point before breakpoint */210 dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1);211 wmb(); /* Sync point after breakpoint */212}213 214/* hns_rcb_set_tx_ring_bs - init rcb ring buf size regester215 *@q: hnae_queue216 *@buf_size: buffer size set to hw217 */218void hns_rcb_set_tx_ring_bs(struct hnae_queue *q, u32 buf_size)219{220 u32 bd_size_type = hns_rcb_buf_size2type(buf_size);221 222 dsaf_write_dev(q, RCB_RING_TX_RING_BD_LEN_REG,223 bd_size_type);224}225 226/* hns_rcb_set_rx_ring_bs - init rcb ring buf size regester227 *@q: hnae_queue228 *@buf_size: buffer size set to hw229 */230void hns_rcb_set_rx_ring_bs(struct hnae_queue *q, u32 buf_size)231{232 u32 bd_size_type = hns_rcb_buf_size2type(buf_size);233 234 dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG,235 bd_size_type);236}237 238/**239 *hns_rcb_ring_init - init rcb ring240 *@ring_pair: ring pair control block241 *@ring_type: ring type, RX_RING or TX_RING242 */243static void hns_rcb_ring_init(struct ring_pair_cb *ring_pair, int ring_type)244{245 struct hnae_queue *q = &ring_pair->q;246 struct hnae_ring *ring =247 (ring_type == RX_RING) ? &q->rx_ring : &q->tx_ring;248 dma_addr_t dma = ring->desc_dma_addr;249 250 if (ring_type == RX_RING) {251 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG,252 (u32)dma);253 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG,254 (u32)((dma >> 31) >> 1));255 256 hns_rcb_set_rx_ring_bs(q, ring->buf_size);257 258 dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG,259 ring_pair->port_id_in_comm);260 dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG,261 ring_pair->port_id_in_comm);262 } else {263 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_L_REG,264 (u32)dma);265 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_H_REG,266 (u32)((dma >> 31) >> 1));267 268 hns_rcb_set_tx_ring_bs(q, ring->buf_size);269 270 dsaf_write_dev(q, RCB_RING_TX_RING_BD_NUM_REG,271 ring_pair->port_id_in_comm);272 dsaf_write_dev(q, RCB_RING_TX_RING_PKTLINE_REG,273 ring_pair->port_id_in_comm + HNS_RCB_TX_PKTLINE_OFFSET);274 }275}276 277/**278 *hns_rcb_init_hw - init rcb hardware279 *@ring: rcb ring280 */281void hns_rcb_init_hw(struct ring_pair_cb *ring)282{283 hns_rcb_ring_init(ring, RX_RING);284 hns_rcb_ring_init(ring, TX_RING);285}286 287/**288 *hns_rcb_set_port_desc_cnt - set rcb port description num289 *@rcb_common: rcb_common device290 *@port_idx:port index291 *@desc_cnt:BD num292 */293static void hns_rcb_set_port_desc_cnt(struct rcb_common_cb *rcb_common,294 u32 port_idx, u32 desc_cnt)295{296 dsaf_write_dev(rcb_common, RCB_CFG_BD_NUM_REG + port_idx * 4,297 desc_cnt);298}299 300static void hns_rcb_set_port_timeout(301 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)302{303 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {304 dsaf_write_dev(rcb_common, RCB_CFG_OVERTIME_REG,305 timeout * HNS_RCB_CLK_FREQ_MHZ);306 } else if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {307 if (timeout > HNS_RCB_DEF_GAP_TIME_USECS)308 dsaf_write_dev(rcb_common,309 RCB_PORT_INT_GAPTIME_REG + port_idx * 4,310 HNS_RCB_DEF_GAP_TIME_USECS);311 else312 dsaf_write_dev(rcb_common,313 RCB_PORT_INT_GAPTIME_REG + port_idx * 4,314 timeout);315 316 dsaf_write_dev(rcb_common,317 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,318 timeout);319 } else {320 dsaf_write_dev(rcb_common,321 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,322 timeout);323 }324}325 326static int hns_rcb_common_get_port_num(struct rcb_common_cb *rcb_common)327{328 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))329 return HNS_RCB_SERVICE_NW_ENGINE_NUM;330 else331 return HNS_RCB_DEBUG_NW_ENGINE_NUM;332}333 334/*clr rcb comm exception irq**/335static void hns_rcb_comm_exc_irq_en(336 struct rcb_common_cb *rcb_common, int en)337{338 u32 clr_vlue = 0xfffffffful;339 u32 msk_vlue = en ? 0 : 0xfffffffful;340 341 /* clr int*/342 dsaf_write_dev(rcb_common, RCB_COM_INTSTS_ECC_ERR_REG, clr_vlue);343 344 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_RING_STS, clr_vlue);345 346 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_BD_RINT_STS, clr_vlue);347 348 dsaf_write_dev(rcb_common, RCB_COM_RINT_TX_PKT_REG, clr_vlue);349 dsaf_write_dev(rcb_common, RCB_COM_AXI_ERR_STS, clr_vlue);350 351 /*en msk*/352 dsaf_write_dev(rcb_common, RCB_COM_INTMASK_ECC_ERR_REG, msk_vlue);353 354 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_RING, msk_vlue);355 356 /*for tx bd neednot cacheline, so msk sf_txring_fbd_intmask (bit 1)**/357 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_BD, msk_vlue | 2);358 359 dsaf_write_dev(rcb_common, RCB_COM_INTMSK_TX_PKT_REG, msk_vlue);360 dsaf_write_dev(rcb_common, RCB_COM_AXI_WR_ERR_INTMASK, msk_vlue);361}362 363/**364 *hns_rcb_common_init_hw - init rcb common hardware365 *@rcb_common: rcb_common device366 *retuen 0 - success , negative --fail367 */368int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common)369{370 u32 reg_val;371 int i;372 int port_num = hns_rcb_common_get_port_num(rcb_common);373 374 hns_rcb_comm_exc_irq_en(rcb_common, 0);375 376 reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG);377 if (0x1 != (reg_val & 0x1)) {378 dev_err(rcb_common->dsaf_dev->dev,379 "RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val);380 return -EBUSY;381 }382 383 for (i = 0; i < port_num; i++) {384 hns_rcb_set_port_desc_cnt(rcb_common, i, rcb_common->desc_num);385 hns_rcb_set_rx_coalesced_frames(386 rcb_common, i, HNS_RCB_DEF_RX_COALESCED_FRAMES);387 if (!AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver) &&388 !HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))389 hns_rcb_set_tx_coalesced_frames(390 rcb_common, i, HNS_RCB_DEF_TX_COALESCED_FRAMES);391 hns_rcb_set_port_timeout(392 rcb_common, i, HNS_RCB_DEF_COALESCED_USECS);393 }394 395 dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG,396 HNS_RCB_COMMON_ENDIAN);397 398 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {399 dsaf_write_dev(rcb_common, RCB_COM_CFG_FNA_REG, 0x0);400 dsaf_write_dev(rcb_common, RCB_COM_CFG_FA_REG, 0x1);401 } else {402 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,403 RCB_COM_CFG_FNA_B, false);404 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,405 RCB_COM_CFG_FA_B, true);406 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_TSO_MODE_REG,407 RCB_COM_TSO_MODE_B, HNS_TSO_MODE_8BD_32K);408 }409 410 return 0;411}412 413int hns_rcb_buf_size2type(u32 buf_size)414{415 int bd_size_type;416 417 switch (buf_size) {418 case 512:419 bd_size_type = HNS_BD_SIZE_512_TYPE;420 break;421 case 1024:422 bd_size_type = HNS_BD_SIZE_1024_TYPE;423 break;424 case 2048:425 bd_size_type = HNS_BD_SIZE_2048_TYPE;426 break;427 case 4096:428 bd_size_type = HNS_BD_SIZE_4096_TYPE;429 break;430 default:431 bd_size_type = -EINVAL;432 }433 434 return bd_size_type;435}436 437static void hns_rcb_ring_get_cfg(struct hnae_queue *q, int ring_type)438{439 struct hnae_ring *ring;440 struct rcb_common_cb *rcb_common;441 struct ring_pair_cb *ring_pair_cb;442 u16 desc_num, mdnum_ppkt;443 bool irq_idx, is_ver1;444 445 ring_pair_cb = container_of(q, struct ring_pair_cb, q);446 is_ver1 = AE_IS_VER1(ring_pair_cb->rcb_common->dsaf_dev->dsaf_ver);447 if (ring_type == RX_RING) {448 ring = &q->rx_ring;449 ring->io_base = ring_pair_cb->q.io_base;450 irq_idx = HNS_RCB_IRQ_IDX_RX;451 mdnum_ppkt = HNS_RCB_RING_MAX_BD_PER_PKT;452 } else {453 ring = &q->tx_ring;454 ring->io_base = ring_pair_cb->q.io_base +455 HNS_RCB_TX_REG_OFFSET;456 irq_idx = HNS_RCB_IRQ_IDX_TX;457 mdnum_ppkt = is_ver1 ? HNS_RCB_RING_MAX_TXBD_PER_PKT :458 HNS_RCBV2_RING_MAX_TXBD_PER_PKT;459 }460 461 rcb_common = ring_pair_cb->rcb_common;462 desc_num = rcb_common->dsaf_dev->desc_num;463 464 ring->desc = NULL;465 ring->desc_cb = NULL;466 467 ring->irq = ring_pair_cb->virq[irq_idx];468 ring->desc_dma_addr = 0;469 470 ring->buf_size = RCB_DEFAULT_BUFFER_SIZE;471 ring->desc_num = desc_num;472 ring->max_desc_num_per_pkt = mdnum_ppkt;473 ring->max_raw_data_sz_per_desc = HNS_RCB_MAX_PKT_SIZE;474 ring->max_pkt_size = HNS_RCB_MAX_PKT_SIZE;475 ring->next_to_use = 0;476 ring->next_to_clean = 0;477}478 479static void hns_rcb_ring_pair_get_cfg(struct ring_pair_cb *ring_pair_cb)480{481 ring_pair_cb->q.handle = NULL;482 483 hns_rcb_ring_get_cfg(&ring_pair_cb->q, RX_RING);484 hns_rcb_ring_get_cfg(&ring_pair_cb->q, TX_RING);485}486 487static int hns_rcb_get_port_in_comm(488 struct rcb_common_cb *rcb_common, int ring_idx)489{490 return ring_idx / (rcb_common->max_q_per_vf * rcb_common->max_vfn);491}492 493#define SERVICE_RING_IRQ_IDX(v1) \494 ((v1) ? HNS_SERVICE_RING_IRQ_IDX : HNSV2_SERVICE_RING_IRQ_IDX)495static int hns_rcb_get_base_irq_idx(struct rcb_common_cb *rcb_common)496{497 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);498 499 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))500 return SERVICE_RING_IRQ_IDX(is_ver1);501 else502 return HNS_DEBUG_RING_IRQ_IDX;503}504 505#define RCB_COMM_BASE_TO_RING_BASE(base, ringid)\506 ((base) + 0x10000 + HNS_RCB_REG_OFFSET * (ringid))507/**508 *hns_rcb_get_cfg - get rcb config509 *@rcb_common: rcb common device510 */511int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common)512{513 struct ring_pair_cb *ring_pair_cb;514 u32 i;515 u32 ring_num = rcb_common->ring_num;516 int base_irq_idx = hns_rcb_get_base_irq_idx(rcb_common);517 struct platform_device *pdev =518 to_platform_device(rcb_common->dsaf_dev->dev);519 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);520 521 for (i = 0; i < ring_num; i++) {522 ring_pair_cb = &rcb_common->ring_pair_cb[i];523 ring_pair_cb->rcb_common = rcb_common;524 ring_pair_cb->dev = rcb_common->dsaf_dev->dev;525 ring_pair_cb->index = i;526 ring_pair_cb->q.io_base =527 RCB_COMM_BASE_TO_RING_BASE(rcb_common->io_base, i);528 ring_pair_cb->port_id_in_comm =529 hns_rcb_get_port_in_comm(rcb_common, i);530 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] =531 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2) :532 platform_get_irq(pdev, base_irq_idx + i * 3 + 1);533 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] =534 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2 + 1) :535 platform_get_irq(pdev, base_irq_idx + i * 3);536 if ((ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] == -EPROBE_DEFER) ||537 (ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] == -EPROBE_DEFER))538 return -EPROBE_DEFER;539 540 ring_pair_cb->q.phy_base =541 RCB_COMM_BASE_TO_RING_BASE(rcb_common->phy_base, i);542 hns_rcb_ring_pair_get_cfg(ring_pair_cb);543 }544 545 return 0;546}547 548/**549 *hns_rcb_get_rx_coalesced_frames - get rcb port rx coalesced frames550 *@rcb_common: rcb_common device551 *@port_idx:port id in comm552 *553 *Returns: coalesced_frames554 */555u32 hns_rcb_get_rx_coalesced_frames(556 struct rcb_common_cb *rcb_common, u32 port_idx)557{558 return dsaf_read_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4);559}560 561/**562 *hns_rcb_get_tx_coalesced_frames - get rcb port tx coalesced frames563 *@rcb_common: rcb_common device564 *@port_idx:port id in comm565 *566 *Returns: coalesced_frames567 */568u32 hns_rcb_get_tx_coalesced_frames(569 struct rcb_common_cb *rcb_common, u32 port_idx)570{571 u64 reg;572 573 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;574 return dsaf_read_dev(rcb_common, reg);575}576 577/**578 *hns_rcb_get_coalesce_usecs - get rcb port coalesced time_out579 *@rcb_common: rcb_common device580 *@port_idx:port id in comm581 *582 *Returns: time_out583 */584u32 hns_rcb_get_coalesce_usecs(585 struct rcb_common_cb *rcb_common, u32 port_idx)586{587 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver))588 return dsaf_read_dev(rcb_common, RCB_CFG_OVERTIME_REG) /589 HNS_RCB_CLK_FREQ_MHZ;590 else591 return dsaf_read_dev(rcb_common,592 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4);593}594 595/**596 *hns_rcb_set_coalesce_usecs - set rcb port coalesced time_out597 *@rcb_common: rcb_common device598 *@port_idx:port id in comm599 *@timeout:tx/rx time for coalesced time_out600 *601 * Returns:602 * Zero for success, or an error code in case of failure603 */604int hns_rcb_set_coalesce_usecs(605 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)606{607 u32 old_timeout = hns_rcb_get_coalesce_usecs(rcb_common, port_idx);608 609 if (timeout == old_timeout)610 return 0;611 612 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {613 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {614 dev_err(rcb_common->dsaf_dev->dev,615 "error: not support coalesce_usecs setting!\n");616 return -EINVAL;617 }618 }619 if (timeout > HNS_RCB_MAX_COALESCED_USECS || timeout == 0) {620 dev_err(rcb_common->dsaf_dev->dev,621 "error: coalesce_usecs setting supports 1~1023us\n");622 return -EINVAL;623 }624 hns_rcb_set_port_timeout(rcb_common, port_idx, timeout);625 return 0;626}627 628/**629 *hns_rcb_set_tx_coalesced_frames - set rcb coalesced frames630 *@rcb_common: rcb_common device631 *@port_idx:port id in comm632 *@coalesced_frames:tx/rx BD num for coalesced frames633 *634 * Returns:635 * Zero for success, or an error code in case of failure636 */637int hns_rcb_set_tx_coalesced_frames(638 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)639{640 u32 old_waterline =641 hns_rcb_get_tx_coalesced_frames(rcb_common, port_idx);642 u64 reg;643 644 if (coalesced_frames == old_waterline)645 return 0;646 647 if (coalesced_frames != 1) {648 dev_err(rcb_common->dsaf_dev->dev,649 "error: not support tx coalesce_frames setting!\n");650 return -EINVAL;651 }652 653 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;654 dsaf_write_dev(rcb_common, reg, coalesced_frames);655 return 0;656}657 658/**659 *hns_rcb_set_rx_coalesced_frames - set rcb rx coalesced frames660 *@rcb_common: rcb_common device661 *@port_idx:port id in comm662 *@coalesced_frames:tx/rx BD num for coalesced frames663 *664 * Returns:665 * Zero for success, or an error code in case of failure666 */667int hns_rcb_set_rx_coalesced_frames(668 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)669{670 u32 old_waterline =671 hns_rcb_get_rx_coalesced_frames(rcb_common, port_idx);672 673 if (coalesced_frames == old_waterline)674 return 0;675 676 if (coalesced_frames >= rcb_common->desc_num ||677 coalesced_frames > HNS_RCB_MAX_COALESCED_FRAMES ||678 coalesced_frames < HNS_RCB_MIN_COALESCED_FRAMES) {679 dev_err(rcb_common->dsaf_dev->dev,680 "error: not support coalesce_frames setting!\n");681 return -EINVAL;682 }683 684 dsaf_write_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4,685 coalesced_frames);686 return 0;687}688 689/**690 *hns_rcb_get_queue_mode - get max VM number and max ring number per VM691 * accordding to dsaf mode692 *@dsaf_mode: dsaf mode693 *@max_vfn : max vfn number694 *@max_q_per_vf:max ring number per vm695 */696void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, u16 *max_vfn,697 u16 *max_q_per_vf)698{699 switch (dsaf_mode) {700 case DSAF_MODE_DISABLE_6PORT_0VM:701 *max_vfn = 1;702 *max_q_per_vf = 16;703 break;704 case DSAF_MODE_DISABLE_FIX:705 case DSAF_MODE_DISABLE_SP:706 *max_vfn = 1;707 *max_q_per_vf = 1;708 break;709 case DSAF_MODE_DISABLE_2PORT_64VM:710 *max_vfn = 64;711 *max_q_per_vf = 1;712 break;713 case DSAF_MODE_DISABLE_6PORT_16VM:714 *max_vfn = 16;715 *max_q_per_vf = 1;716 break;717 default:718 *max_vfn = 1;719 *max_q_per_vf = 16;720 break;721 }722}723 724static int hns_rcb_get_ring_num(struct dsaf_device *dsaf_dev)725{726 switch (dsaf_dev->dsaf_mode) {727 case DSAF_MODE_ENABLE_FIX:728 case DSAF_MODE_DISABLE_SP:729 return 1;730 731 case DSAF_MODE_DISABLE_FIX:732 return 6;733 734 case DSAF_MODE_ENABLE_0VM:735 return 32;736 737 case DSAF_MODE_DISABLE_6PORT_0VM:738 case DSAF_MODE_ENABLE_16VM:739 case DSAF_MODE_DISABLE_6PORT_2VM:740 case DSAF_MODE_DISABLE_6PORT_16VM:741 case DSAF_MODE_DISABLE_6PORT_4VM:742 case DSAF_MODE_ENABLE_8VM:743 return 96;744 745 case DSAF_MODE_DISABLE_2PORT_16VM:746 case DSAF_MODE_DISABLE_2PORT_8VM:747 case DSAF_MODE_ENABLE_32VM:748 case DSAF_MODE_DISABLE_2PORT_64VM:749 case DSAF_MODE_ENABLE_128VM:750 return 128;751 752 default:753 dev_warn(dsaf_dev->dev,754 "get ring num fail,use default!dsaf_mode=%d\n",755 dsaf_dev->dsaf_mode);756 return 128;757 }758}759 760static u8 __iomem *hns_rcb_common_get_vaddr(struct rcb_common_cb *rcb_common)761{762 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;763 764 return dsaf_dev->ppe_base + RCB_COMMON_REG_OFFSET;765}766 767static phys_addr_t hns_rcb_common_get_paddr(struct rcb_common_cb *rcb_common)768{769 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;770 771 return dsaf_dev->ppe_paddr + RCB_COMMON_REG_OFFSET;772}773 774int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev,775 int comm_index)776{777 struct rcb_common_cb *rcb_common;778 enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;779 u16 max_vfn;780 u16 max_q_per_vf;781 int ring_num = hns_rcb_get_ring_num(dsaf_dev);782 783 rcb_common =784 devm_kzalloc(dsaf_dev->dev,785 struct_size(rcb_common, ring_pair_cb, ring_num),786 GFP_KERNEL);787 if (!rcb_common) {788 dev_err(dsaf_dev->dev, "rcb common devm_kzalloc fail!\n");789 return -ENOMEM;790 }791 rcb_common->comm_index = comm_index;792 rcb_common->ring_num = ring_num;793 rcb_common->dsaf_dev = dsaf_dev;794 795 rcb_common->desc_num = dsaf_dev->desc_num;796 797 hns_rcb_get_queue_mode(dsaf_mode, &max_vfn, &max_q_per_vf);798 rcb_common->max_vfn = max_vfn;799 rcb_common->max_q_per_vf = max_q_per_vf;800 801 rcb_common->io_base = hns_rcb_common_get_vaddr(rcb_common);802 rcb_common->phy_base = hns_rcb_common_get_paddr(rcb_common);803 804 dsaf_dev->rcb_common[comm_index] = rcb_common;805 return 0;806}807 808void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev,809 u32 comm_index)810{811 dsaf_dev->rcb_common[comm_index] = NULL;812}813 814void hns_rcb_update_stats(struct hnae_queue *queue)815{816 struct ring_pair_cb *ring =817 container_of(queue, struct ring_pair_cb, q);818 struct dsaf_device *dsaf_dev = ring->rcb_common->dsaf_dev;819 struct ppe_common_cb *ppe_common820 = dsaf_dev->ppe_common[ring->rcb_common->comm_index];821 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;822 823 hw_stats->rx_pkts += dsaf_read_dev(queue,824 RCB_RING_RX_RING_PKTNUM_RECORD_REG);825 dsaf_write_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG, 0x1);826 827 hw_stats->ppe_rx_ok_pkts += dsaf_read_dev(ppe_common,828 PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 4 * ring->index);829 hw_stats->ppe_rx_drop_pkts += dsaf_read_dev(ppe_common,830 PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 4 * ring->index);831 832 hw_stats->tx_pkts += dsaf_read_dev(queue,833 RCB_RING_TX_RING_PKTNUM_RECORD_REG);834 dsaf_write_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG, 0x1);835 836 hw_stats->ppe_tx_ok_pkts += dsaf_read_dev(ppe_common,837 PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 4 * ring->index);838 hw_stats->ppe_tx_drop_pkts += dsaf_read_dev(ppe_common,839 PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 4 * ring->index);840}841 842/**843 *hns_rcb_get_stats - get rcb statistic844 *@queue: rcb ring845 *@data:statistic value846 */847void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data)848{849 u64 *regs_buff = data;850 struct ring_pair_cb *ring =851 container_of(queue, struct ring_pair_cb, q);852 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;853 854 regs_buff[0] = hw_stats->tx_pkts;855 regs_buff[1] = hw_stats->ppe_tx_ok_pkts;856 regs_buff[2] = hw_stats->ppe_tx_drop_pkts;857 regs_buff[3] =858 dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);859 860 regs_buff[4] = queue->tx_ring.stats.tx_pkts;861 regs_buff[5] = queue->tx_ring.stats.tx_bytes;862 regs_buff[6] = queue->tx_ring.stats.tx_err_cnt;863 regs_buff[7] = queue->tx_ring.stats.io_err_cnt;864 regs_buff[8] = queue->tx_ring.stats.sw_err_cnt;865 regs_buff[9] = queue->tx_ring.stats.seg_pkt_cnt;866 regs_buff[10] = queue->tx_ring.stats.restart_queue;867 regs_buff[11] = queue->tx_ring.stats.tx_busy;868 869 regs_buff[12] = hw_stats->rx_pkts;870 regs_buff[13] = hw_stats->ppe_rx_ok_pkts;871 regs_buff[14] = hw_stats->ppe_rx_drop_pkts;872 regs_buff[15] =873 dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);874 875 regs_buff[16] = queue->rx_ring.stats.rx_pkts;876 regs_buff[17] = queue->rx_ring.stats.rx_bytes;877 regs_buff[18] = queue->rx_ring.stats.rx_err_cnt;878 regs_buff[19] = queue->rx_ring.stats.io_err_cnt;879 regs_buff[20] = queue->rx_ring.stats.sw_err_cnt;880 regs_buff[21] = queue->rx_ring.stats.seg_pkt_cnt;881 regs_buff[22] = queue->rx_ring.stats.reuse_pg_cnt;882 regs_buff[23] = queue->rx_ring.stats.err_pkt_len;883 regs_buff[24] = queue->rx_ring.stats.non_vld_descs;884 regs_buff[25] = queue->rx_ring.stats.err_bd_num;885 regs_buff[26] = queue->rx_ring.stats.l2_err;886 regs_buff[27] = queue->rx_ring.stats.l3l4_csum_err;887}888 889/**890 *hns_rcb_get_ring_sset_count - rcb string set count891 *@stringset:ethtool cmd892 *return rcb ring string set count893 */894int hns_rcb_get_ring_sset_count(int stringset)895{896 if (stringset == ETH_SS_STATS)897 return HNS_RING_STATIC_REG_NUM;898 899 return 0;900}901 902/**903 *hns_rcb_get_common_regs_count - rcb common regs count904 *return regs count905 */906int hns_rcb_get_common_regs_count(void)907{908 return HNS_RCB_COMMON_DUMP_REG_NUM;909}910 911/**912 *hns_rcb_get_ring_regs_count - rcb ring regs count913 *return regs count914 */915int hns_rcb_get_ring_regs_count(void)916{917 return HNS_RCB_RING_DUMP_REG_NUM;918}919 920/**921 *hns_rcb_get_strings - get rcb string set922 *@stringset:string set index923 *@data:strings name value924 *@index:queue index925 */926void hns_rcb_get_strings(int stringset, u8 *data, int index)927{928 u8 *buff = data;929 930 if (stringset != ETH_SS_STATS)931 return;932 933 ethtool_sprintf(&buff, "tx_ring%d_rcb_pkt_num", index);934 ethtool_sprintf(&buff, "tx_ring%d_ppe_tx_pkt_num", index);935 ethtool_sprintf(&buff, "tx_ring%d_ppe_drop_pkt_num", index);936 ethtool_sprintf(&buff, "tx_ring%d_fbd_num", index);937 938 ethtool_sprintf(&buff, "tx_ring%d_pkt_num", index);939 ethtool_sprintf(&buff, "tx_ring%d_bytes", index);940 ethtool_sprintf(&buff, "tx_ring%d_err_cnt", index);941 ethtool_sprintf(&buff, "tx_ring%d_io_err", index);942 ethtool_sprintf(&buff, "tx_ring%d_sw_err", index);943 ethtool_sprintf(&buff, "tx_ring%d_seg_pkt", index);944 ethtool_sprintf(&buff, "tx_ring%d_restart_queue", index);945 ethtool_sprintf(&buff, "tx_ring%d_tx_busy", index);946 947 ethtool_sprintf(&buff, "rx_ring%d_rcb_pkt_num", index);948 ethtool_sprintf(&buff, "rx_ring%d_ppe_pkt_num", index);949 ethtool_sprintf(&buff, "rx_ring%d_ppe_drop_pkt_num", index);950 ethtool_sprintf(&buff, "rx_ring%d_fbd_num", index);951 952 ethtool_sprintf(&buff, "rx_ring%d_pkt_num", index);953 ethtool_sprintf(&buff, "rx_ring%d_bytes", index);954 ethtool_sprintf(&buff, "rx_ring%d_err_cnt", index);955 ethtool_sprintf(&buff, "rx_ring%d_io_err", index);956 ethtool_sprintf(&buff, "rx_ring%d_sw_err", index);957 ethtool_sprintf(&buff, "rx_ring%d_seg_pkt", index);958 ethtool_sprintf(&buff, "rx_ring%d_reuse_pg", index);959 ethtool_sprintf(&buff, "rx_ring%d_len_err", index);960 ethtool_sprintf(&buff, "rx_ring%d_non_vld_desc_err", index);961 ethtool_sprintf(&buff, "rx_ring%d_bd_num_err", index);962 ethtool_sprintf(&buff, "rx_ring%d_l2_err", index);963 ethtool_sprintf(&buff, "rx_ring%d_l3l4csum_err", index);964}965 966void hns_rcb_get_common_regs(struct rcb_common_cb *rcb_com, void *data)967{968 u32 *regs = data;969 bool is_ver1 = AE_IS_VER1(rcb_com->dsaf_dev->dsaf_ver);970 bool is_dbg = HNS_DSAF_IS_DEBUG(rcb_com->dsaf_dev);971 u32 reg_tmp;972 u32 reg_num_tmp;973 u32 i;974 975 /*rcb common registers */976 regs[0] = dsaf_read_dev(rcb_com, RCB_COM_CFG_ENDIAN_REG);977 regs[1] = dsaf_read_dev(rcb_com, RCB_COM_CFG_SYS_FSH_REG);978 regs[2] = dsaf_read_dev(rcb_com, RCB_COM_CFG_INIT_FLAG_REG);979 980 regs[3] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_REG);981 regs[4] = dsaf_read_dev(rcb_com, RCB_COM_CFG_RINVLD_REG);982 regs[5] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FNA_REG);983 regs[6] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FA_REG);984 regs[7] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_TC_BP_REG);985 regs[8] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PPE_TNL_CLKEN_REG);986 987 regs[9] = dsaf_read_dev(rcb_com, RCB_COM_INTMSK_TX_PKT_REG);988 regs[10] = dsaf_read_dev(rcb_com, RCB_COM_RINT_TX_PKT_REG);989 regs[11] = dsaf_read_dev(rcb_com, RCB_COM_INTMASK_ECC_ERR_REG);990 regs[12] = dsaf_read_dev(rcb_com, RCB_COM_INTSTS_ECC_ERR_REG);991 regs[13] = dsaf_read_dev(rcb_com, RCB_COM_EBD_SRAM_ERR_REG);992 regs[14] = dsaf_read_dev(rcb_com, RCB_COM_RXRING_ERR_REG);993 regs[15] = dsaf_read_dev(rcb_com, RCB_COM_TXRING_ERR_REG);994 regs[16] = dsaf_read_dev(rcb_com, RCB_COM_TX_FBD_ERR_REG);995 regs[17] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK_EN_REG);996 regs[18] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK0_REG);997 regs[19] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK1_REG);998 regs[20] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK2_REG);999 regs[21] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK3_REG);1000 regs[22] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK4_REG);1001 regs[23] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK5_REG);1002 regs[24] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR0_REG);1003 regs[25] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR3_REG);1004 regs[26] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR4_REG);1005 regs[27] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR5_REG);1006 1007 regs[28] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_RING);1008 regs[29] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING_STS);1009 regs[30] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING);1010 regs[31] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_BD);1011 regs[32] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_BD_RINT_STS);1012 regs[33] = dsaf_read_dev(rcb_com, RCB_COM_RCB_RD_BD_BUSY);1013 regs[34] = dsaf_read_dev(rcb_com, RCB_COM_RCB_FBD_CRT_EN);1014 regs[35] = dsaf_read_dev(rcb_com, RCB_COM_AXI_WR_ERR_INTMASK);1015 regs[36] = dsaf_read_dev(rcb_com, RCB_COM_AXI_ERR_STS);1016 regs[37] = dsaf_read_dev(rcb_com, RCB_COM_CHK_TX_FBD_NUM_REG);1017 1018 /* rcb common entry registers */1019 for (i = 0; i < 16; i++) { /* total 16 model registers */1020 regs[38 + i]1021 = dsaf_read_dev(rcb_com, RCB_CFG_BD_NUM_REG + 4 * i);1022 regs[54 + i]1023 = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_REG + 4 * i);1024 }1025 1026 reg_tmp = is_ver1 ? RCB_CFG_OVERTIME_REG : RCB_PORT_CFG_OVERTIME_REG;1027 reg_num_tmp = (is_ver1 || is_dbg) ? 1 : 6;1028 for (i = 0; i < reg_num_tmp; i++)1029 regs[70 + i] = dsaf_read_dev(rcb_com, reg_tmp);1030 1031 regs[76] = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_INT_NUM_REG);1032 regs[77] = dsaf_read_dev(rcb_com, RCB_CFG_OVERTIME_INT_NUM_REG);1033 1034 /* mark end of rcb common regs */1035 for (i = 78; i < 80; i++)1036 regs[i] = 0xcccccccc;1037}1038 1039void hns_rcb_get_ring_regs(struct hnae_queue *queue, void *data)1040{1041 u32 *regs = data;1042 struct ring_pair_cb *ring_pair1043 = container_of(queue, struct ring_pair_cb, q);1044 u32 i;1045 1046 /*rcb ring registers */1047 regs[0] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_L_REG);1048 regs[1] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_H_REG);1049 regs[2] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_NUM_REG);1050 regs[3] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_LEN_REG);1051 regs[4] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTLINE_REG);1052 regs[5] = dsaf_read_dev(queue, RCB_RING_RX_RING_TAIL_REG);1053 regs[6] = dsaf_read_dev(queue, RCB_RING_RX_RING_HEAD_REG);1054 regs[7] = dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);1055 regs[8] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG);1056 1057 regs[9] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_L_REG);1058 regs[10] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_H_REG);1059 regs[11] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_NUM_REG);1060 regs[12] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_LEN_REG);1061 regs[13] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTLINE_REG);1062 regs[15] = dsaf_read_dev(queue, RCB_RING_TX_RING_TAIL_REG);1063 regs[16] = dsaf_read_dev(queue, RCB_RING_TX_RING_HEAD_REG);1064 regs[17] = dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);1065 regs[18] = dsaf_read_dev(queue, RCB_RING_TX_RING_OFFSET_REG);1066 regs[19] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG);1067 1068 regs[20] = dsaf_read_dev(queue, RCB_RING_PREFETCH_EN_REG);1069 regs[21] = dsaf_read_dev(queue, RCB_RING_CFG_VF_NUM_REG);1070 regs[22] = dsaf_read_dev(queue, RCB_RING_ASID_REG);1071 regs[23] = dsaf_read_dev(queue, RCB_RING_RX_VM_REG);1072 regs[24] = dsaf_read_dev(queue, RCB_RING_T0_BE_RST);1073 regs[25] = dsaf_read_dev(queue, RCB_RING_COULD_BE_RST);1074 regs[26] = dsaf_read_dev(queue, RCB_RING_WRR_WEIGHT_REG);1075 1076 regs[27] = dsaf_read_dev(queue, RCB_RING_INTMSK_RXWL_REG);1077 regs[28] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_RING_REG);1078 regs[29] = dsaf_read_dev(queue, RCB_RING_INTMSK_TXWL_REG);1079 regs[30] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_RING_REG);1080 regs[31] = dsaf_read_dev(queue, RCB_RING_INTMSK_RX_OVERTIME_REG);1081 regs[32] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_OVERTIME_REG);1082 regs[33] = dsaf_read_dev(queue, RCB_RING_INTMSK_TX_OVERTIME_REG);1083 regs[34] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_OVERTIME_REG);1084 1085 /* mark end of ring regs */1086 for (i = 35; i < 40; i++)1087 regs[i] = 0xcccccc00 + ring_pair->index;1088}1089