1096 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2014-2015 Hisilicon Limited.4 */5 6#ifndef _DSAF_REG_H_7#define _DSAF_REG_H_8 9#include <linux/regmap.h>10#define HNS_DEBUG_RING_IRQ_IDX 011#define HNS_SERVICE_RING_IRQ_IDX 5912#define HNSV2_SERVICE_RING_IRQ_IDX 2513 14#define DSAF_MAX_PORT_NUM 615#define DSAF_MAX_VM_NUM 12816 17#define DSAF_COMM_DEV_NUM 118#define DSAF_PPE_INODE_BASE 619#define DSAF_DEBUG_NW_NUM 220#define DSAF_SERVICE_NW_NUM 621#define DSAF_COMM_CHN DSAF_SERVICE_NW_NUM22#define DSAF_GE_NUM ((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM))23#define DSAF_XGE_NUM DSAF_SERVICE_NW_NUM24#define DSAF_PORT_TYPE_NUM 325#define DSAF_NODE_NUM 1826#define DSAF_XOD_BIG_NUM DSAF_NODE_NUM27#define DSAF_SBM_NUM DSAF_NODE_NUM28#define DSAFV2_SBM_NUM 829#define DSAFV2_SBM_XGE_CHN 630#define DSAFV2_SBM_PPE_CHN 131#define DASFV2_ROCEE_CRD_NUM 132 33#define DSAF_VOQ_NUM DSAF_NODE_NUM34#define DSAF_INODE_NUM DSAF_NODE_NUM35#define DSAF_XOD_NUM 836#define DSAF_TBL_NUM 837#define DSAF_SW_PORT_NUM 838#define DSAF_TOTAL_QUEUE_NUM 12939 40/* reserved a tcam entry for each port to support promisc by fuzzy match */41#define DSAFV2_MAC_FUZZY_TCAM_NUM DSAF_MAX_PORT_NUM42 43#define DSAF_TCAM_SUM 51244#define DSAF_LINE_SUM (2048 * 14)45 46#define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x10047#define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x18048#define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x18449#define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x18850#define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C51#define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x19052#define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x19453#define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x30054#define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x30455#define DSAF_SUB_SC_NT_CLK_EN_REG 0x30856#define DSAF_SUB_SC_NT_CLK_DIS_REG 0x30C57#define DSAF_SUB_SC_XGE_CLK_EN_REG 0x31058#define DSAF_SUB_SC_XGE_CLK_DIS_REG 0x31459#define DSAF_SUB_SC_GE_CLK_EN_REG 0x31860#define DSAF_SUB_SC_GE_CLK_DIS_REG 0x31C61#define DSAF_SUB_SC_PPE_CLK_EN_REG 0x32062#define DSAF_SUB_SC_PPE_CLK_DIS_REG 0x32463#define DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG 0x35064#define DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG 0x35465#define DSAF_SUB_SC_XBAR_RESET_REQ_REG 0xA0066#define DSAF_SUB_SC_XBAR_RESET_DREQ_REG 0xA0467#define DSAF_SUB_SC_NT_RESET_REQ_REG 0xA0868#define DSAF_SUB_SC_NT_RESET_DREQ_REG 0xA0C69#define DSAF_SUB_SC_XGE_RESET_REQ_REG 0xA1070#define DSAF_SUB_SC_XGE_RESET_DREQ_REG 0xA1471#define DSAF_SUB_SC_GE_RESET_REQ0_REG 0xA1872#define DSAF_SUB_SC_GE_RESET_DREQ0_REG 0xA1C73#define DSAF_SUB_SC_GE_RESET_REQ1_REG 0xA2074#define DSAF_SUB_SC_GE_RESET_DREQ1_REG 0xA2475#define DSAF_SUB_SC_PPE_RESET_REQ_REG 0xA4876#define DSAF_SUB_SC_PPE_RESET_DREQ_REG 0xA4C77#define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG 0xA8878#define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG 0xA8C79#define DSAF_SUB_SC_DSAF_RESET_REQ_REG 0xAA880#define DSAF_SUB_SC_DSAF_RESET_DREQ_REG 0xAAC81#define DSAF_SUB_SC_ROCEE_RESET_REQ_REG 0xA5082#define DSAF_SUB_SC_ROCEE_RESET_DREQ_REG 0xA5483#define DSAF_SUB_SC_ROCEE_CLK_DIS_REG 0x32C84#define DSAF_SUB_SC_ROCEE_CLK_EN_REG 0x32885#define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG 0x206086#define DSAF_SUB_SC_TCAM_MBIST_EN_REG 0x230087#define DSAF_SUB_SC_DSAF_CLK_ST_REG 0x530088#define DSAF_SUB_SC_NT_CLK_ST_REG 0x530489#define DSAF_SUB_SC_XGE_CLK_ST_REG 0x530890#define DSAF_SUB_SC_GE_CLK_ST_REG 0x530C91#define DSAF_SUB_SC_PPE_CLK_ST_REG 0x531092#define DSAF_SUB_SC_ROCEE_CLK_ST_REG 0x531493#define DSAF_SUB_SC_CPU_CLK_ST_REG 0x531894#define DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG 0x532895#define DSAF_SUB_SC_XBAR_RESET_ST_REG 0x5A0096#define DSAF_SUB_SC_NT_RESET_ST_REG 0x5A0497#define DSAF_SUB_SC_XGE_RESET_ST_REG 0x5A0898#define DSAF_SUB_SC_GE_RESET_ST0_REG 0x5A0C99#define DSAF_SUB_SC_GE_RESET_ST1_REG 0x5A10100#define DSAF_SUB_SC_PPE_RESET_ST_REG 0x5A24101#define DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG 0x5A44102 103/*serdes offset**/104#define HNS_MAC_HILINK3_REG DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG105#define HNS_MAC_HILINK4_REG DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG106#define HNS_MAC_HILINK3V2_REG DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG107#define HNS_MAC_HILINK4V2_REG DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG108#define HNS_MAC_LANE0_CTLEDFE_REG 0x000BFFCCULL109#define HNS_MAC_LANE1_CTLEDFE_REG 0x000BFFBCULL110#define HNS_MAC_LANE2_CTLEDFE_REG 0x000BFFACULL111#define HNS_MAC_LANE3_CTLEDFE_REG 0x000BFF9CULL112#define HNS_MAC_LANE0_STATE_REG 0x000BFFD4ULL113#define HNS_MAC_LANE1_STATE_REG 0x000BFFC4ULL114#define HNS_MAC_LANE2_STATE_REG 0x000BFFB4ULL115#define HNS_MAC_LANE3_STATE_REG 0x000BFFA4ULL116 117#define HILINK_RESET_TIMOUT 10000118 119#define DSAF_SRAM_INIT_OVER_0_REG 0x0120#define DSAF_CFG_0_REG 0x4121#define DSAF_ECC_ERR_INVERT_0_REG 0x8122#define DSAF_ABNORMAL_TIMEOUT_0_REG 0x1C123#define DSAF_FSM_TIMEOUT_0_REG 0x20124#define DSAF_DSA_REG_CNT_CLR_CE_REG 0x2C125#define DSAF_DSA_SBM_INF_FIFO_THRD_REG 0x30126#define DSAF_DSA_SRAM_1BIT_ECC_SEL_REG 0x34127#define DSAF_DSA_SRAM_1BIT_ECC_CNT_REG 0x38128#define DSAF_PFC_EN_0_REG 0x50129#define DSAF_PFC_UNIT_CNT_0_REG 0x70130#define DSAF_XGE_INT_MSK_0_REG 0x100131#define DSAF_PPE_INT_MSK_0_REG 0x120132#define DSAF_ROCEE_INT_MSK_0_REG 0x140133#define DSAF_XGE_INT_SRC_0_REG 0x160134#define DSAF_PPE_INT_SRC_0_REG 0x180135#define DSAF_ROCEE_INT_SRC_0_REG 0x1A0136#define DSAF_XGE_INT_STS_0_REG 0x1C0137#define DSAF_PPE_INT_STS_0_REG 0x1E0138#define DSAF_ROCEE_INT_STS_0_REG 0x200139#define DSAFV2_SERDES_LBK_0_REG 0x220140#define DSAF_PAUSE_CFG_REG 0x240141#define DSAF_ROCE_PORT_MAP_REG 0x2A0142#define DSAF_ROCE_SL_MAP_REG 0x2A4143#define DSAF_PPE_QID_CFG_0_REG 0x300144#define DSAF_SW_PORT_TYPE_0_REG 0x320145#define DSAF_STP_PORT_TYPE_0_REG 0x340146#define DSAF_MIX_DEF_QID_0_REG 0x360147#define DSAF_PORT_DEF_VLAN_0_REG 0x380148#define DSAF_VM_DEF_VLAN_0_REG 0x400149 150#define DSAF_INODE_CUT_THROUGH_CFG_0_REG 0x1000151#define DSAF_INODE_ECC_INVERT_EN_0_REG 0x1008152#define DSAF_INODE_ECC_ERR_ADDR_0_REG 0x100C153#define DSAF_INODE_IN_PORT_NUM_0_REG 0x1018154#define DSAF_INODE_PRI_TC_CFG_0_REG 0x101C155#define DSAF_INODE_BP_STATUS_0_REG 0x1020156#define DSAF_INODE_PAD_DISCARD_NUM_0_REG 0x1028157#define DSAF_INODE_FINAL_IN_MAN_NUM_0_REG 0x102C158#define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG 0x1030159#define DSAF_INODE_SBM_PID_NUM_0_REG 0x1038160#define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x103C161#define DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x1024162#define DSAF_INODE_SBM_RELS_NUM_0_REG 0x104C163#define DSAF_INODE_SBM_DROP_NUM_0_REG 0x1050164#define DSAF_INODE_CRC_FALSE_NUM_0_REG 0x1054165#define DSAF_INODE_BP_DISCARD_NUM_0_REG 0x1058166#define DSAF_INODE_RSLT_DISCARD_NUM_0_REG 0x105C167#define DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG 0x1060168#define DSAF_INODE_VOQ_OVER_NUM_0_REG 0x1068169#define DSAF_INODE_BD_SAVE_STATUS_0_REG 0x1900170#define DSAF_INODE_BD_ORDER_STATUS_0_REG 0x1950171#define DSAF_INODE_SW_VLAN_TAG_DISC_0_REG 0x1A00172#define DSAF_INODE_IN_DATA_STP_DISC_0_REG 0x1A50173#define DSAF_INODE_GE_FC_EN_0_REG 0x1B00174#define DSAF_INODE_VC0_IN_PKT_NUM_0_REG 0x1B50175#define DSAF_INODE_VC1_IN_PKT_NUM_0_REG 0x103C176#define DSAF_INODE_IN_PRIO_PAUSE_BASE_REG 0x1C00177#define DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET 0x100178#define DSAF_INODE_IN_PRIO_PAUSE_OFFSET 0x50179 180#define DSAF_SBM_CFG_REG_0_REG 0x2000181#define DSAF_SBM_BP_CFG_0_XGE_REG_0_REG 0x2004182#define DSAF_SBM_BP_CFG_0_PPE_REG_0_REG 0x2304183#define DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG 0x2604184#define DSAF_SBM_BP_CFG_1_REG_0_REG 0x2008185#define DSAF_SBM_BP_CFG_2_XGE_REG_0_REG 0x200C186#define DSAF_SBM_BP_CFG_2_PPE_REG_0_REG 0x230C187#define DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG 0x260C188#define DSAF_SBM_ROCEE_CFG_REG_REG 0x2380189#define DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG 0x238C190#define DSAF_SBM_FREE_CNT_0_0_REG 0x2010191#define DSAF_SBM_FREE_CNT_1_0_REG 0x2014192#define DSAF_SBM_BP_CNT_0_0_REG 0x2018193#define DSAF_SBM_BP_CNT_1_0_REG 0x201C194#define DSAF_SBM_BP_CNT_2_0_REG 0x2020195#define DSAF_SBM_BP_CNT_3_0_REG 0x2024196#define DSAF_SBM_INER_ST_0_REG 0x2028197#define DSAF_SBM_MIB_REQ_FAILED_TC_0_REG 0x202C198#define DSAF_SBM_LNK_INPORT_CNT_0_REG 0x2030199#define DSAF_SBM_LNK_DROP_CNT_0_REG 0x2034200#define DSAF_SBM_INF_OUTPORT_CNT_0_REG 0x2038201#define DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG 0x203C202#define DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG 0x2040203#define DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG 0x2044204#define DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG 0x2048205#define DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG 0x204C206#define DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG 0x2050207#define DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG 0x2054208#define DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG 0x2058209#define DSAF_SBM_LNK_REQ_CNT_0_REG 0x205C210#define DSAF_SBM_LNK_RELS_CNT_0_REG 0x2060211#define DSAF_SBM_BP_CFG_3_REG_0_REG 0x2068212#define DSAF_SBM_BP_CFG_4_REG_0_REG 0x206C213 214#define DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG 0x3000215#define DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG 0x3004216#define DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG 0x3008217#define DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG 0x300C218#define DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG 0x3010219#define DSAF_XOD_ETS_TOKEN_CFG_0_REG 0x3014220#define DSAF_XOD_PFS_CFG_0_0_REG 0x3018221#define DSAF_XOD_PFS_CFG_1_0_REG 0x301C222#define DSAF_XOD_PFS_CFG_2_0_REG 0x3020223#define DSAF_XOD_GNT_L_0_REG 0x3024224#define DSAF_XOD_GNT_H_0_REG 0x3028225#define DSAF_XOD_CONNECT_STATE_0_REG 0x302C226#define DSAF_XOD_RCVPKT_CNT_0_REG 0x3030227#define DSAF_XOD_RCVTC0_CNT_0_REG 0x3034228#define DSAF_XOD_RCVTC1_CNT_0_REG 0x3038229#define DSAF_XOD_RCVTC2_CNT_0_REG 0x303C230#define DSAF_XOD_RCVTC3_CNT_0_REG 0x3040231#define DSAF_XOD_RCVVC0_CNT_0_REG 0x3044232#define DSAF_XOD_RCVVC1_CNT_0_REG 0x3048233#define DSAF_XOD_XGE_RCVIN0_CNT_0_REG 0x304C234#define DSAF_XOD_XGE_RCVIN1_CNT_0_REG 0x3050235#define DSAF_XOD_XGE_RCVIN2_CNT_0_REG 0x3054236#define DSAF_XOD_XGE_RCVIN3_CNT_0_REG 0x3058237#define DSAF_XOD_XGE_RCVIN4_CNT_0_REG 0x305C238#define DSAF_XOD_XGE_RCVIN5_CNT_0_REG 0x3060239#define DSAF_XOD_XGE_RCVIN6_CNT_0_REG 0x3064240#define DSAF_XOD_XGE_RCVIN7_CNT_0_REG 0x3068241#define DSAF_XOD_PPE_RCVIN0_CNT_0_REG 0x306C242#define DSAF_XOD_PPE_RCVIN1_CNT_0_REG 0x3070243#define DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG 0x3074244#define DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG 0x3078245#define DSAF_XOD_FIFO_STATUS_0_REG 0x307C246#define DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG 0x3A00247#define DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET 0x4248 249#define DSAF_VOQ_ECC_INVERT_EN_0_REG 0x4004250#define DSAF_VOQ_SRAM_PKT_NUM_0_REG 0x4008251#define DSAF_VOQ_IN_PKT_NUM_0_REG 0x400C252#define DSAF_VOQ_OUT_PKT_NUM_0_REG 0x4010253#define DSAF_VOQ_ECC_ERR_ADDR_0_REG 0x4014254#define DSAF_VOQ_BP_STATUS_0_REG 0x4018255#define DSAF_VOQ_SPUP_IDLE_0_REG 0x401C256#define DSAF_VOQ_XGE_XOD_REQ_0_0_REG 0x4024257#define DSAF_VOQ_XGE_XOD_REQ_1_0_REG 0x4028258#define DSAF_VOQ_PPE_XOD_REQ_0_REG 0x402C259#define DSAF_VOQ_ROCEE_XOD_REQ_0_REG 0x4030260#define DSAF_VOQ_BP_ALL_THRD_0_REG 0x4034261 262#define DSAF_TBL_CTRL_0_REG 0x5000263#define DSAF_TBL_INT_MSK_0_REG 0x5004264#define DSAF_TBL_INT_SRC_0_REG 0x5008265#define DSAF_TBL_INT_STS_0_REG 0x5100266#define DSAF_TBL_TCAM_ADDR_0_REG 0x500C267#define DSAF_TBL_LINE_ADDR_0_REG 0x5010268#define DSAF_TBL_TCAM_HIGH_0_REG 0x5014269#define DSAF_TBL_TCAM_LOW_0_REG 0x5018270#define DSAF_TBL_TCAM_MCAST_CFG_4_0_REG 0x501C271#define DSAF_TBL_TCAM_MCAST_CFG_3_0_REG 0x5020272#define DSAF_TBL_TCAM_MCAST_CFG_2_0_REG 0x5024273#define DSAF_TBL_TCAM_MCAST_CFG_1_0_REG 0x5028274#define DSAF_TBL_TCAM_MCAST_CFG_0_0_REG 0x502C275#define DSAF_TBL_TCAM_UCAST_CFG_0_REG 0x5030276#define DSAF_TBL_LIN_CFG_0_REG 0x5034277#define DSAF_TBL_TCAM_RDATA_HIGH_0_REG 0x5038278#define DSAF_TBL_TCAM_RDATA_LOW_0_REG 0x503C279#define DSAF_TBL_TCAM_RAM_RDATA4_0_REG 0x5040280#define DSAF_TBL_TCAM_RAM_RDATA3_0_REG 0x5044281#define DSAF_TBL_TCAM_RAM_RDATA2_0_REG 0x5048282#define DSAF_TBL_TCAM_RAM_RDATA1_0_REG 0x504C283#define DSAF_TBL_TCAM_RAM_RDATA0_0_REG 0x5050284#define DSAF_TBL_LIN_RDATA_0_REG 0x5054285#define DSAF_TBL_DA0_MIS_INFO1_0_REG 0x5058286#define DSAF_TBL_DA0_MIS_INFO0_0_REG 0x505C287#define DSAF_TBL_SA_MIS_INFO2_0_REG 0x5104288#define DSAF_TBL_SA_MIS_INFO1_0_REG 0x5098289#define DSAF_TBL_SA_MIS_INFO0_0_REG 0x509C290#define DSAF_TBL_PUL_0_REG 0x50A0291#define DSAF_TBL_OLD_RSLT_0_REG 0x50A4292#define DSAF_TBL_OLD_SCAN_VAL_0_REG 0x50A8293#define DSAF_TBL_DFX_CTRL_0_REG 0x50AC294#define DSAF_TBL_DFX_STAT_0_REG 0x50B0295#define DSAF_TBL_DFX_STAT_2_0_REG 0x5108296#define DSAF_TBL_LKUP_NUM_I_0_REG 0x50C0297#define DSAF_TBL_LKUP_NUM_O_0_REG 0x50E0298#define DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG 0x510C299#define DSAF_TBL_TCAM_MATCH_CFG_H_REG 0x5130300#define DSAF_TBL_TCAM_MATCH_CFG_L_REG 0x5134301 302#define DSAF_INODE_FIFO_WL_0_REG 0x6000303#define DSAF_ONODE_FIFO_WL_0_REG 0x6020304#define DSAF_XGE_GE_WORK_MODE_0_REG 0x6040305#define DSAF_XGE_APP_RX_LINK_UP_0_REG 0x6080306#define DSAF_NETPORT_CTRL_SIG_0_REG 0x60A0307#define DSAF_XGE_CTRL_SIG_CFG_0_REG 0x60C0308 309#define PPE_COM_CFG_QID_MODE_REG 0x0310#define PPE_COM_INTEN_REG 0x110311#define PPE_COM_RINT_REG 0x114312#define PPE_COM_INTSTS_REG 0x118313#define PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG 0x300314#define PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG 0x600315#define PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG 0x900316#define PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG 0xC00317#define PPE_COM_COMMON_CNT_CLR_CE_REG 0x1120318 319#define PPE_CFG_TX_FIFO_THRSLD_REG 0x0320#define PPE_CFG_RX_FIFO_THRSLD_REG 0x4321#define PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG 0x8322#define PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG 0xC323#define PPE_CFG_PAUSE_IDLE_CNT_REG 0x10324#define PPE_CFG_BUS_CTRL_REG 0x40325#define PPE_CFG_TNL_TO_BE_RST_REG 0x48326#define PPE_CURR_TNL_CAN_RST_REG 0x4C327#define PPE_CFG_XGE_MODE_REG 0x80328#define PPE_CFG_MAX_FRAME_LEN_REG 0x84329#define PPE_CFG_RX_PKT_MODE_REG 0x88330#define PPE_CFG_RX_VLAN_TAG_REG 0x8C331#define PPE_CFG_TAG_GEN_REG 0x90332#define PPE_CFG_PARSE_TAG_REG 0x94333#define PPE_CFG_PRO_CHECK_EN_REG 0x98334#define PPEV2_CFG_TSO_EN_REG 0xA0335#define PPEV2_VLAN_STRIP_EN_REG 0xAC336#define PPE_INTEN_REG 0x100337#define PPE_RINT_REG 0x104338#define PPE_INTSTS_REG 0x108339#define PPE_CFG_RX_PKT_INT_REG 0x140340#define PPE_CFG_HEAT_DECT_TIME0_REG 0x144341#define PPE_CFG_HEAT_DECT_TIME1_REG 0x148342#define PPE_HIS_RX_SW_PKT_CNT_REG 0x200343#define PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG 0x204344#define PPE_HIS_RX_PKT_NO_BUF_CNT_REG 0x208345#define PPE_HIS_TX_BD_CNT_REG 0x20C346#define PPE_HIS_TX_PKT_CNT_REG 0x210347#define PPE_HIS_TX_PKT_OK_CNT_REG 0x214348#define PPE_HIS_TX_PKT_EPT_CNT_REG 0x218349#define PPE_HIS_TX_PKT_CS_FAIL_CNT_REG 0x21C350#define PPE_HIS_RX_APP_BUF_FAIL_CNT_REG 0x220351#define PPE_HIS_RX_APP_BUF_WAIT_CNT_REG 0x224352#define PPE_HIS_RX_PKT_DROP_FUL_CNT_REG 0x228353#define PPE_HIS_RX_PKT_DROP_PRT_CNT_REG 0x22C354#define PPE_TNL_0_5_CNT_CLR_CE_REG 0x300355#define PPE_CFG_AXI_DBG_REG 0x304356#define PPE_HIS_PRO_ERR_REG 0x308357#define PPE_HIS_TNL_FIFO_ERR_REG 0x30C358#define PPE_CURR_CFF_DATA_NUM_REG 0x310359#define PPE_CURR_RX_ST_REG 0x314360#define PPE_CURR_TX_ST_REG 0x318361#define PPE_CURR_RX_FIFO0_REG 0x31C362#define PPE_CURR_RX_FIFO1_REG 0x320363#define PPE_CURR_TX_FIFO0_REG 0x324364#define PPE_CURR_TX_FIFO1_REG 0x328365#define PPE_ECO0_REG 0x32C366#define PPE_ECO1_REG 0x330367#define PPE_ECO2_REG 0x334368#define PPEV2_INDRECTION_TBL_REG 0x800369#define PPEV2_RSS_KEY_REG 0x900370 371#define RCB_COM_CFG_ENDIAN_REG 0x0372#define RCB_COM_CFG_SYS_FSH_REG 0xC373#define RCB_COM_CFG_INIT_FLAG_REG 0x10374#define RCB_COM_CFG_PKT_REG 0x30375#define RCB_COM_CFG_RINVLD_REG 0x34376#define RCB_COM_CFG_FNA_REG 0x38377#define RCB_COM_CFG_FA_REG 0x3C378#define RCB_COM_CFG_PKT_TC_BP_REG 0x40379#define RCB_COM_CFG_PPE_TNL_CLKEN_REG 0x44380#define RCBV2_COM_CFG_USER_REG 0x30381#define RCBV2_COM_CFG_TSO_MODE_REG 0x50382 383#define RCB_COM_INTMSK_TX_PKT_REG 0x3A0384#define RCB_COM_RINT_TX_PKT_REG 0x3A8385#define RCB_COM_INTMASK_ECC_ERR_REG 0x400386#define RCB_COM_INTSTS_ECC_ERR_REG 0x408387#define RCB_COM_EBD_SRAM_ERR_REG 0x410388#define RCB_COM_RXRING_ERR_REG 0x41C389#define RCB_COM_TXRING_ERR_REG 0x420390#define RCB_COM_TX_FBD_ERR_REG 0x424391#define RCB_SRAM_ECC_CHK_EN_REG 0x428392#define RCB_SRAM_ECC_CHK0_REG 0x42C393#define RCB_SRAM_ECC_CHK1_REG 0x430394#define RCB_SRAM_ECC_CHK2_REG 0x434395#define RCB_SRAM_ECC_CHK3_REG 0x438396#define RCB_SRAM_ECC_CHK4_REG 0x43c397#define RCB_SRAM_ECC_CHK5_REG 0x440398#define RCB_ECC_ERR_ADDR0_REG 0x450399#define RCB_ECC_ERR_ADDR3_REG 0x45C400#define RCB_ECC_ERR_ADDR4_REG 0x460401#define RCB_ECC_ERR_ADDR5_REG 0x464402 403#define RCB_COM_SF_CFG_INTMASK_RING 0x470404#define RCB_COM_SF_CFG_RING_STS 0x474405#define RCB_COM_SF_CFG_RING 0x478406#define RCB_COM_SF_CFG_INTMASK_BD 0x47C407#define RCB_COM_SF_CFG_BD_RINT_STS 0x480408#define RCB_COM_RCB_RD_BD_BUSY 0x490409#define RCB_COM_RCB_FBD_CRT_EN 0x494410#define RCB_COM_AXI_WR_ERR_INTMASK 0x498411#define RCB_COM_AXI_ERR_STS 0x49C412#define RCB_COM_CHK_TX_FBD_NUM_REG 0x4a0413 414#define RCB_CFG_BD_NUM_REG 0x9000415#define RCB_CFG_PKTLINE_REG 0x9050416 417#define RCB_CFG_OVERTIME_REG 0x9300418#define RCB_CFG_PKTLINE_INT_NUM_REG 0x9304419#define RCB_CFG_OVERTIME_INT_NUM_REG 0x9308420#define RCB_PORT_INT_GAPTIME_REG 0x9400421#define RCB_PORT_CFG_OVERTIME_REG 0x9430422 423#define RCB_RING_RX_RING_BASEADDR_L_REG 0x00000424#define RCB_RING_RX_RING_BASEADDR_H_REG 0x00004425#define RCB_RING_RX_RING_BD_NUM_REG 0x00008426#define RCB_RING_RX_RING_BD_LEN_REG 0x0000C427#define RCB_RING_RX_RING_PKTLINE_REG 0x00010428#define RCB_RING_RX_RING_TAIL_REG 0x00018429#define RCB_RING_RX_RING_HEAD_REG 0x0001C430#define RCB_RING_RX_RING_FBDNUM_REG 0x00020431#define RCB_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C432 433#define RCB_RING_TX_RING_BASEADDR_L_REG 0x00040434#define RCB_RING_TX_RING_BASEADDR_H_REG 0x00044435#define RCB_RING_TX_RING_BD_NUM_REG 0x00048436#define RCB_RING_TX_RING_BD_LEN_REG 0x0004C437#define RCB_RING_TX_RING_PKTLINE_REG 0x00050438#define RCB_RING_TX_RING_TAIL_REG 0x00058439#define RCB_RING_TX_RING_HEAD_REG 0x0005C440#define RCB_RING_TX_RING_FBDNUM_REG 0x00060441#define RCB_RING_TX_RING_OFFSET_REG 0x00064442#define RCB_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C443 444#define RCB_RING_PREFETCH_EN_REG 0x0007C445#define RCB_RING_CFG_VF_NUM_REG 0x00080446#define RCB_RING_ASID_REG 0x0008C447#define RCB_RING_RX_VM_REG 0x00090448#define RCB_RING_T0_BE_RST 0x00094449#define RCB_RING_COULD_BE_RST 0x00098450#define RCB_RING_WRR_WEIGHT_REG 0x0009c451 452#define RCB_RING_INTMSK_RXWL_REG 0x000A0453#define RCB_RING_INTSTS_RX_RING_REG 0x000A4454#define RCBV2_RX_RING_INT_STS_REG 0x000A8455#define RCB_RING_INTMSK_TXWL_REG 0x000AC456#define RCB_RING_INTSTS_TX_RING_REG 0x000B0457#define RCBV2_TX_RING_INT_STS_REG 0x000B4458#define RCB_RING_INTMSK_RX_OVERTIME_REG 0x000B8459#define RCB_RING_INTSTS_RX_OVERTIME_REG 0x000BC460#define RCB_RING_INTMSK_TX_OVERTIME_REG 0x000C4461#define RCB_RING_INTSTS_TX_OVERTIME_REG 0x000C8462 463#define GMAC_FIFO_STATE_REG 0x0000UL464#define GMAC_DUPLEX_TYPE_REG 0x0008UL465#define GMAC_FD_FC_TYPE_REG 0x000CUL466#define GMAC_TX_WATER_LINE_REG 0x0010UL467#define GMAC_FC_TX_TIMER_REG 0x001CUL468#define GMAC_FD_FC_ADDR_LOW_REG 0x0020UL469#define GMAC_FD_FC_ADDR_HIGH_REG 0x0024UL470#define GMAC_IPG_TX_TIMER_REG 0x0030UL471#define GMAC_PAUSE_THR_REG 0x0038UL472#define GMAC_MAX_FRM_SIZE_REG 0x003CUL473#define GMAC_PORT_MODE_REG 0x0040UL474#define GMAC_PORT_EN_REG 0x0044UL475#define GMAC_PAUSE_EN_REG 0x0048UL476#define GMAC_SHORT_RUNTS_THR_REG 0x0050UL477#define GMAC_AN_NEG_STATE_REG 0x0058UL478#define GMAC_TX_LOCAL_PAGE_REG 0x005CUL479#define GMAC_TRANSMIT_CONTROL_REG 0x0060UL480#define GMAC_REC_FILT_CONTROL_REG 0x0064UL481#define GMAC_PTP_CONFIG_REG 0x0074UL482 483#define GMAC_RX_OCTETS_TOTAL_OK_REG 0x0080UL484#define GMAC_RX_OCTETS_BAD_REG 0x0084UL485#define GMAC_RX_UC_PKTS_REG 0x0088UL486#define GMAC_RX_MC_PKTS_REG 0x008CUL487#define GMAC_RX_BC_PKTS_REG 0x0090UL488#define GMAC_RX_PKTS_64OCTETS_REG 0x0094UL489#define GMAC_RX_PKTS_65TO127OCTETS_REG 0x0098UL490#define GMAC_RX_PKTS_128TO255OCTETS_REG 0x009CUL491#define GMAC_RX_PKTS_255TO511OCTETS_REG 0x00A0UL492#define GMAC_RX_PKTS_512TO1023OCTETS_REG 0x00A4UL493#define GMAC_RX_PKTS_1024TO1518OCTETS_REG 0x00A8UL494#define GMAC_RX_PKTS_1519TOMAXOCTETS_REG 0x00ACUL495#define GMAC_RX_FCS_ERRORS_REG 0x00B0UL496#define GMAC_RX_TAGGED_REG 0x00B4UL497#define GMAC_RX_DATA_ERR_REG 0x00B8UL498#define GMAC_RX_ALIGN_ERRORS_REG 0x00BCUL499#define GMAC_RX_LONG_ERRORS_REG 0x00C0UL500#define GMAC_RX_JABBER_ERRORS_REG 0x00C4UL501#define GMAC_RX_PAUSE_MACCTRL_FRAM_REG 0x00C8UL502#define GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG 0x00CCUL503#define GMAC_RX_VERY_LONG_ERR_CNT_REG 0x00D0UL504#define GMAC_RX_RUNT_ERR_CNT_REG 0x00D4UL505#define GMAC_RX_SHORT_ERR_CNT_REG 0x00D8UL506#define GMAC_RX_FILT_PKT_CNT_REG 0x00E8UL507#define GMAC_RX_OCTETS_TOTAL_FILT_REG 0x00ECUL508#define GMAC_OCTETS_TRANSMITTED_OK_REG 0x0100UL509#define GMAC_OCTETS_TRANSMITTED_BAD_REG 0x0104UL510#define GMAC_TX_UC_PKTS_REG 0x0108UL511#define GMAC_TX_MC_PKTS_REG 0x010CUL512#define GMAC_TX_BC_PKTS_REG 0x0110UL513#define GMAC_TX_PKTS_64OCTETS_REG 0x0114UL514#define GMAC_TX_PKTS_65TO127OCTETS_REG 0x0118UL515#define GMAC_TX_PKTS_128TO255OCTETS_REG 0x011CUL516#define GMAC_TX_PKTS_255TO511OCTETS_REG 0x0120UL517#define GMAC_TX_PKTS_512TO1023OCTETS_REG 0x0124UL518#define GMAC_TX_PKTS_1024TO1518OCTETS_REG 0x0128UL519#define GMAC_TX_PKTS_1519TOMAXOCTETS_REG 0x012CUL520#define GMAC_TX_EXCESSIVE_LENGTH_DROP_REG 0x014CUL521#define GMAC_TX_UNDERRUN_REG 0x0150UL522#define GMAC_TX_TAGGED_REG 0x0154UL523#define GMAC_TX_CRC_ERROR_REG 0x0158UL524#define GMAC_TX_PAUSE_FRAMES_REG 0x015CUL525#define GAMC_RX_MAX_FRAME 0x0170UL526#define GMAC_LINE_LOOP_BACK_REG 0x01A8UL527#define GMAC_CF_CRC_STRIP_REG 0x01B0UL528#define GMAC_MODE_CHANGE_EN_REG 0x01B4UL529#define GMAC_SIXTEEN_BIT_CNTR_REG 0x01CCUL530#define GMAC_LD_LINK_COUNTER_REG 0x01D0UL531#define GMAC_LOOP_REG 0x01DCUL532#define GMAC_RECV_CONTROL_REG 0x01E0UL533#define GMAC_PCS_RX_EN_REG 0x01E4UL534#define GMAC_VLAN_CODE_REG 0x01E8UL535#define GMAC_RX_OVERRUN_CNT_REG 0x01ECUL536#define GMAC_RX_LENGTHFIELD_ERR_CNT_REG 0x01F4UL537#define GMAC_RX_FAIL_COMMA_CNT_REG 0x01F8UL538#define GMAC_STATION_ADDR_LOW_0_REG 0x0200UL539#define GMAC_STATION_ADDR_HIGH_0_REG 0x0204UL540#define GMAC_STATION_ADDR_LOW_1_REG 0x0208UL541#define GMAC_STATION_ADDR_HIGH_1_REG 0x020CUL542#define GMAC_STATION_ADDR_LOW_2_REG 0x0210UL543#define GMAC_STATION_ADDR_HIGH_2_REG 0x0214UL544#define GMAC_STATION_ADDR_LOW_3_REG 0x0218UL545#define GMAC_STATION_ADDR_HIGH_3_REG 0x021CUL546#define GMAC_STATION_ADDR_LOW_4_REG 0x0220UL547#define GMAC_STATION_ADDR_HIGH_4_REG 0x0224UL548#define GMAC_STATION_ADDR_LOW_5_REG 0x0228UL549#define GMAC_STATION_ADDR_HIGH_5_REG 0x022CUL550#define GMAC_STATION_ADDR_LOW_MSK_0_REG 0x0230UL551#define GMAC_STATION_ADDR_HIGH_MSK_0_REG 0x0234UL552#define GMAC_STATION_ADDR_LOW_MSK_1_REG 0x0238UL553#define GMAC_STATION_ADDR_HIGH_MSK_1_REG 0x023CUL554#define GMAC_MAC_SKIP_LEN_REG 0x0240UL555#define GMAC_TX_LOOP_PKT_PRI_REG 0x0378UL556 557#define XGMAC_INT_STATUS_REG 0x0558#define XGMAC_INT_ENABLE_REG 0x4559#define XGMAC_INT_SET_REG 0x8560#define XGMAC_IERR_U_INFO_REG 0xC561#define XGMAC_OVF_INFO_REG 0x10562#define XGMAC_OVF_CNT_REG 0x14563#define XGMAC_PORT_MODE_REG 0x40564#define XGMAC_CLK_ENABLE_REG 0x44565#define XGMAC_RESET_REG 0x48566#define XGMAC_LINK_CONTROL_REG 0x50567#define XGMAC_LINK_STATUS_REG 0x54568#define XGMAC_SPARE_REG 0xC0569#define XGMAC_SPARE_CNT_REG 0xC4570 571#define XGMAC_MAC_ENABLE_REG 0x100572#define XGMAC_MAC_CONTROL_REG 0x104573#define XGMAC_MAC_IPG_REG 0x120574#define XGMAC_MAC_MSG_CRC_EN_REG 0x124575#define XGMAC_MAC_MSG_IMG_REG 0x128576#define XGMAC_MAC_MSG_FC_CFG_REG 0x12C577#define XGMAC_MAC_MSG_TC_CFG_REG 0x130578#define XGMAC_MAC_PAD_SIZE_REG 0x134579#define XGMAC_MAC_MIN_PKT_SIZE_REG 0x138580#define XGMAC_MAC_MAX_PKT_SIZE_REG 0x13C581#define XGMAC_MAC_PAUSE_CTRL_REG 0x160582#define XGMAC_MAC_PAUSE_TIME_REG 0x164583#define XGMAC_MAC_PAUSE_GAP_REG 0x168584#define XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG 0x16C585#define XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG 0x170586#define XGMAC_MAC_PAUSE_PEER_MAC_H_REG 0x174587#define XGMAC_MAC_PAUSE_PEER_MAC_L_REG 0x178588#define XGMAC_MAC_PFC_PRI_EN_REG 0x17C589#define XGMAC_MAC_1588_CTRL_REG 0x180590#define XGMAC_MAC_1588_TX_PORT_DLY_REG 0x184591#define XGMAC_MAC_1588_RX_PORT_DLY_REG 0x188592#define XGMAC_MAC_1588_ASYM_DLY_REG 0x18C593#define XGMAC_MAC_1588_ADJUST_CFG_REG 0x190594#define XGMAC_MAC_Y1731_ETH_TYPE_REG 0x194595#define XGMAC_MAC_MIB_CONTROL_REG 0x198596#define XGMAC_MAC_WAN_RATE_ADJUST_REG 0x19C597#define XGMAC_MAC_TX_ERR_MARK_REG 0x1A0598#define XGMAC_MAC_TX_LF_RF_CONTROL_REG 0x1A4599#define XGMAC_MAC_RX_LF_RF_STATUS_REG 0x1A8600#define XGMAC_MAC_TX_RUNT_PKT_CNT_REG 0x1C0601#define XGMAC_MAC_RX_RUNT_PKT_CNT_REG 0x1C4602#define XGMAC_MAC_RX_PREAM_ERR_PKT_CNT_REG 0x1C8603#define XGMAC_MAC_TX_LF_RF_TERM_PKT_CNT_REG 0x1CC604#define XGMAC_MAC_TX_SN_MISMATCH_PKT_CNT_REG 0x1D0605#define XGMAC_MAC_RX_ERR_MSG_CNT_REG 0x1D4606#define XGMAC_MAC_RX_ERR_EFD_CNT_REG 0x1D8607#define XGMAC_MAC_ERR_INFO_REG 0x1DC608#define XGMAC_MAC_DBG_INFO_REG 0x1E0609 610#define XGMAC_PCS_BASER_SYNC_THD_REG 0x330611#define XGMAC_PCS_STATUS1_REG 0x404612#define XGMAC_PCS_BASER_STATUS1_REG 0x410613#define XGMAC_PCS_BASER_STATUS2_REG 0x414614#define XGMAC_PCS_BASER_SEEDA_0_REG 0x420615#define XGMAC_PCS_BASER_SEEDA_1_REG 0x424616#define XGMAC_PCS_BASER_SEEDB_0_REG 0x428617#define XGMAC_PCS_BASER_SEEDB_1_REG 0x42C618#define XGMAC_PCS_BASER_TEST_CONTROL_REG 0x430619#define XGMAC_PCS_BASER_TEST_ERR_CNT_REG 0x434620#define XGMAC_PCS_DBG_INFO_REG 0x4C0621#define XGMAC_PCS_DBG_INFO1_REG 0x4C4622#define XGMAC_PCS_DBG_INFO2_REG 0x4C8623#define XGMAC_PCS_DBG_INFO3_REG 0x4CC624 625#define XGMAC_PMA_ENABLE_REG 0x700626#define XGMAC_PMA_CONTROL_REG 0x704627#define XGMAC_PMA_SIGNAL_STATUS_REG 0x708628#define XGMAC_PMA_DBG_INFO_REG 0x70C629#define XGMAC_PMA_FEC_ABILITY_REG 0x740630#define XGMAC_PMA_FEC_CONTROL_REG 0x744631#define XGMAC_PMA_FEC_CORR_BLOCK_CNT__REG 0x750632#define XGMAC_PMA_FEC_UNCORR_BLOCK_CNT__REG 0x760633 634#define XGMAC_TX_PKTS_FRAGMENT 0x0000635#define XGMAC_TX_PKTS_UNDERSIZE 0x0008636#define XGMAC_TX_PKTS_UNDERMIN 0x0010637#define XGMAC_TX_PKTS_64OCTETS 0x0018638#define XGMAC_TX_PKTS_65TO127OCTETS 0x0020639#define XGMAC_TX_PKTS_128TO255OCTETS 0x0028640#define XGMAC_TX_PKTS_256TO511OCTETS 0x0030641#define XGMAC_TX_PKTS_512TO1023OCTETS 0x0038642#define XGMAC_TX_PKTS_1024TO1518OCTETS 0x0040643#define XGMAC_TX_PKTS_1519TOMAXOCTETS 0x0048644#define XGMAC_TX_PKTS_1519TOMAXOCTETSOK 0x0050645#define XGMAC_TX_PKTS_OVERSIZE 0x0058646#define XGMAC_TX_PKTS_JABBER 0x0060647#define XGMAC_TX_GOODPKTS 0x0068648#define XGMAC_TX_GOODOCTETS 0x0070649#define XGMAC_TX_TOTAL_PKTS 0x0078650#define XGMAC_TX_TOTALOCTETS 0x0080651#define XGMAC_TX_UNICASTPKTS 0x0088652#define XGMAC_TX_MULTICASTPKTS 0x0090653#define XGMAC_TX_BROADCASTPKTS 0x0098654#define XGMAC_TX_PRI0PAUSEPKTS 0x00a0655#define XGMAC_TX_PRI1PAUSEPKTS 0x00a8656#define XGMAC_TX_PRI2PAUSEPKTS 0x00b0657#define XGMAC_TX_PRI3PAUSEPKTS 0x00b8658#define XGMAC_TX_PRI4PAUSEPKTS 0x00c0659#define XGMAC_TX_PRI5PAUSEPKTS 0x00c8660#define XGMAC_TX_PRI6PAUSEPKTS 0x00d0661#define XGMAC_TX_PRI7PAUSEPKTS 0x00d8662#define XGMAC_TX_MACCTRLPKTS 0x00e0663#define XGMAC_TX_1731PKTS 0x00e8664#define XGMAC_TX_1588PKTS 0x00f0665#define XGMAC_RX_FROMAPPGOODPKTS 0x00f8666#define XGMAC_RX_FROMAPPBADPKTS 0x0100667#define XGMAC_TX_ERRALLPKTS 0x0108668 669#define XGMAC_RX_PKTS_FRAGMENT 0x0110670#define XGMAC_RX_PKTSUNDERSIZE 0x0118671#define XGMAC_RX_PKTS_UNDERMIN 0x0120672#define XGMAC_RX_PKTS_64OCTETS 0x0128673#define XGMAC_RX_PKTS_65TO127OCTETS 0x0130674#define XGMAC_RX_PKTS_128TO255OCTETS 0x0138675#define XGMAC_RX_PKTS_256TO511OCTETS 0x0140676#define XGMAC_RX_PKTS_512TO1023OCTETS 0x0148677#define XGMAC_RX_PKTS_1024TO1518OCTETS 0x0150678#define XGMAC_RX_PKTS_1519TOMAXOCTETS 0x0158679#define XGMAC_RX_PKTS_1519TOMAXOCTETSOK 0x0160680#define XGMAC_RX_PKTS_OVERSIZE 0x0168681#define XGMAC_RX_PKTS_JABBER 0x0170682#define XGMAC_RX_GOODPKTS 0x0178683#define XGMAC_RX_GOODOCTETS 0x0180684#define XGMAC_RX_TOTAL_PKTS 0x0188685#define XGMAC_RX_TOTALOCTETS 0x0190686#define XGMAC_RX_UNICASTPKTS 0x0198687#define XGMAC_RX_MULTICASTPKTS 0x01a0688#define XGMAC_RX_BROADCASTPKTS 0x01a8689#define XGMAC_RX_PRI0PAUSEPKTS 0x01b0690#define XGMAC_RX_PRI1PAUSEPKTS 0x01b8691#define XGMAC_RX_PRI2PAUSEPKTS 0x01c0692#define XGMAC_RX_PRI3PAUSEPKTS 0x01c8693#define XGMAC_RX_PRI4PAUSEPKTS 0x01d0694#define XGMAC_RX_PRI5PAUSEPKTS 0x01d8695#define XGMAC_RX_PRI6PAUSEPKTS 0x01e0696#define XGMAC_RX_PRI7PAUSEPKTS 0x01e8697#define XGMAC_RX_MACCTRLPKTS 0x01f0698#define XGMAC_TX_SENDAPPGOODPKTS 0x01f8699#define XGMAC_TX_SENDAPPBADPKTS 0x0200700#define XGMAC_RX_1731PKTS 0x0208701#define XGMAC_RX_SYMBOLERRPKTS 0x0210702#define XGMAC_RX_FCSERRPKTS 0x0218703 704#define DSAF_SRAM_INIT_OVER_M 0xff705#define DSAFV2_SRAM_INIT_OVER_M 0x3ff706#define DSAF_SRAM_INIT_OVER_S 0707 708#define DSAF_CFG_EN_S 0709#define DSAF_CFG_TC_MODE_S 1710#define DSAF_CFG_CRC_EN_S 2711#define DSAF_CFG_SBM_INIT_S 3712#define DSAF_CFG_MIX_MODE_S 4713#define DSAF_CFG_STP_MODE_S 5714#define DSAF_CFG_LOCA_ADDR_EN_S 6715#define DSAFV2_CFG_VLAN_TAG_MODE_S 17716 717#define DSAF_CNT_CLR_CE_S 0718#define DSAF_SNAP_EN_S 1719 720#define HNS_DSAF_PFC_UNIT_CNT_FOR_XGE 41721#define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000 410722#define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_2500 103723 724#define DSAF_PFC_UNINT_CNT_M ((1ULL << 9) - 1)725#define DSAF_PFC_UNINT_CNT_S 0726 727#define DSAF_MAC_PAUSE_RX_EN_B 2728#define DSAF_PFC_PAUSE_RX_EN_B 1729#define DSAF_PFC_PAUSE_TX_EN_B 0730 731#define DSAF_PPE_QID_CFG_M 0xFF732#define DSAF_PPE_QID_CFG_S 0733 734#define DSAF_SW_PORT_TYPE_M 3735#define DSAF_SW_PORT_TYPE_S 0736 737#define DSAF_STP_PORT_TYPE_M 7738#define DSAF_STP_PORT_TYPE_S 0739 740#define DSAF_INODE_IN_PORT_NUM_M 7741#define DSAF_INODE_IN_PORT_NUM_S 0742#define DSAFV2_INODE_IN_PORT1_NUM_M (7ULL << 3)743#define DSAFV2_INODE_IN_PORT1_NUM_S 3744#define DSAFV2_INODE_IN_PORT2_NUM_M (7ULL << 6)745#define DSAFV2_INODE_IN_PORT2_NUM_S 6746#define DSAFV2_INODE_IN_PORT3_NUM_M (7ULL << 9)747#define DSAFV2_INODE_IN_PORT3_NUM_S 9748#define DSAFV2_INODE_IN_PORT4_NUM_M (7ULL << 12)749#define DSAFV2_INODE_IN_PORT4_NUM_S 12750#define DSAFV2_INODE_IN_PORT5_NUM_M (7ULL << 15)751#define DSAFV2_INODE_IN_PORT5_NUM_S 15752 753#define HNS_DSAF_I4TC_CFG 0x18688688754#define HNS_DSAF_I8TC_CFG 0x18FAC688755 756#define DSAF_SBM_CFG_SHCUT_EN_S 0757#define DSAF_SBM_CFG_EN_S 1758#define DSAF_SBM_CFG_MIB_EN_S 2759#define DSAF_SBM_CFG_ECC_INVERT_EN_S 3760 761#define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S 0762#define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0)763#define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S 10764#define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10)765#define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S 20766#define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 11) - 1) << 20)767 768#define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S 0769#define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0)770#define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S 10771#define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10)772 773#define DSAF_SBM_CFG2_SET_BUF_NUM_S 0774#define DSAF_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 10) - 1) << 0)775#define DSAF_SBM_CFG2_RESET_BUF_NUM_S 10776#define DSAF_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 10) - 1) << 10)777 778#define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0779#define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 0)780#define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 10781#define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 10)782 783#define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S 0784#define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0)785#define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S 9786#define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9)787#define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S 18788#define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 18)789 790#define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S 0791#define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0)792#define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S 9793#define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9)794 795#define DSAFV2_SBM_CFG2_SET_BUF_NUM_S 0796#define DSAFV2_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 9) - 1) << 0)797#define DSAFV2_SBM_CFG2_RESET_BUF_NUM_S 9798#define DSAFV2_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 9) - 1) << 9)799 800#define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0801#define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0)802#define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 9803#define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9)804 805#define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S 0806#define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0)807#define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S 9808#define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9)809 810#define DSAF_CHNS_MASK 0x3f000811#define DSAF_SBM_ROCEE_CFG_CRD_EN_B 2812#define SRST_TIME_INTERVAL 20813#define DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S 0814#define DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M (((1ULL << 8) - 1) << 0)815#define DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S 8816#define DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M (((1ULL << 8) - 1) << 8)817 818#define DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S (0)819#define DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M (((1ULL << 6) - 1) << 0)820#define DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S (6)821#define DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M (((1ULL << 6) - 1) << 6)822#define DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S (12)823#define DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M (((1ULL << 6) - 1) << 12)824 825#define DSAF_TBL_TCAM_ADDR_S 0826#define DSAF_TBL_TCAM_ADDR_M ((1ULL << 9) - 1)827 828#define DSAF_TBL_LINE_ADDR_S 0829#define DSAF_TBL_LINE_ADDR_M ((1ULL << 15) - 1)830 831#define DSAF_TBL_MCAST_CFG4_VM128_112_S 0832#define DSAF_TBL_MCAST_CFG4_VM128_112_M (((1ULL << 7) - 1) << 0)833#define DSAF_TBL_MCAST_CFG4_ITEM_VLD_S 7834#define DSAF_TBL_MCAST_CFG4_OLD_EN_S 8835 836#define DSAF_TBL_MCAST_CFG0_XGE5_0_S 0837#define DSAF_TBL_MCAST_CFG0_XGE5_0_M (((1ULL << 6) - 1) << 0)838#define DSAF_TBL_MCAST_CFG0_VM25_0_S 6839#define DSAF_TBL_MCAST_CFG0_VM25_0_M (((1ULL << 26) - 1) << 6)840 841#define DSAF_TBL_UCAST_CFG1_OUT_PORT_S 0842#define DSAF_TBL_UCAST_CFG1_OUT_PORT_M (((1ULL << 8) - 1) << 0)843#define DSAF_TBL_UCAST_CFG1_DVC_S 8844#define DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S 9845#define DSAF_TBL_UCAST_CFG1_ITEM_VLD_S 10846#define DSAF_TBL_UCAST_CFG1_OLD_EN_S 11847 848#define DSAF_TBL_LINE_CFG_OUT_PORT_S 0849#define DSAF_TBL_LINE_CFG_OUT_PORT_M (((1ULL << 8) - 1) << 0)850#define DSAF_TBL_LINE_CFG_DVC_S 8851#define DSAF_TBL_LINE_CFG_MAC_DISCARD_S 9852 853#define DSAF_TBL_PUL_OLD_RSLT_RE_S 0854#define DSAF_TBL_PUL_MCAST_VLD_S 1855#define DSAF_TBL_PUL_TCAM_DATA_VLD_S 2856#define DSAF_TBL_PUL_UCAST_VLD_S 3857#define DSAF_TBL_PUL_LINE_VLD_S 4858#define DSAF_TBL_PUL_TCAM_LOAD_S 5859#define DSAF_TBL_PUL_LINE_LOAD_S 6860 861#define DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S 0862#define DSAF_TBL_DFX_UC_LKUP_NUM_EN_S 1863#define DSAF_TBL_DFX_MC_LKUP_NUM_EN_S 2864#define DSAF_TBL_DFX_BC_LKUP_NUM_EN_S 3865#define DSAF_TBL_DFX_RAM_ERR_INJECT_EN_S 4866 867#define DSAF_VOQ_BP_ALL_DOWNTHRD_S 0868#define DSAF_VOQ_BP_ALL_DOWNTHRD_M (((1ULL << 10) - 1) << 0)869#define DSAF_VOQ_BP_ALL_UPTHRD_S 10870#define DSAF_VOQ_BP_ALL_UPTHRD_M (((1ULL << 10) - 1) << 10)871 872#define DSAF_XGE_GE_WORK_MODE_S 0873#define DSAF_XGE_GE_LOOPBACK_S 1874 875#define DSAF_FC_XGE_TX_PAUSE_S 0876#define DSAF_REGS_XGE_CNT_CAR_S 1877 878#define PPE_CFG_QID_MODE_DEF_QID_S 0879#define PPE_CFG_QID_MODE_DEF_QID_M (0xff << PPE_CFG_QID_MODE_DEF_QID_S)880 881#define PPE_CFG_QID_MODE_CF_QID_MODE_S 8882#define PPE_CFG_QID_MODE_CF_QID_MODE_M (0x7 << PPE_CFG_QID_MODE_CF_QID_MODE_S)883 884#define PPEV2_CFG_RSS_TBL_4N0_S 0885#define PPEV2_CFG_RSS_TBL_4N0_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N0_S)886 887#define PPEV2_CFG_RSS_TBL_4N1_S 8888#define PPEV2_CFG_RSS_TBL_4N1_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N1_S)889 890#define PPEV2_CFG_RSS_TBL_4N2_S 16891#define PPEV2_CFG_RSS_TBL_4N2_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N2_S)892 893#define PPEV2_CFG_RSS_TBL_4N3_S 24894#define PPEV2_CFG_RSS_TBL_4N3_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N3_S)895 896#define DSAFV2_SERDES_LBK_EN_B 8897#define DSAFV2_SERDES_LBK_QID_S 0898#define DSAFV2_SERDES_LBK_QID_M (((1UL << 8) - 1) << DSAFV2_SERDES_LBK_QID_S)899 900#define PPE_CNT_CLR_CE_B 0901#define PPE_CNT_CLR_SNAP_EN_B 1902 903#define PPE_INT_GAPTIME_B 0904#define PPE_INT_GAPTIME_M 0x3ff905 906#define PPE_COMMON_CNT_CLR_CE_B 0907#define PPE_COMMON_CNT_CLR_SNAP_EN_B 1908#define RCB_COM_TSO_MODE_B 0909#define RCB_COM_CFG_FNA_B 1910#define RCB_COM_CFG_FA_B 0911 912#define GMAC_DUPLEX_TYPE_B 0913 914#define GMAC_TX_WATER_LINE_MASK ((1UL << 8) - 1)915#define GMAC_TX_WATER_LINE_SHIFT 0916 917#define GMAC_FC_TX_TIMER_S 0918#define GMAC_FC_TX_TIMER_M 0xffff919 920#define GMAC_MAX_FRM_SIZE_S 0921#define GMAC_MAX_FRM_SIZE_M 0xffff922 923#define GMAC_PORT_MODE_S 0924#define GMAC_PORT_MODE_M 0xf925 926#define GMAC_RGMII_1000M_DELAY_B 4927#define GMAC_MII_TX_EDGE_SEL_B 5928#define GMAC_FIFO_ERR_AUTO_RST_B 6929#define GMAC_DBG_CLK_LOS_MSK_B 7930 931#define GMAC_PORT_RX_EN_B 1932#define GMAC_PORT_TX_EN_B 2933 934#define GMAC_PAUSE_EN_RX_FDFC_B 0935#define GMAC_PAUSE_EN_TX_FDFC_B 1936#define GMAC_PAUSE_EN_TX_HDFC_B 2937 938#define GMAC_SHORT_RUNTS_THR_S 0939#define GMAC_SHORT_RUNTS_THR_M 0x1f940 941#define GMAC_AN_NEG_STAT_FD_B 5942#define GMAC_AN_NEG_STAT_HD_B 6943#define GMAC_AN_NEG_STAT_RF1_DUPLIEX_B 12944#define GMAC_AN_NEG_STAT_RF2_B 13945 946#define GMAC_AN_NEG_STAT_NP_LNK_OK_B 15947#define GMAC_AN_NEG_STAT_RX_SYNC_OK_B 20948#define GMAC_AN_NEG_STAT_AN_DONE_B 21949 950#define GMAC_AN_NEG_STAT_PS_S 7951#define GMAC_AN_NEG_STAT_PS_M (0x3 << GMAC_AN_NEG_STAT_PS_S)952 953#define GMAC_AN_NEG_STAT_SPEED_S 10954#define GMAC_AN_NEG_STAT_SPEED_M (0x3 << GMAC_AN_NEG_STAT_SPEED_S)955 956#define GMAC_TX_AN_EN_B 5957#define GMAC_TX_CRC_ADD_B 6958#define GMAC_TX_PAD_EN_B 7959 960#define GMAC_LINE_LOOPBACK_B 0961 962#define GMAC_LP_REG_CF_EXT_DRV_LP_B 1963#define GMAC_LP_REG_CF2MI_LP_EN_B 2964 965#define GMAC_MODE_CHANGE_EB_B 0966#define GMAC_UC_MATCH_EN_B 0967#define GMAC_ADDR_EN_B 16968 969#define GMAC_RECV_CTRL_STRIP_PAD_EN_B 3970#define GMAC_RECV_CTRL_RUNT_PKT_EN_B 4971 972#define GMAC_TX_LOOP_PKT_HIG_PRI_B 0973#define GMAC_TX_LOOP_PKT_EN_B 1974 975#define XGMAC_PORT_MODE_TX_S 0x0976#define XGMAC_PORT_MODE_TX_M (0x3 << XGMAC_PORT_MODE_TX_S)977#define XGMAC_PORT_MODE_TX_40G_B 0x3978#define XGMAC_PORT_MODE_RX_S 0x4979#define XGMAC_PORT_MODE_RX_M (0x3 << XGMAC_PORT_MODE_RX_S)980#define XGMAC_PORT_MODE_RX_40G_B 0x7981 982#define XGMAC_ENABLE_TX_B 0983#define XGMAC_ENABLE_RX_B 1984 985#define XGMAC_UNIDIR_EN_B 0986#define XGMAC_RF_TX_EN_B 1987#define XGMAC_LF_RF_INSERT_S 2988#define XGMAC_LF_RF_INSERT_M (0x3 << XGMAC_LF_RF_INSERT_S)989 990#define XGMAC_CTL_TX_FCS_B 0991#define XGMAC_CTL_TX_PAD_B 1992#define XGMAC_CTL_TX_PREAMBLE_TRANS_B 3993#define XGMAC_CTL_TX_UNDER_MIN_ERR_B 4994#define XGMAC_CTL_TX_TRUNCATE_B 5995#define XGMAC_CTL_TX_1588_B 8996#define XGMAC_CTL_TX_1731_B 9997#define XGMAC_CTL_TX_PFC_B 10998#define XGMAC_CTL_RX_FCS_B 16999#define XGMAC_CTL_RX_FCS_STRIP_B 171000#define XGMAC_CTL_RX_PREAMBLE_TRANS_B 191001#define XGMAC_CTL_RX_UNDER_MIN_ERR_B 201002#define XGMAC_CTL_RX_TRUNCATE_B 211003#define XGMAC_CTL_RX_1588_B 241004#define XGMAC_CTL_RX_1731_B 251005#define XGMAC_CTL_RX_PFC_B 261006 1007#define XGMAC_PMA_FEC_CTL_TX_B 01008#define XGMAC_PMA_FEC_CTL_RX_B 11009#define XGMAC_PMA_FEC_CTL_ERR_EN 21010#define XGMAC_PMA_FEC_CTL_ERR_SH 31011 1012#define XGMAC_PAUSE_CTL_TX_B 01013#define XGMAC_PAUSE_CTL_RX_B 11014#define XGMAC_PAUSE_CTL_RSP_MODE_B 21015#define XGMAC_PAUSE_CTL_TX_XOFF_B 31016 1017static inline void dsaf_write_reg(u8 __iomem *base, u32 reg, u32 value)1018{1019 writel(value, base + reg);1020}1021 1022#define dsaf_write_dev(a, reg, value) \1023 dsaf_write_reg((a)->io_base, (reg), (value))1024 1025static inline u32 dsaf_read_reg(u8 __iomem *base, u32 reg)1026{1027 return readl(base + reg);1028}1029 1030static inline void dsaf_write_syscon(struct regmap *base, u32 reg, u32 value)1031{1032 regmap_write(base, reg, value);1033}1034 1035static inline int dsaf_read_syscon(struct regmap *base, u32 reg, u32 *val)1036{1037 return regmap_read(base, reg, val);1038}1039 1040#define dsaf_read_dev(a, reg) \1041 dsaf_read_reg((a)->io_base, (reg))1042 1043#define dsaf_set_field(origin, mask, shift, val) \1044 do { \1045 (origin) &= (~(mask)); \1046 (origin) |= (((val) << (shift)) & (mask)); \1047 } while (0)1048 1049#define dsaf_set_bit(origin, shift, val) \1050 dsaf_set_field((origin), (1ull << (shift)), (shift), (val))1051 1052static inline void dsaf_set_reg_field(u8 __iomem *base, u32 reg, u32 mask,1053 u32 shift, u32 val)1054{1055 u32 origin = dsaf_read_reg(base, reg);1056 1057 dsaf_set_field(origin, mask, shift, val);1058 dsaf_write_reg(base, reg, origin);1059}1060 1061#define dsaf_set_dev_field(dev, reg, mask, shift, val) \1062 dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val))1063 1064#define dsaf_set_dev_bit(dev, reg, bit, val) \1065 dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val))1066 1067#define dsaf_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))1068 1069#define dsaf_get_bit(origin, shift) \1070 dsaf_get_field((origin), (1ull << (shift)), (shift))1071 1072static inline u32 dsaf_get_reg_field(u8 __iomem *base, u32 reg, u32 mask,1073 u32 shift)1074{1075 u32 origin;1076 1077 origin = dsaf_read_reg(base, reg);1078 return dsaf_get_field(origin, mask, shift);1079}1080 1081#define dsaf_get_dev_field(dev, reg, mask, shift) \1082 dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift))1083 1084#define dsaf_get_dev_bit(dev, reg, bit) \1085 dsaf_get_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit))1086 1087#define dsaf_write_b(addr, data)\1088 writeb((data), (__iomem u8 *)(addr))1089#define dsaf_read_b(addr)\1090 readb((__iomem u8 *)(addr))1091 1092#define hns_mac_reg_read64(drv, offset) \1093 readq((__iomem void *)(((drv)->io_base + 0xc00 + (offset))))1094 1095#endif /* _DSAF_REG_H */1096