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1/* SPDX-License-Identifier: GPL-2.0+ */2// Copyright (c) 2016-2017 Hisilicon Limited.3 4#ifndef __HNAE3_H5#define __HNAE3_H6 7/* Names used in this framework:8 * ae handle (handle):9 * a set of queues provided by AE10 * ring buffer queue (rbq):11 * the channel between upper layer and the AE, can do tx and rx12 * ring:13 * a tx or rx channel within a rbq14 * ring description (desc):15 * an element in the ring with packet information16 * buffer:17 * a memory region referred by desc with the full packet payload18 *19 * "num" means a static number set as a parameter, "count" mean a dynamic20 * number set while running21 * "cb" means control block22 */23 24#include <linux/acpi.h>25#include <linux/dcbnl.h>26#include <linux/delay.h>27#include <linux/device.h>28#include <linux/ethtool.h>29#include <linux/module.h>30#include <linux/netdevice.h>31#include <linux/pci.h>32#include <linux/pkt_sched.h>33#include <linux/types.h>34#include <linux/bitmap.h>35#include <net/pkt_cls.h>36#include <net/pkt_sched.h>37 38#define HNAE3_MOD_VERSION "1.0"39 40#define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */41 42/* Device version */43#define HNAE3_DEVICE_VERSION_V1 0x0002044#define HNAE3_DEVICE_VERSION_V2 0x0002145#define HNAE3_DEVICE_VERSION_V3 0x0003046 47#define HNAE3_PCI_REVISION_BIT_SIZE 848 49/* Device IDs */50#define HNAE3_DEV_ID_GE 0xA22051#define HNAE3_DEV_ID_25GE 0xA22152#define HNAE3_DEV_ID_25GE_RDMA 0xA22253#define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA22354#define HNAE3_DEV_ID_50GE_RDMA 0xA22455#define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA22556#define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA22657#define HNAE3_DEV_ID_200G_RDMA 0xA22858#define HNAE3_DEV_ID_VF 0xA22E59#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F60 61#define HNAE3_CLASS_NAME_SIZE 1662 63#define HNAE3_DEV_INITED_B 0x064#define HNAE3_DEV_SUPPORT_ROCE_B 0x165#define HNAE3_DEV_SUPPORT_DCB_B 0x266#define HNAE3_KNIC_CLIENT_INITED_B 0x367#define HNAE3_UNIC_CLIENT_INITED_B 0x468#define HNAE3_ROCE_CLIENT_INITED_B 0x569 70#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \71 BIT(HNAE3_DEV_SUPPORT_ROCE_B))72 73#define hnae3_dev_roce_supported(hdev) \74 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)75 76#define hnae3_dev_dcb_supported(hdev) \77 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)78 79enum HNAE3_DEV_CAP_BITS {80 HNAE3_DEV_SUPPORT_FD_B,81 HNAE3_DEV_SUPPORT_GRO_B,82 HNAE3_DEV_SUPPORT_FEC_B,83 HNAE3_DEV_SUPPORT_UDP_GSO_B,84 HNAE3_DEV_SUPPORT_QB_B,85 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,86 HNAE3_DEV_SUPPORT_PTP_B,87 HNAE3_DEV_SUPPORT_INT_QL_B,88 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,89 HNAE3_DEV_SUPPORT_TX_PUSH_B,90 HNAE3_DEV_SUPPORT_PHY_IMP_B,91 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,92 HNAE3_DEV_SUPPORT_HW_PAD_B,93 HNAE3_DEV_SUPPORT_STASH_B,94 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,95 HNAE3_DEV_SUPPORT_PAUSE_B,96 HNAE3_DEV_SUPPORT_RAS_IMP_B,97 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,98 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,99 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,100 HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,101 HNAE3_DEV_SUPPORT_CQ_B,102 HNAE3_DEV_SUPPORT_FEC_STATS_B,103 HNAE3_DEV_SUPPORT_LANE_NUM_B,104 HNAE3_DEV_SUPPORT_WOL_B,105 HNAE3_DEV_SUPPORT_TM_FLUSH_B,106 HNAE3_DEV_SUPPORT_VF_FAULT_B,107 HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B,108};109 110#define hnae3_ae_dev_fd_supported(ae_dev) \111 test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)112 113#define hnae3_ae_dev_gro_supported(ae_dev) \114 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps)115 116#define hnae3_dev_fec_supported(hdev) \117 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)118 119#define hnae3_dev_udp_gso_supported(hdev) \120 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)121 122#define hnae3_dev_qb_supported(hdev) \123 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)124 125#define hnae3_dev_fd_forward_tc_supported(hdev) \126 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)127 128#define hnae3_dev_ptp_supported(hdev) \129 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)130 131#define hnae3_dev_int_ql_supported(hdev) \132 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)133 134#define hnae3_dev_hw_csum_supported(hdev) \135 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)136 137#define hnae3_dev_tx_push_supported(hdev) \138 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)139 140#define hnae3_dev_phy_imp_supported(hdev) \141 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)142 143#define hnae3_dev_ras_imp_supported(hdev) \144 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)145 146#define hnae3_dev_tqp_txrx_indep_supported(hdev) \147 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)148 149#define hnae3_dev_hw_pad_supported(hdev) \150 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)151 152#define hnae3_dev_stash_supported(hdev) \153 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)154 155#define hnae3_dev_pause_supported(hdev) \156 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)157 158#define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \159 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)160 161#define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \162 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)163 164#define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \165 test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)166 167#define hnae3_ae_dev_cq_supported(ae_dev) \168 test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)169 170#define hnae3_ae_dev_fec_stats_supported(ae_dev) \171 test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)172 173#define hnae3_ae_dev_lane_num_supported(ae_dev) \174 test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)175 176#define hnae3_ae_dev_wol_supported(ae_dev) \177 test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps)178 179#define hnae3_ae_dev_tm_flush_supported(hdev) \180 test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps)181 182#define hnae3_ae_dev_vf_fault_supported(ae_dev) \183 test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps)184 185#define hnae3_ae_dev_gen_reg_dfx_supported(hdev) \186 test_bit(HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, (hdev)->ae_dev->caps)187 188enum HNAE3_PF_CAP_BITS {189 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,190};191#define ring_ptr_move_fw(ring, p) \192 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)193#define ring_ptr_move_bw(ring, p) \194 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)195 196struct hnae3_handle;197 198struct hnae3_queue {199 void __iomem *io_base;200 void __iomem *mem_base;201 struct hnae3_ae_algo *ae_algo;202 struct hnae3_handle *handle;203 int tqp_index; /* index in a handle */204 u32 buf_size; /* size for hnae_desc->addr, preset by AE */205 u16 tx_desc_num; /* total number of tx desc */206 u16 rx_desc_num; /* total number of rx desc */207};208 209struct hns3_mac_stats {210 u64 tx_pause_cnt;211 u64 rx_pause_cnt;212};213 214/* hnae3 loop mode */215enum hnae3_loop {216 HNAE3_LOOP_EXTERNAL,217 HNAE3_LOOP_APP,218 HNAE3_LOOP_SERIAL_SERDES,219 HNAE3_LOOP_PARALLEL_SERDES,220 HNAE3_LOOP_PHY,221 HNAE3_LOOP_NONE,222};223 224enum hnae3_client_type {225 HNAE3_CLIENT_KNIC,226 HNAE3_CLIENT_ROCE,227};228 229/* mac media type */230enum hnae3_media_type {231 HNAE3_MEDIA_TYPE_UNKNOWN,232 HNAE3_MEDIA_TYPE_FIBER,233 HNAE3_MEDIA_TYPE_COPPER,234 HNAE3_MEDIA_TYPE_BACKPLANE,235 HNAE3_MEDIA_TYPE_NONE,236};237 238/* must be consistent with definition in firmware */239enum hnae3_module_type {240 HNAE3_MODULE_TYPE_UNKNOWN = 0x00,241 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01,242 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02,243 HNAE3_MODULE_TYPE_AOC = 0x03,244 HNAE3_MODULE_TYPE_CR = 0x04,245 HNAE3_MODULE_TYPE_KR = 0x05,246 HNAE3_MODULE_TYPE_TP = 0x06,247};248 249enum hnae3_fec_mode {250 HNAE3_FEC_AUTO = 0,251 HNAE3_FEC_BASER,252 HNAE3_FEC_RS,253 HNAE3_FEC_LLRS,254 HNAE3_FEC_NONE,255 HNAE3_FEC_USER_DEF,256};257 258enum hnae3_reset_notify_type {259 HNAE3_UP_CLIENT,260 HNAE3_DOWN_CLIENT,261 HNAE3_INIT_CLIENT,262 HNAE3_UNINIT_CLIENT,263};264 265enum hnae3_hw_error_type {266 HNAE3_PPU_POISON_ERROR,267 HNAE3_CMDQ_ECC_ERROR,268 HNAE3_IMP_RD_POISON_ERROR,269 HNAE3_ROCEE_AXI_RESP_ERROR,270};271 272enum hnae3_reset_type {273 HNAE3_VF_RESET,274 HNAE3_VF_FUNC_RESET,275 HNAE3_VF_PF_FUNC_RESET,276 HNAE3_VF_FULL_RESET,277 HNAE3_FLR_RESET,278 HNAE3_FUNC_RESET,279 HNAE3_GLOBAL_RESET,280 HNAE3_IMP_RESET,281 HNAE3_NONE_RESET,282 HNAE3_VF_EXP_RESET,283 HNAE3_MAX_RESET,284};285 286enum hnae3_port_base_vlan_state {287 HNAE3_PORT_BASE_VLAN_DISABLE,288 HNAE3_PORT_BASE_VLAN_ENABLE,289 HNAE3_PORT_BASE_VLAN_MODIFY,290 HNAE3_PORT_BASE_VLAN_NOCHANGE,291};292 293enum hnae3_dbg_cmd {294 HNAE3_DBG_CMD_TM_NODES,295 HNAE3_DBG_CMD_TM_PRI,296 HNAE3_DBG_CMD_TM_QSET,297 HNAE3_DBG_CMD_TM_MAP,298 HNAE3_DBG_CMD_TM_PG,299 HNAE3_DBG_CMD_TM_PORT,300 HNAE3_DBG_CMD_TC_SCH_INFO,301 HNAE3_DBG_CMD_QOS_PAUSE_CFG,302 HNAE3_DBG_CMD_QOS_PRI_MAP,303 HNAE3_DBG_CMD_QOS_DSCP_MAP,304 HNAE3_DBG_CMD_QOS_BUF_CFG,305 HNAE3_DBG_CMD_DEV_INFO,306 HNAE3_DBG_CMD_TX_BD,307 HNAE3_DBG_CMD_RX_BD,308 HNAE3_DBG_CMD_MAC_UC,309 HNAE3_DBG_CMD_MAC_MC,310 HNAE3_DBG_CMD_MNG_TBL,311 HNAE3_DBG_CMD_LOOPBACK,312 HNAE3_DBG_CMD_PTP_INFO,313 HNAE3_DBG_CMD_INTERRUPT_INFO,314 HNAE3_DBG_CMD_RESET_INFO,315 HNAE3_DBG_CMD_IMP_INFO,316 HNAE3_DBG_CMD_NCL_CONFIG,317 HNAE3_DBG_CMD_REG_BIOS_COMMON,318 HNAE3_DBG_CMD_REG_SSU,319 HNAE3_DBG_CMD_REG_IGU_EGU,320 HNAE3_DBG_CMD_REG_RPU,321 HNAE3_DBG_CMD_REG_NCSI,322 HNAE3_DBG_CMD_REG_RTC,323 HNAE3_DBG_CMD_REG_PPP,324 HNAE3_DBG_CMD_REG_RCB,325 HNAE3_DBG_CMD_REG_TQP,326 HNAE3_DBG_CMD_REG_MAC,327 HNAE3_DBG_CMD_REG_DCB,328 HNAE3_DBG_CMD_VLAN_CONFIG,329 HNAE3_DBG_CMD_QUEUE_MAP,330 HNAE3_DBG_CMD_RX_QUEUE_INFO,331 HNAE3_DBG_CMD_TX_QUEUE_INFO,332 HNAE3_DBG_CMD_FD_TCAM,333 HNAE3_DBG_CMD_FD_COUNTER,334 HNAE3_DBG_CMD_MAC_TNL_STATUS,335 HNAE3_DBG_CMD_SERV_INFO,336 HNAE3_DBG_CMD_UMV_INFO,337 HNAE3_DBG_CMD_PAGE_POOL_INFO,338 HNAE3_DBG_CMD_COAL_INFO,339 HNAE3_DBG_CMD_UNKNOWN,340};341 342enum hnae3_tc_map_mode {343 HNAE3_TC_MAP_MODE_PRIO,344 HNAE3_TC_MAP_MODE_DSCP,345};346 347struct hnae3_vector_info {348 u8 __iomem *io_addr;349 int vector;350};351 352#define HNAE3_RING_TYPE_B 0353#define HNAE3_RING_TYPE_TX 0354#define HNAE3_RING_TYPE_RX 1355#define HNAE3_RING_GL_IDX_S 0356#define HNAE3_RING_GL_IDX_M GENMASK(1, 0)357#define HNAE3_RING_GL_RX 0358#define HNAE3_RING_GL_TX 1359 360#define HNAE3_FW_VERSION_BYTE3_SHIFT 24361#define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)362#define HNAE3_FW_VERSION_BYTE2_SHIFT 16363#define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)364#define HNAE3_FW_VERSION_BYTE1_SHIFT 8365#define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)366#define HNAE3_FW_VERSION_BYTE0_SHIFT 0367#define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)368 369#define HNAE3_SCC_VERSION_BYTE3_SHIFT 24370#define HNAE3_SCC_VERSION_BYTE3_MASK GENMASK(31, 24)371#define HNAE3_SCC_VERSION_BYTE2_SHIFT 16372#define HNAE3_SCC_VERSION_BYTE2_MASK GENMASK(23, 16)373#define HNAE3_SCC_VERSION_BYTE1_SHIFT 8374#define HNAE3_SCC_VERSION_BYTE1_MASK GENMASK(15, 8)375#define HNAE3_SCC_VERSION_BYTE0_SHIFT 0376#define HNAE3_SCC_VERSION_BYTE0_MASK GENMASK(7, 0)377 378struct hnae3_ring_chain_node {379 struct hnae3_ring_chain_node *next;380 u32 tqp_index;381 u32 flag;382 u32 int_gl_idx;383};384 385#define HNAE3_IS_TX_RING(node) \386 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)387 388/* device specification info from firmware */389struct hnae3_dev_specs {390 u32 mac_entry_num; /* number of mac-vlan table entry */391 u32 mng_entry_num; /* number of manager table entry */392 u32 max_tm_rate;393 u16 rss_ind_tbl_size;394 u16 rss_key_size;395 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */396 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */397 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */398 u16 max_frm_size;399 u16 max_qset_num;400 u16 umv_size;401 u16 mc_mac_size;402 u32 mac_stats_num;403 u8 tnl_num;404 u8 hilink_version;405};406 407struct hnae3_client_ops {408 int (*init_instance)(struct hnae3_handle *handle);409 void (*uninit_instance)(struct hnae3_handle *handle, bool reset);410 void (*link_status_change)(struct hnae3_handle *handle, bool state);411 int (*reset_notify)(struct hnae3_handle *handle,412 enum hnae3_reset_notify_type type);413 void (*process_hw_error)(struct hnae3_handle *handle,414 enum hnae3_hw_error_type);415};416 417#define HNAE3_CLIENT_NAME_LENGTH 16418struct hnae3_client {419 char name[HNAE3_CLIENT_NAME_LENGTH];420 unsigned long state;421 enum hnae3_client_type type;422 const struct hnae3_client_ops *ops;423 struct list_head node;424};425 426#define HNAE3_DEV_CAPS_MAX_NUM 96427struct hnae3_ae_dev {428 struct pci_dev *pdev;429 const struct hnae3_ae_ops *ops;430 struct list_head node;431 u32 flag;432 unsigned long hw_err_reset_req;433 struct hnae3_dev_specs dev_specs;434 u32 dev_version;435 DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM);436 void *priv;437};438 439/* This struct defines the operation on the handle.440 *441 * init_ae_dev(): (mandatory)442 * Get PF configure from pci_dev and initialize PF hardware443 * uninit_ae_dev()444 * Disable PF device and release PF resource445 * register_client446 * Register client to ae_dev447 * unregister_client()448 * Unregister client from ae_dev449 * start()450 * Enable the hardware451 * stop()452 * Disable the hardware453 * start_client()454 * Inform the hclge that client has been started455 * stop_client()456 * Inform the hclge that client has been stopped457 * get_status()458 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for459 * non-ok460 * get_ksettings_an_result()461 * Get negotiation status,speed and duplex462 * get_media_type()463 * Get media type of MAC464 * check_port_speed()465 * Check target speed whether is supported466 * adjust_link()467 * Adjust link status468 * set_loopback()469 * Set loopback470 * set_promisc_mode471 * Set promisc mode472 * request_update_promisc_mode473 * request to hclge(vf) to update promisc mode474 * set_mtu()475 * set mtu476 * get_pauseparam()477 * get tx and rx of pause frame use478 * set_pauseparam()479 * set tx and rx of pause frame use480 * set_autoneg()481 * set auto autonegotiation of pause frame use482 * get_autoneg()483 * get auto autonegotiation of pause frame use484 * restart_autoneg()485 * restart autonegotiation486 * halt_autoneg()487 * halt/resume autonegotiation when autonegotiation on488 * get_coalesce_usecs()489 * get usecs to delay a TX interrupt after a packet is sent490 * get_rx_max_coalesced_frames()491 * get Maximum number of packets to be sent before a TX interrupt.492 * set_coalesce_usecs()493 * set usecs to delay a TX interrupt after a packet is sent494 * set_coalesce_frames()495 * set Maximum number of packets to be sent before a TX interrupt.496 * get_mac_addr()497 * get mac address498 * set_mac_addr()499 * set mac address500 * add_uc_addr501 * Add unicast addr to mac table502 * rm_uc_addr503 * Remove unicast addr from mac table504 * set_mc_addr()505 * Set multicast address506 * add_mc_addr507 * Add multicast address to mac table508 * rm_mc_addr509 * Remove multicast address from mac table510 * update_stats()511 * Update Old network device statistics512 * get_mac_stats()513 * get mac pause statistics including tx_cnt and rx_cnt514 * get_ethtool_stats()515 * Get ethtool network device statistics516 * get_strings()517 * Get a set of strings that describe the requested objects518 * get_sset_count()519 * Get number of strings that @get_strings will write520 * update_led_status()521 * Update the led status522 * set_led_id()523 * Set led id524 * get_regs()525 * Get regs dump526 * get_regs_len()527 * Get the len of the regs dump528 * get_rss_key_size()529 * Get rss key size530 * get_rss()531 * Get rss table532 * set_rss()533 * Set rss table534 * get_tc_size()535 * Get tc size of handle536 * get_vector()537 * Get vector number and vector information538 * put_vector()539 * Put the vector in hdev540 * map_ring_to_vector()541 * Map rings to vector542 * unmap_ring_from_vector()543 * Unmap rings from vector544 * reset_queue()545 * Reset queue546 * get_fw_version()547 * Get firmware version548 * get_mdix_mode()549 * Get media typr of phy550 * enable_vlan_filter()551 * Enable vlan filter552 * set_vlan_filter()553 * Set vlan filter config of Ports554 * set_vf_vlan_filter()555 * Set vlan filter config of vf556 * enable_hw_strip_rxvtag()557 * Enable/disable hardware strip vlan tag of packets received558 * set_gro_en559 * Enable/disable HW GRO560 * add_arfs_entry561 * Check the 5-tuples of flow, and create flow director rule562 * get_vf_config563 * Get the VF configuration setting by the host564 * set_vf_link_state565 * Set VF link status566 * set_vf_spoofchk567 * Enable/disable spoof check for specified vf568 * set_vf_trust569 * Enable/disable trust for specified vf, if the vf being trusted, then570 * it can enable promisc mode571 * set_vf_rate572 * Set the max tx rate of specified vf.573 * set_vf_mac574 * Configure the default MAC for specified VF575 * get_module_eeprom576 * Get the optical module eeprom info.577 * add_cls_flower578 * Add clsflower rule579 * del_cls_flower580 * Delete clsflower rule581 * cls_flower_active582 * Check if any cls flower rule exist583 * dbg_read_cmd584 * Execute debugfs read command.585 * set_tx_hwts_info586 * Save information for 1588 tx packet587 * get_rx_hwts588 * Get 1588 rx hwstamp589 * get_ts_info590 * Get phc info591 * clean_vf_config592 * Clean residual vf info after disable sriov593 * get_wol594 * Get wake on lan info595 * set_wol596 * Config wake on lan597 */598struct hnae3_ae_ops {599 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);600 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);601 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,602 enum hnae3_reset_type rst_type);603 void (*reset_done)(struct hnae3_ae_dev *ae_dev);604 int (*init_client_instance)(struct hnae3_client *client,605 struct hnae3_ae_dev *ae_dev);606 void (*uninit_client_instance)(struct hnae3_client *client,607 struct hnae3_ae_dev *ae_dev);608 int (*start)(struct hnae3_handle *handle);609 void (*stop)(struct hnae3_handle *handle);610 int (*client_start)(struct hnae3_handle *handle);611 void (*client_stop)(struct hnae3_handle *handle);612 int (*get_status)(struct hnae3_handle *handle);613 void (*get_ksettings_an_result)(struct hnae3_handle *handle,614 u8 *auto_neg, u32 *speed, u8 *duplex,615 u32 *lane_num);616 617 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,618 u8 duplex, u8 lane_num);619 620 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,621 u8 *module_type);622 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);623 void (*get_fec_stats)(struct hnae3_handle *handle,624 struct ethtool_fec_stats *fec_stats);625 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,626 u8 *fec_mode);627 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);628 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);629 int (*set_loopback)(struct hnae3_handle *handle,630 enum hnae3_loop loop_mode, bool en);631 632 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,633 bool en_mc_pmc);634 void (*request_update_promisc_mode)(struct hnae3_handle *handle);635 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);636 637 void (*get_pauseparam)(struct hnae3_handle *handle,638 u32 *auto_neg, u32 *rx_en, u32 *tx_en);639 int (*set_pauseparam)(struct hnae3_handle *handle,640 u32 auto_neg, u32 rx_en, u32 tx_en);641 642 int (*set_autoneg)(struct hnae3_handle *handle, bool enable);643 int (*get_autoneg)(struct hnae3_handle *handle);644 int (*restart_autoneg)(struct hnae3_handle *handle);645 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);646 647 void (*get_coalesce_usecs)(struct hnae3_handle *handle,648 u32 *tx_usecs, u32 *rx_usecs);649 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,650 u32 *tx_frames, u32 *rx_frames);651 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);652 int (*set_coalesce_frames)(struct hnae3_handle *handle,653 u32 coalesce_frames);654 void (*get_coalesce_range)(struct hnae3_handle *handle,655 u32 *tx_frames_low, u32 *rx_frames_low,656 u32 *tx_frames_high, u32 *rx_frames_high,657 u32 *tx_usecs_low, u32 *rx_usecs_low,658 u32 *tx_usecs_high, u32 *rx_usecs_high);659 660 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);661 int (*set_mac_addr)(struct hnae3_handle *handle, const void *p,662 bool is_first);663 int (*do_ioctl)(struct hnae3_handle *handle,664 struct ifreq *ifr, int cmd);665 int (*add_uc_addr)(struct hnae3_handle *handle,666 const unsigned char *addr);667 int (*rm_uc_addr)(struct hnae3_handle *handle,668 const unsigned char *addr);669 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);670 int (*add_mc_addr)(struct hnae3_handle *handle,671 const unsigned char *addr);672 int (*rm_mc_addr)(struct hnae3_handle *handle,673 const unsigned char *addr);674 void (*set_tso_stats)(struct hnae3_handle *handle, int enable);675 void (*update_stats)(struct hnae3_handle *handle);676 void (*get_stats)(struct hnae3_handle *handle, u64 *data);677 void (*get_mac_stats)(struct hnae3_handle *handle,678 struct hns3_mac_stats *mac_stats);679 void (*get_strings)(struct hnae3_handle *handle,680 u32 stringset, u8 *data);681 int (*get_sset_count)(struct hnae3_handle *handle, int stringset);682 683 void (*get_regs)(struct hnae3_handle *handle, u32 *version,684 void *data);685 int (*get_regs_len)(struct hnae3_handle *handle);686 687 u32 (*get_rss_key_size)(struct hnae3_handle *handle);688 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,689 u8 *hfunc);690 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,691 const u8 *key, const u8 hfunc);692 int (*set_rss_tuple)(struct hnae3_handle *handle,693 struct ethtool_rxnfc *cmd);694 int (*get_rss_tuple)(struct hnae3_handle *handle,695 struct ethtool_rxnfc *cmd);696 697 int (*get_tc_size)(struct hnae3_handle *handle);698 699 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,700 struct hnae3_vector_info *vector_info);701 int (*put_vector)(struct hnae3_handle *handle, int vector_num);702 int (*map_ring_to_vector)(struct hnae3_handle *handle,703 int vector_num,704 struct hnae3_ring_chain_node *vr_chain);705 int (*unmap_ring_from_vector)(struct hnae3_handle *handle,706 int vector_num,707 struct hnae3_ring_chain_node *vr_chain);708 709 int (*reset_queue)(struct hnae3_handle *handle);710 u32 (*get_fw_version)(struct hnae3_handle *handle);711 void (*get_mdix_mode)(struct hnae3_handle *handle,712 u8 *tp_mdix_ctrl, u8 *tp_mdix);713 714 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);715 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,716 u16 vlan_id, bool is_kill);717 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,718 u16 vlan, u8 qos, __be16 proto);719 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);720 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);721 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,722 unsigned long *addr);723 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,724 enum hnae3_reset_type rst_type);725 void (*get_channels)(struct hnae3_handle *handle,726 struct ethtool_channels *ch);727 void (*get_tqps_and_rss_info)(struct hnae3_handle *h,728 u16 *alloc_tqps, u16 *max_rss_size);729 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,730 bool rxfh_configured);731 void (*get_flowctrl_adv)(struct hnae3_handle *handle,732 u32 *flowctrl_adv);733 int (*set_led_id)(struct hnae3_handle *handle,734 enum ethtool_phys_id_state status);735 void (*get_link_mode)(struct hnae3_handle *handle,736 unsigned long *supported,737 unsigned long *advertising);738 int (*add_fd_entry)(struct hnae3_handle *handle,739 struct ethtool_rxnfc *cmd);740 int (*del_fd_entry)(struct hnae3_handle *handle,741 struct ethtool_rxnfc *cmd);742 int (*get_fd_rule_cnt)(struct hnae3_handle *handle,743 struct ethtool_rxnfc *cmd);744 int (*get_fd_rule_info)(struct hnae3_handle *handle,745 struct ethtool_rxnfc *cmd);746 int (*get_fd_all_rules)(struct hnae3_handle *handle,747 struct ethtool_rxnfc *cmd, u32 *rule_locs);748 void (*enable_fd)(struct hnae3_handle *handle, bool enable);749 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,750 u16 flow_id, struct flow_keys *fkeys);751 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,752 char *buf, int len);753 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);754 bool (*get_hw_reset_stat)(struct hnae3_handle *handle);755 bool (*ae_dev_resetting)(struct hnae3_handle *handle);756 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);757 int (*set_gro_en)(struct hnae3_handle *handle, bool enable);758 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);759 void (*set_timer_task)(struct hnae3_handle *handle, bool enable);760 int (*mac_connect_phy)(struct hnae3_handle *handle);761 void (*mac_disconnect_phy)(struct hnae3_handle *handle);762 int (*get_vf_config)(struct hnae3_handle *handle, int vf,763 struct ifla_vf_info *ivf);764 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,765 int link_state);766 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,767 bool enable);768 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);769 int (*set_vf_rate)(struct hnae3_handle *handle, int vf,770 int min_tx_rate, int max_tx_rate, bool force);771 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);772 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,773 u32 len, u8 *data);774 bool (*get_cmdq_stat)(struct hnae3_handle *handle);775 int (*add_cls_flower)(struct hnae3_handle *handle,776 struct flow_cls_offload *cls_flower, int tc);777 int (*del_cls_flower)(struct hnae3_handle *handle,778 struct flow_cls_offload *cls_flower);779 bool (*cls_flower_active)(struct hnae3_handle *handle);780 int (*get_phy_link_ksettings)(struct hnae3_handle *handle,781 struct ethtool_link_ksettings *cmd);782 int (*set_phy_link_ksettings)(struct hnae3_handle *handle,783 const struct ethtool_link_ksettings *cmd);784 bool (*set_tx_hwts_info)(struct hnae3_handle *handle,785 struct sk_buff *skb);786 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,787 u32 nsec, u32 sec);788 int (*get_ts_info)(struct hnae3_handle *handle,789 struct kernel_ethtool_ts_info *info);790 int (*get_link_diagnosis_info)(struct hnae3_handle *handle,791 u32 *status_code);792 void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);793 int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp,794 u8 *tc_map_mode, u8 *priority);795 void (*get_wol)(struct hnae3_handle *handle,796 struct ethtool_wolinfo *wol);797 int (*set_wol)(struct hnae3_handle *handle,798 struct ethtool_wolinfo *wol);799};800 801struct hnae3_dcb_ops {802 /* IEEE 802.1Qaz std */803 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);804 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);805 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);806 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);807 int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app);808 int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app);809 810 /* DCBX configuration */811 u8 (*getdcbx)(struct hnae3_handle *);812 u8 (*setdcbx)(struct hnae3_handle *, u8);813 814 int (*setup_tc)(struct hnae3_handle *handle,815 struct tc_mqprio_qopt_offload *mqprio_qopt);816};817 818struct hnae3_ae_algo {819 const struct hnae3_ae_ops *ops;820 struct list_head node;821 const struct pci_device_id *pdev_id_table;822};823 824#define HNAE3_INT_NAME_LEN 32825#define HNAE3_ITR_COUNTDOWN_START 100826 827#define HNAE3_MAX_TC 8828#define HNAE3_MAX_USER_PRIO 8829struct hnae3_tc_info {830 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */831 u16 tqp_count[HNAE3_MAX_TC];832 u16 tqp_offset[HNAE3_MAX_TC];833 u8 max_tc; /* Total number of TCs */834 u8 num_tc; /* Total number of enabled TCs */835 bool mqprio_active;836 bool mqprio_destroy;837 bool dcb_ets_active;838};839 840#define HNAE3_MAX_DSCP 64841#define HNAE3_PRIO_ID_INVALID 0xff842struct hnae3_knic_private_info {843 struct net_device *netdev; /* Set by KNIC client when init instance */844 u16 rss_size; /* Allocated RSS queues */845 u16 req_rss_size;846 u16 rx_buf_len;847 u16 num_tx_desc;848 u16 num_rx_desc;849 u32 tx_spare_buf_size;850 851 struct hnae3_tc_info tc_info;852 u8 tc_map_mode;853 u8 dscp_app_cnt;854 u8 dscp_prio[HNAE3_MAX_DSCP];855 856 u16 num_tqps; /* total number of TQPs in this handle */857 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */858 const struct hnae3_dcb_ops *dcb_ops;859 860 u16 int_rl_setting;861 void __iomem *io_base;862};863 864struct hnae3_roce_private_info {865 struct net_device *netdev;866 void __iomem *roce_io_base;867 void __iomem *roce_mem_base;868 int base_vector;869 int num_vectors;870 871 /* The below attributes defined for RoCE client, hnae3 gives872 * initial values to them, and RoCE client can modify and use873 * them.874 */875 unsigned long reset_state;876 unsigned long instance_state;877 unsigned long state;878};879 880#define HNAE3_SUPPORT_APP_LOOPBACK BIT(0)881#define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)882#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2)883#define HNAE3_SUPPORT_VF BIT(3)884#define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4)885#define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5)886 887#define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */888#define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */889#define HNAE3_BPE BIT(2) /* broadcast promisc enable */890#define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */891#define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */892#define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)893#define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)894 895enum hnae3_pflag {896 HNAE3_PFLAG_LIMIT_PROMISC,897 HNAE3_PFLAG_MAX898};899 900struct hnae3_handle {901 struct hnae3_client *client;902 struct pci_dev *pdev;903 void *priv;904 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */905 u64 flags; /* Indicate the capabilities for this handle */906 907 union {908 struct net_device *netdev; /* first member */909 struct hnae3_knic_private_info kinfo;910 struct hnae3_roce_private_info rinfo;911 };912 913 nodemask_t numa_node_mask; /* for multi-chip support */914 915 enum hnae3_port_base_vlan_state port_base_vlan_state;916 917 u8 netdev_flags;918 struct dentry *hnae3_dbgfs;919 /* protects concurrent contention between debugfs commands */920 struct mutex dbgfs_lock;921 char **dbgfs_buf;922 923 /* Network interface message level enabled bits */924 u32 msg_enable;925 926 unsigned long supported_pflags;927 unsigned long priv_flags;928};929 930#define hnae3_set_field(origin, mask, shift, val) \931 do { \932 (origin) &= (~(mask)); \933 (origin) |= ((val) << (shift)) & (mask); \934 } while (0)935#define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))936 937#define hnae3_set_bit(origin, shift, val) \938 hnae3_set_field(origin, 0x1 << (shift), shift, val)939#define hnae3_get_bit(origin, shift) \940 hnae3_get_field(origin, 0x1 << (shift), shift)941 942#define HNAE3_FORMAT_MAC_ADDR_LEN 18943#define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0944#define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4945#define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5946 947static inline void hnae3_format_mac_addr(char *format_mac_addr,948 const u8 *mac_addr)949{950 snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x",951 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0],952 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4],953 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]);954}955 956int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);957void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);958 959void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);960void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);961void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);962 963void hnae3_unregister_client(struct hnae3_client *client);964int hnae3_register_client(struct hnae3_client *client);965 966void hnae3_set_client_init_flag(struct hnae3_client *client,967 struct hnae3_ae_dev *ae_dev,968 unsigned int inited);969#endif970