501 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2// Copyright (c) 2021-2021 Hisilicon Limited.3 4#ifndef __HCLGE_COMM_CMD_H5#define __HCLGE_COMM_CMD_H6#include <linux/types.h>7 8#include "hnae3.h"9 10#define HCLGE_COMM_CMD_FLAG_IN BIT(0)11#define HCLGE_COMM_CMD_FLAG_NEXT BIT(2)12#define HCLGE_COMM_CMD_FLAG_WR BIT(3)13#define HCLGE_COMM_CMD_FLAG_NO_INTR BIT(4)14 15#define HCLGE_COMM_SEND_SYNC(flag) \16 ((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)17 18#define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 019#define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B 120#define HCLGE_COMM_PHY_IMP_EN_B 221#define HCLGE_COMM_MAC_STATS_EXT_EN_B 322#define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B 423#define HCLGE_COMM_LLRS_FEC_EN_B 524 25#define hclge_comm_dev_phy_imp_supported(ae_dev) \26 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)27 28#define HCLGE_COMM_TYPE_CRQ 029#define HCLGE_COMM_TYPE_CSQ 130 31#define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME 20032 33/* bar registers for cmdq */34#define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x2700035#define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x2700436#define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x2700837#define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x2701038#define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x2701439#define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x2701840#define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C41#define HCLGE_COMM_NIC_CRQ_DEPTH_REG 0x2702042#define HCLGE_COMM_NIC_CRQ_TAIL_REG 0x2702443#define HCLGE_COMM_NIC_CRQ_HEAD_REG 0x2702844/* Vector0 interrupt CMDQ event source register(RW) */45#define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG 0x2710046/* Vector0 interrupt CMDQ event status register(RO) */47#define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG 0x2710448#define HCLGE_COMM_CMDQ_INTR_EN_REG 0x2710849#define HCLGE_COMM_CMDQ_INTR_GEN_REG 0x2710C50#define HCLGE_COMM_CMDQ_INTR_STS_REG 0x2710451 52/* this bit indicates that the driver is ready for hardware reset */53#define HCLGE_COMM_NIC_SW_RST_RDY_B 1654#define HCLGE_COMM_NIC_SW_RST_RDY BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)55#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S 356#define HCLGE_COMM_NIC_CMQ_DESC_NUM 102457#define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT 3000058#define HCLGE_COMM_CMDQ_CFG_RST_TIMEOUT 100000059 60enum hclge_opcode_type {61 /* Generic commands */62 HCLGE_OPC_QUERY_FW_VER = 0x0001,63 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,64 HCLGE_OPC_GBL_RST_STATUS = 0x0021,65 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,66 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,67 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,68 HCLGE_OPC_GET_CFG_PARAM = 0x0025,69 HCLGE_OPC_PF_RST_DONE = 0x0026,70 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,71 72 HCLGE_OPC_STATS_64_BIT = 0x0030,73 HCLGE_OPC_STATS_32_BIT = 0x0031,74 HCLGE_OPC_STATS_MAC = 0x0032,75 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,76 HCLGE_OPC_STATS_MAC_ALL = 0x0034,77 78 HCLGE_OPC_QUERY_REG_NUM = 0x0040,79 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,80 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,81 HCLGE_OPC_DFX_BD_NUM = 0x0043,82 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,83 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,84 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,85 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,86 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,87 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,88 HCLGE_OPC_DFX_NCSI_REG = 0x004A,89 HCLGE_OPC_DFX_RTC_REG = 0x004B,90 HCLGE_OPC_DFX_PPP_REG = 0x004C,91 HCLGE_OPC_DFX_RCB_REG = 0x004D,92 HCLGE_OPC_DFX_TQP_REG = 0x004E,93 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,94 HCLGE_OPC_DFX_GEN_REG = 0x7038,95 96 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,97 HCLGE_OPC_GET_QUEUE_ERR_VF = 0x0067,98 99 /* MAC command */100 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,101 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,102 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,103 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,104 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,105 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,106 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,107 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,108 HCLGE_OPC_COMMON_LOOPBACK = 0x0315,109 HCLGE_OPC_QUERY_FEC_STATS = 0x0316,110 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,111 HCLGE_OPC_QUERY_ROH_TYPE_INFO = 0x0389,112 113 /* PTP commands */114 HCLGE_OPC_PTP_INT_EN = 0x0501,115 HCLGE_OPC_PTP_MODE_CFG = 0x0507,116 117 /* PFC/Pause commands */118 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,119 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,120 HCLGE_OPC_CFG_MAC_PARA = 0x0703,121 HCLGE_OPC_CFG_PFC_PARA = 0x0704,122 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,123 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,124 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,125 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,126 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,127 HCLGE_OPC_QOS_MAP = 0x070A,128 129 /* ETS/scheduler commands */130 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,131 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,132 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,133 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,134 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,135 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,136 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,137 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,138 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,139 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,140 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,141 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,142 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,143 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,144 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,145 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,146 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,147 HCLGE_OPC_TM_NODES = 0x0816,148 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,149 HCLGE_OPC_QSET_DFX_STS = 0x0844,150 HCLGE_OPC_PRI_DFX_STS = 0x0845,151 HCLGE_OPC_PG_DFX_STS = 0x0846,152 HCLGE_OPC_PORT_DFX_STS = 0x0847,153 HCLGE_OPC_SCH_NQ_CNT = 0x0848,154 HCLGE_OPC_SCH_RQ_CNT = 0x0849,155 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,156 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,157 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,158 HCLGE_OPC_TM_FLUSH = 0x0872,159 160 /* Packet buffer allocate commands */161 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,162 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,163 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,164 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,165 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,166 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,167 168 /* TQP management command */169 HCLGE_OPC_SET_TQP_MAP = 0x0A01,170 171 /* TQP commands */172 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,173 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,174 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,175 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,176 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,177 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,178 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,179 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,180 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,181 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,182 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,183 184 /* PPU commands */185 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,186 187 /* TSO command */188 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,189 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,190 191 /* RSS commands */192 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,193 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,194 HCLGE_OPC_RSS_TC_MODE = 0x0D08,195 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,196 197 /* Promisuous mode command */198 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,199 200 /* Vlan offload commands */201 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,202 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,203 204 /* Interrupts commands */205 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,206 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,207 208 /* MAC commands */209 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,210 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,211 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,212 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,213 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,214 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,215 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,216 217 /* MAC VLAN commands */218 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,219 220 /* VLAN commands */221 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,222 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,223 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,224 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103,225 226 /* Flow Director commands */227 HCLGE_OPC_FD_MODE_CTRL = 0x1200,228 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,229 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,230 HCLGE_OPC_FD_TCAM_OP = 0x1203,231 HCLGE_OPC_FD_AD_OP = 0x1204,232 HCLGE_OPC_FD_CNT_OP = 0x1205,233 HCLGE_OPC_FD_USER_DEF_OP = 0x1207,234 HCLGE_OPC_FD_QB_CTRL = 0x1210,235 HCLGE_OPC_FD_QB_AD_OP = 0x1211,236 237 /* MDIO command */238 HCLGE_OPC_MDIO_CONFIG = 0x1900,239 240 /* QCN commands */241 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,242 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,243 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,244 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,245 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,246 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,247 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,248 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,249 250 /* SCC commands */251 HCLGE_OPC_QUERY_SCC_VER = 0x1A84,252 253 /* Mailbox command */254 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,255 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,256 257 /* Led command */258 HCLGE_OPC_LED_STATUS_CFG = 0xB000,259 260 /* clear hardware resource command */261 HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,262 263 /* NCL config command */264 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,265 266 /* IMP stats command */267 HCLGE_OPC_IMP_STATS_BD = 0x7012,268 HCLGE_OPC_IMP_STATS_INFO = 0x7013,269 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A,270 271 /* SFP command */272 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,273 HCLGE_OPC_GET_SFP_EXIST = 0x7101,274 HCLGE_OPC_GET_SFP_INFO = 0x7104,275 276 /* Error INT commands */277 HCLGE_MAC_COMMON_INT_EN = 0x030E,278 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,279 HCLGE_SSU_ECC_INT_CMD = 0x0989,280 HCLGE_SSU_COMMON_INT_CMD = 0x098C,281 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,282 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,283 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,284 HCLGE_COMMON_ECC_INT_CFG = 0x1505,285 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,286 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,287 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,288 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,289 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,290 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,291 HCLGE_QUERY_ALL_ERR_BD_NUM = 0x1516,292 HCLGE_QUERY_ALL_ERR_INFO = 0x1517,293 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,294 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,295 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,296 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,297 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,298 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,299 HCLGE_IGU_COMMON_INT_EN = 0x1806,300 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,301 HCLGE_PPP_CMD0_INT_CMD = 0x2100,302 HCLGE_PPP_CMD1_INT_CMD = 0x2101,303 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,304 HCLGE_OPC_WOL_GET_SUPPORTED_MODE = 0x2201,305 HCLGE_OPC_WOL_CFG = 0x2202,306 HCLGE_NCSI_INT_EN = 0x2401,307 308 /* ROH MAC commands */309 HCLGE_OPC_MAC_ADDR_CHECK = 0x9004,310 311 /* PHY command */312 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025,313 HCLGE_OPC_PHY_REG = 0x7026,314 315 /* Query link diagnosis info command */316 HCLGE_OPC_QUERY_LINK_DIAGNOSIS = 0x702A,317};318 319enum hclge_comm_cmd_return_status {320 HCLGE_COMM_CMD_EXEC_SUCCESS = 0,321 HCLGE_COMM_CMD_NO_AUTH = 1,322 HCLGE_COMM_CMD_NOT_SUPPORTED = 2,323 HCLGE_COMM_CMD_QUEUE_FULL = 3,324 HCLGE_COMM_CMD_NEXT_ERR = 4,325 HCLGE_COMM_CMD_UNEXE_ERR = 5,326 HCLGE_COMM_CMD_PARA_ERR = 6,327 HCLGE_COMM_CMD_RESULT_ERR = 7,328 HCLGE_COMM_CMD_TIMEOUT = 8,329 HCLGE_COMM_CMD_HILINK_ERR = 9,330 HCLGE_COMM_CMD_QUEUE_ILLEGAL = 10,331 HCLGE_COMM_CMD_INVALID = 11,332};333 334enum HCLGE_COMM_CAP_BITS {335 HCLGE_COMM_CAP_UDP_GSO_B,336 HCLGE_COMM_CAP_QB_B,337 HCLGE_COMM_CAP_FD_FORWARD_TC_B,338 HCLGE_COMM_CAP_PTP_B,339 HCLGE_COMM_CAP_INT_QL_B,340 HCLGE_COMM_CAP_HW_TX_CSUM_B,341 HCLGE_COMM_CAP_TX_PUSH_B,342 HCLGE_COMM_CAP_PHY_IMP_B,343 HCLGE_COMM_CAP_TQP_TXRX_INDEP_B,344 HCLGE_COMM_CAP_HW_PAD_B,345 HCLGE_COMM_CAP_STASH_B,346 HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B,347 HCLGE_COMM_CAP_RAS_IMP_B = 12,348 HCLGE_COMM_CAP_FEC_B = 13,349 HCLGE_COMM_CAP_PAUSE_B = 14,350 HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,351 HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,352 HCLGE_COMM_CAP_CQ_B = 18,353 HCLGE_COMM_CAP_GRO_B = 20,354 HCLGE_COMM_CAP_FD_B = 21,355 HCLGE_COMM_CAP_FEC_STATS_B = 25,356 HCLGE_COMM_CAP_VF_FAULT_B = 26,357 HCLGE_COMM_CAP_LANE_NUM_B = 27,358 HCLGE_COMM_CAP_WOL_B = 28,359 HCLGE_COMM_CAP_TM_FLUSH_B = 31,360 HCLGE_COMM_CAP_ERR_MOD_GEN_REG_B = 32,361};362 363enum HCLGE_COMM_API_CAP_BITS {364 HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,365};366 367/* capabilities bits map between imp firmware and local driver */368struct hclge_comm_caps_bit_map {369 u16 imp_bit;370 u16 local_bit;371};372 373struct hclge_cmdq_tx_timeout_map {374 u32 opcode;375 u32 tx_timeout;376};377 378struct hclge_comm_firmware_compat_cmd {379 __le32 compat;380 u8 rsv[20];381};382 383enum hclge_comm_cmd_state {384 HCLGE_COMM_STATE_CMD_DISABLE,385};386 387struct hclge_comm_errcode {388 u32 imp_errcode;389 int common_errno;390};391 392#define HCLGE_COMM_QUERY_CAP_LENGTH 3393struct hclge_comm_query_version_cmd {394 __le32 firmware;395 __le32 hardware;396 __le32 api_caps;397 __le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */398};399 400struct hclge_comm_query_scc_cmd {401 __le32 scc_version;402 u8 rsv[20];403};404 405#define HCLGE_DESC_DATA_LEN 6406struct hclge_desc {407 __le16 opcode;408 __le16 flag;409 __le16 retval;410 __le16 rsv;411 __le32 data[HCLGE_DESC_DATA_LEN];412};413 414struct hclge_comm_cmq_ring {415 dma_addr_t desc_dma_addr;416 struct hclge_desc *desc;417 struct pci_dev *pdev;418 u32 head;419 u32 tail;420 421 u16 buf_size;422 u16 desc_num;423 int next_to_use;424 int next_to_clean;425 u8 ring_type; /* cmq ring type */426 spinlock_t lock; /* Command queue lock */427};428 429enum hclge_comm_cmd_status {430 HCLGE_COMM_STATUS_SUCCESS = 0,431 HCLGE_COMM_ERR_CSQ_FULL = -1,432 HCLGE_COMM_ERR_CSQ_TIMEOUT = -2,433 HCLGE_COMM_ERR_CSQ_ERROR = -3,434};435 436struct hclge_comm_hw;437struct hclge_comm_cmq_ops {438 void (*trace_cmd_send)(struct hclge_comm_hw *hw,439 struct hclge_desc *desc,440 int num, bool is_special);441 void (*trace_cmd_get)(struct hclge_comm_hw *hw,442 struct hclge_desc *desc,443 int num, bool is_special);444};445 446struct hclge_comm_cmq {447 struct hclge_comm_cmq_ring csq;448 struct hclge_comm_cmq_ring crq;449 u16 tx_timeout;450 enum hclge_comm_cmd_status last_status;451 struct hclge_comm_cmq_ops ops;452};453 454struct hclge_comm_hw {455 void __iomem *io_base;456 void __iomem *mem_base;457 struct hclge_comm_cmq cmq;458 unsigned long comm_state;459};460 461static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value)462{463 writel(value, base + reg);464}465 466static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)467{468 u8 __iomem *reg_addr = READ_ONCE(base);469 470 return readl(reg_addr + reg);471}472 473#define hclge_comm_write_dev(a, reg, value) \474 hclge_comm_write_reg((a)->io_base, reg, value)475#define hclge_comm_read_dev(a, reg) \476 hclge_comm_read_reg((a)->io_base, reg)477 478void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);479int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,480 struct hclge_comm_hw *hw,481 u32 *fw_version, bool is_pf);482int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);483int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,484 int num);485void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);486int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,487 struct hclge_comm_hw *hw, bool en);488void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);489void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,490 enum hclge_opcode_type opcode,491 bool is_read);492void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,493 struct hclge_comm_hw *hw);494int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw);495int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,496 u32 *fw_version, bool is_pf,497 unsigned long reset_pending);498void hclge_comm_cmd_init_ops(struct hclge_comm_hw *hw,499 const struct hclge_comm_cmq_ops *ops);500#endif501