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1/* SPDX-License-Identifier: GPL-2.0+ */2// Copyright (c) 2016-2017 Hisilicon Limited.3 4#ifndef __HCLGE_CMD_H5#define __HCLGE_CMD_H6#include <linux/types.h>7#include <linux/io.h>8#include <linux/etherdevice.h>9#include "hnae3.h"10#include "hclge_comm_cmd.h"11 12struct hclge_dev;13 14#define HCLGE_CMDQ_RX_INVLD_B 015#define HCLGE_CMDQ_RX_OUTVLD_B 116 17struct hclge_misc_vector {18 u8 __iomem *addr;19 int vector_irq;20 char name[HNAE3_INT_NAME_LEN];21};22 23#define hclge_cmd_setup_basic_desc(desc, opcode, is_read) \24 hclge_comm_cmd_setup_basic_desc(desc, opcode, is_read)25 26#define HCLGE_TQP_REG_OFFSET 0x8000027#define HCLGE_TQP_REG_SIZE 0x20028 29#define HCLGE_TQP_MAX_SIZE_DEV_V2 102430#define HCLGE_TQP_EXT_REG_OFFSET 0x10031 32#define HCLGE_RCB_INIT_QUERY_TIMEOUT 1033#define HCLGE_RCB_INIT_FLAG_EN_B 034#define HCLGE_RCB_INIT_FLAG_FINI_B 835struct hclge_config_rcb_init_cmd {36 __le16 rcb_init_flag;37 u8 rsv[22];38};39 40struct hclge_tqp_map_cmd {41 __le16 tqp_id; /* Absolute tqp id for in this pf */42 u8 tqp_vf; /* VF id */43#define HCLGE_TQP_MAP_TYPE_PF 044#define HCLGE_TQP_MAP_TYPE_VF 145#define HCLGE_TQP_MAP_TYPE_B 046#define HCLGE_TQP_MAP_EN_B 147 u8 tqp_flag; /* Indicate it's pf or vf tqp */48 __le16 tqp_vid; /* Virtual id in this pf/vf */49 u8 rsv[18];50};51 52#define HCLGE_VECTOR_ELEMENTS_PER_CMD 1053 54enum hclge_int_type {55 HCLGE_INT_TX,56 HCLGE_INT_RX,57 HCLGE_INT_EVENT,58};59 60struct hclge_ctrl_vector_chain_cmd {61#define HCLGE_VECTOR_ID_L_S 062#define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)63 u8 int_vector_id_l;64 u8 int_cause_num;65#define HCLGE_INT_TYPE_S 066#define HCLGE_INT_TYPE_M GENMASK(1, 0)67#define HCLGE_TQP_ID_S 268#define HCLGE_TQP_ID_M GENMASK(12, 2)69#define HCLGE_INT_GL_IDX_S 1370#define HCLGE_INT_GL_IDX_M GENMASK(14, 13)71 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];72 u8 vfid;73#define HCLGE_VECTOR_ID_H_S 874#define HCLGE_VECTOR_ID_H_M GENMASK(15, 8)75 u8 int_vector_id_h;76};77 78#define HCLGE_MAX_TC_NUM 879#define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */80#define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */81struct hclge_tx_buff_alloc_cmd {82 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];83 u8 tx_buff_rsv[8];84};85 86struct hclge_rx_priv_buff_cmd {87 __le16 buf_num[HCLGE_MAX_TC_NUM];88 __le16 shared_buf;89 u8 rsv[6];90};91 92#define HCLGE_RX_PRIV_EN_B 1593#define HCLGE_TC_NUM_ONE_DESC 494struct hclge_priv_wl {95 __le16 high;96 __le16 low;97};98 99struct hclge_rx_priv_wl_buf {100 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];101};102 103struct hclge_rx_com_thrd {104 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];105};106 107struct hclge_rx_com_wl {108 struct hclge_priv_wl com_wl;109};110 111struct hclge_waterline {112 u32 low;113 u32 high;114};115 116struct hclge_tc_thrd {117 u32 low;118 u32 high;119};120 121struct hclge_priv_buf {122 struct hclge_waterline wl; /* Waterline for low and high */123 u32 buf_size; /* TC private buffer size */124 u32 tx_buf_size;125 u32 enable; /* Enable TC private buffer or not */126};127 128struct hclge_shared_buf {129 struct hclge_waterline self;130 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];131 u32 buf_size;132};133 134struct hclge_pkt_buf_alloc {135 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];136 struct hclge_shared_buf s_buf;137};138 139#define HCLGE_RX_COM_WL_EN_B 15140struct hclge_rx_com_wl_buf_cmd {141 __le16 high_wl;142 __le16 low_wl;143 u8 rsv[20];144};145 146#define HCLGE_RX_PKT_EN_B 15147struct hclge_rx_pkt_buf_cmd {148 __le16 high_pkt;149 __le16 low_pkt;150 u8 rsv[20];151};152 153#define HCLGE_PF_STATE_DONE_B 0154#define HCLGE_PF_STATE_MAIN_B 1155#define HCLGE_PF_STATE_BOND_B 2156#define HCLGE_PF_STATE_MAC_N_B 6157#define HCLGE_PF_MAC_NUM_MASK 0x3158#define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)159#define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)160#define HCLGE_VF_RST_STATUS_CMD 4161 162struct hclge_func_status_cmd {163 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];164 u8 pf_state;165 u8 mac_id;166 u8 rsv1;167 u8 pf_cnt_in_mac;168 u8 pf_num;169 u8 vf_num;170 u8 rsv[2];171};172 173struct hclge_pf_res_cmd {174 __le16 tqp_num;175 __le16 buf_size;176 __le16 msixcap_localid_ba_nic;177 __le16 msixcap_localid_number_nic;178 __le16 pf_intr_vector_number_roce;179 __le16 pf_own_fun_number;180 __le16 tx_buf_size;181 __le16 dv_buf_size;182 __le16 ext_tqp_num;183 u8 rsv[6];184};185 186#define HCLGE_CFG_OFFSET_S 0187#define HCLGE_CFG_OFFSET_M GENMASK(19, 0)188#define HCLGE_CFG_RD_LEN_S 24189#define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)190#define HCLGE_CFG_RD_LEN_BYTES 16191#define HCLGE_CFG_RD_LEN_UNIT 4192 193#define HCLGE_CFG_TC_NUM_S 8194#define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)195#define HCLGE_CFG_TQP_DESC_N_S 16196#define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)197#define HCLGE_CFG_PHY_ADDR_S 0198#define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)199#define HCLGE_CFG_MEDIA_TP_S 8200#define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)201#define HCLGE_CFG_RX_BUF_LEN_S 16202#define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)203#define HCLGE_CFG_MAC_ADDR_H_S 0204#define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)205#define HCLGE_CFG_DEFAULT_SPEED_S 16206#define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)207#define HCLGE_CFG_RSS_SIZE_S 24208#define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)209#define HCLGE_CFG_SPEED_ABILITY_S 0210#define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)211#define HCLGE_CFG_SPEED_ABILITY_EXT_S 10212#define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)213#define HCLGE_CFG_VLAN_FLTR_CAP_S 8214#define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8)215#define HCLGE_CFG_UMV_TBL_SPACE_S 16216#define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)217#define HCLGE_CFG_PF_RSS_SIZE_S 0218#define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)219#define HCLGE_CFG_TX_SPARE_BUF_SIZE_S 4220#define HCLGE_CFG_TX_SPARE_BUF_SIZE_M GENMASK(15, 4)221 222#define HCLGE_CFG_CMD_CNT 4223 224struct hclge_cfg_param_cmd {225 __le32 offset;226 __le32 rsv;227 __le32 param[HCLGE_CFG_CMD_CNT];228};229 230#define HCLGE_MAC_MODE 0x0231#define HCLGE_DESC_NUM 0x40232 233#define HCLGE_ALLOC_VALID_B 0234struct hclge_vf_num_cmd {235 u8 alloc_valid;236 u8 rsv[23];237};238 239#define HCLGE_RSS_DEFAULT_OUTPORT_B 4240 241#define HCLGE_RSS_CFG_TBL_SIZE_H 4242#define HCLGE_RSS_CFG_TBL_BW_L 8U243 244#define HCLGE_RSS_TC_OFFSET_S 0245#define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0)246#define HCLGE_RSS_TC_SIZE_MSB_B 11247#define HCLGE_RSS_TC_SIZE_S 12248#define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)249#define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3250#define HCLGE_RSS_TC_VALID_B 15251 252#define HCLGE_LINK_STATUS_UP_B 0253#define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)254struct hclge_link_status_cmd {255 u8 status;256 u8 rsv[23];257};258 259/* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */260#define HCLGE_PROMISC_EN_UC 1261#define HCLGE_PROMISC_EN_MC 2262#define HCLGE_PROMISC_EN_BC 3263#define HCLGE_PROMISC_TX_EN 4264#define HCLGE_PROMISC_RX_EN 5265 266/* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */267#define HCLGE_PROMISC_UC_RX_EN 2268#define HCLGE_PROMISC_MC_RX_EN 3269#define HCLGE_PROMISC_BC_RX_EN 4270#define HCLGE_PROMISC_UC_TX_EN 5271#define HCLGE_PROMISC_MC_TX_EN 6272#define HCLGE_PROMISC_BC_TX_EN 7273 274struct hclge_promisc_cfg_cmd {275 u8 promisc;276 u8 vf_id;277 u8 extend_promisc;278 u8 rsv0[21];279};280 281enum hclge_promisc_type {282 HCLGE_UNICAST = 1,283 HCLGE_MULTICAST = 2,284 HCLGE_BROADCAST = 3,285};286 287#define HCLGE_MAC_TX_EN_B 6288#define HCLGE_MAC_RX_EN_B 7289#define HCLGE_MAC_PAD_TX_B 11290#define HCLGE_MAC_PAD_RX_B 12291#define HCLGE_MAC_1588_TX_B 13292#define HCLGE_MAC_1588_RX_B 14293#define HCLGE_MAC_APP_LP_B 15294#define HCLGE_MAC_LINE_LP_B 16295#define HCLGE_MAC_FCS_TX_B 17296#define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18297#define HCLGE_MAC_RX_FCS_STRIP_B 19298#define HCLGE_MAC_RX_FCS_B 20299#define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21300#define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22301 302struct hclge_config_mac_mode_cmd {303 __le32 txrx_pad_fcs_loop_en;304 u8 rsv[20];305};306 307struct hclge_pf_rst_sync_cmd {308#define HCLGE_PF_RST_ALL_VF_RDY_B 0309 u8 all_vf_ready;310 u8 rsv[23];311};312 313#define HCLGE_CFG_SPEED_S 0314#define HCLGE_CFG_SPEED_M GENMASK(5, 0)315 316#define HCLGE_CFG_DUPLEX_B 7317#define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)318 319struct hclge_config_mac_speed_dup_cmd {320 u8 speed_dup;321 322#define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0323 u8 mac_change_fec_en;324 u8 rsv[4];325 u8 lane_num;326 u8 rsv1[17];327};328 329#define HCLGE_TQP_ENABLE_B 0330 331#define HCLGE_MAC_CFG_AN_EN_B 0332#define HCLGE_MAC_CFG_AN_INT_EN_B 1333#define HCLGE_MAC_CFG_AN_INT_MSK_B 2334#define HCLGE_MAC_CFG_AN_INT_CLR_B 3335#define HCLGE_MAC_CFG_AN_RST_B 4336 337#define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)338 339struct hclge_config_auto_neg_cmd {340 __le32 cfg_an_cmd_flag;341 u8 rsv[20];342};343 344struct hclge_sfp_info_cmd {345 __le32 speed;346 u8 query_type; /* 0: sfp speed, 1: active speed */347 u8 active_fec;348 u8 autoneg; /* autoneg state */349 u8 autoneg_ability; /* whether support autoneg */350 __le32 speed_ability; /* speed ability for current media */351 __le32 module_type;352 u8 fec_ability;353 u8 lane_num;354 u8 rsv[6];355};356 357#define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0358#define HCLGE_MAC_CFG_FEC_MODE_S 1359#define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)360#define HCLGE_MAC_CFG_FEC_SET_DEF_B 0361#define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1362 363#define HCLGE_MAC_FEC_OFF 0364#define HCLGE_MAC_FEC_BASER 1365#define HCLGE_MAC_FEC_RS 2366#define HCLGE_MAC_FEC_LLRS 3367struct hclge_config_fec_cmd {368 u8 fec_mode;369 u8 default_config;370 u8 rsv[22];371};372 373#define HCLGE_FEC_STATS_CMD_NUM 4374 375struct hclge_query_fec_stats_cmd {376 /* fec rs mode total stats */377 __le32 rs_fec_corr_blocks;378 __le32 rs_fec_uncorr_blocks;379 __le32 rs_fec_error_blocks;380 /* fec base-r mode per lanes stats */381 u8 base_r_lane_num;382 u8 rsv[3];383 __le32 base_r_fec_corr_blocks;384 __le32 base_r_fec_uncorr_blocks;385};386 387#define HCLGE_MAC_UPLINK_PORT 0x100388 389struct hclge_config_max_frm_size_cmd {390 __le16 max_frm_size;391 u8 min_frm_size;392 u8 rsv[21];393};394 395enum hclge_mac_vlan_tbl_opcode {396 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */397 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */398 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */399 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */400};401 402enum hclge_mac_vlan_add_resp_code {403 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */404 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */405};406 407#define HCLGE_MAC_VLAN_BIT0_EN_B 0408#define HCLGE_MAC_VLAN_BIT1_EN_B 1409#define HCLGE_MAC_EPORT_SW_EN_B 12410#define HCLGE_MAC_EPORT_TYPE_B 11411#define HCLGE_MAC_EPORT_VFID_S 3412#define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)413#define HCLGE_MAC_EPORT_PFID_S 0414#define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)415struct hclge_mac_vlan_tbl_entry_cmd {416 u8 flags;417 u8 resp_code;418 __le16 vlan_tag;419 __le32 mac_addr_hi32;420 __le16 mac_addr_lo16;421 __le16 rsv1;422 u8 entry_type;423 u8 mc_mac_en;424 __le16 egress_port;425 __le16 egress_queue;426 u8 rsv2[6];427};428 429#define HCLGE_UMV_SPC_ALC_B 0430struct hclge_umv_spc_alc_cmd {431 u8 allocate;432 u8 rsv1[3];433 __le32 space_size;434 u8 rsv2[16];435};436 437#define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)438#define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)439#define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)440 441struct hclge_mac_mgr_tbl_entry_cmd {442 u8 flags;443 u8 resp_code;444 __le16 vlan_tag;445 u8 mac_addr[ETH_ALEN];446 __le16 rsv1;447 __le16 ethter_type;448 __le16 egress_port;449 __le16 egress_queue;450 u8 sw_port_id_aware;451 u8 rsv2;452 u8 i_port_bitmap;453 u8 i_port_direction;454 u8 rsv3[2];455};456 457struct hclge_vlan_filter_ctrl_cmd {458 u8 vlan_type;459 u8 vlan_fe;460 u8 rsv1[2];461 u8 vf_id;462 u8 rsv2[19];463};464 465#define HCLGE_VLAN_ID_OFFSET_STEP 160466#define HCLGE_VLAN_BYTE_SIZE 8467#define HCLGE_VLAN_OFFSET_BITMAP \468 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)469 470struct hclge_vlan_filter_pf_cfg_cmd {471 u8 vlan_offset;472 u8 vlan_cfg;473 u8 rsv[2];474 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];475};476 477#define HCLGE_MAX_VF_BYTES 16478 479struct hclge_vlan_filter_vf_cfg_cmd {480 __le16 vlan_id;481 u8 resp_code;482 u8 rsv;483 u8 vlan_cfg;484 u8 rsv1[3];485 u8 vf_bitmap[HCLGE_MAX_VF_BYTES];486};487 488#define HCLGE_INGRESS_BYPASS_B 0489struct hclge_port_vlan_filter_bypass_cmd {490 u8 bypass_state;491 u8 rsv1[3];492 u8 vf_id;493 u8 rsv2[19];494};495 496#define HCLGE_SWITCH_ANTI_SPOOF_B 0U497#define HCLGE_SWITCH_ALW_LPBK_B 1U498#define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U499#define HCLGE_SWITCH_ALW_DST_OVRD_B 3U500#define HCLGE_SWITCH_NO_MASK 0x0501#define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE502#define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD503#define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB504#define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7505 506struct hclge_mac_vlan_switch_cmd {507 u8 roce_sel;508 u8 rsv1[3];509 __le32 func_id;510 u8 switch_param;511 u8 rsv2[3];512 u8 param_mask;513 u8 rsv3[11];514};515 516enum hclge_mac_vlan_cfg_sel {517 HCLGE_MAC_VLAN_NIC_SEL = 0,518 HCLGE_MAC_VLAN_ROCE_SEL,519};520 521#define HCLGE_ACCEPT_TAG1_B 0522#define HCLGE_ACCEPT_UNTAG1_B 1523#define HCLGE_PORT_INS_TAG1_EN_B 2524#define HCLGE_PORT_INS_TAG2_EN_B 3525#define HCLGE_CFG_NIC_ROCE_SEL_B 4526#define HCLGE_ACCEPT_TAG2_B 5527#define HCLGE_ACCEPT_UNTAG2_B 6528#define HCLGE_TAG_SHIFT_MODE_EN_B 7529#define HCLGE_VF_NUM_PER_BYTE 8530 531struct hclge_vport_vtag_tx_cfg_cmd {532 u8 vport_vlan_cfg;533 u8 vf_offset;534 u8 rsv1[2];535 __le16 def_vlan_tag1;536 __le16 def_vlan_tag2;537 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];538 u8 rsv2[8];539};540 541#define HCLGE_REM_TAG1_EN_B 0542#define HCLGE_REM_TAG2_EN_B 1543#define HCLGE_SHOW_TAG1_EN_B 2544#define HCLGE_SHOW_TAG2_EN_B 3545#define HCLGE_DISCARD_TAG1_EN_B 5546#define HCLGE_DISCARD_TAG2_EN_B 6547struct hclge_vport_vtag_rx_cfg_cmd {548 u8 vport_vlan_cfg;549 u8 vf_offset;550 u8 rsv1[6];551 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];552 u8 rsv2[8];553};554 555struct hclge_tx_vlan_type_cfg_cmd {556 __le16 ot_vlan_type;557 __le16 in_vlan_type;558 u8 rsv[20];559};560 561struct hclge_rx_vlan_type_cfg_cmd {562 __le16 ot_fst_vlan_type;563 __le16 ot_sec_vlan_type;564 __le16 in_fst_vlan_type;565 __le16 in_sec_vlan_type;566 u8 rsv[16];567};568 569struct hclge_cfg_com_tqp_queue_cmd {570 __le16 tqp_id;571 __le16 stream_id;572 u8 enable;573 u8 rsv[19];574};575 576struct hclge_cfg_tx_queue_pointer_cmd {577 __le16 tqp_id;578 __le16 tx_tail;579 __le16 tx_head;580 __le16 fbd_num;581 __le16 ring_offset;582 u8 rsv[14];583};584 585#pragma pack(1)586struct hclge_mac_ethertype_idx_rd_cmd {587 u8 flags;588 u8 resp_code;589 __le16 vlan_tag;590 u8 mac_addr[ETH_ALEN];591 __le16 index;592 __le16 ethter_type;593 __le16 egress_port;594 __le16 egress_queue;595 __le16 rev0;596 u8 i_port_bitmap;597 u8 i_port_direction;598 u8 rev1[2];599};600 601#pragma pack()602 603#define HCLGE_TSO_MSS_MIN_S 0604#define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)605 606#define HCLGE_TSO_MSS_MAX_S 16607#define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)608 609struct hclge_cfg_tso_status_cmd {610 __le16 tso_mss_min;611 __le16 tso_mss_max;612 u8 rsv[20];613};614 615#define HCLGE_GRO_EN_B 0616struct hclge_cfg_gro_status_cmd {617 u8 gro_en;618 u8 rsv[23];619};620 621#define HCLGE_TSO_MSS_MIN 256622#define HCLGE_TSO_MSS_MAX 9668623 624#define HCLGE_TQP_RESET_B 0625struct hclge_reset_tqp_queue_cmd {626 __le16 tqp_id;627 u8 reset_req;628 u8 ready_to_reset;629 u8 rsv[20];630};631 632#define HCLGE_CFG_RESET_MAC_B 3633#define HCLGE_CFG_RESET_FUNC_B 7634#define HCLGE_CFG_RESET_RCB_B 1635struct hclge_reset_cmd {636 u8 mac_func_reset;637 u8 fun_reset_vfid;638 u8 fun_reset_rcb;639 u8 rsv;640 __le16 fun_reset_rcb_vqid_start;641 __le16 fun_reset_rcb_vqid_num;642 u8 fun_reset_rcb_return_status;643 u8 rsv1[15];644};645 646#define HCLGE_PF_RESET_DONE_BIT BIT(0)647 648struct hclge_pf_rst_done_cmd {649 u8 pf_rst_done;650 u8 rsv[23];651};652 653#define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)654#define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)655#define HCLGE_CMD_GE_PHY_INNER_LOOP_B BIT(3)656#define HCLGE_CMD_COMMON_LB_DONE_B BIT(0)657#define HCLGE_CMD_COMMON_LB_SUCCESS_B BIT(1)658struct hclge_common_lb_cmd {659 u8 mask;660 u8 enable;661 u8 result;662 u8 rsv[21];663};664 665#define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */666#define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */667#define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */668#define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */669#define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */670 671#define HCLGE_LED_LOCATE_STATE_S 0672#define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)673 674struct hclge_set_led_state_cmd {675 u8 rsv1[3];676 u8 locate_led_config;677 u8 rsv2[20];678};679 680struct hclge_get_fd_mode_cmd {681 u8 mode;682 u8 enable;683 u8 rsv[22];684};685 686struct hclge_get_fd_allocation_cmd {687 __le32 stage1_entry_num;688 __le32 stage2_entry_num;689 __le16 stage1_counter_num;690 __le16 stage2_counter_num;691 u8 rsv[12];692};693 694struct hclge_set_fd_key_config_cmd {695 u8 stage;696 u8 key_select;697 u8 inner_sipv6_word_en;698 u8 inner_dipv6_word_en;699 u8 outer_sipv6_word_en;700 u8 outer_dipv6_word_en;701 u8 rsv1[2];702 __le32 tuple_mask;703 __le32 meta_data_mask;704 u8 rsv2[8];705};706 707#define HCLGE_FD_EPORT_SW_EN_B 0708struct hclge_fd_tcam_config_1_cmd {709 u8 stage;710 u8 xy_sel;711 u8 port_info;712 u8 rsv1[1];713 __le32 index;714 u8 entry_vld;715 u8 rsv2[7];716 u8 tcam_data[8];717};718 719struct hclge_fd_tcam_config_2_cmd {720 u8 tcam_data[24];721};722 723struct hclge_fd_tcam_config_3_cmd {724 u8 tcam_data[20];725 u8 rsv[4];726};727 728#define HCLGE_FD_AD_DROP_B 0729#define HCLGE_FD_AD_DIRECT_QID_B 1730#define HCLGE_FD_AD_QID_S 2731#define HCLGE_FD_AD_QID_M GENMASK(11, 2)732#define HCLGE_FD_AD_USE_COUNTER_B 12733#define HCLGE_FD_AD_COUNTER_NUM_S 13734#define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)735#define HCLGE_FD_AD_NXT_STEP_B 20736#define HCLGE_FD_AD_NXT_KEY_S 21737#define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)738#define HCLGE_FD_AD_WR_RULE_ID_B 0739#define HCLGE_FD_AD_RULE_ID_S 1740#define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)741#define HCLGE_FD_AD_TC_OVRD_B 16742#define HCLGE_FD_AD_TC_SIZE_S 17743#define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17)744 745struct hclge_fd_ad_config_cmd {746 u8 stage;747 u8 rsv1[3];748 __le32 index;749 __le64 ad_data;750 u8 rsv2[8];751};752 753struct hclge_fd_ad_cnt_read_cmd {754 u8 rsv0[4];755 __le16 index;756 u8 rsv1[2];757 __le64 cnt;758 u8 rsv2[8];759};760 761#define HCLGE_FD_USER_DEF_OFT_S 0762#define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0)763#define HCLGE_FD_USER_DEF_EN_B 15764struct hclge_fd_user_def_cfg_cmd {765 __le16 ol2_cfg;766 __le16 l2_cfg;767 __le16 ol3_cfg;768 __le16 l3_cfg;769 __le16 ol4_cfg;770 __le16 l4_cfg;771 u8 rsv[12];772};773 774struct hclge_get_imp_bd_cmd {775 __le32 bd_num;776 u8 rsv[20];777};778 779struct hclge_query_ppu_pf_other_int_dfx_cmd {780 __le16 over_8bd_no_fe_qid;781 __le16 over_8bd_no_fe_vf_id;782 __le16 tso_mss_cmp_min_err_qid;783 __le16 tso_mss_cmp_min_err_vf_id;784 __le16 tso_mss_cmp_max_err_qid;785 __le16 tso_mss_cmp_max_err_vf_id;786 __le16 tx_rd_fbd_poison_qid;787 __le16 tx_rd_fbd_poison_vf_id;788 __le16 rx_rd_fbd_poison_qid;789 __le16 rx_rd_fbd_poison_vf_id;790 u8 rsv[4];791};792 793#define HCLGE_SFP_INFO_CMD_NUM 6794#define HCLGE_SFP_INFO_BD0_LEN 20795#define HCLGE_SFP_INFO_BDX_LEN 24796#define HCLGE_SFP_INFO_MAX_LEN \797 (HCLGE_SFP_INFO_BD0_LEN + \798 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)799 800struct hclge_sfp_info_bd0_cmd {801 __le16 offset;802 __le16 read_len;803 u8 data[HCLGE_SFP_INFO_BD0_LEN];804};805 806#define HCLGE_QUERY_DEV_SPECS_BD_NUM 4807 808struct hclge_dev_specs_0_cmd {809 __le32 rsv0;810 __le32 mac_entry_num;811 __le32 mng_entry_num;812 __le16 rss_ind_tbl_size;813 __le16 rss_key_size;814 __le16 int_ql_max;815 u8 max_non_tso_bd_num;816 u8 rsv1;817 __le32 max_tm_rate;818};819 820#define HCLGE_DEF_MAX_INT_GL 0x1FE0U821 822struct hclge_dev_specs_1_cmd {823 __le16 max_frm_size;824 __le16 max_qset_num;825 __le16 max_int_gl;826 u8 rsv0[2];827 __le16 umv_size;828 __le16 mc_mac_size;829 u8 rsv1[6];830 u8 tnl_num;831 u8 hilink_version;832 u8 rsv2[4];833};834 835/* mac speed type defined in firmware command */836enum HCLGE_FIRMWARE_MAC_SPEED {837 HCLGE_FW_MAC_SPEED_1G,838 HCLGE_FW_MAC_SPEED_10G,839 HCLGE_FW_MAC_SPEED_25G,840 HCLGE_FW_MAC_SPEED_40G,841 HCLGE_FW_MAC_SPEED_50G,842 HCLGE_FW_MAC_SPEED_100G,843 HCLGE_FW_MAC_SPEED_10M,844 HCLGE_FW_MAC_SPEED_100M,845 HCLGE_FW_MAC_SPEED_200G,846};847 848#define HCLGE_PHY_LINK_SETTING_BD_NUM 2849 850struct hclge_phy_link_ksetting_0_cmd {851 __le32 speed;852 u8 duplex;853 u8 autoneg;854 u8 eth_tp_mdix;855 u8 eth_tp_mdix_ctrl;856 u8 port;857 u8 transceiver;858 u8 phy_address;859 u8 rsv;860 __le32 supported;861 __le32 advertising;862 __le32 lp_advertising;863};864 865struct hclge_phy_link_ksetting_1_cmd {866 u8 master_slave_cfg;867 u8 master_slave_state;868 u8 rsv[22];869};870 871struct hclge_phy_reg_cmd {872 __le16 reg_addr;873 u8 rsv0[2];874 __le16 reg_val;875 u8 rsv1[18];876};877 878struct hclge_wol_cfg_cmd {879 __le32 wake_on_lan_mode;880 u8 sopass[SOPASS_MAX];881 u8 sopass_size;882 u8 rsv[13];883};884 885struct hclge_query_wol_supported_cmd {886 __le32 supported_wake_mode;887 u8 rsv[20];888};889 890struct hclge_hw;891int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);892#endif893