270 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/* Copyright (c) 2016-2017 Hisilicon Limited. */3 4#ifndef __HCLGE_ERR_H5#define __HCLGE_ERR_H6 7#include "hclge_main.h"8#include "hclge_debugfs.h"9#include "hnae3.h"10 11#define HCLGE_MPF_RAS_INT_MIN_BD_NUM 1012#define HCLGE_PF_RAS_INT_MIN_BD_NUM 413#define HCLGE_MPF_MSIX_INT_MIN_BD_NUM 1014#define HCLGE_PF_MSIX_INT_MIN_BD_NUM 415 16#define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B0017#define HCLGE_RAS_REG_NFE_MASK 0xFF0018#define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x300000019#define HCLGE_RAS_REG_ERR_MASK \20 (HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK)21 22#define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF0023 24#define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF000025#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF000026#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x30027#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x30028#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF29#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF30#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF000031#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF000032#define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x010033#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x010034#define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF35#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF36#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F00000037#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F00000038#define HCLGE_IGU_ERR_INT_EN 0x0000000F39#define HCLGE_IGU_ERR_INT_TYPE 0x0000066040#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F41#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF42#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F43#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF44#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF45#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF46#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF47#define HCLGE_PPP_PF_ERR_INT_EN 0x000348#define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x000349#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F50#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F51#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F52#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F53#define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x354#define HCLGE_TM_QCN_ERR_INT_TYPE 0x2955#define HCLGE_TM_QCN_FIFO_INT_EN 0xFFFF0056#define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF57#define HCLGE_NCSI_ERR_INT_EN 0x358#define HCLGE_NCSI_ERR_INT_TYPE 0x959#define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF60#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF61#define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)62#define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)63#define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)64#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)65#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)66#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)67#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)68#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF69#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF70#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB71#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB72#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)73#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)74#define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)75#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)76#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)77#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)78#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)79#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)80#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x010181#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x010182#define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)83#define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)84#define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF85#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF000086#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)87#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)88 89#define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)90#define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF91#define HCLGE_IGU_INT_MASK GENMASK(3, 0)92#define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)93#define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)94#define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)95#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29)96#define HCLGE_PPU_PF_INT_RAS_MASK 0x1897#define HCLGE_PPU_PF_INT_MSIX_MASK 0x2698#define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x0199#define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)100#define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)101#define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)102 103#define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF104#define HCLGE_ROCEE_RAS_CE_INT_EN 0x1105#define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF106#define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1107#define HCLGE_ROCEE_RERR_INT_MASK BIT(0)108#define HCLGE_ROCEE_BERR_INT_MASK BIT(1)109#define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0)110#define HCLGE_ROCEE_ECC_INT_MASK BIT(2)111#define HCLGE_ROCEE_OVF_INT_MASK BIT(3)112#define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000113#define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F114 115#define HCLGE_DESC_DATA_MAX 8116#define HCLGE_REG_NUM_MAX 256117#define HCLGE_DESC_NO_DATA_LEN 8118 119#define HCLGE_BD_NUM_SSU_REG_0 10120#define HCLGE_BD_NUM_SSU_REG_1 15121#define HCLGE_BD_NUM_RPU_REG_0 1122#define HCLGE_BD_NUM_RPU_REG_1 2123#define HCLGE_BD_NUM_IGU_EGU_REG 9124#define HCLGE_BD_NUM_GEN_REG 8125#define HCLGE_MOD_REG_INFO_LEN_MAX 256126#define HCLGE_MOD_REG_EXTRA_LEN 11127#define HCLGE_MOD_REG_VALUE_LEN 9128#define HCLGE_MOD_REG_GROUP_MAX_SIZE 6129#define HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE 8130 131enum hclge_err_int_type {132 HCLGE_ERR_INT_MSIX = 0,133 HCLGE_ERR_INT_RAS_CE = 1,134 HCLGE_ERR_INT_RAS_NFE = 2,135 HCLGE_ERR_INT_RAS_FE = 3,136};137 138enum hclge_mod_name_list {139 MODULE_NONE = 0,140 MODULE_BIOS_COMMON = 1,141 MODULE_GE = 2,142 MODULE_IGU_EGU = 3,143 MODULE_LGE = 4,144 MODULE_NCSI = 5,145 MODULE_PPP = 6,146 MODULE_QCN = 7,147 MODULE_RCB_RX = 8,148 MODULE_RTC = 9,149 MODULE_SSU = 10,150 MODULE_TM = 11,151 MODULE_RCB_TX = 12,152 MODULE_TXDMA = 13,153 MODULE_MASTER = 14,154 MODULE_HIMAC = 15,155 /* add new MODULE NAME for NIC here in order */156 MODULE_ROCEE_TOP = 40,157 MODULE_ROCEE_TIMER = 41,158 MODULE_ROCEE_MDB = 42,159 MODULE_ROCEE_TSP = 43,160 MODULE_ROCEE_TRP = 44,161 MODULE_ROCEE_SCC = 45,162 MODULE_ROCEE_CAEP = 46,163 MODULE_ROCEE_GEN_AC = 47,164 MODULE_ROCEE_QMM = 48,165 MODULE_ROCEE_LSAN = 49,166 /* add new MODULE NAME for RoCEE here in order */167};168 169enum hclge_err_type_list {170 NONE_ERROR = 0,171 FIFO_ERROR = 1,172 MEMORY_ERROR = 2,173 POISON_ERROR = 3,174 MSIX_ECC_ERROR = 4,175 TQP_INT_ECC_ERROR = 5,176 PF_ABNORMAL_INT_ERROR = 6,177 MPF_ABNORMAL_INT_ERROR = 7,178 COMMON_ERROR = 8,179 PORT_ERROR = 9,180 ETS_ERROR = 10,181 NCSI_ERROR = 11,182 GLB_ERROR = 12,183 LINK_ERROR = 13,184 PTP_ERROR = 14,185 /* add new ERROR TYPE for NIC here in order */186 ROCEE_NORMAL_ERR = 40,187 ROCEE_OVF_ERR = 41,188 ROCEE_BUS_ERR = 42,189 /* add new ERROR TYPE for ROCEE here in order */190};191 192struct hclge_hw_blk {193 u32 msk;194 const char *name;195 int (*config_err_int)(struct hclge_dev *hdev, bool en);196};197 198struct hclge_hw_error {199 u32 int_msk;200 const char *msg;201 enum hnae3_reset_type reset_level;202};203 204struct hclge_hw_module_id {205 enum hclge_mod_name_list module_id;206 const char *msg;207 void (*query_reg_info)(struct hclge_dev *hdev);208};209 210struct hclge_hw_type_id {211 enum hclge_err_type_list type_id;212 const char *msg;213 bool cause_by_vf; /* indicate the error may from vf exception */214};215 216struct hclge_sum_err_info {217 u8 reset_type;218 u8 mod_num;219 u8 rsv[2];220};221 222struct hclge_mod_err_info {223 u8 mod_id;224 u8 err_num;225 u8 rsv[2];226};227 228struct hclge_type_reg_err_info {229 u8 type_id;230 u8 reg_num;231 u8 rsv[2];232 u32 hclge_reg[HCLGE_REG_NUM_MAX];233};234 235struct hclge_mod_reg_info {236 const char *reg_name;237 bool has_suffix; /* add suffix for register name */238 /* the positions of reg values in hclge_desc.data */239 u8 reg_offset_group[HCLGE_MOD_REG_GROUP_MAX_SIZE];240 u8 group_size;241};242 243/* This structure defines cmdq used to query the hardware module debug244 * regisgers.245 */246struct hclge_mod_reg_common_msg {247 enum hclge_opcode_type cmd;248 struct hclge_desc *desc;249 u8 bd_num; /* the bd number of hclge_desc used */250 bool need_para; /* whether this cmdq needs to add para */251 252 /* the regs need to print */253 const struct hclge_mod_reg_info *result_regs;254 u16 result_regs_size;255};256 257int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);258int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);259int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);260void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);261bool hclge_find_error_source(struct hclge_dev *hdev);262void hclge_handle_occurred_error(struct hclge_dev *hdev);263pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);264int hclge_handle_hw_msix_error(struct hclge_dev *hdev,265 unsigned long *reset_requests);266int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);267int hclge_handle_mac_tnl(struct hclge_dev *hdev);268int hclge_handle_vf_queue_err_ras(struct hclge_dev *hdev);269#endif270