1179 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2// Copyright (c) 2016-2017 Hisilicon Limited.3 4#ifndef __HCLGE_MAIN_H5#define __HCLGE_MAIN_H6#include <linux/fs.h>7#include <linux/types.h>8#include <linux/phy.h>9#include <linux/if_vlan.h>10#include <linux/kfifo.h>11 12#include <net/devlink.h>13#include <net/ipv6.h>14 15#include "hclge_cmd.h"16#include "hclge_ptp.h"17#include "hnae3.h"18#include "hclge_comm_rss.h"19#include "hclge_comm_tqp_stats.h"20 21#define HCLGE_MOD_VERSION "1.0"22#define HCLGE_DRIVER_NAME "hclge"23 24#define HCLGE_MAX_PF_NUM 825 26#define HCLGE_VF_VPORT_START_NUM 127 28#define HCLGE_RD_FIRST_STATS_NUM 229#define HCLGE_RD_OTHER_STATS_NUM 430 31#define HCLGE_INVALID_VPORT 0xffff32 33#define HCLGE_PF_CFG_BLOCK_SIZE 3234#define HCLGE_PF_CFG_DESC_NUM \35 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)36 37#define HCLGE_VECTOR_REG_BASE 0x2000038#define HCLGE_VECTOR_EXT_REG_BASE 0x3000039#define HCLGE_MISC_VECTOR_REG_BASE 0x2040040 41#define HCLGE_VECTOR_REG_OFFSET 0x442#define HCLGE_VECTOR_REG_OFFSET_H 0x100043#define HCLGE_VECTOR_VF_OFFSET 0x10000044 45#define HCLGE_NIC_CSQ_DEPTH_REG 0x2700846 47/* bar registers for common func */48#define HCLGE_GRO_EN_REG 0x2800049#define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x2800850 51/* bar registers for rcb */52#define HCLGE_RING_RX_ADDR_L_REG 0x8000053#define HCLGE_RING_RX_ADDR_H_REG 0x8000454#define HCLGE_RING_RX_BD_NUM_REG 0x8000855#define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C56#define HCLGE_RING_RX_MERGE_EN_REG 0x8001457#define HCLGE_RING_RX_TAIL_REG 0x8001858#define HCLGE_RING_RX_HEAD_REG 0x8001C59#define HCLGE_RING_RX_FBD_NUM_REG 0x8002060#define HCLGE_RING_RX_OFFSET_REG 0x8002461#define HCLGE_RING_RX_FBD_OFFSET_REG 0x8002862#define HCLGE_RING_RX_STASH_REG 0x8003063#define HCLGE_RING_RX_BD_ERR_REG 0x8003464#define HCLGE_RING_TX_ADDR_L_REG 0x8004065#define HCLGE_RING_TX_ADDR_H_REG 0x8004466#define HCLGE_RING_TX_BD_NUM_REG 0x8004867#define HCLGE_RING_TX_PRIORITY_REG 0x8004C68#define HCLGE_RING_TX_TC_REG 0x8005069#define HCLGE_RING_TX_MERGE_EN_REG 0x8005470#define HCLGE_RING_TX_TAIL_REG 0x8005871#define HCLGE_RING_TX_HEAD_REG 0x8005C72#define HCLGE_RING_TX_FBD_NUM_REG 0x8006073#define HCLGE_RING_TX_OFFSET_REG 0x8006474#define HCLGE_RING_TX_EBD_NUM_REG 0x8006875#define HCLGE_RING_TX_EBD_OFFSET_REG 0x8007076#define HCLGE_RING_TX_BD_ERR_REG 0x8007477#define HCLGE_RING_EN_REG 0x8009078 79/* bar registers for tqp interrupt */80#define HCLGE_TQP_INTR_CTRL_REG 0x2000081#define HCLGE_TQP_INTR_GL0_REG 0x2010082#define HCLGE_TQP_INTR_GL1_REG 0x2020083#define HCLGE_TQP_INTR_GL2_REG 0x2030084#define HCLGE_TQP_INTR_RL_REG 0x2090085 86#define HCLGE_RSS_IND_TBL_SIZE 51287 88#define HCLGE_RSS_TC_SIZE_0 189#define HCLGE_RSS_TC_SIZE_1 290#define HCLGE_RSS_TC_SIZE_2 491#define HCLGE_RSS_TC_SIZE_3 892#define HCLGE_RSS_TC_SIZE_4 1693#define HCLGE_RSS_TC_SIZE_5 3294#define HCLGE_RSS_TC_SIZE_6 6495#define HCLGE_RSS_TC_SIZE_7 12896 97#define HCLGE_UMV_TBL_SIZE 307298#define HCLGE_DEFAULT_UMV_SPACE_PER_PF \99 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)100 101#define HCLGE_TQP_RESET_TRY_TIMES 200102 103#define HCLGE_PHY_PAGE_MDIX 0104#define HCLGE_PHY_PAGE_COPPER 0105 106/* Page Selection Reg. */107#define HCLGE_PHY_PAGE_REG 22108 109/* Copper Specific Control Register */110#define HCLGE_PHY_CSC_REG 16111 112/* Copper Specific Status Register */113#define HCLGE_PHY_CSS_REG 17114 115#define HCLGE_PHY_MDIX_CTRL_S 5116#define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)117 118#define HCLGE_PHY_MDIX_STATUS_B 6119#define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11120 121#define HCLGE_GET_DFX_REG_TYPE_CNT 4122 123/* Factor used to calculate offset and bitmap of VF num */124#define HCLGE_VF_NUM_PER_CMD 64125 126#define HCLGE_MAX_QSET_NUM 1024127 128#define HCLGE_DBG_RESET_INFO_LEN 1024129 130enum HLCGE_PORT_TYPE {131 HOST_PORT,132 NETWORK_PORT133};134 135#define PF_VPORT_ID 0136 137#define HCLGE_PF_ID_S 0138#define HCLGE_PF_ID_M GENMASK(2, 0)139#define HCLGE_VF_ID_S 3140#define HCLGE_VF_ID_M GENMASK(10, 3)141#define HCLGE_PORT_TYPE_B 11142#define HCLGE_NETWORK_PORT_ID_S 0143#define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)144 145/* Reset related Registers */146#define HCLGE_PF_OTHER_INT_REG 0x20600147#define HCLGE_MISC_RESET_STS_REG 0x20700148#define HCLGE_MISC_VECTOR_INT_STS 0x20800149#define HCLGE_GLOBAL_RESET_REG 0x20A00150#define HCLGE_GLOBAL_RESET_BIT 0151#define HCLGE_CORE_RESET_BIT 1152#define HCLGE_IMP_RESET_BIT 2153#define HCLGE_RESET_INT_M GENMASK(7, 5)154#define HCLGE_FUN_RST_ING 0x20C00155#define HCLGE_FUN_RST_ING_B 0156 157/* Vector0 register bits define */158#define HCLGE_VECTOR0_REG_PTP_INT_B 0159#define HCLGE_VECTOR0_GLOBALRESET_INT_B 5160#define HCLGE_VECTOR0_CORERESET_INT_B 6161#define HCLGE_VECTOR0_IMPRESET_INT_B 7162 163/* Vector0 interrupt CMDQ event source register(RW) */164#define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100165/* CMDQ register bits for RX event(=MBX event) */166#define HCLGE_VECTOR0_RX_CMDQ_INT_B 1167 168#define HCLGE_VECTOR0_IMP_RESET_INT_B 1169#define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U170#define HCLGE_VECTOR0_IMP_RD_POISON_B 5U171#define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U172#define HCLGE_TRIGGER_IMP_RESET_B 7U173 174#define HCLGE_TQP_MEM_SIZE 0x10000175#define HCLGE_MEM_BAR 4176/* in the bar4, the first half is for roce, and the second half is for nic */177#define HCLGE_NIC_MEM_OFFSET(hdev) \178 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1)179#define HCLGE_TQP_MEM_OFFSET(hdev, i) \180 (HCLGE_NIC_MEM_OFFSET(hdev) + HCLGE_TQP_MEM_SIZE * (i))181 182#define HCLGE_MAC_DEFAULT_FRAME \183 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)184#define HCLGE_MAC_MIN_FRAME 64185#define HCLGE_MAC_MAX_FRAME 9728186 187#define HCLGE_SUPPORT_1G_BIT BIT(0)188#define HCLGE_SUPPORT_10G_BIT BIT(1)189#define HCLGE_SUPPORT_25G_BIT BIT(2)190#define HCLGE_SUPPORT_50G_R2_BIT BIT(3)191#define HCLGE_SUPPORT_100G_R4_BIT BIT(4)192/* to be compatible with exsit board */193#define HCLGE_SUPPORT_40G_BIT BIT(5)194#define HCLGE_SUPPORT_100M_BIT BIT(6)195#define HCLGE_SUPPORT_10M_BIT BIT(7)196#define HCLGE_SUPPORT_200G_R4_EXT_BIT BIT(8)197#define HCLGE_SUPPORT_50G_R1_BIT BIT(9)198#define HCLGE_SUPPORT_100G_R2_BIT BIT(10)199#define HCLGE_SUPPORT_200G_R4_BIT BIT(11)200 201#define HCLGE_SUPPORT_GE \202 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)203#define HCLGE_SUPPORT_50G_BITS \204 (HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT)205#define HCLGE_SUPPORT_100G_BITS \206 (HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT)207#define HCLGE_SUPPORT_200G_BITS \208 (HCLGE_SUPPORT_200G_R4_EXT_BIT | HCLGE_SUPPORT_200G_R4_BIT)209 210enum HCLGE_DEV_STATE {211 HCLGE_STATE_REINITING,212 HCLGE_STATE_DOWN,213 HCLGE_STATE_DISABLED,214 HCLGE_STATE_REMOVING,215 HCLGE_STATE_NIC_REGISTERED,216 HCLGE_STATE_ROCE_REGISTERED,217 HCLGE_STATE_SERVICE_INITED,218 HCLGE_STATE_RST_SERVICE_SCHED,219 HCLGE_STATE_RST_HANDLING,220 HCLGE_STATE_MBX_SERVICE_SCHED,221 HCLGE_STATE_MBX_HANDLING,222 HCLGE_STATE_ERR_SERVICE_SCHED,223 HCLGE_STATE_STATISTICS_UPDATING,224 HCLGE_STATE_LINK_UPDATING,225 HCLGE_STATE_RST_FAIL,226 HCLGE_STATE_FD_TBL_CHANGED,227 HCLGE_STATE_FD_CLEAR_ALL,228 HCLGE_STATE_FD_USER_DEF_CHANGED,229 HCLGE_STATE_PTP_EN,230 HCLGE_STATE_PTP_TX_HANDLING,231 HCLGE_STATE_FEC_STATS_UPDATING,232 HCLGE_STATE_MAX233};234 235enum hclge_evt_cause {236 HCLGE_VECTOR0_EVENT_RST,237 HCLGE_VECTOR0_EVENT_MBX,238 HCLGE_VECTOR0_EVENT_ERR,239 HCLGE_VECTOR0_EVENT_PTP,240 HCLGE_VECTOR0_EVENT_OTHER,241};242 243enum HCLGE_MAC_SPEED {244 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */245 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */246 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */252 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */253 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */254};255 256enum HCLGE_MAC_DUPLEX {257 HCLGE_MAC_HALF,258 HCLGE_MAC_FULL259};260 261/* hilink version */262enum hclge_hilink_version {263 HCLGE_HILINK_H32 = 0,264 HCLGE_HILINK_H60 = 1,265};266 267#define QUERY_SFP_SPEED 0268#define QUERY_ACTIVE_SPEED 1269 270struct hclge_wol_info {271 u32 wol_support_mode; /* store the wake on lan info */272 u32 wol_current_mode;273 u8 wol_sopass[SOPASS_MAX];274 u8 wol_sopass_size;275};276 277struct hclge_mac {278 u8 mac_id;279 u8 phy_addr;280 u8 flag;281 u8 media_type; /* port media type, e.g. fibre/copper/backplane */282 u8 mac_addr[ETH_ALEN];283 u8 autoneg;284 u8 req_autoneg;285 u8 duplex;286 u8 req_duplex;287 u8 support_autoneg;288 u8 speed_type; /* 0: sfp speed, 1: active speed */289 u8 lane_num;290 u32 speed;291 u32 req_speed;292 u32 max_speed;293 u32 speed_ability; /* speed ability supported by current media */294 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */295 u32 fec_mode; /* active fec mode */296 u32 user_fec_mode;297 u32 fec_ability;298 int link; /* store the link status of mac & phy (if phy exists) */299 struct hclge_wol_info wol;300 struct phy_device *phydev;301 struct mii_bus *mdio_bus;302 phy_interface_t phy_if;303 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);304 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);305};306 307struct hclge_hw {308 struct hclge_comm_hw hw;309 struct hclge_mac mac;310 int num_vec;311};312 313enum hclge_fc_mode {314 HCLGE_FC_NONE,315 HCLGE_FC_RX_PAUSE,316 HCLGE_FC_TX_PAUSE,317 HCLGE_FC_FULL,318 HCLGE_FC_PFC,319 HCLGE_FC_DEFAULT320};321 322#define HCLGE_FILTER_TYPE_VF 0323#define HCLGE_FILTER_TYPE_PORT 1324#define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)325#define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)326#define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)327#define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)328#define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)329#define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \330 | HCLGE_FILTER_FE_ROCE_EGRESS_B)331#define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \332 | HCLGE_FILTER_FE_ROCE_INGRESS_B)333 334enum hclge_vlan_fltr_cap {335 HCLGE_VLAN_FLTR_DEF,336 HCLGE_VLAN_FLTR_CAN_MDF,337};338enum hclge_link_fail_code {339 HCLGE_LF_NORMAL,340 HCLGE_LF_REF_CLOCK_LOST,341 HCLGE_LF_XSFP_TX_DISABLE,342 HCLGE_LF_XSFP_ABSENT,343};344 345#define HCLGE_LINK_STATUS_DOWN 0346#define HCLGE_LINK_STATUS_UP 1347 348#define HCLGE_PG_NUM 4349#define HCLGE_SCH_MODE_SP 0350#define HCLGE_SCH_MODE_DWRR 1351struct hclge_pg_info {352 u8 pg_id;353 u8 pg_sch_mode; /* 0: sp; 1: dwrr */354 u8 tc_bit_map;355 u32 bw_limit;356 u8 tc_dwrr[HNAE3_MAX_TC];357};358 359struct hclge_tc_info {360 u8 tc_id;361 u8 tc_sch_mode; /* 0: sp; 1: dwrr */362 u8 pgid;363 u32 bw_limit;364};365 366struct hclge_cfg {367 u8 tc_num;368 u8 vlan_fliter_cap;369 u16 tqp_desc_num;370 u16 rx_buf_len;371 u16 vf_rss_size_max;372 u16 pf_rss_size_max;373 u8 phy_addr;374 u8 media_type;375 u8 mac_addr[ETH_ALEN];376 u8 default_speed;377 u32 numa_node_map;378 u32 tx_spare_buf_size;379 u16 speed_ability;380 u16 umv_space;381};382 383struct hclge_tm_info {384 u8 num_tc;385 u8 num_pg; /* It must be 1 if vNET-Base schd */386 u8 pg_dwrr[HCLGE_PG_NUM];387 u8 prio_tc[HNAE3_MAX_USER_PRIO];388 struct hclge_pg_info pg_info[HCLGE_PG_NUM];389 struct hclge_tc_info tc_info[HNAE3_MAX_TC];390 enum hclge_fc_mode fc_mode;391 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */392 u8 pfc_en; /* PFC enabled or not for user priority */393};394 395/* max number of mac statistics on each version */396#define HCLGE_MAC_STATS_MAX_NUM_V1 87397#define HCLGE_MAC_STATS_MAX_NUM_V2 105398 399struct hclge_comm_stats_str {400 char desc[ETH_GSTRING_LEN];401 u32 stats_num;402 unsigned long offset;403};404 405/* mac stats ,opcode id: 0x0032 */406struct hclge_mac_stats {407 u64 mac_tx_mac_pause_num;408 u64 mac_rx_mac_pause_num;409 u64 rsv0;410 u64 mac_tx_pfc_pri0_pkt_num;411 u64 mac_tx_pfc_pri1_pkt_num;412 u64 mac_tx_pfc_pri2_pkt_num;413 u64 mac_tx_pfc_pri3_pkt_num;414 u64 mac_tx_pfc_pri4_pkt_num;415 u64 mac_tx_pfc_pri5_pkt_num;416 u64 mac_tx_pfc_pri6_pkt_num;417 u64 mac_tx_pfc_pri7_pkt_num;418 u64 mac_rx_pfc_pri0_pkt_num;419 u64 mac_rx_pfc_pri1_pkt_num;420 u64 mac_rx_pfc_pri2_pkt_num;421 u64 mac_rx_pfc_pri3_pkt_num;422 u64 mac_rx_pfc_pri4_pkt_num;423 u64 mac_rx_pfc_pri5_pkt_num;424 u64 mac_rx_pfc_pri6_pkt_num;425 u64 mac_rx_pfc_pri7_pkt_num;426 u64 mac_tx_total_pkt_num;427 u64 mac_tx_total_oct_num;428 u64 mac_tx_good_pkt_num;429 u64 mac_tx_bad_pkt_num;430 u64 mac_tx_good_oct_num;431 u64 mac_tx_bad_oct_num;432 u64 mac_tx_uni_pkt_num;433 u64 mac_tx_multi_pkt_num;434 u64 mac_tx_broad_pkt_num;435 u64 mac_tx_undersize_pkt_num;436 u64 mac_tx_oversize_pkt_num;437 u64 mac_tx_64_oct_pkt_num;438 u64 mac_tx_65_127_oct_pkt_num;439 u64 mac_tx_128_255_oct_pkt_num;440 u64 mac_tx_256_511_oct_pkt_num;441 u64 mac_tx_512_1023_oct_pkt_num;442 u64 mac_tx_1024_1518_oct_pkt_num;443 u64 mac_tx_1519_2047_oct_pkt_num;444 u64 mac_tx_2048_4095_oct_pkt_num;445 u64 mac_tx_4096_8191_oct_pkt_num;446 u64 rsv1;447 u64 mac_tx_8192_9216_oct_pkt_num;448 u64 mac_tx_9217_12287_oct_pkt_num;449 u64 mac_tx_12288_16383_oct_pkt_num;450 u64 mac_tx_1519_max_good_oct_pkt_num;451 u64 mac_tx_1519_max_bad_oct_pkt_num;452 453 u64 mac_rx_total_pkt_num;454 u64 mac_rx_total_oct_num;455 u64 mac_rx_good_pkt_num;456 u64 mac_rx_bad_pkt_num;457 u64 mac_rx_good_oct_num;458 u64 mac_rx_bad_oct_num;459 u64 mac_rx_uni_pkt_num;460 u64 mac_rx_multi_pkt_num;461 u64 mac_rx_broad_pkt_num;462 u64 mac_rx_undersize_pkt_num;463 u64 mac_rx_oversize_pkt_num;464 u64 mac_rx_64_oct_pkt_num;465 u64 mac_rx_65_127_oct_pkt_num;466 u64 mac_rx_128_255_oct_pkt_num;467 u64 mac_rx_256_511_oct_pkt_num;468 u64 mac_rx_512_1023_oct_pkt_num;469 u64 mac_rx_1024_1518_oct_pkt_num;470 u64 mac_rx_1519_2047_oct_pkt_num;471 u64 mac_rx_2048_4095_oct_pkt_num;472 u64 mac_rx_4096_8191_oct_pkt_num;473 u64 rsv2;474 u64 mac_rx_8192_9216_oct_pkt_num;475 u64 mac_rx_9217_12287_oct_pkt_num;476 u64 mac_rx_12288_16383_oct_pkt_num;477 u64 mac_rx_1519_max_good_oct_pkt_num;478 u64 mac_rx_1519_max_bad_oct_pkt_num;479 480 u64 mac_tx_fragment_pkt_num;481 u64 mac_tx_undermin_pkt_num;482 u64 mac_tx_jabber_pkt_num;483 u64 mac_tx_err_all_pkt_num;484 u64 mac_tx_from_app_good_pkt_num;485 u64 mac_tx_from_app_bad_pkt_num;486 u64 mac_rx_fragment_pkt_num;487 u64 mac_rx_undermin_pkt_num;488 u64 mac_rx_jabber_pkt_num;489 u64 mac_rx_fcs_err_pkt_num;490 u64 mac_rx_send_app_good_pkt_num;491 u64 mac_rx_send_app_bad_pkt_num;492 u64 mac_tx_pfc_pause_pkt_num;493 u64 mac_rx_pfc_pause_pkt_num;494 u64 mac_tx_ctrl_pkt_num;495 u64 mac_rx_ctrl_pkt_num;496 497 /* duration of pfc */498 u64 mac_tx_pfc_pri0_xoff_time;499 u64 mac_tx_pfc_pri1_xoff_time;500 u64 mac_tx_pfc_pri2_xoff_time;501 u64 mac_tx_pfc_pri3_xoff_time;502 u64 mac_tx_pfc_pri4_xoff_time;503 u64 mac_tx_pfc_pri5_xoff_time;504 u64 mac_tx_pfc_pri6_xoff_time;505 u64 mac_tx_pfc_pri7_xoff_time;506 u64 mac_rx_pfc_pri0_xoff_time;507 u64 mac_rx_pfc_pri1_xoff_time;508 u64 mac_rx_pfc_pri2_xoff_time;509 u64 mac_rx_pfc_pri3_xoff_time;510 u64 mac_rx_pfc_pri4_xoff_time;511 u64 mac_rx_pfc_pri5_xoff_time;512 u64 mac_rx_pfc_pri6_xoff_time;513 u64 mac_rx_pfc_pri7_xoff_time;514 515 /* duration of pause */516 u64 mac_tx_pause_xoff_time;517 u64 mac_rx_pause_xoff_time;518};519 520#define HCLGE_STATS_TIMER_INTERVAL 300UL521 522/* fec stats ,opcode id: 0x0316 */523#define HCLGE_FEC_STATS_MAX_LANES 8524struct hclge_fec_stats {525 /* fec rs mode total stats */526 u64 rs_corr_blocks;527 u64 rs_uncorr_blocks;528 u64 rs_error_blocks;529 /* fec base-r mode per lanes stats */530 u64 base_r_lane_num;531 u64 base_r_corr_blocks;532 u64 base_r_uncorr_blocks;533 union {534 struct {535 u64 base_r_corr_per_lanes[HCLGE_FEC_STATS_MAX_LANES];536 u64 base_r_uncorr_per_lanes[HCLGE_FEC_STATS_MAX_LANES];537 };538 u64 per_lanes[HCLGE_FEC_STATS_MAX_LANES * 2];539 };540};541 542struct hclge_vlan_type_cfg {543 u16 rx_ot_fst_vlan_type;544 u16 rx_ot_sec_vlan_type;545 u16 rx_in_fst_vlan_type;546 u16 rx_in_sec_vlan_type;547 u16 tx_ot_vlan_type;548 u16 tx_in_vlan_type;549};550 551enum HCLGE_FD_MODE {552 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,553 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,554 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,555 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,556};557 558enum HCLGE_FD_KEY_TYPE {559 HCLGE_FD_KEY_BASE_ON_PTYPE,560 HCLGE_FD_KEY_BASE_ON_TUPLE,561};562 563enum HCLGE_FD_STAGE {564 HCLGE_FD_STAGE_1,565 HCLGE_FD_STAGE_2,566 MAX_STAGE_NUM,567};568 569/* OUTER_XXX indicates tuples in tunnel header of tunnel packet570 * INNER_XXX indicate tuples in tunneled header of tunnel packet or571 * tuples of non-tunnel packet572 */573enum HCLGE_FD_TUPLE {574 OUTER_DST_MAC,575 OUTER_SRC_MAC,576 OUTER_VLAN_TAG_FST,577 OUTER_VLAN_TAG_SEC,578 OUTER_ETH_TYPE,579 OUTER_L2_RSV,580 OUTER_IP_TOS,581 OUTER_IP_PROTO,582 OUTER_SRC_IP,583 OUTER_DST_IP,584 OUTER_L3_RSV,585 OUTER_SRC_PORT,586 OUTER_DST_PORT,587 OUTER_L4_RSV,588 OUTER_TUN_VNI,589 OUTER_TUN_FLOW_ID,590 INNER_DST_MAC,591 INNER_SRC_MAC,592 INNER_VLAN_TAG_FST,593 INNER_VLAN_TAG_SEC,594 INNER_ETH_TYPE,595 INNER_L2_RSV,596 INNER_IP_TOS,597 INNER_IP_PROTO,598 INNER_SRC_IP,599 INNER_DST_IP,600 INNER_L3_RSV,601 INNER_SRC_PORT,602 INNER_DST_PORT,603 INNER_L4_RSV,604 MAX_TUPLE,605};606 607#define HCLGE_FD_TUPLE_USER_DEF_TUPLES \608 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV))609 610enum HCLGE_FD_META_DATA {611 PACKET_TYPE_ID,612 IP_FRAGEMENT,613 ROCE_TYPE,614 NEXT_KEY,615 VLAN_NUMBER,616 SRC_VPORT,617 DST_VPORT,618 TUNNEL_PACKET,619 MAX_META_DATA,620};621 622enum HCLGE_FD_KEY_OPT {623 KEY_OPT_U8,624 KEY_OPT_LE16,625 KEY_OPT_LE32,626 KEY_OPT_MAC,627 KEY_OPT_IP,628 KEY_OPT_VNI,629};630 631struct key_info {632 u8 key_type;633 u8 key_length; /* use bit as unit */634 enum HCLGE_FD_KEY_OPT key_opt;635 int offset;636 int moffset;637};638 639#define MAX_KEY_LENGTH 400640#define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)641#define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)642#define MAX_META_DATA_LENGTH 32643 644#define HCLGE_FD_MAX_USER_DEF_OFFSET 9000645#define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0)646#define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0)647#define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0)648 649/* assigned by firmware, the real filter number for each pf may be less */650#define MAX_FD_FILTER_NUM 4096651#define HCLGE_ARFS_EXPIRE_INTERVAL 5UL652 653#define hclge_read_dev(a, reg) \654 hclge_comm_read_reg((a)->hw.io_base, reg)655#define hclge_write_dev(a, reg, value) \656 hclge_comm_write_reg((a)->hw.io_base, reg, value)657 658enum HCLGE_FD_ACTIVE_RULE_TYPE {659 HCLGE_FD_RULE_NONE,660 HCLGE_FD_ARFS_ACTIVE,661 HCLGE_FD_EP_ACTIVE,662 HCLGE_FD_TC_FLOWER_ACTIVE,663};664 665enum HCLGE_FD_PACKET_TYPE {666 NIC_PACKET,667 ROCE_PACKET,668};669 670enum HCLGE_FD_ACTION {671 HCLGE_FD_ACTION_SELECT_QUEUE,672 HCLGE_FD_ACTION_DROP_PACKET,673 HCLGE_FD_ACTION_SELECT_TC,674};675 676enum HCLGE_FD_NODE_STATE {677 HCLGE_FD_TO_ADD,678 HCLGE_FD_TO_DEL,679 HCLGE_FD_ACTIVE,680 HCLGE_FD_DELETED,681};682 683enum HCLGE_FD_USER_DEF_LAYER {684 HCLGE_FD_USER_DEF_NONE,685 HCLGE_FD_USER_DEF_L2,686 HCLGE_FD_USER_DEF_L3,687 HCLGE_FD_USER_DEF_L4,688};689 690#define HCLGE_FD_USER_DEF_LAYER_NUM 3691struct hclge_fd_user_def_cfg {692 u16 ref_cnt;693 u16 offset;694};695 696struct hclge_fd_user_def_info {697 enum HCLGE_FD_USER_DEF_LAYER layer;698 u16 data;699 u16 data_mask;700 u16 offset;701};702 703struct hclge_fd_key_cfg {704 u8 key_sel;705 u8 inner_sipv6_word_en;706 u8 inner_dipv6_word_en;707 u8 outer_sipv6_word_en;708 u8 outer_dipv6_word_en;709 u32 tuple_active;710 u32 meta_data_active;711};712 713struct hclge_fd_cfg {714 u8 fd_mode;715 u16 max_key_length; /* use bit as unit */716 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */717 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */718 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];719 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM];720};721 722#define IPV4_INDEX 3723 724struct hclge_fd_rule_tuples {725 u8 src_mac[ETH_ALEN];726 u8 dst_mac[ETH_ALEN];727 /* Be compatible for ip address of both ipv4 and ipv6.728 * For ipv4 address, we store it in src/dst_ip[3].729 */730 u32 src_ip[IPV6_ADDR_WORDS];731 u32 dst_ip[IPV6_ADDR_WORDS];732 u16 src_port;733 u16 dst_port;734 u16 vlan_tag1;735 u16 ether_proto;736 u16 l2_user_def;737 u16 l3_user_def;738 u32 l4_user_def;739 u8 ip_tos;740 u8 ip_proto;741};742 743struct hclge_fd_rule {744 struct hlist_node rule_node;745 struct hclge_fd_rule_tuples tuples;746 struct hclge_fd_rule_tuples tuples_mask;747 u32 unused_tuple;748 u32 flow_type;749 union {750 struct {751 unsigned long cookie;752 u8 tc;753 } cls_flower;754 struct {755 u16 flow_id; /* only used for arfs */756 } arfs;757 struct {758 struct hclge_fd_user_def_info user_def;759 } ep;760 };761 u16 queue_id;762 u16 vf_id;763 u16 location;764 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;765 enum HCLGE_FD_NODE_STATE state;766 u8 action;767};768 769struct hclge_fd_ad_data {770 u16 ad_id;771 u8 drop_packet;772 u8 forward_to_direct_queue;773 u16 queue_id;774 u8 use_counter;775 u8 counter_id;776 u8 use_next_stage;777 u8 write_rule_id_to_bd;778 u8 next_input_key;779 u16 rule_id;780 u16 tc_size;781 u8 override_tc;782};783 784enum HCLGE_MAC_NODE_STATE {785 HCLGE_MAC_TO_ADD,786 HCLGE_MAC_TO_DEL,787 HCLGE_MAC_ACTIVE788};789 790struct hclge_mac_node {791 struct list_head node;792 enum HCLGE_MAC_NODE_STATE state;793 u8 mac_addr[ETH_ALEN];794};795 796enum HCLGE_MAC_ADDR_TYPE {797 HCLGE_MAC_ADDR_UC,798 HCLGE_MAC_ADDR_MC799};800 801struct hclge_vport_vlan_cfg {802 struct list_head node;803 int hd_tbl_status;804 u16 vlan_id;805};806 807struct hclge_rst_stats {808 u32 reset_done_cnt; /* the number of reset has completed */809 u32 hw_reset_done_cnt; /* the number of HW reset has completed */810 u32 pf_rst_cnt; /* the number of PF reset */811 u32 flr_rst_cnt; /* the number of FLR */812 u32 global_rst_cnt; /* the number of GLOBAL */813 u32 imp_rst_cnt; /* the number of IMP reset */814 u32 reset_cnt; /* the number of reset */815 u32 reset_fail_cnt; /* the number of reset fail */816};817 818/* time and register status when mac tunnel interruption occur */819struct hclge_mac_tnl_stats {820 u64 time;821 u32 status;822};823 824#define HCLGE_RESET_INTERVAL (10 * HZ)825#define HCLGE_WAIT_RESET_DONE 100826 827#pragma pack(1)828struct hclge_vf_vlan_cfg {829 u8 mbx_cmd;830 u8 subcode;831 union {832 struct {833 u8 is_kill;834 __le16 vlan;835 __le16 proto;836 };837 u8 enable;838 };839};840 841#pragma pack()842 843/* For each bit of TCAM entry, it uses a pair of 'x' and844 * 'y' to indicate which value to match, like below:845 * ----------------------------------846 * | bit x | bit y | search value |847 * ----------------------------------848 * | 0 | 0 | always hit |849 * ----------------------------------850 * | 1 | 0 | match '0' |851 * ----------------------------------852 * | 0 | 1 | match '1' |853 * ----------------------------------854 * | 1 | 1 | invalid |855 * ----------------------------------856 * Then for input key(k) and mask(v), we can calculate the value by857 * the formulae:858 * x = (~k) & v859 * y = k & v860 */861#define calc_x(x, k, v) ((x) = ~(k) & (v))862#define calc_y(y, k, v) ((y) = (k) & (v))863 864#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))865#define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset)))866 867#define HCLGE_MAC_TNL_LOG_SIZE 8868#define HCLGE_VPORT_NUM 256869struct hclge_dev {870 struct pci_dev *pdev;871 struct hnae3_ae_dev *ae_dev;872 struct hclge_hw hw;873 struct hclge_misc_vector misc_vector;874 struct hclge_mac_stats mac_stats;875 struct hclge_fec_stats fec_stats;876 unsigned long state;877 unsigned long flr_state;878 unsigned long last_reset_time;879 880 enum hnae3_reset_type reset_type;881 enum hnae3_reset_type reset_level;882 unsigned long default_reset_request;883 unsigned long reset_request; /* reset has been requested */884 unsigned long reset_pending; /* client rst is pending to be served */885 struct hclge_rst_stats rst_stats;886 struct semaphore reset_sem; /* protect reset process */887 u32 fw_version;888 u16 num_tqps; /* Num task queue pairs of this PF */889 u16 num_req_vfs; /* Num VFs requested for this PF */890 891 u16 base_tqp_pid; /* Base task tqp physical id of this PF */892 u16 alloc_rss_size; /* Allocated RSS task queue */893 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */894 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */895 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */896 897 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */898 u16 num_alloc_vport; /* Num vports this driver supports */899 nodemask_t numa_node_mask;900 u16 rx_buf_len;901 u16 num_tx_desc; /* desc num of per tx queue */902 u16 num_rx_desc; /* desc num of per rx queue */903 u8 hw_tc_map;904 enum hclge_fc_mode fc_mode_last_time;905 u8 support_sfp_query;906 907#define HCLGE_FLAG_TC_BASE_SCH_MODE 1908#define HCLGE_FLAG_VNET_BASE_SCH_MODE 2909 u8 tx_sch_mode;910 u8 tc_max;911 u8 pfc_max;912 913 u8 default_up;914 u8 dcbx_cap;915 struct hclge_tm_info tm_info;916 917 u16 num_msi;918 u16 num_msi_left;919 u16 num_msi_used;920 u16 *vector_status;921 int *vector_irq;922 u16 num_nic_msi; /* Num of nic vectors for this PF */923 u16 num_roce_msi; /* Num of roce vectors for this PF */924 925 unsigned long service_timer_period;926 unsigned long service_timer_previous;927 struct timer_list reset_timer;928 struct delayed_work service_task;929 930 bool cur_promisc;931 int num_alloc_vfs; /* Actual number of VFs allocated */932 933 struct hclge_comm_tqp *htqp;934 struct hclge_vport *vport;935 936 struct dentry *hclge_dbgfs;937 938 struct hnae3_client *nic_client;939 struct hnae3_client *roce_client;940 941#define HCLGE_FLAG_MAIN BIT(0)942#define HCLGE_FLAG_DCB_CAPABLE BIT(1)943 u32 flag;944 945 u32 pkt_buf_size; /* Total pf buf size for tx/rx */946 u32 tx_buf_size; /* Tx buffer size for each TC */947 u32 dv_buf_size; /* Dv buffer size for each TC */948 949 u32 mps; /* Max packet size */950 /* vport_lock protect resource shared by vports */951 struct mutex vport_lock;952 953 struct hclge_vlan_type_cfg vlan_type_cfg;954 955 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];956 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];957 958 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];959 960 struct hclge_fd_cfg fd_cfg;961 struct hlist_head fd_rule_list;962 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */963 u16 hclge_fd_rule_num;964 unsigned long serv_processed_cnt;965 unsigned long last_serv_processed;966 unsigned long last_rst_scheduled;967 unsigned long last_mbx_scheduled;968 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];969 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;970 u8 fd_en;971 bool gro_en;972 973 u16 wanted_umv_size;974 /* max available unicast mac vlan space */975 u16 max_umv_size;976 /* private unicast mac vlan space, it's same for PF and its VFs */977 u16 priv_umv_size;978 /* unicast mac vlan space shared by PF and its VFs */979 u16 share_umv_size;980 /* multicast mac address number used by PF and its VFs */981 u16 used_mc_mac_num;982 983 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,984 HCLGE_MAC_TNL_LOG_SIZE);985 986 struct hclge_ptp *ptp;987 struct devlink *devlink;988 struct hclge_comm_rss_cfg rss_cfg;989};990 991/* VPort level vlan tag configuration for TX direction */992struct hclge_tx_vtag_cfg {993 bool accept_tag1; /* Whether accept tag1 packet from host */994 bool accept_untag1; /* Whether accept untag1 packet from host */995 bool accept_tag2;996 bool accept_untag2;997 bool insert_tag1_en; /* Whether insert inner vlan tag */998 bool insert_tag2_en; /* Whether insert outer vlan tag */999 u16 default_tag1; /* The default inner vlan tag to insert */1000 u16 default_tag2; /* The default outer vlan tag to insert */1001 bool tag_shift_mode_en;1002};1003 1004/* VPort level vlan tag configuration for RX direction */1005struct hclge_rx_vtag_cfg {1006 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */1007 bool strip_tag1_en; /* Whether strip inner vlan tag */1008 bool strip_tag2_en; /* Whether strip outer vlan tag */1009 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */1010 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */1011 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */1012 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */1013};1014 1015enum HCLGE_VPORT_STATE {1016 HCLGE_VPORT_STATE_ALIVE,1017 HCLGE_VPORT_STATE_MAC_TBL_CHANGE,1018 HCLGE_VPORT_STATE_PROMISC_CHANGE,1019 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,1020 HCLGE_VPORT_STATE_INITED,1021 HCLGE_VPORT_STATE_MAX1022};1023 1024enum HCLGE_VPORT_NEED_NOTIFY {1025 HCLGE_VPORT_NEED_NOTIFY_RESET,1026 HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,1027};1028 1029struct hclge_vlan_info {1030 u16 vlan_proto; /* so far support 802.1Q only */1031 u16 qos;1032 u16 vlan_tag;1033};1034 1035struct hclge_port_base_vlan_config {1036 u16 state;1037 bool tbl_sta;1038 struct hclge_vlan_info vlan_info;1039 struct hclge_vlan_info old_vlan_info;1040};1041 1042struct hclge_vf_info {1043 int link_state;1044 u8 mac[ETH_ALEN];1045 u32 spoofchk;1046 u32 max_tx_rate;1047 u32 trusted;1048 u8 request_uc_en;1049 u8 request_mc_en;1050 u8 request_bc_en;1051};1052 1053struct hclge_vport {1054 u16 alloc_tqps; /* Allocated Tx/Rx queues */1055 1056 u16 qs_offset;1057 u32 bw_limit; /* VSI BW Limit (0 = disabled) */1058 u8 dwrr;1059 1060 bool req_vlan_fltr_en;1061 bool cur_vlan_fltr_en;1062 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];1063 struct hclge_port_base_vlan_config port_base_vlan_cfg;1064 struct hclge_tx_vtag_cfg txvlan_cfg;1065 struct hclge_rx_vtag_cfg rxvlan_cfg;1066 1067 u16 used_umv_num;1068 1069 u16 vport_id;1070 struct hclge_dev *back; /* Back reference to associated dev */1071 struct hnae3_handle nic;1072 struct hnae3_handle roce;1073 1074 unsigned long state;1075 unsigned long need_notify;1076 unsigned long last_active_jiffies;1077 u32 mps; /* Max packet size */1078 struct hclge_vf_info vf_info;1079 1080 u8 overflow_promisc_flags;1081 u8 last_promisc_flags;1082 1083 spinlock_t mac_list_lock; /* protect mac address need to add/detele */1084 struct list_head uc_mac_list; /* Store VF unicast table */1085 struct list_head mc_mac_list; /* Store VF multicast table */1086 1087 struct list_head vlan_list; /* Store VF vlan table */1088};1089 1090struct hclge_speed_bit_map {1091 u32 speed;1092 u32 speed_bit;1093};1094 1095struct hclge_mac_speed_map {1096 u32 speed_drv; /* speed defined in driver */1097 u32 speed_fw; /* speed defined in firmware */1098};1099 1100struct hclge_link_mode_bmap {1101 u16 support_bit;1102 enum ethtool_link_mode_bit_indices link_mode;1103};1104 1105int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,1106 bool en_mc_pmc, bool en_bc_pmc);1107int hclge_add_uc_addr_common(struct hclge_vport *vport,1108 const unsigned char *addr);1109int hclge_rm_uc_addr_common(struct hclge_vport *vport,1110 const unsigned char *addr);1111int hclge_add_mc_addr_common(struct hclge_vport *vport,1112 const unsigned char *addr);1113int hclge_rm_mc_addr_common(struct hclge_vport *vport,1114 const unsigned char *addr);1115 1116struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);1117int hclge_bind_ring_with_vector(struct hclge_vport *vport,1118 int vector_id, bool en,1119 struct hnae3_ring_chain_node *ring_chain);1120 1121static inline int hclge_get_queue_id(struct hnae3_queue *queue)1122{1123 struct hclge_comm_tqp *tqp =1124 container_of(queue, struct hclge_comm_tqp, q);1125 1126 return tqp->index;1127}1128 1129int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);1130int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num);1131int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,1132 u16 vlan_id, bool is_kill);1133int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);1134 1135int hclge_buffer_alloc(struct hclge_dev *hdev);1136int hclge_rss_init_hw(struct hclge_dev *hdev);1137 1138void hclge_mbx_handler(struct hclge_dev *hdev);1139int hclge_reset_tqp(struct hnae3_handle *handle);1140int hclge_cfg_flowctrl(struct hclge_dev *hdev);1141int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);1142int hclge_vport_start(struct hclge_vport *vport);1143void hclge_vport_stop(struct hclge_vport *vport);1144int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);1145int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,1146 char *buf, int len);1147u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);1148int hclge_notify_client(struct hclge_dev *hdev,1149 enum hnae3_reset_notify_type type);1150int hclge_update_mac_list(struct hclge_vport *vport,1151 enum HCLGE_MAC_NODE_STATE state,1152 enum HCLGE_MAC_ADDR_TYPE mac_type,1153 const unsigned char *addr);1154int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,1155 const u8 *old_addr, const u8 *new_addr);1156void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,1157 enum HCLGE_MAC_ADDR_TYPE mac_type);1158void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);1159void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);1160void hclge_restore_mac_table_common(struct hclge_vport *vport);1161void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev);1162void hclge_restore_vport_vlan_table(struct hclge_vport *vport);1163int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,1164 struct hclge_vlan_info *vlan_info);1165int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,1166 u16 state,1167 struct hclge_vlan_info *vlan_info);1168void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);1169void hclge_report_hw_error(struct hclge_dev *hdev,1170 enum hnae3_hw_error_type type);1171int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len);1172int hclge_push_vf_link_status(struct hclge_vport *vport);1173int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);1174int hclge_mac_update_stats(struct hclge_dev *hdev);1175struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf);1176int hclge_inform_vf_reset(struct hclge_vport *vport, u16 reset_type);1177int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version);1178#endif1179