brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0+2// Copyright (c) 2016-2017 Hisilicon Limited.3 4#include <linux/etherdevice.h>5#include <linux/iopoll.h>6#include <net/rtnetlink.h>7#include "hclgevf_cmd.h"8#include "hclgevf_main.h"9#include "hclgevf_regs.h"10#include "hclge_mbx.h"11#include "hnae3.h"12#include "hclgevf_devlink.h"13#include "hclge_comm_rss.h"14#include "hclgevf_trace.h"15 16#define HCLGEVF_NAME	"hclgevf"17 18#define HCLGEVF_RESET_MAX_FAIL_CNT	519 20static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);21static void hclgevf_task_schedule(struct hclgevf_dev *hdev,22				  unsigned long delay);23 24static struct hnae3_ae_algo ae_algovf;25 26static struct workqueue_struct *hclgevf_wq;27 28static const struct pci_device_id ae_algovf_pci_tbl[] = {29	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},30	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),31	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},32	/* required last entry */33	{0, }34};35 36MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);37 38/* hclgevf_cmd_send - send command to command queue39 * @hw: pointer to the hw struct40 * @desc: prefilled descriptor for describing the command41 * @num : the number of descriptors to be sent42 *43 * This is the main send command for command queue, it44 * sends the queue, cleans the queue, etc45 */46int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)47{48	return hclge_comm_cmd_send(&hw->hw, desc, num);49}50 51static void hclgevf_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,52				   int num, bool is_special)53{54	int i;55 56	trace_hclge_vf_cmd_send(hw, desc, 0, num);57 58	if (is_special)59		return;60 61	for (i = 1; i < num; i++)62		trace_hclge_vf_cmd_send(hw, &desc[i], i, num);63}64 65static void hclgevf_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc,66				  int num, bool is_special)67{68	int i;69 70	if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))71		return;72 73	trace_hclge_vf_cmd_get(hw, desc, 0, num);74 75	if (is_special)76		return;77 78	for (i = 1; i < num; i++)79		trace_hclge_vf_cmd_get(hw, &desc[i], i, num);80}81 82static const struct hclge_comm_cmq_ops hclgevf_cmq_ops = {83	.trace_cmd_send = hclgevf_trace_cmd_send,84	.trace_cmd_get = hclgevf_trace_cmd_get,85};86 87void hclgevf_arq_init(struct hclgevf_dev *hdev)88{89	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;90 91	spin_lock(&cmdq->crq.lock);92	/* initialize the pointers of async rx queue of mailbox */93	hdev->arq.hdev = hdev;94	hdev->arq.head = 0;95	hdev->arq.tail = 0;96	atomic_set(&hdev->arq.count, 0);97	spin_unlock(&cmdq->crq.lock);98}99 100struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)101{102	if (!handle->client)103		return container_of(handle, struct hclgevf_dev, nic);104	else if (handle->client->type == HNAE3_CLIENT_ROCE)105		return container_of(handle, struct hclgevf_dev, roce);106	else107		return container_of(handle, struct hclgevf_dev, nic);108}109 110static void hclgevf_update_stats(struct hnae3_handle *handle)111{112	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);113	int status;114 115	status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);116	if (status)117		dev_err(&hdev->pdev->dev,118			"VF update of TQPS stats fail, status = %d.\n",119			status);120}121 122static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)123{124	if (strset == ETH_SS_TEST)125		return -EOPNOTSUPP;126	else if (strset == ETH_SS_STATS)127		return hclge_comm_tqps_get_sset_count(handle);128 129	return 0;130}131 132static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,133				u8 *data)134{135	u8 *p = (char *)data;136 137	if (strset == ETH_SS_STATS)138		p = hclge_comm_tqps_get_strings(handle, p);139}140 141static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)142{143	hclge_comm_tqps_get_stats(handle, data);144}145 146static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,147				   u8 subcode)148{149	if (msg) {150		memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));151		msg->code = code;152		msg->subcode = subcode;153	}154}155 156static int hclgevf_get_basic_info(struct hclgevf_dev *hdev)157{158	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;159	u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE];160	struct hclge_basic_info *basic_info;161	struct hclge_vf_to_pf_msg send_msg;162	unsigned long caps;163	int status;164 165	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0);166	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,167				      sizeof(resp_msg));168	if (status) {169		dev_err(&hdev->pdev->dev,170			"failed to get basic info from pf, ret = %d", status);171		return status;172	}173 174	basic_info = (struct hclge_basic_info *)resp_msg;175 176	hdev->hw_tc_map = basic_info->hw_tc_map;177	hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version);178	caps = le32_to_cpu(basic_info->pf_caps);179	if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps))180		set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);181 182	return 0;183}184 185static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)186{187	struct hnae3_handle *nic = &hdev->nic;188	struct hclge_vf_to_pf_msg send_msg;189	u8 resp_msg;190	int ret;191 192	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,193			       HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);194	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,195				   sizeof(u8));196	if (ret) {197		dev_err(&hdev->pdev->dev,198			"VF request to get port based vlan state failed %d",199			ret);200		return ret;201	}202 203	nic->port_base_vlan_state = resp_msg;204 205	return 0;206}207 208static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)209{210#define HCLGEVF_TQPS_RSS_INFO_LEN	6211 212	struct hclge_mbx_vf_queue_info *queue_info;213	u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];214	struct hclge_vf_to_pf_msg send_msg;215	int status;216 217	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);218	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,219				      HCLGEVF_TQPS_RSS_INFO_LEN);220	if (status) {221		dev_err(&hdev->pdev->dev,222			"VF request to get tqp info from PF failed %d",223			status);224		return status;225	}226 227	queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg;228	hdev->num_tqps = le16_to_cpu(queue_info->num_tqps);229	hdev->rss_size_max = le16_to_cpu(queue_info->rss_size);230	hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len);231 232	return 0;233}234 235static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)236{237#define HCLGEVF_TQPS_DEPTH_INFO_LEN	4238 239	struct hclge_mbx_vf_queue_depth *queue_depth;240	u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];241	struct hclge_vf_to_pf_msg send_msg;242	int ret;243 244	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);245	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,246				   HCLGEVF_TQPS_DEPTH_INFO_LEN);247	if (ret) {248		dev_err(&hdev->pdev->dev,249			"VF request to get tqp depth info from PF failed %d",250			ret);251		return ret;252	}253 254	queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg;255	hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc);256	hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc);257 258	return 0;259}260 261static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)262{263	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);264	struct hclge_vf_to_pf_msg send_msg;265	u16 qid_in_pf = 0;266	u8 resp_data[2];267	int ret;268 269	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);270	*(__le16 *)send_msg.data = cpu_to_le16(queue_id);271	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,272				   sizeof(resp_data));273	if (!ret)274		qid_in_pf = le16_to_cpu(*(__le16 *)resp_data);275 276	return qid_in_pf;277}278 279static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)280{281	struct hclge_vf_to_pf_msg send_msg;282	u8 resp_msg[2];283	int ret;284 285	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);286	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,287				   sizeof(resp_msg));288	if (ret) {289		dev_err(&hdev->pdev->dev,290			"VF request to get the pf port media type failed %d",291			ret);292		return ret;293	}294 295	hdev->hw.mac.media_type = resp_msg[0];296	hdev->hw.mac.module_type = resp_msg[1];297 298	return 0;299}300 301static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)302{303	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);304	struct hclge_comm_tqp *tqp;305	int i;306 307	hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,308				  sizeof(struct hclge_comm_tqp), GFP_KERNEL);309	if (!hdev->htqp)310		return -ENOMEM;311 312	tqp = hdev->htqp;313 314	for (i = 0; i < hdev->num_tqps; i++) {315		tqp->dev = &hdev->pdev->dev;316		tqp->index = i;317 318		tqp->q.ae_algo = &ae_algovf;319		tqp->q.buf_size = hdev->rx_buf_len;320		tqp->q.tx_desc_num = hdev->num_tx_desc;321		tqp->q.rx_desc_num = hdev->num_rx_desc;322 323		/* need an extended offset to configure queues >=324		 * HCLGEVF_TQP_MAX_SIZE_DEV_V2.325		 */326		if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)327			tqp->q.io_base = hdev->hw.hw.io_base +328					 HCLGEVF_TQP_REG_OFFSET +329					 i * HCLGEVF_TQP_REG_SIZE;330		else331			tqp->q.io_base = hdev->hw.hw.io_base +332					 HCLGEVF_TQP_REG_OFFSET +333					 HCLGEVF_TQP_EXT_REG_OFFSET +334					 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *335					 HCLGEVF_TQP_REG_SIZE;336 337		/* when device supports tx push and has device memory,338		 * the queue can execute push mode or doorbell mode on339		 * device memory.340		 */341		if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))342			tqp->q.mem_base = hdev->hw.hw.mem_base +343					  HCLGEVF_TQP_MEM_OFFSET(hdev, i);344 345		tqp++;346	}347 348	return 0;349}350 351static int hclgevf_knic_setup(struct hclgevf_dev *hdev)352{353	struct hnae3_handle *nic = &hdev->nic;354	struct hnae3_knic_private_info *kinfo;355	u16 new_tqps = hdev->num_tqps;356	unsigned int i;357	u8 num_tc = 0;358 359	kinfo = &nic->kinfo;360	kinfo->num_tx_desc = hdev->num_tx_desc;361	kinfo->num_rx_desc = hdev->num_rx_desc;362	kinfo->rx_buf_len = hdev->rx_buf_len;363	for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++)364		if (hdev->hw_tc_map & BIT(i))365			num_tc++;366 367	num_tc = num_tc ? num_tc : 1;368	kinfo->tc_info.num_tc = num_tc;369	kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc);370	new_tqps = kinfo->rss_size * num_tc;371	kinfo->num_tqps = min(new_tqps, hdev->num_tqps);372 373	kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,374				  sizeof(struct hnae3_queue *), GFP_KERNEL);375	if (!kinfo->tqp)376		return -ENOMEM;377 378	for (i = 0; i < kinfo->num_tqps; i++) {379		hdev->htqp[i].q.handle = &hdev->nic;380		hdev->htqp[i].q.tqp_index = i;381		kinfo->tqp[i] = &hdev->htqp[i].q;382	}383 384	/* after init the max rss_size and tqps, adjust the default tqp numbers385	 * and rss size with the actual vector numbers386	 */387	kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);388	kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc,389				kinfo->rss_size);390 391	return 0;392}393 394static void hclgevf_request_link_info(struct hclgevf_dev *hdev)395{396	struct hclge_vf_to_pf_msg send_msg;397	int status;398 399	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);400	status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);401	if (status)402		dev_err(&hdev->pdev->dev,403			"VF failed to fetch link status(%d) from PF", status);404}405 406void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)407{408	struct hnae3_handle *rhandle = &hdev->roce;409	struct hnae3_handle *handle = &hdev->nic;410	struct hnae3_client *rclient;411	struct hnae3_client *client;412 413	if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))414		return;415 416	client = handle->client;417	rclient = hdev->roce_client;418 419	link_state =420		test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;421	if (link_state != hdev->hw.mac.link) {422		hdev->hw.mac.link = link_state;423		client->ops->link_status_change(handle, !!link_state);424		if (rclient && rclient->ops->link_status_change)425			rclient->ops->link_status_change(rhandle, !!link_state);426	}427 428	clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);429}430 431static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)432{433#define HCLGEVF_ADVERTISING	0434#define HCLGEVF_SUPPORTED	1435 436	struct hclge_vf_to_pf_msg send_msg;437 438	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);439	send_msg.data[0] = HCLGEVF_ADVERTISING;440	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);441	send_msg.data[0] = HCLGEVF_SUPPORTED;442	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);443}444 445static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)446{447	struct hnae3_handle *nic = &hdev->nic;448	int ret;449 450	nic->ae_algo = &ae_algovf;451	nic->pdev = hdev->pdev;452	bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits,453		    MAX_NUMNODES);454	nic->flags |= HNAE3_SUPPORT_VF;455	nic->kinfo.io_base = hdev->hw.hw.io_base;456 457	ret = hclgevf_knic_setup(hdev);458	if (ret)459		dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",460			ret);461	return ret;462}463 464static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)465{466	if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {467		dev_warn(&hdev->pdev->dev,468			 "vector(vector_id %d) has been freed.\n", vector_id);469		return;470	}471 472	hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;473	hdev->num_msi_left += 1;474	hdev->num_msi_used -= 1;475}476 477static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,478			      struct hnae3_vector_info *vector_info)479{480	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);481	struct hnae3_vector_info *vector = vector_info;482	int alloc = 0;483	int i, j;484 485	vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);486	vector_num = min(hdev->num_msi_left, vector_num);487 488	for (j = 0; j < vector_num; j++) {489		for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {490			if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {491				vector->vector = pci_irq_vector(hdev->pdev, i);492				vector->io_addr = hdev->hw.hw.io_base +493					HCLGEVF_VECTOR_REG_BASE +494					(i - 1) * HCLGEVF_VECTOR_REG_OFFSET;495				hdev->vector_status[i] = 0;496				hdev->vector_irq[i] = vector->vector;497 498				vector++;499				alloc++;500 501				break;502			}503		}504	}505	hdev->num_msi_left -= alloc;506	hdev->num_msi_used += alloc;507 508	return alloc;509}510 511static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)512{513	int i;514 515	for (i = 0; i < hdev->num_msi; i++)516		if (vector == hdev->vector_irq[i])517			return i;518 519	return -EINVAL;520}521 522/* for revision 0x20, vf shared the same rss config with pf */523static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)524{525#define HCLGEVF_RSS_MBX_RESP_LEN	8526	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;527	u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];528	struct hclge_vf_to_pf_msg send_msg;529	u16 msg_num, hash_key_index;530	u8 index;531	int ret;532 533	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);534	msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /535			HCLGEVF_RSS_MBX_RESP_LEN;536	for (index = 0; index < msg_num; index++) {537		send_msg.data[0] = index;538		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,539					   HCLGEVF_RSS_MBX_RESP_LEN);540		if (ret) {541			dev_err(&hdev->pdev->dev,542				"VF get rss hash key from PF failed, ret=%d",543				ret);544			return ret;545		}546 547		hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;548		if (index == msg_num - 1)549			memcpy(&rss_cfg->rss_hash_key[hash_key_index],550			       &resp_msg[0],551			       HCLGE_COMM_RSS_KEY_SIZE - hash_key_index);552		else553			memcpy(&rss_cfg->rss_hash_key[hash_key_index],554			       &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);555	}556 557	return 0;558}559 560static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,561			   u8 *hfunc)562{563	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);564	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;565	int ret;566 567	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {568		hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);569	} else {570		if (hfunc)571			*hfunc = ETH_RSS_HASH_TOP;572		if (key) {573			ret = hclgevf_get_rss_hash_key(hdev);574			if (ret)575				return ret;576			memcpy(key, rss_cfg->rss_hash_key,577			       HCLGE_COMM_RSS_KEY_SIZE);578		}579	}580 581	hclge_comm_get_rss_indir_tbl(rss_cfg, indir,582				     hdev->ae_dev->dev_specs.rss_ind_tbl_size);583 584	return 0;585}586 587static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,588			   const u8 *key, const u8 hfunc)589{590	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);591	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;592	int ret, i;593 594	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {595		ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key,596						  hfunc);597		if (ret)598			return ret;599	}600 601	/* update the shadow RSS table with user specified qids */602	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)603		rss_cfg->rss_indirection_tbl[i] = indir[i];604 605	/* update the hardware */606	return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,607					      rss_cfg->rss_indirection_tbl);608}609 610static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,611				 struct ethtool_rxnfc *nfc)612{613	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);614	int ret;615 616	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)617		return -EOPNOTSUPP;618 619	ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,620				       &hdev->rss_cfg, nfc);621	if (ret)622		dev_err(&hdev->pdev->dev,623		"failed to set rss tuple, ret = %d.\n", ret);624 625	return ret;626}627 628static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,629				 struct ethtool_rxnfc *nfc)630{631	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);632	u8 tuple_sets;633	int ret;634 635	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)636		return -EOPNOTSUPP;637 638	nfc->data = 0;639 640	ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type,641				       &tuple_sets);642	if (ret || !tuple_sets)643		return ret;644 645	nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);646 647	return 0;648}649 650static int hclgevf_get_tc_size(struct hnae3_handle *handle)651{652	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);653	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;654 655	return rss_cfg->rss_size;656}657 658static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,659				       int vector_id,660				       struct hnae3_ring_chain_node *ring_chain)661{662	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);663	struct hclge_vf_to_pf_msg send_msg;664	struct hnae3_ring_chain_node *node;665	int status;666	int i = 0;667 668	memset(&send_msg, 0, sizeof(send_msg));669	send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :670		HCLGE_MBX_UNMAP_RING_TO_VECTOR;671	send_msg.vector_id = vector_id;672 673	for (node = ring_chain; node; node = node->next) {674		send_msg.param[i].ring_type =675				hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);676 677		send_msg.param[i].tqp_index = node->tqp_index;678		send_msg.param[i].int_gl_index =679					hnae3_get_field(node->int_gl_idx,680							HNAE3_RING_GL_IDX_M,681							HNAE3_RING_GL_IDX_S);682 683		i++;684		if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {685			send_msg.ring_num = i;686 687			status = hclgevf_send_mbx_msg(hdev, &send_msg, false,688						      NULL, 0);689			if (status) {690				dev_err(&hdev->pdev->dev,691					"Map TQP fail, status is %d.\n",692					status);693				return status;694			}695			i = 0;696		}697	}698 699	return 0;700}701 702static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,703				      struct hnae3_ring_chain_node *ring_chain)704{705	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);706	int vector_id;707 708	vector_id = hclgevf_get_vector_index(hdev, vector);709	if (vector_id < 0) {710		dev_err(&handle->pdev->dev,711			"Get vector index fail. ret =%d\n", vector_id);712		return vector_id;713	}714 715	return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);716}717 718static int hclgevf_unmap_ring_from_vector(719				struct hnae3_handle *handle,720				int vector,721				struct hnae3_ring_chain_node *ring_chain)722{723	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);724	int ret, vector_id;725 726	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))727		return 0;728 729	vector_id = hclgevf_get_vector_index(hdev, vector);730	if (vector_id < 0) {731		dev_err(&handle->pdev->dev,732			"Get vector index fail. ret =%d\n", vector_id);733		return vector_id;734	}735 736	ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);737	if (ret)738		dev_err(&handle->pdev->dev,739			"Unmap ring from vector fail. vector=%d, ret =%d\n",740			vector_id,741			ret);742 743	return ret;744}745 746static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)747{748	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);749	int vector_id;750 751	vector_id = hclgevf_get_vector_index(hdev, vector);752	if (vector_id < 0) {753		dev_err(&handle->pdev->dev,754			"hclgevf_put_vector get vector index fail. ret =%d\n",755			vector_id);756		return vector_id;757	}758 759	hclgevf_free_vector(hdev, vector_id);760 761	return 0;762}763 764static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,765					bool en_uc_pmc, bool en_mc_pmc,766					bool en_bc_pmc)767{768	struct hnae3_handle *handle = &hdev->nic;769	struct hclge_vf_to_pf_msg send_msg;770	int ret;771 772	memset(&send_msg, 0, sizeof(send_msg));773	send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;774	send_msg.en_bc = en_bc_pmc ? 1 : 0;775	send_msg.en_uc = en_uc_pmc ? 1 : 0;776	send_msg.en_mc = en_mc_pmc ? 1 : 0;777	send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,778					     &handle->priv_flags) ? 1 : 0;779 780	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);781	if (ret)782		dev_err(&hdev->pdev->dev,783			"Set promisc mode fail, status is %d.\n", ret);784 785	return ret;786}787 788static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,789				    bool en_mc_pmc)790{791	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);792	bool en_bc_pmc;793 794	en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;795 796	return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,797					    en_bc_pmc);798}799 800static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)801{802	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);803 804	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);805	hclgevf_task_schedule(hdev, 0);806}807 808static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)809{810	struct hnae3_handle *handle = &hdev->nic;811	bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;812	bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;813	int ret;814 815	if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {816		ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);817		if (!ret)818			clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);819	}820}821 822static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,823				       u16 stream_id, bool enable)824{825	struct hclgevf_cfg_com_tqp_queue_cmd *req;826	struct hclge_desc desc;827 828	req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;829 830	hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);831	req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);832	req->stream_id = cpu_to_le16(stream_id);833	if (enable)834		req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;835 836	return hclgevf_cmd_send(&hdev->hw, &desc, 1);837}838 839static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable)840{841	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);842	int ret;843	u16 i;844 845	for (i = 0; i < handle->kinfo.num_tqps; i++) {846		ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable);847		if (ret)848			return ret;849	}850 851	return 0;852}853 854static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)855{856	struct hclge_vf_to_pf_msg send_msg;857	u8 host_mac[ETH_ALEN];858	int status;859 860	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);861	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,862				      ETH_ALEN);863	if (status) {864		dev_err(&hdev->pdev->dev,865			"fail to get VF MAC from host %d", status);866		return status;867	}868 869	ether_addr_copy(p, host_mac);870 871	return 0;872}873 874static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)875{876	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);877	u8 host_mac_addr[ETH_ALEN];878 879	if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))880		return;881 882	hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);883	if (hdev->has_pf_mac)884		ether_addr_copy(p, host_mac_addr);885	else886		ether_addr_copy(p, hdev->hw.mac.mac_addr);887}888 889static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p,890				bool is_first)891{892	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);893	u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;894	struct hclge_vf_to_pf_msg send_msg;895	u8 *new_mac_addr = (u8 *)p;896	int status;897 898	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);899	send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;900	ether_addr_copy(send_msg.data, new_mac_addr);901	if (is_first && !hdev->has_pf_mac)902		eth_zero_addr(&send_msg.data[ETH_ALEN]);903	else904		ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);905	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);906	if (!status)907		ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);908 909	return status;910}911 912static struct hclgevf_mac_addr_node *913hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)914{915	struct hclgevf_mac_addr_node *mac_node, *tmp;916 917	list_for_each_entry_safe(mac_node, tmp, list, node)918		if (ether_addr_equal(mac_addr, mac_node->mac_addr))919			return mac_node;920 921	return NULL;922}923 924static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,925				    enum HCLGEVF_MAC_NODE_STATE state)926{927	switch (state) {928	/* from set_rx_mode or tmp_add_list */929	case HCLGEVF_MAC_TO_ADD:930		if (mac_node->state == HCLGEVF_MAC_TO_DEL)931			mac_node->state = HCLGEVF_MAC_ACTIVE;932		break;933	/* only from set_rx_mode */934	case HCLGEVF_MAC_TO_DEL:935		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {936			list_del(&mac_node->node);937			kfree(mac_node);938		} else {939			mac_node->state = HCLGEVF_MAC_TO_DEL;940		}941		break;942	/* only from tmp_add_list, the mac_node->state won't be943	 * HCLGEVF_MAC_ACTIVE944	 */945	case HCLGEVF_MAC_ACTIVE:946		if (mac_node->state == HCLGEVF_MAC_TO_ADD)947			mac_node->state = HCLGEVF_MAC_ACTIVE;948		break;949	}950}951 952static int hclgevf_update_mac_list(struct hnae3_handle *handle,953				   enum HCLGEVF_MAC_NODE_STATE state,954				   enum HCLGEVF_MAC_ADDR_TYPE mac_type,955				   const unsigned char *addr)956{957	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);958	struct hclgevf_mac_addr_node *mac_node;959	struct list_head *list;960 961	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?962	       &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;963 964	spin_lock_bh(&hdev->mac_table.mac_list_lock);965 966	/* if the mac addr is already in the mac list, no need to add a new967	 * one into it, just check the mac addr state, convert it to a new968	 * state, or just remove it, or do nothing.969	 */970	mac_node = hclgevf_find_mac_node(list, addr);971	if (mac_node) {972		hclgevf_update_mac_node(mac_node, state);973		spin_unlock_bh(&hdev->mac_table.mac_list_lock);974		return 0;975	}976	/* if this address is never added, unnecessary to delete */977	if (state == HCLGEVF_MAC_TO_DEL) {978		spin_unlock_bh(&hdev->mac_table.mac_list_lock);979		return -ENOENT;980	}981 982	mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);983	if (!mac_node) {984		spin_unlock_bh(&hdev->mac_table.mac_list_lock);985		return -ENOMEM;986	}987 988	mac_node->state = state;989	ether_addr_copy(mac_node->mac_addr, addr);990	list_add_tail(&mac_node->node, list);991 992	spin_unlock_bh(&hdev->mac_table.mac_list_lock);993	return 0;994}995 996static int hclgevf_add_uc_addr(struct hnae3_handle *handle,997			       const unsigned char *addr)998{999	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,1000				       HCLGEVF_MAC_ADDR_UC, addr);1001}1002 1003static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,1004			      const unsigned char *addr)1005{1006	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,1007				       HCLGEVF_MAC_ADDR_UC, addr);1008}1009 1010static int hclgevf_add_mc_addr(struct hnae3_handle *handle,1011			       const unsigned char *addr)1012{1013	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,1014				       HCLGEVF_MAC_ADDR_MC, addr);1015}1016 1017static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,1018			      const unsigned char *addr)1019{1020	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,1021				       HCLGEVF_MAC_ADDR_MC, addr);1022}1023 1024static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,1025				    struct hclgevf_mac_addr_node *mac_node,1026				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)1027{1028	struct hclge_vf_to_pf_msg send_msg;1029	u8 code, subcode;1030 1031	if (mac_type == HCLGEVF_MAC_ADDR_UC) {1032		code = HCLGE_MBX_SET_UNICAST;1033		if (mac_node->state == HCLGEVF_MAC_TO_ADD)1034			subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;1035		else1036			subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;1037	} else {1038		code = HCLGE_MBX_SET_MULTICAST;1039		if (mac_node->state == HCLGEVF_MAC_TO_ADD)1040			subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;1041		else1042			subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;1043	}1044 1045	hclgevf_build_send_msg(&send_msg, code, subcode);1046	ether_addr_copy(send_msg.data, mac_node->mac_addr);1047	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);1048}1049 1050static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,1051				    struct list_head *list,1052				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)1053{1054	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];1055	struct hclgevf_mac_addr_node *mac_node, *tmp;1056	int ret;1057 1058	list_for_each_entry_safe(mac_node, tmp, list, node) {1059		ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);1060		if  (ret) {1061			hnae3_format_mac_addr(format_mac_addr,1062					      mac_node->mac_addr);1063			dev_err(&hdev->pdev->dev,1064				"failed to configure mac %s, state = %d, ret = %d\n",1065				format_mac_addr, mac_node->state, ret);1066			return;1067		}1068		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {1069			mac_node->state = HCLGEVF_MAC_ACTIVE;1070		} else {1071			list_del(&mac_node->node);1072			kfree(mac_node);1073		}1074	}1075}1076 1077static void hclgevf_sync_from_add_list(struct list_head *add_list,1078				       struct list_head *mac_list)1079{1080	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;1081 1082	list_for_each_entry_safe(mac_node, tmp, add_list, node) {1083		/* if the mac address from tmp_add_list is not in the1084		 * uc/mc_mac_list, it means have received a TO_DEL request1085		 * during the time window of sending mac config request to PF1086		 * If mac_node state is ACTIVE, then change its state to TO_DEL,1087		 * then it will be removed at next time. If is TO_ADD, it means1088		 * send TO_ADD request failed, so just remove the mac node.1089		 */1090		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);1091		if (new_node) {1092			hclgevf_update_mac_node(new_node, mac_node->state);1093			list_del(&mac_node->node);1094			kfree(mac_node);1095		} else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {1096			mac_node->state = HCLGEVF_MAC_TO_DEL;1097			list_move_tail(&mac_node->node, mac_list);1098		} else {1099			list_del(&mac_node->node);1100			kfree(mac_node);1101		}1102	}1103}1104 1105static void hclgevf_sync_from_del_list(struct list_head *del_list,1106				       struct list_head *mac_list)1107{1108	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;1109 1110	list_for_each_entry_safe(mac_node, tmp, del_list, node) {1111		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);1112		if (new_node) {1113			/* If the mac addr is exist in the mac list, it means1114			 * received a new request TO_ADD during the time window1115			 * of sending mac addr configurrequest to PF, so just1116			 * change the mac state to ACTIVE.1117			 */1118			new_node->state = HCLGEVF_MAC_ACTIVE;1119			list_del(&mac_node->node);1120			kfree(mac_node);1121		} else {1122			list_move_tail(&mac_node->node, mac_list);1123		}1124	}1125}1126 1127static void hclgevf_clear_list(struct list_head *list)1128{1129	struct hclgevf_mac_addr_node *mac_node, *tmp;1130 1131	list_for_each_entry_safe(mac_node, tmp, list, node) {1132		list_del(&mac_node->node);1133		kfree(mac_node);1134	}1135}1136 1137static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,1138				  enum HCLGEVF_MAC_ADDR_TYPE mac_type)1139{1140	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;1141	struct list_head tmp_add_list, tmp_del_list;1142	struct list_head *list;1143 1144	INIT_LIST_HEAD(&tmp_add_list);1145	INIT_LIST_HEAD(&tmp_del_list);1146 1147	/* move the mac addr to the tmp_add_list and tmp_del_list, then1148	 * we can add/delete these mac addr outside the spin lock1149	 */1150	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?1151		&hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;1152 1153	spin_lock_bh(&hdev->mac_table.mac_list_lock);1154 1155	list_for_each_entry_safe(mac_node, tmp, list, node) {1156		switch (mac_node->state) {1157		case HCLGEVF_MAC_TO_DEL:1158			list_move_tail(&mac_node->node, &tmp_del_list);1159			break;1160		case HCLGEVF_MAC_TO_ADD:1161			new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);1162			if (!new_node)1163				goto stop_traverse;1164 1165			ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);1166			new_node->state = mac_node->state;1167			list_add_tail(&new_node->node, &tmp_add_list);1168			break;1169		default:1170			break;1171		}1172	}1173 1174stop_traverse:1175	spin_unlock_bh(&hdev->mac_table.mac_list_lock);1176 1177	/* delete first, in order to get max mac table space for adding */1178	hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);1179	hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);1180 1181	/* if some mac addresses were added/deleted fail, move back to the1182	 * mac_list, and retry at next time.1183	 */1184	spin_lock_bh(&hdev->mac_table.mac_list_lock);1185 1186	hclgevf_sync_from_del_list(&tmp_del_list, list);1187	hclgevf_sync_from_add_list(&tmp_add_list, list);1188 1189	spin_unlock_bh(&hdev->mac_table.mac_list_lock);1190}1191 1192static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)1193{1194	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);1195	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);1196}1197 1198static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)1199{1200	spin_lock_bh(&hdev->mac_table.mac_list_lock);1201 1202	hclgevf_clear_list(&hdev->mac_table.uc_mac_list);1203	hclgevf_clear_list(&hdev->mac_table.mc_mac_list);1204 1205	spin_unlock_bh(&hdev->mac_table.mac_list_lock);1206}1207 1208static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable)1209{1210	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);1211	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;1212	struct hclge_vf_to_pf_msg send_msg;1213 1214	if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))1215		return -EOPNOTSUPP;1216 1217	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,1218			       HCLGE_MBX_ENABLE_VLAN_FILTER);1219	send_msg.data[0] = enable ? 1 : 0;1220 1221	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);1222}1223 1224static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,1225				   __be16 proto, u16 vlan_id,1226				   bool is_kill)1227{1228	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);1229	struct hclge_mbx_vlan_filter *vlan_filter;1230	struct hclge_vf_to_pf_msg send_msg;1231	int ret;1232 1233	if (vlan_id > HCLGEVF_MAX_VLAN_ID)1234		return -EINVAL;1235 1236	if (proto != htons(ETH_P_8021Q))1237		return -EPROTONOSUPPORT;1238 1239	/* When device is resetting or reset failed, firmware is unable to1240	 * handle mailbox. Just record the vlan id, and remove it after1241	 * reset finished.1242	 */1243	if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||1244	     test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {1245		set_bit(vlan_id, hdev->vlan_del_fail_bmap);1246		return -EBUSY;1247	} else if (!is_kill && test_bit(vlan_id, hdev->vlan_del_fail_bmap)) {1248		clear_bit(vlan_id, hdev->vlan_del_fail_bmap);1249	}1250 1251	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,1252			       HCLGE_MBX_VLAN_FILTER);1253	vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data;1254	vlan_filter->is_kill = is_kill;1255	vlan_filter->vlan_id = cpu_to_le16(vlan_id);1256	vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto));1257 1258	/* when remove hw vlan filter failed, record the vlan id,1259	 * and try to remove it from hw later, to be consistence1260	 * with stack.1261	 */1262	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);1263	if (is_kill && ret)1264		set_bit(vlan_id, hdev->vlan_del_fail_bmap);1265 1266	return ret;1267}1268 1269static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)1270{1271#define HCLGEVF_MAX_SYNC_COUNT	601272	struct hnae3_handle *handle = &hdev->nic;1273	int ret, sync_cnt = 0;1274	u16 vlan_id;1275 1276	if (bitmap_empty(hdev->vlan_del_fail_bmap, VLAN_N_VID))1277		return;1278 1279	rtnl_lock();1280	vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);1281	while (vlan_id != VLAN_N_VID) {1282		ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),1283					      vlan_id, true);1284		if (ret)1285			break;1286 1287		clear_bit(vlan_id, hdev->vlan_del_fail_bmap);1288		sync_cnt++;1289		if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)1290			break;1291 1292		vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);1293	}1294	rtnl_unlock();1295}1296 1297static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)1298{1299	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);1300	struct hclge_vf_to_pf_msg send_msg;1301 1302	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,1303			       HCLGE_MBX_VLAN_RX_OFF_CFG);1304	send_msg.data[0] = enable ? 1 : 0;1305	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);1306}1307 1308static int hclgevf_reset_tqp(struct hnae3_handle *handle)1309{1310#define HCLGEVF_RESET_ALL_QUEUE_DONE	1U1311	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);1312	struct hclge_vf_to_pf_msg send_msg;1313	u8 return_status = 0;1314	int ret;1315	u16 i;1316 1317	/* disable vf queue before send queue reset msg to PF */1318	ret = hclgevf_tqp_enable(handle, false);1319	if (ret) {1320		dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n",1321			ret);1322		return ret;1323	}1324 1325	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);1326 1327	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status,1328				   sizeof(return_status));1329	if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE)1330		return ret;1331 1332	for (i = 1; i < handle->kinfo.num_tqps; i++) {1333		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);1334		*(__le16 *)send_msg.data = cpu_to_le16(i);1335		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);1336		if (ret)1337			return ret;1338	}1339 1340	return 0;1341}1342 1343static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)1344{1345	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);1346	struct hclge_mbx_mtu_info *mtu_info;1347	struct hclge_vf_to_pf_msg send_msg;1348 1349	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);1350	mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data;1351	mtu_info->mtu = cpu_to_le32(new_mtu);1352 1353	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);1354}1355 1356static int hclgevf_notify_client(struct hclgevf_dev *hdev,1357				 enum hnae3_reset_notify_type type)1358{1359	struct hnae3_client *client = hdev->nic_client;1360	struct hnae3_handle *handle = &hdev->nic;1361	int ret;1362 1363	if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||1364	    !client)1365		return 0;1366 1367	if (!client->ops->reset_notify)1368		return -EOPNOTSUPP;1369 1370	ret = client->ops->reset_notify(handle, type);1371	if (ret)1372		dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",1373			type, ret);1374 1375	return ret;1376}1377 1378static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,1379				      enum hnae3_reset_notify_type type)1380{1381	struct hnae3_client *client = hdev->roce_client;1382	struct hnae3_handle *handle = &hdev->roce;1383	int ret;1384 1385	if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)1386		return 0;1387 1388	if (!client->ops->reset_notify)1389		return -EOPNOTSUPP;1390 1391	ret = client->ops->reset_notify(handle, type);1392	if (ret)1393		dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",1394			type, ret);1395	return ret;1396}1397 1398static int hclgevf_reset_wait(struct hclgevf_dev *hdev)1399{1400#define HCLGEVF_RESET_WAIT_US	200001401#define HCLGEVF_RESET_WAIT_CNT	20001402#define HCLGEVF_RESET_WAIT_TIMEOUT_US	\1403	(HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)1404 1405	u32 val;1406	int ret;1407 1408	if (hdev->reset_type == HNAE3_VF_RESET)1409		ret = readl_poll_timeout(hdev->hw.hw.io_base +1410					 HCLGEVF_VF_RST_ING, val,1411					 !(val & HCLGEVF_VF_RST_ING_BIT),1412					 HCLGEVF_RESET_WAIT_US,1413					 HCLGEVF_RESET_WAIT_TIMEOUT_US);1414	else1415		ret = readl_poll_timeout(hdev->hw.hw.io_base +1416					 HCLGEVF_RST_ING, val,1417					 !(val & HCLGEVF_RST_ING_BITS),1418					 HCLGEVF_RESET_WAIT_US,1419					 HCLGEVF_RESET_WAIT_TIMEOUT_US);1420 1421	/* hardware completion status should be available by this time */1422	if (ret) {1423		dev_err(&hdev->pdev->dev,1424			"couldn't get reset done status from h/w, timeout!\n");1425		return ret;1426	}1427 1428	/* we will wait a bit more to let reset of the stack to complete. This1429	 * might happen in case reset assertion was made by PF. Yes, this also1430	 * means we might end up waiting bit more even for VF reset.1431	 */1432	if (hdev->reset_type == HNAE3_VF_FULL_RESET)1433		msleep(5000);1434	else1435		msleep(500);1436 1437	return 0;1438}1439 1440static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)1441{1442	u32 reg_val;1443 1444	reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);1445	if (enable)1446		reg_val |= HCLGEVF_NIC_SW_RST_RDY;1447	else1448		reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;1449 1450	hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG,1451			  reg_val);1452}1453 1454static int hclgevf_reset_stack(struct hclgevf_dev *hdev)1455{1456	int ret;1457 1458	/* uninitialize the nic client */1459	ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);1460	if (ret)1461		return ret;1462 1463	/* re-initialize the hclge device */1464	ret = hclgevf_reset_hdev(hdev);1465	if (ret) {1466		dev_err(&hdev->pdev->dev,1467			"hclge device re-init failed, VF is disabled!\n");1468		return ret;1469	}1470 1471	/* bring up the nic client again */1472	ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);1473	if (ret)1474		return ret;1475 1476	/* clear handshake status with IMP */1477	hclgevf_reset_handshake(hdev, false);1478 1479	/* bring up the nic to enable TX/RX again */1480	return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);1481}1482 1483static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)1484{1485#define HCLGEVF_RESET_SYNC_TIME 1001486 1487	if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {1488		struct hclge_vf_to_pf_msg send_msg;1489		int ret;1490 1491		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);1492		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);1493		if (ret) {1494			dev_err(&hdev->pdev->dev,1495				"failed to assert VF reset, ret = %d\n", ret);1496			return ret;1497		}1498		hdev->rst_stats.vf_func_rst_cnt++;1499	}1500 1501	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);1502	/* inform hardware that preparatory work is done */1503	msleep(HCLGEVF_RESET_SYNC_TIME);1504	hclgevf_reset_handshake(hdev, true);1505	dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",1506		 hdev->reset_type);1507 1508	return 0;1509}1510 1511static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)1512{1513	dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",1514		 hdev->rst_stats.vf_func_rst_cnt);1515	dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",1516		 hdev->rst_stats.flr_rst_cnt);1517	dev_info(&hdev->pdev->dev, "VF reset count: %u\n",1518		 hdev->rst_stats.vf_rst_cnt);1519	dev_info(&hdev->pdev->dev, "reset done count: %u\n",1520		 hdev->rst_stats.rst_done_cnt);1521	dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",1522		 hdev->rst_stats.hw_rst_done_cnt);1523	dev_info(&hdev->pdev->dev, "reset count: %u\n",1524		 hdev->rst_stats.rst_cnt);1525	dev_info(&hdev->pdev->dev, "reset fail count: %u\n",1526		 hdev->rst_stats.rst_fail_cnt);1527	dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",1528		 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));1529	dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",1530		 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG));1531	dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",1532		 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG));1533	dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",1534		 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));1535	dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);1536}1537 1538static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)1539{1540	/* recover handshake status with IMP when reset fail */1541	hclgevf_reset_handshake(hdev, true);1542	hdev->rst_stats.rst_fail_cnt++;1543	dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",1544		hdev->rst_stats.rst_fail_cnt);1545 1546	if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)1547		set_bit(hdev->reset_type, &hdev->reset_pending);1548 1549	if (hclgevf_is_reset_pending(hdev)) {1550		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);1551		hclgevf_reset_task_schedule(hdev);1552	} else {1553		set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);1554		hclgevf_dump_rst_info(hdev);1555	}1556}1557 1558static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)1559{1560	int ret;1561 1562	hdev->rst_stats.rst_cnt++;1563 1564	/* perform reset of the stack & ae device for a client */1565	ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);1566	if (ret)1567		return ret;1568 1569	rtnl_lock();1570	/* bring down the nic to stop any ongoing TX/RX */1571	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);1572	rtnl_unlock();1573	if (ret)1574		return ret;1575 1576	return hclgevf_reset_prepare_wait(hdev);1577}1578 1579static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)1580{1581	int ret;1582 1583	hdev->rst_stats.hw_rst_done_cnt++;1584	ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);1585	if (ret)1586		return ret;1587 1588	rtnl_lock();1589	/* now, re-initialize the nic client and ae device */1590	ret = hclgevf_reset_stack(hdev);1591	rtnl_unlock();1592	if (ret) {1593		dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");1594		return ret;1595	}1596 1597	ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);1598	/* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 11599	 * times1600	 */1601	if (ret &&1602	    hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)1603		return ret;1604 1605	ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);1606	if (ret)1607		return ret;1608 1609	hdev->last_reset_time = jiffies;1610	hdev->rst_stats.rst_done_cnt++;1611	hdev->rst_stats.rst_fail_cnt = 0;1612	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);1613 1614	return 0;1615}1616 1617static void hclgevf_reset(struct hclgevf_dev *hdev)1618{1619	if (hclgevf_reset_prepare(hdev))1620		goto err_reset;1621 1622	/* check if VF could successfully fetch the hardware reset completion1623	 * status from the hardware1624	 */1625	if (hclgevf_reset_wait(hdev)) {1626		/* can't do much in this situation, will disable VF */1627		dev_err(&hdev->pdev->dev,1628			"failed to fetch H/W reset completion status\n");1629		goto err_reset;1630	}1631 1632	if (hclgevf_reset_rebuild(hdev))1633		goto err_reset;1634 1635	return;1636 1637err_reset:1638	hclgevf_reset_err_handle(hdev);1639}1640 1641static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr)1642{1643	enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;1644 1645	/* return the highest priority reset level amongst all */1646	if (test_bit(HNAE3_VF_RESET, addr)) {1647		rst_level = HNAE3_VF_RESET;1648		clear_bit(HNAE3_VF_RESET, addr);1649		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);1650		clear_bit(HNAE3_VF_FUNC_RESET, addr);1651	} else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {1652		rst_level = HNAE3_VF_FULL_RESET;1653		clear_bit(HNAE3_VF_FULL_RESET, addr);1654		clear_bit(HNAE3_VF_FUNC_RESET, addr);1655	} else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {1656		rst_level = HNAE3_VF_PF_FUNC_RESET;1657		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);1658		clear_bit(HNAE3_VF_FUNC_RESET, addr);1659	} else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {1660		rst_level = HNAE3_VF_FUNC_RESET;1661		clear_bit(HNAE3_VF_FUNC_RESET, addr);1662	} else if (test_bit(HNAE3_FLR_RESET, addr)) {1663		rst_level = HNAE3_FLR_RESET;1664		clear_bit(HNAE3_FLR_RESET, addr);1665	}1666 1667	return rst_level;1668}1669 1670static void hclgevf_reset_event(struct pci_dev *pdev,1671				struct hnae3_handle *handle)1672{1673	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);1674	struct hclgevf_dev *hdev = ae_dev->priv;1675 1676	dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");1677 1678	if (hdev->default_reset_request)1679		hdev->reset_level =1680			hclgevf_get_reset_level(&hdev->default_reset_request);1681	else1682		hdev->reset_level = HNAE3_VF_FUNC_RESET;1683 1684	/* reset of this VF requested */1685	set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);1686	hclgevf_reset_task_schedule(hdev);1687 1688	hdev->last_reset_time = jiffies;1689}1690 1691static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,1692					  enum hnae3_reset_type rst_type)1693{1694	struct hclgevf_dev *hdev = ae_dev->priv;1695 1696	set_bit(rst_type, &hdev->default_reset_request);1697}1698 1699static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)1700{1701	writel(en ? 1 : 0, vector->addr);1702}1703 1704static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev,1705					  enum hnae3_reset_type rst_type)1706{1707#define HCLGEVF_RESET_RETRY_WAIT_MS	5001708#define HCLGEVF_RESET_RETRY_CNT		51709 1710	struct hclgevf_dev *hdev = ae_dev->priv;1711	int retry_cnt = 0;1712	int ret;1713 1714	while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) {1715		down(&hdev->reset_sem);1716		set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);1717		hdev->reset_type = rst_type;1718		ret = hclgevf_reset_prepare(hdev);1719		if (!ret && !hdev->reset_pending)1720			break;1721 1722		dev_err(&hdev->pdev->dev,1723			"failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",1724			ret, hdev->reset_pending, retry_cnt);1725		clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);1726		up(&hdev->reset_sem);1727		msleep(HCLGEVF_RESET_RETRY_WAIT_MS);1728	}1729 1730	/* disable misc vector before reset done */1731	hclgevf_enable_vector(&hdev->misc_vector, false);1732 1733	if (hdev->reset_type == HNAE3_FLR_RESET)1734		hdev->rst_stats.flr_rst_cnt++;1735}1736 1737static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev)1738{1739	struct hclgevf_dev *hdev = ae_dev->priv;1740	int ret;1741 1742	hclgevf_enable_vector(&hdev->misc_vector, true);1743 1744	ret = hclgevf_reset_rebuild(hdev);1745	if (ret)1746		dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",1747			 ret);1748 1749	hdev->reset_type = HNAE3_NONE_RESET;1750	if (test_and_clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))1751		up(&hdev->reset_sem);1752}1753 1754static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)1755{1756	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);1757 1758	return hdev->fw_version;1759}1760 1761static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)1762{1763	struct hclgevf_misc_vector *vector = &hdev->misc_vector;1764 1765	vector->vector_irq = pci_irq_vector(hdev->pdev,1766					    HCLGEVF_MISC_VECTOR_NUM);1767	vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;1768	/* vector status always valid for Vector 0 */1769	hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;1770	hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;1771 1772	hdev->num_msi_left -= 1;1773	hdev->num_msi_used += 1;1774}1775 1776void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)1777{1778	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&1779	    test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) &&1780	    !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,1781			      &hdev->state))1782		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);1783}1784 1785void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)1786{1787	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&1788	    !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,1789			      &hdev->state))1790		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);1791}1792 1793static void hclgevf_task_schedule(struct hclgevf_dev *hdev,1794				  unsigned long delay)1795{1796	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&1797	    !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))1798		mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);1799}1800 1801static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)1802{1803#define	HCLGEVF_MAX_RESET_ATTEMPTS_CNT	31804 1805	if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))1806		return;1807 1808	down(&hdev->reset_sem);1809	set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);1810 1811	if (test_and_clear_bit(HCLGEVF_RESET_PENDING,1812			       &hdev->reset_state)) {1813		/* PF has intimated that it is about to reset the hardware.1814		 * We now have to poll & check if hardware has actually1815		 * completed the reset sequence. On hardware reset completion,1816		 * VF needs to reset the client and ae device.1817		 */1818		hdev->reset_attempts = 0;1819 1820		hdev->last_reset_time = jiffies;1821		hdev->reset_type =1822			hclgevf_get_reset_level(&hdev->reset_pending);1823		if (hdev->reset_type != HNAE3_NONE_RESET)1824			hclgevf_reset(hdev);1825	} else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,1826				      &hdev->reset_state)) {1827		/* we could be here when either of below happens:1828		 * 1. reset was initiated due to watchdog timeout caused by1829		 *    a. IMP was earlier reset and our TX got choked down and1830		 *       which resulted in watchdog reacting and inducing VF1831		 *       reset. This also means our cmdq would be unreliable.1832		 *    b. problem in TX due to other lower layer(example link1833		 *       layer not functioning properly etc.)1834		 * 2. VF reset might have been initiated due to some config1835		 *    change.1836		 *1837		 * NOTE: Theres no clear way to detect above cases than to react1838		 * to the response of PF for this reset request. PF will ack the1839		 * 1b and 2. cases but we will not get any intimation about 1a1840		 * from PF as cmdq would be in unreliable state i.e. mailbox1841		 * communication between PF and VF would be broken.1842		 *1843		 * if we are never geting into pending state it means either:1844		 * 1. PF is not receiving our request which could be due to IMP1845		 *    reset1846		 * 2. PF is screwed1847		 * We cannot do much for 2. but to check first we can try reset1848		 * our PCIe + stack and see if it alleviates the problem.1849		 */1850		if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {1851			/* prepare for full reset of stack + pcie interface */1852			set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);1853 1854			/* "defer" schedule the reset task again */1855			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);1856		} else {1857			hdev->reset_attempts++;1858 1859			set_bit(hdev->reset_level, &hdev->reset_pending);1860			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);1861		}1862		hclgevf_reset_task_schedule(hdev);1863	}1864 1865	hdev->reset_type = HNAE3_NONE_RESET;1866	clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);1867	up(&hdev->reset_sem);1868}1869 1870static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)1871{1872	if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))1873		return;1874 1875	if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))1876		return;1877 1878	hclgevf_mbx_async_handler(hdev);1879 1880	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);1881}1882 1883static void hclgevf_keep_alive(struct hclgevf_dev *hdev)1884{1885	struct hclge_vf_to_pf_msg send_msg;1886	int ret;1887 1888	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))1889		return;1890 1891	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);1892	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);1893	if (ret)1894		dev_err(&hdev->pdev->dev,1895			"VF sends keep alive cmd failed(=%d)\n", ret);1896}1897 1898static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)1899{1900	unsigned long delta = round_jiffies_relative(HZ);1901	struct hnae3_handle *handle = &hdev->nic;1902 1903	if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) ||1904	    test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))1905		return;1906 1907	if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {1908		delta = jiffies - hdev->last_serv_processed;1909 1910		if (delta < round_jiffies_relative(HZ)) {1911			delta = round_jiffies_relative(HZ) - delta;1912			goto out;1913		}1914	}1915 1916	hdev->serv_processed_cnt++;1917	if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))1918		hclgevf_keep_alive(hdev);1919 1920	if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {1921		hdev->last_serv_processed = jiffies;1922		goto out;1923	}1924 1925	if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))1926		hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);1927 1928	/* VF does not need to request link status when this bit is set, because1929	 * PF will push its link status to VFs when link status changed.1930	 */1931	if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state))1932		hclgevf_request_link_info(hdev);1933 1934	hclgevf_update_link_mode(hdev);1935 1936	hclgevf_sync_vlan_filter(hdev);1937 1938	hclgevf_sync_mac_table(hdev);1939 1940	hclgevf_sync_promisc_mode(hdev);1941 1942	hdev->last_serv_processed = jiffies;1943 1944out:1945	hclgevf_task_schedule(hdev, delta);1946}1947 1948static void hclgevf_service_task(struct work_struct *work)1949{1950	struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,1951						service_task.work);1952 1953	hclgevf_reset_service_task(hdev);1954	hclgevf_mailbox_service_task(hdev);1955	hclgevf_periodic_service_task(hdev);1956 1957	/* Handle reset and mbx again in case periodical task delays the1958	 * handling by calling hclgevf_task_schedule() in1959	 * hclgevf_periodic_service_task()1960	 */1961	hclgevf_reset_service_task(hdev);1962	hclgevf_mailbox_service_task(hdev);1963}1964 1965static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)1966{1967	hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr);1968}1969 1970static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,1971						      u32 *clearval)1972{1973	u32 val, cmdq_stat_reg, rst_ing_reg;1974 1975	/* fetch the events from their corresponding regs */1976	cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,1977					 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG);1978	if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {1979		rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);1980		dev_info(&hdev->pdev->dev,1981			 "receive reset interrupt 0x%x!\n", rst_ing_reg);1982		set_bit(HNAE3_VF_RESET, &hdev->reset_pending);1983		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);1984		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);1985		*clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);1986		hdev->rst_stats.vf_rst_cnt++;1987		/* set up VF hardware reset status, its PF will clear1988		 * this status when PF has initialized done.1989		 */1990		val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);1991		hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,1992				  val | HCLGEVF_VF_RST_ING_BIT);1993		return HCLGEVF_VECTOR0_EVENT_RST;1994	}1995 1996	/* check for vector0 mailbox(=CMDQ RX) event source */1997	if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {1998		/* for revision 0x21, clearing interrupt is writing bit 01999		 * to the clear register, writing bit 1 means to keep the2000		 * old value.2001		 * for revision 0x20, the clear register is a read & write2002		 * register, so we should just write 0 to the bit we are2003		 * handling, and keep other bits as cmdq_stat_reg.2004		 */2005		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)2006			*clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);2007		else2008			*clearval = cmdq_stat_reg &2009				    ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);2010 2011		return HCLGEVF_VECTOR0_EVENT_MBX;2012	}2013 2014	/* print other vector0 event source */2015	dev_info(&hdev->pdev->dev,2016		 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",2017		 cmdq_stat_reg);2018 2019	return HCLGEVF_VECTOR0_EVENT_OTHER;2020}2021 2022static void hclgevf_reset_timer(struct timer_list *t)2023{2024	struct hclgevf_dev *hdev = from_timer(hdev, t, reset_timer);2025 2026	hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST);2027	hclgevf_reset_task_schedule(hdev);2028}2029 2030static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)2031{2032#define HCLGEVF_RESET_DELAY	52033 2034	enum hclgevf_evt_cause event_cause;2035	struct hclgevf_dev *hdev = data;2036	u32 clearval;2037 2038	hclgevf_enable_vector(&hdev->misc_vector, false);2039	event_cause = hclgevf_check_evt_cause(hdev, &clearval);2040	if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)2041		hclgevf_clear_event_cause(hdev, clearval);2042 2043	switch (event_cause) {2044	case HCLGEVF_VECTOR0_EVENT_RST:2045		mod_timer(&hdev->reset_timer,2046			  jiffies + msecs_to_jiffies(HCLGEVF_RESET_DELAY));2047		break;2048	case HCLGEVF_VECTOR0_EVENT_MBX:2049		hclgevf_mbx_handler(hdev);2050		break;2051	default:2052		break;2053	}2054 2055	hclgevf_enable_vector(&hdev->misc_vector, true);2056 2057	return IRQ_HANDLED;2058}2059 2060static int hclgevf_configure(struct hclgevf_dev *hdev)2061{2062	int ret;2063 2064	hdev->gro_en = true;2065 2066	ret = hclgevf_get_basic_info(hdev);2067	if (ret)2068		return ret;2069 2070	/* get current port based vlan state from PF */2071	ret = hclgevf_get_port_base_vlan_filter_state(hdev);2072	if (ret)2073		return ret;2074 2075	/* get queue configuration from PF */2076	ret = hclgevf_get_queue_info(hdev);2077	if (ret)2078		return ret;2079 2080	/* get queue depth info from PF */2081	ret = hclgevf_get_queue_depth(hdev);2082	if (ret)2083		return ret;2084 2085	return hclgevf_get_pf_media_type(hdev);2086}2087 2088static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)2089{2090	struct pci_dev *pdev = ae_dev->pdev;2091	struct hclgevf_dev *hdev;2092 2093	hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);2094	if (!hdev)2095		return -ENOMEM;2096 2097	hdev->pdev = pdev;2098	hdev->ae_dev = ae_dev;2099	ae_dev->priv = hdev;2100 2101	return 0;2102}2103 2104static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)2105{2106	struct hnae3_handle *roce = &hdev->roce;2107	struct hnae3_handle *nic = &hdev->nic;2108 2109	roce->rinfo.num_vectors = hdev->num_roce_msix;2110 2111	if (hdev->num_msi_left < roce->rinfo.num_vectors ||2112	    hdev->num_msi_left == 0)2113		return -EINVAL;2114 2115	roce->rinfo.base_vector = hdev->roce_base_msix_offset;2116 2117	roce->rinfo.netdev = nic->kinfo.netdev;2118	roce->rinfo.roce_io_base = hdev->hw.hw.io_base;2119	roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;2120 2121	roce->pdev = nic->pdev;2122	roce->ae_algo = nic->ae_algo;2123	bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits,2124		    MAX_NUMNODES);2125	return 0;2126}2127 2128static int hclgevf_config_gro(struct hclgevf_dev *hdev)2129{2130	struct hclgevf_cfg_gro_status_cmd *req;2131	struct hclge_desc desc;2132	int ret;2133 2134	if (!hnae3_ae_dev_gro_supported(hdev->ae_dev))2135		return 0;2136 2137	hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG,2138				     false);2139	req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;2140 2141	req->gro_en = hdev->gro_en ? 1 : 0;2142 2143	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);2144	if (ret)2145		dev_err(&hdev->pdev->dev,2146			"VF GRO hardware config cmd failed, ret = %d.\n", ret);2147 2148	return ret;2149}2150 2151static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)2152{2153	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;2154	u16 tc_offset[HCLGE_COMM_MAX_TC_NUM];2155	u16 tc_valid[HCLGE_COMM_MAX_TC_NUM];2156	u16 tc_size[HCLGE_COMM_MAX_TC_NUM];2157	int ret;2158 2159	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {2160		ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw,2161						  rss_cfg->rss_algo,2162						  rss_cfg->rss_hash_key);2163		if (ret)2164			return ret;2165 2166		ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, rss_cfg);2167		if (ret)2168			return ret;2169	}2170 2171	ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,2172					     rss_cfg->rss_indirection_tbl);2173	if (ret)2174		return ret;2175 2176	hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map,2177				   tc_offset, tc_valid, tc_size);2178 2179	return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset,2180					  tc_valid, tc_size);2181}2182 2183static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)2184{2185	struct hnae3_handle *nic = &hdev->nic;2186	int ret;2187 2188	ret = hclgevf_en_hw_strip_rxvtag(nic, true);2189	if (ret) {2190		dev_err(&hdev->pdev->dev,2191			"failed to enable rx vlan offload, ret = %d\n", ret);2192		return ret;2193	}2194 2195	return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,2196				       false);2197}2198 2199static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)2200{2201#define HCLGEVF_FLUSH_LINK_TIMEOUT	1000002202 2203	unsigned long last = hdev->serv_processed_cnt;2204	int i = 0;2205 2206	while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&2207	       i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&2208	       last == hdev->serv_processed_cnt)2209		usleep_range(1, 1);2210}2211 2212static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)2213{2214	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);2215 2216	if (enable) {2217		hclgevf_task_schedule(hdev, 0);2218	} else {2219		set_bit(HCLGEVF_STATE_DOWN, &hdev->state);2220 2221		smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */2222		hclgevf_flush_link_update(hdev);2223	}2224}2225 2226static int hclgevf_ae_start(struct hnae3_handle *handle)2227{2228	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);2229 2230	clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);2231	clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state);2232 2233	hclge_comm_reset_tqp_stats(handle);2234 2235	hclgevf_request_link_info(hdev);2236 2237	hclgevf_update_link_mode(hdev);2238 2239	return 0;2240}2241 2242static void hclgevf_ae_stop(struct hnae3_handle *handle)2243{2244	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);2245 2246	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);2247 2248	if (hdev->reset_type != HNAE3_VF_RESET)2249		hclgevf_reset_tqp(handle);2250 2251	hclge_comm_reset_tqp_stats(handle);2252	hclgevf_update_link_status(hdev, 0);2253}2254 2255static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)2256{2257#define HCLGEVF_STATE_ALIVE	12258#define HCLGEVF_STATE_NOT_ALIVE	02259 2260	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);2261	struct hclge_vf_to_pf_msg send_msg;2262 2263	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);2264	send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :2265				HCLGEVF_STATE_NOT_ALIVE;2266	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);2267}2268 2269static int hclgevf_client_start(struct hnae3_handle *handle)2270{2271	return hclgevf_set_alive(handle, true);2272}2273 2274static void hclgevf_client_stop(struct hnae3_handle *handle)2275{2276	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);2277	int ret;2278 2279	ret = hclgevf_set_alive(handle, false);2280	if (ret)2281		dev_warn(&hdev->pdev->dev,2282			 "%s failed %d\n", __func__, ret);2283}2284 2285static void hclgevf_state_init(struct hclgevf_dev *hdev)2286{2287	clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);2288	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);2289	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);2290 2291	INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);2292 2293	mutex_init(&hdev->mbx_resp.mbx_mutex);2294	sema_init(&hdev->reset_sem, 1);2295 2296	spin_lock_init(&hdev->mac_table.mac_list_lock);2297	INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);2298	INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);2299 2300	/* bring the device down */2301	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);2302}2303 2304static void hclgevf_state_uninit(struct hclgevf_dev *hdev)2305{2306	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);2307	set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);2308 2309	if (hdev->service_task.work.func)2310		cancel_delayed_work_sync(&hdev->service_task);2311 2312	mutex_destroy(&hdev->mbx_resp.mbx_mutex);2313}2314 2315static int hclgevf_init_msi(struct hclgevf_dev *hdev)2316{2317	struct pci_dev *pdev = hdev->pdev;2318	int vectors;2319	int i;2320 2321	if (hnae3_dev_roce_supported(hdev))2322		vectors = pci_alloc_irq_vectors(pdev,2323						hdev->roce_base_msix_offset + 1,2324						hdev->num_msi,2325						PCI_IRQ_MSIX);2326	else2327		vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,2328						hdev->num_msi,2329						PCI_IRQ_MSI | PCI_IRQ_MSIX);2330 2331	if (vectors < 0) {2332		dev_err(&pdev->dev,2333			"failed(%d) to allocate MSI/MSI-X vectors\n",2334			vectors);2335		return vectors;2336	}2337	if (vectors < hdev->num_msi)2338		dev_warn(&hdev->pdev->dev,2339			 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",2340			 hdev->num_msi, vectors);2341 2342	hdev->num_msi = vectors;2343	hdev->num_msi_left = vectors;2344 2345	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,2346					   sizeof(u16), GFP_KERNEL);2347	if (!hdev->vector_status) {2348		pci_free_irq_vectors(pdev);2349		return -ENOMEM;2350	}2351 2352	for (i = 0; i < hdev->num_msi; i++)2353		hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;2354 2355	hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,2356					sizeof(int), GFP_KERNEL);2357	if (!hdev->vector_irq) {2358		devm_kfree(&pdev->dev, hdev->vector_status);2359		pci_free_irq_vectors(pdev);2360		return -ENOMEM;2361	}2362 2363	return 0;2364}2365 2366static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)2367{2368	struct pci_dev *pdev = hdev->pdev;2369 2370	devm_kfree(&pdev->dev, hdev->vector_status);2371	devm_kfree(&pdev->dev, hdev->vector_irq);2372	pci_free_irq_vectors(pdev);2373}2374 2375static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)2376{2377	int ret;2378 2379	hclgevf_get_misc_vector(hdev);2380 2381	snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",2382		 HCLGEVF_NAME, pci_name(hdev->pdev));2383	ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,2384			  0, hdev->misc_vector.name, hdev);2385	if (ret) {2386		dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",2387			hdev->misc_vector.vector_irq);2388		return ret;2389	}2390 2391	hclgevf_clear_event_cause(hdev, 0);2392 2393	/* enable misc. vector(vector 0) */2394	hclgevf_enable_vector(&hdev->misc_vector, true);2395 2396	return ret;2397}2398 2399static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)2400{2401	/* disable misc vector(vector 0) */2402	hclgevf_enable_vector(&hdev->misc_vector, false);2403	synchronize_irq(hdev->misc_vector.vector_irq);2404	free_irq(hdev->misc_vector.vector_irq, hdev);2405	hclgevf_free_vector(hdev, 0);2406}2407 2408static void hclgevf_info_show(struct hclgevf_dev *hdev)2409{2410	struct device *dev = &hdev->pdev->dev;2411 2412	dev_info(dev, "VF info begin:\n");2413 2414	dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);2415	dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);2416	dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);2417	dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);2418	dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);2419	dev_info(dev, "PF media type of this VF: %u\n",2420		 hdev->hw.mac.media_type);2421 2422	dev_info(dev, "VF info end.\n");2423}2424 2425static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,2426					    struct hnae3_client *client)2427{2428	struct hclgevf_dev *hdev = ae_dev->priv;2429	int rst_cnt = hdev->rst_stats.rst_cnt;2430	int ret;2431 2432	ret = client->ops->init_instance(&hdev->nic);2433	if (ret)2434		return ret;2435 2436	set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);2437	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||2438	    rst_cnt != hdev->rst_stats.rst_cnt) {2439		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);2440 2441		client->ops->uninit_instance(&hdev->nic, 0);2442		return -EBUSY;2443	}2444 2445	hnae3_set_client_init_flag(client, ae_dev, 1);2446 2447	if (netif_msg_drv(&hdev->nic))2448		hclgevf_info_show(hdev);2449 2450	return 0;2451}2452 2453static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,2454					     struct hnae3_client *client)2455{2456	struct hclgevf_dev *hdev = ae_dev->priv;2457	int ret;2458 2459	if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||2460	    !hdev->nic_client)2461		return 0;2462 2463	ret = hclgevf_init_roce_base_info(hdev);2464	if (ret)2465		return ret;2466 2467	ret = client->ops->init_instance(&hdev->roce);2468	if (ret)2469		return ret;2470 2471	set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);2472	hnae3_set_client_init_flag(client, ae_dev, 1);2473 2474	return 0;2475}2476 2477static int hclgevf_init_client_instance(struct hnae3_client *client,2478					struct hnae3_ae_dev *ae_dev)2479{2480	struct hclgevf_dev *hdev = ae_dev->priv;2481	int ret;2482 2483	switch (client->type) {2484	case HNAE3_CLIENT_KNIC:2485		hdev->nic_client = client;2486		hdev->nic.client = client;2487 2488		ret = hclgevf_init_nic_client_instance(ae_dev, client);2489		if (ret)2490			goto clear_nic;2491 2492		ret = hclgevf_init_roce_client_instance(ae_dev,2493							hdev->roce_client);2494		if (ret)2495			goto clear_roce;2496 2497		break;2498	case HNAE3_CLIENT_ROCE:2499		if (hnae3_dev_roce_supported(hdev)) {2500			hdev->roce_client = client;2501			hdev->roce.client = client;2502		}2503 2504		ret = hclgevf_init_roce_client_instance(ae_dev, client);2505		if (ret)2506			goto clear_roce;2507 2508		break;2509	default:2510		return -EINVAL;2511	}2512 2513	return 0;2514 2515clear_nic:2516	hdev->nic_client = NULL;2517	hdev->nic.client = NULL;2518	return ret;2519clear_roce:2520	hdev->roce_client = NULL;2521	hdev->roce.client = NULL;2522	return ret;2523}2524 2525static void hclgevf_uninit_client_instance(struct hnae3_client *client,2526					   struct hnae3_ae_dev *ae_dev)2527{2528	struct hclgevf_dev *hdev = ae_dev->priv;2529 2530	/* un-init roce, if it exists */2531	if (hdev->roce_client) {2532		while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))2533			msleep(HCLGEVF_WAIT_RESET_DONE);2534		clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);2535 2536		hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);2537		hdev->roce_client = NULL;2538		hdev->roce.client = NULL;2539	}2540 2541	/* un-init nic/unic, if this was not called by roce client */2542	if (client->ops->uninit_instance && hdev->nic_client &&2543	    client->type != HNAE3_CLIENT_ROCE) {2544		while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))2545			msleep(HCLGEVF_WAIT_RESET_DONE);2546		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);2547 2548		client->ops->uninit_instance(&hdev->nic, 0);2549		hdev->nic_client = NULL;2550		hdev->nic.client = NULL;2551	}2552}2553 2554static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)2555{2556	struct pci_dev *pdev = hdev->pdev;2557	struct hclgevf_hw *hw = &hdev->hw;2558 2559	/* for device does not have device memory, return directly */2560	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))2561		return 0;2562 2563	hw->hw.mem_base =2564		devm_ioremap_wc(&pdev->dev,2565				pci_resource_start(pdev, HCLGEVF_MEM_BAR),2566				pci_resource_len(pdev, HCLGEVF_MEM_BAR));2567	if (!hw->hw.mem_base) {2568		dev_err(&pdev->dev, "failed to map device memory\n");2569		return -EFAULT;2570	}2571 2572	return 0;2573}2574 2575static int hclgevf_pci_init(struct hclgevf_dev *hdev)2576{2577	struct pci_dev *pdev = hdev->pdev;2578	struct hclgevf_hw *hw;2579	int ret;2580 2581	ret = pci_enable_device(pdev);2582	if (ret) {2583		dev_err(&pdev->dev, "failed to enable PCI device\n");2584		return ret;2585	}2586 2587	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));2588	if (ret) {2589		dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");2590		goto err_disable_device;2591	}2592 2593	ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);2594	if (ret) {2595		dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);2596		goto err_disable_device;2597	}2598 2599	pci_set_master(pdev);2600	hw = &hdev->hw;2601	hw->hw.io_base = pci_iomap(pdev, 2, 0);2602	if (!hw->hw.io_base) {2603		dev_err(&pdev->dev, "can't map configuration register space\n");2604		ret = -ENOMEM;2605		goto err_release_regions;2606	}2607 2608	ret = hclgevf_dev_mem_map(hdev);2609	if (ret)2610		goto err_unmap_io_base;2611 2612	return 0;2613 2614err_unmap_io_base:2615	pci_iounmap(pdev, hdev->hw.hw.io_base);2616err_release_regions:2617	pci_release_regions(pdev);2618err_disable_device:2619	pci_disable_device(pdev);2620 2621	return ret;2622}2623 2624static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)2625{2626	struct pci_dev *pdev = hdev->pdev;2627 2628	if (hdev->hw.hw.mem_base)2629		devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);2630 2631	pci_iounmap(pdev, hdev->hw.hw.io_base);2632	pci_release_regions(pdev);2633	pci_disable_device(pdev);2634}2635 2636static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)2637{2638	struct hclgevf_query_res_cmd *req;2639	struct hclge_desc desc;2640	int ret;2641 2642	hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true);2643	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);2644	if (ret) {2645		dev_err(&hdev->pdev->dev,2646			"query vf resource failed, ret = %d.\n", ret);2647		return ret;2648	}2649 2650	req = (struct hclgevf_query_res_cmd *)desc.data;2651 2652	if (hnae3_dev_roce_supported(hdev)) {2653		hdev->roce_base_msix_offset =2654		hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),2655				HCLGEVF_MSIX_OFT_ROCEE_M,2656				HCLGEVF_MSIX_OFT_ROCEE_S);2657		hdev->num_roce_msix =2658		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),2659				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);2660 2661		/* nic's msix numbers is always equals to the roce's. */2662		hdev->num_nic_msix = hdev->num_roce_msix;2663 2664		/* VF should have NIC vectors and Roce vectors, NIC vectors2665		 * are queued before Roce vectors. The offset is fixed to 64.2666		 */2667		hdev->num_msi = hdev->num_roce_msix +2668				hdev->roce_base_msix_offset;2669	} else {2670		hdev->num_msi =2671		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),2672				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);2673 2674		hdev->num_nic_msix = hdev->num_msi;2675	}2676 2677	if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {2678		dev_err(&hdev->pdev->dev,2679			"Just %u msi resources, not enough for vf(min:2).\n",2680			hdev->num_nic_msix);2681		return -EINVAL;2682	}2683 2684	return 0;2685}2686 2687static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)2688{2689#define HCLGEVF_MAX_NON_TSO_BD_NUM			8U2690 2691	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);2692 2693	ae_dev->dev_specs.max_non_tso_bd_num =2694					HCLGEVF_MAX_NON_TSO_BD_NUM;2695	ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;2696	ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;2697	ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;2698	ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME;2699}2700 2701static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,2702				    struct hclge_desc *desc)2703{2704	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);2705	struct hclgevf_dev_specs_0_cmd *req0;2706	struct hclgevf_dev_specs_1_cmd *req1;2707 2708	req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;2709	req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;2710 2711	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;2712	ae_dev->dev_specs.rss_ind_tbl_size =2713					le16_to_cpu(req0->rss_ind_tbl_size);2714	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);2715	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);2716	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);2717	ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);2718}2719 2720static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)2721{2722	struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;2723 2724	if (!dev_specs->max_non_tso_bd_num)2725		dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;2726	if (!dev_specs->rss_ind_tbl_size)2727		dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;2728	if (!dev_specs->rss_key_size)2729		dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;2730	if (!dev_specs->max_int_gl)2731		dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;2732	if (!dev_specs->max_frm_size)2733		dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME;2734}2735 2736static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)2737{2738	struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];2739	int ret;2740	int i;2741 2742	/* set default specifications as devices lower than version V3 do not2743	 * support querying specifications from firmware.2744	 */2745	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {2746		hclgevf_set_default_dev_specs(hdev);2747		return 0;2748	}2749 2750	for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {2751		hclgevf_cmd_setup_basic_desc(&desc[i],2752					     HCLGE_OPC_QUERY_DEV_SPECS, true);2753		desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);2754	}2755	hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);2756 2757	ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);2758	if (ret)2759		return ret;2760 2761	hclgevf_parse_dev_specs(hdev, desc);2762	hclgevf_check_dev_specs(hdev);2763 2764	return 0;2765}2766 2767static int hclgevf_pci_reset(struct hclgevf_dev *hdev)2768{2769	struct pci_dev *pdev = hdev->pdev;2770	int ret = 0;2771 2772	if ((hdev->reset_type == HNAE3_VF_FULL_RESET ||2773	     hdev->reset_type == HNAE3_FLR_RESET) &&2774	    test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {2775		hclgevf_misc_irq_uninit(hdev);2776		hclgevf_uninit_msi(hdev);2777		clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);2778	}2779 2780	if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {2781		pci_set_master(pdev);2782		ret = hclgevf_init_msi(hdev);2783		if (ret) {2784			dev_err(&pdev->dev,2785				"failed(%d) to init MSI/MSI-X\n", ret);2786			return ret;2787		}2788 2789		ret = hclgevf_misc_irq_init(hdev);2790		if (ret) {2791			hclgevf_uninit_msi(hdev);2792			dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",2793				ret);2794			return ret;2795		}2796 2797		set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);2798	}2799 2800	return ret;2801}2802 2803static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)2804{2805	struct hclge_vf_to_pf_msg send_msg;2806 2807	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,2808			       HCLGE_MBX_VPORT_LIST_CLEAR);2809	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);2810}2811 2812static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev)2813{2814	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))2815		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1);2816}2817 2818static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev)2819{2820	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))2821		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0);2822}2823 2824static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)2825{2826	struct pci_dev *pdev = hdev->pdev;2827	int ret;2828 2829	ret = hclgevf_pci_reset(hdev);2830	if (ret) {2831		dev_err(&pdev->dev, "pci reset failed %d\n", ret);2832		return ret;2833	}2834 2835	hclgevf_arq_init(hdev);2836 2837	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,2838				  &hdev->fw_version, false,2839				  hdev->reset_pending);2840	if (ret) {2841		dev_err(&pdev->dev, "cmd failed %d\n", ret);2842		return ret;2843	}2844 2845	ret = hclgevf_rss_init_hw(hdev);2846	if (ret) {2847		dev_err(&hdev->pdev->dev,2848			"failed(%d) to initialize RSS\n", ret);2849		return ret;2850	}2851 2852	ret = hclgevf_config_gro(hdev);2853	if (ret)2854		return ret;2855 2856	ret = hclgevf_init_vlan_config(hdev);2857	if (ret) {2858		dev_err(&hdev->pdev->dev,2859			"failed(%d) to initialize VLAN config\n", ret);2860		return ret;2861	}2862 2863	/* get current port based vlan state from PF */2864	ret = hclgevf_get_port_base_vlan_filter_state(hdev);2865	if (ret)2866		return ret;2867 2868	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);2869 2870	hclgevf_init_rxd_adv_layout(hdev);2871 2872	dev_info(&hdev->pdev->dev, "Reset done\n");2873 2874	return 0;2875}2876 2877static int hclgevf_init_hdev(struct hclgevf_dev *hdev)2878{2879	struct pci_dev *pdev = hdev->pdev;2880	int ret;2881 2882	ret = hclgevf_pci_init(hdev);2883	if (ret)2884		return ret;2885 2886	ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);2887	if (ret)2888		goto err_cmd_queue_init;2889 2890	hclgevf_arq_init(hdev);2891 2892	hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclgevf_cmq_ops);2893	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,2894				  &hdev->fw_version, false,2895				  hdev->reset_pending);2896	if (ret)2897		goto err_cmd_init;2898 2899	/* Get vf resource */2900	ret = hclgevf_query_vf_resource(hdev);2901	if (ret)2902		goto err_cmd_init;2903 2904	ret = hclgevf_query_dev_specs(hdev);2905	if (ret) {2906		dev_err(&pdev->dev,2907			"failed to query dev specifications, ret = %d\n", ret);2908		goto err_cmd_init;2909	}2910 2911	ret = hclgevf_init_msi(hdev);2912	if (ret) {2913		dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);2914		goto err_cmd_init;2915	}2916 2917	hclgevf_state_init(hdev);2918	hdev->reset_level = HNAE3_VF_FUNC_RESET;2919	hdev->reset_type = HNAE3_NONE_RESET;2920 2921	ret = hclgevf_misc_irq_init(hdev);2922	if (ret)2923		goto err_misc_irq_init;2924 2925	set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);2926 2927	ret = hclgevf_configure(hdev);2928	if (ret) {2929		dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);2930		goto err_config;2931	}2932 2933	ret = hclgevf_alloc_tqps(hdev);2934	if (ret) {2935		dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);2936		goto err_config;2937	}2938 2939	ret = hclgevf_set_handle_info(hdev);2940	if (ret)2941		goto err_config;2942 2943	ret = hclgevf_config_gro(hdev);2944	if (ret)2945		goto err_config;2946 2947	/* Initialize RSS for this VF */2948	ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev,2949				      &hdev->rss_cfg);2950	if (ret) {2951		dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);2952		goto err_config;2953	}2954 2955	ret = hclgevf_rss_init_hw(hdev);2956	if (ret) {2957		dev_err(&hdev->pdev->dev,2958			"failed(%d) to initialize RSS\n", ret);2959		goto err_config;2960	}2961 2962	/* ensure vf tbl list as empty before init */2963	ret = hclgevf_clear_vport_list(hdev);2964	if (ret) {2965		dev_err(&pdev->dev,2966			"failed to clear tbl list configuration, ret = %d.\n",2967			ret);2968		goto err_config;2969	}2970 2971	ret = hclgevf_init_vlan_config(hdev);2972	if (ret) {2973		dev_err(&hdev->pdev->dev,2974			"failed(%d) to initialize VLAN config\n", ret);2975		goto err_config;2976	}2977 2978	hclgevf_init_rxd_adv_layout(hdev);2979 2980	ret = hclgevf_devlink_init(hdev);2981	if (ret)2982		goto err_config;2983 2984	set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state);2985 2986	hdev->last_reset_time = jiffies;2987	dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",2988		 HCLGEVF_DRIVER_NAME);2989 2990	hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));2991	timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0);2992 2993	return 0;2994 2995err_config:2996	hclgevf_misc_irq_uninit(hdev);2997err_misc_irq_init:2998	hclgevf_state_uninit(hdev);2999	hclgevf_uninit_msi(hdev);3000err_cmd_init:3001	hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);3002err_cmd_queue_init:3003	hclgevf_pci_uninit(hdev);3004	clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);3005	return ret;3006}3007 3008static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)3009{3010	struct hclge_vf_to_pf_msg send_msg;3011 3012	hclgevf_state_uninit(hdev);3013	hclgevf_uninit_rxd_adv_layout(hdev);3014 3015	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);3016	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);3017 3018	if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {3019		hclgevf_misc_irq_uninit(hdev);3020		hclgevf_uninit_msi(hdev);3021	}3022 3023	hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);3024	hclgevf_devlink_uninit(hdev);3025	hclgevf_pci_uninit(hdev);3026	hclgevf_uninit_mac_list(hdev);3027}3028 3029static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)3030{3031	struct pci_dev *pdev = ae_dev->pdev;3032	int ret;3033 3034	ret = hclgevf_alloc_hdev(ae_dev);3035	if (ret) {3036		dev_err(&pdev->dev, "hclge device allocation failed\n");3037		return ret;3038	}3039 3040	ret = hclgevf_init_hdev(ae_dev->priv);3041	if (ret) {3042		dev_err(&pdev->dev, "hclge device initialization failed\n");3043		return ret;3044	}3045 3046	return 0;3047}3048 3049static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)3050{3051	struct hclgevf_dev *hdev = ae_dev->priv;3052 3053	hclgevf_uninit_hdev(hdev);3054	ae_dev->priv = NULL;3055}3056 3057static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)3058{3059	struct hnae3_handle *nic = &hdev->nic;3060	struct hnae3_knic_private_info *kinfo = &nic->kinfo;3061 3062	return min_t(u32, hdev->rss_size_max,3063		     hdev->num_tqps / kinfo->tc_info.num_tc);3064}3065 3066/**3067 * hclgevf_get_channels - Get the current channels enabled and max supported.3068 * @handle: hardware information for network interface3069 * @ch: ethtool channels structure3070 *3071 * We don't support separate tx and rx queues as channels. The other count3072 * represents how many queues are being used for control. max_combined counts3073 * how many queue pairs we can support. They may not be mapped 1 to 1 with3074 * q_vectors since we support a lot more queue pairs than q_vectors.3075 **/3076static void hclgevf_get_channels(struct hnae3_handle *handle,3077				 struct ethtool_channels *ch)3078{3079	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3080 3081	ch->max_combined = hclgevf_get_max_channels(hdev);3082	ch->other_count = 0;3083	ch->max_other = 0;3084	ch->combined_count = handle->kinfo.rss_size;3085}3086 3087static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,3088					  u16 *alloc_tqps, u16 *max_rss_size)3089{3090	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3091 3092	*alloc_tqps = hdev->num_tqps;3093	*max_rss_size = hdev->rss_size_max;3094}3095 3096static void hclgevf_update_rss_size(struct hnae3_handle *handle,3097				    u32 new_tqps_num)3098{3099	struct hnae3_knic_private_info *kinfo = &handle->kinfo;3100	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3101	u16 max_rss_size;3102 3103	kinfo->req_rss_size = new_tqps_num;3104 3105	max_rss_size = min_t(u16, hdev->rss_size_max,3106			     hdev->num_tqps / kinfo->tc_info.num_tc);3107 3108	/* Use the user's configuration when it is not larger than3109	 * max_rss_size, otherwise, use the maximum specification value.3110	 */3111	if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&3112	    kinfo->req_rss_size <= max_rss_size)3113		kinfo->rss_size = kinfo->req_rss_size;3114	else if (kinfo->rss_size > max_rss_size ||3115		 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))3116		kinfo->rss_size = max_rss_size;3117 3118	kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size;3119}3120 3121static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,3122				bool rxfh_configured)3123{3124	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3125	struct hnae3_knic_private_info *kinfo = &handle->kinfo;3126	u16 tc_offset[HCLGE_COMM_MAX_TC_NUM];3127	u16 tc_valid[HCLGE_COMM_MAX_TC_NUM];3128	u16 tc_size[HCLGE_COMM_MAX_TC_NUM];3129	u16 cur_rss_size = kinfo->rss_size;3130	u16 cur_tqps = kinfo->num_tqps;3131	u32 *rss_indir;3132	unsigned int i;3133	int ret;3134 3135	hclgevf_update_rss_size(handle, new_tqps_num);3136 3137	hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map,3138				   tc_offset, tc_valid, tc_size);3139	ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset,3140					 tc_valid, tc_size);3141	if (ret)3142		return ret;3143 3144	/* RSS indirection table has been configured by user */3145	if (rxfh_configured)3146		goto out;3147 3148	/* Reinitializes the rss indirect table according to the new RSS size */3149	rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size,3150			    sizeof(u32), GFP_KERNEL);3151	if (!rss_indir)3152		return -ENOMEM;3153 3154	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)3155		rss_indir[i] = i % kinfo->rss_size;3156 3157	hdev->rss_cfg.rss_size = kinfo->rss_size;3158 3159	ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);3160	if (ret)3161		dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",3162			ret);3163 3164	kfree(rss_indir);3165 3166out:3167	if (!ret)3168		dev_info(&hdev->pdev->dev,3169			 "Channels changed, rss_size from %u to %u, tqps from %u to %u",3170			 cur_rss_size, kinfo->rss_size,3171			 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);3172 3173	return ret;3174}3175 3176static int hclgevf_get_status(struct hnae3_handle *handle)3177{3178	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3179 3180	return hdev->hw.mac.link;3181}3182 3183static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,3184					    u8 *auto_neg, u32 *speed,3185					    u8 *duplex, u32 *lane_num)3186{3187	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3188 3189	if (speed)3190		*speed = hdev->hw.mac.speed;3191	if (duplex)3192		*duplex = hdev->hw.mac.duplex;3193	if (auto_neg)3194		*auto_neg = AUTONEG_DISABLE;3195}3196 3197void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,3198				 u8 duplex)3199{3200	hdev->hw.mac.speed = speed;3201	hdev->hw.mac.duplex = duplex;3202}3203 3204static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)3205{3206	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3207	bool gro_en_old = hdev->gro_en;3208	int ret;3209 3210	hdev->gro_en = enable;3211	ret = hclgevf_config_gro(hdev);3212	if (ret)3213		hdev->gro_en = gro_en_old;3214 3215	return ret;3216}3217 3218static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,3219				   u8 *module_type)3220{3221	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3222 3223	if (media_type)3224		*media_type = hdev->hw.mac.media_type;3225 3226	if (module_type)3227		*module_type = hdev->hw.mac.module_type;3228}3229 3230static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)3231{3232	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3233 3234	return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);3235}3236 3237static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)3238{3239	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3240 3241	return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);3242}3243 3244static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)3245{3246	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3247 3248	return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);3249}3250 3251static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)3252{3253	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3254 3255	return hdev->rst_stats.hw_rst_done_cnt;3256}3257 3258static void hclgevf_get_link_mode(struct hnae3_handle *handle,3259				  unsigned long *supported,3260				  unsigned long *advertising)3261{3262	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);3263 3264	*supported = hdev->hw.mac.supported;3265	*advertising = hdev->hw.mac.advertising;3266}3267 3268void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,3269				struct hclge_mbx_port_base_vlan *port_base_vlan)3270{3271	struct hnae3_handle *nic = &hdev->nic;3272	struct hclge_vf_to_pf_msg send_msg;3273	int ret;3274 3275	rtnl_lock();3276 3277	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||3278	    test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {3279		dev_warn(&hdev->pdev->dev,3280			 "is resetting when updating port based vlan info\n");3281		rtnl_unlock();3282		return;3283	}3284 3285	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);3286	if (ret) {3287		rtnl_unlock();3288		return;3289	}3290 3291	/* send msg to PF and wait update port based vlan info */3292	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,3293			       HCLGE_MBX_PORT_BASE_VLAN_CFG);3294	memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan));3295	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);3296	if (!ret) {3297		if (state == HNAE3_PORT_BASE_VLAN_DISABLE)3298			nic->port_base_vlan_state = state;3299		else3300			nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;3301	}3302 3303	hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);3304	rtnl_unlock();3305}3306 3307static const struct hnae3_ae_ops hclgevf_ops = {3308	.init_ae_dev = hclgevf_init_ae_dev,3309	.uninit_ae_dev = hclgevf_uninit_ae_dev,3310	.reset_prepare = hclgevf_reset_prepare_general,3311	.reset_done = hclgevf_reset_done,3312	.init_client_instance = hclgevf_init_client_instance,3313	.uninit_client_instance = hclgevf_uninit_client_instance,3314	.start = hclgevf_ae_start,3315	.stop = hclgevf_ae_stop,3316	.client_start = hclgevf_client_start,3317	.client_stop = hclgevf_client_stop,3318	.map_ring_to_vector = hclgevf_map_ring_to_vector,3319	.unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,3320	.get_vector = hclgevf_get_vector,3321	.put_vector = hclgevf_put_vector,3322	.reset_queue = hclgevf_reset_tqp,3323	.get_mac_addr = hclgevf_get_mac_addr,3324	.set_mac_addr = hclgevf_set_mac_addr,3325	.add_uc_addr = hclgevf_add_uc_addr,3326	.rm_uc_addr = hclgevf_rm_uc_addr,3327	.add_mc_addr = hclgevf_add_mc_addr,3328	.rm_mc_addr = hclgevf_rm_mc_addr,3329	.get_stats = hclgevf_get_stats,3330	.update_stats = hclgevf_update_stats,3331	.get_strings = hclgevf_get_strings,3332	.get_sset_count = hclgevf_get_sset_count,3333	.get_rss_key_size = hclge_comm_get_rss_key_size,3334	.get_rss = hclgevf_get_rss,3335	.set_rss = hclgevf_set_rss,3336	.get_rss_tuple = hclgevf_get_rss_tuple,3337	.set_rss_tuple = hclgevf_set_rss_tuple,3338	.get_tc_size = hclgevf_get_tc_size,3339	.get_fw_version = hclgevf_get_fw_version,3340	.set_vlan_filter = hclgevf_set_vlan_filter,3341	.enable_vlan_filter = hclgevf_enable_vlan_filter,3342	.enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,3343	.reset_event = hclgevf_reset_event,3344	.set_default_reset_request = hclgevf_set_def_reset_request,3345	.set_channels = hclgevf_set_channels,3346	.get_channels = hclgevf_get_channels,3347	.get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,3348	.get_regs_len = hclgevf_get_regs_len,3349	.get_regs = hclgevf_get_regs,3350	.get_status = hclgevf_get_status,3351	.get_ksettings_an_result = hclgevf_get_ksettings_an_result,3352	.get_media_type = hclgevf_get_media_type,3353	.get_hw_reset_stat = hclgevf_get_hw_reset_stat,3354	.ae_dev_resetting = hclgevf_ae_dev_resetting,3355	.ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,3356	.set_gro_en = hclgevf_gro_en,3357	.set_mtu = hclgevf_set_mtu,3358	.get_global_queue_id = hclgevf_get_qid_global,3359	.set_timer_task = hclgevf_set_timer_task,3360	.get_link_mode = hclgevf_get_link_mode,3361	.set_promisc_mode = hclgevf_set_promisc_mode,3362	.request_update_promisc_mode = hclgevf_request_update_promisc_mode,3363	.get_cmdq_stat = hclgevf_get_cmdq_stat,3364};3365 3366static struct hnae3_ae_algo ae_algovf = {3367	.ops = &hclgevf_ops,3368	.pdev_id_table = ae_algovf_pci_tbl,3369};3370 3371static int __init hclgevf_init(void)3372{3373	pr_info("%s is initializing\n", HCLGEVF_NAME);3374 3375	hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME);3376	if (!hclgevf_wq) {3377		pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);3378		return -ENOMEM;3379	}3380 3381	hnae3_register_ae_algo(&ae_algovf);3382 3383	return 0;3384}3385 3386static void __exit hclgevf_exit(void)3387{3388	hnae3_unregister_ae_algo(&ae_algovf);3389	destroy_workqueue(hclgevf_wq);3390}3391module_init(hclgevf_init);3392module_exit(hclgevf_exit);3393 3394MODULE_LICENSE("GPL");3395MODULE_AUTHOR("Huawei Tech. Co., Ltd.");3396MODULE_DESCRIPTION("HCLGEVF Driver");3397MODULE_VERSION(HCLGEVF_MOD_VERSION);3398