661 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Huawei HiNIC PCI Express Linux driver4 * Copyright(c) 2017 Huawei Technologies Co., Ltd5 */6 7#ifndef HINIC_HW_DEV_H8#define HINIC_HW_DEV_H9 10#include <linux/pci.h>11#include <linux/types.h>12#include <linux/bitops.h>13#include <net/devlink.h>14 15#include "hinic_hw_if.h"16#include "hinic_hw_eqs.h"17#include "hinic_hw_mgmt.h"18#include "hinic_hw_qp.h"19#include "hinic_hw_io.h"20#include "hinic_hw_mbox.h"21 22#define HINIC_MAX_QPS 3223 24#define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \25 HINIC_MGMT_MSG_CMD_BASE)26 27#define HINIC_PF_SET_VF_ALREADY 0x428#define HINIC_MGMT_STATUS_EXIST 0x629#define HINIC_MGMT_CMD_UNSUPPORTED 0xFF30 31#define HINIC_CMD_VER_FUNC_ID 232 33struct hinic_cap {34 u16 max_qps;35 u16 num_qps;36 u8 max_vf;37 u16 max_vf_qps;38};39 40enum hw_ioctxt_set_cmdq_depth {41 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT,42 HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE,43};44 45enum hinic_port_cmd {46 HINIC_PORT_CMD_VF_REGISTER = 0x0,47 HINIC_PORT_CMD_VF_UNREGISTER = 0x1,48 49 HINIC_PORT_CMD_CHANGE_MTU = 0x2,50 51 HINIC_PORT_CMD_ADD_VLAN = 0x3,52 HINIC_PORT_CMD_DEL_VLAN = 0x4,53 54 HINIC_PORT_CMD_SET_ETS = 0x7,55 HINIC_PORT_CMD_GET_ETS = 0x8,56 57 HINIC_PORT_CMD_SET_PFC = 0x5,58 59 HINIC_PORT_CMD_SET_MAC = 0x9,60 HINIC_PORT_CMD_GET_MAC = 0xA,61 HINIC_PORT_CMD_DEL_MAC = 0xB,62 63 HINIC_PORT_CMD_SET_RX_MODE = 0xC,64 65 HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xD,66 67 HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14,68 HINIC_PORT_CMD_SET_PAUSE_INFO = 0x15,69 70 HINIC_PORT_CMD_GET_LINK_STATE = 0x18,71 72 HINIC_PORT_CMD_SET_LRO = 0x19,73 74 HINIC_PORT_CMD_SET_RX_CSUM = 0x1A,75 76 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1B,77 78 HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1C,79 80 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 0x1D,81 82 HINIC_PORT_CMD_GET_VPORT_STAT = 0x1E,83 84 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 0x1F,85 86 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,87 88 HINIC_PORT_CMD_SET_PORT_STATE = 0x29,89 HINIC_PORT_CMD_GET_PORT_STATE = 0x30,90 91 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2B,92 93 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 0x2C,94 95 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 0x2D,96 97 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 0x2E,98 99 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 0x2F,100 101 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 0x30,102 103 HINIC_PORT_CMD_RSS_TEMP_MGR = 0x31,104 105 HINIC_PORT_CMD_RD_LINE_TBL = 0x39,106 107 HINIC_PORT_CMD_RSS_CFG = 0x42,108 109 HINIC_PORT_CMD_GET_PHY_TYPE = 0x44,110 111 HINIC_PORT_CMD_FWCTXT_INIT = 0x45,112 113 HINIC_PORT_CMD_GET_LOOPBACK_MODE = 0x48,114 HINIC_PORT_CMD_SET_LOOPBACK_MODE = 0x49,115 116 HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4A,117 HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE = 0x4B,118 119 HINIC_PORT_CMD_ENABLE_SPOOFCHK = 0x4E,120 121 HINIC_PORT_CMD_GET_MGMT_VERSION = 0x58,122 123 HINIC_PORT_CMD_GET_PORT_TYPE = 0x5B,124 125 HINIC_PORT_CMD_SET_FUNC_STATE = 0x5D,126 127 HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID = 0x5E,128 129 HINIC_PORT_CMD_GET_DMA_CS = 0x64,130 HINIC_PORT_CMD_SET_DMA_CS = 0x65,131 132 HINIC_PORT_CMD_GET_GLOBAL_QPN = 0x66,133 134 HINIC_PORT_CMD_SET_VF_RATE = 0x69,135 136 HINIC_PORT_CMD_SET_VF_VLAN = 0x6A,137 138 HINIC_PORT_CMD_CLR_VF_VLAN = 0x6B,139 140 HINIC_PORT_CMD_SET_TSO = 0x70,141 142 HINIC_PORT_CMD_UPDATE_FW = 0x72,143 144 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 0x73,145 146 HINIC_PORT_CMD_SET_PFC_THD = 0x75,147 148 HINIC_PORT_CMD_LINK_STATUS_REPORT = 0xA0,149 150 HINIC_PORT_CMD_SET_LOSSLESS_ETH = 0xA3,151 152 HINIC_PORT_CMD_UPDATE_MAC = 0xA4,153 154 HINIC_PORT_CMD_GET_CAP = 0xAA,155 156 HINIC_PORT_CMD_UP_TC_ADD_FLOW = 0xAF,157 HINIC_PORT_CMD_UP_TC_DEL_FLOW = 0xB0,158 HINIC_PORT_CMD_UP_TC_GET_FLOW = 0xB1,159 160 HINIC_PORT_CMD_UP_TC_FLUSH_TCAM = 0xB2,161 162 HINIC_PORT_CMD_UP_TC_CTRL_TCAM_BLOCK = 0xB3,163 164 HINIC_PORT_CMD_UP_TC_ENABLE = 0xB4,165 166 HINIC_PORT_CMD_UP_TC_GET_TCAM_BLOCK = 0xB5,167 168 HINIC_PORT_CMD_SET_IPSU_MAC = 0xCB,169 HINIC_PORT_CMD_GET_IPSU_MAC = 0xCC,170 171 HINIC_PORT_CMD_SET_XSFP_STATUS = 0xD4,172 173 HINIC_PORT_CMD_GET_LINK_MODE = 0xD9,174 175 HINIC_PORT_CMD_SET_SPEED = 0xDA,176 177 HINIC_PORT_CMD_SET_AUTONEG = 0xDB,178 179 HINIC_PORT_CMD_CLEAR_QP_RES = 0xDD,180 181 HINIC_PORT_CMD_SET_SUPER_CQE = 0xDE,182 183 HINIC_PORT_CMD_SET_VF_COS = 0xDF,184 HINIC_PORT_CMD_GET_VF_COS = 0xE1,185 186 HINIC_PORT_CMD_CABLE_PLUG_EVENT = 0xE5,187 188 HINIC_PORT_CMD_LINK_ERR_EVENT = 0xE6,189 190 HINIC_PORT_CMD_SET_COS_UP_MAP = 0xE8,191 192 HINIC_PORT_CMD_RESET_LINK_CFG = 0xEB,193 194 HINIC_PORT_CMD_GET_STD_SFP_INFO = 0xF0,195 196 HINIC_PORT_CMD_FORCE_PKT_DROP = 0xF3,197 198 HINIC_PORT_CMD_SET_LRO_TIMER = 0xF4,199 200 HINIC_PORT_CMD_SET_VHD_CFG = 0xF7,201 202 HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8,203 204 HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 0xF9,205 206 HINIC_PORT_CMD_GET_SFP_ABS = 0xFB,207 208 HINIC_PORT_CMD_Q_FILTER = 0xFC,209 210 HINIC_PORT_CMD_TCAM_FILTER = 0xFE,211 212 HINIC_PORT_CMD_SET_VLAN_FILTER = 0xFF,213};214 215/* cmd of mgmt CPU message for HILINK module */216enum hinic_hilink_cmd {217 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3,218 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8,219};220 221enum hinic_ucode_cmd {222 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0,223 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,224 HINIC_UCODE_CMD_ARM_SQ,225 HINIC_UCODE_CMD_ARM_RQ,226 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,227 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,228 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,229 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,230 HINIC_UCODE_CMD_SET_IQ_ENABLE,231 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10232};233 234#define NIC_RSS_CMD_TEMP_ALLOC 0x01235#define NIC_RSS_CMD_TEMP_FREE 0x02236 237enum hinic_mgmt_msg_cmd {238 HINIC_MGMT_MSG_CMD_BASE = 0xA0,239 240 HINIC_MGMT_MSG_CMD_LINK_STATUS = 0xA0,241 242 HINIC_MGMT_MSG_CMD_CABLE_PLUG_EVENT = 0xE5,243 HINIC_MGMT_MSG_CMD_LINK_ERR_EVENT = 0xE6,244 245 HINIC_MGMT_MSG_CMD_MAX,246};247 248enum hinic_cb_state {249 HINIC_CB_ENABLED = BIT(0),250 HINIC_CB_RUNNING = BIT(1),251};252 253enum hinic_res_state {254 HINIC_RES_CLEAN = 0,255 HINIC_RES_ACTIVE = 1,256};257 258struct hinic_cmd_fw_ctxt {259 u8 status;260 u8 version;261 u8 rsvd0[6];262 263 u16 func_idx;264 u16 rx_buf_sz;265 266 u32 rsvd1;267};268 269struct hinic_cmd_hw_ioctxt {270 u8 status;271 u8 version;272 u8 rsvd0[6];273 274 u16 func_idx;275 276 u16 rsvd1;277 278 u8 set_cmdq_depth;279 u8 cmdq_depth;280 281 u8 lro_en;282 u8 rsvd3;283 u8 ppf_idx;284 u8 rsvd4;285 286 u16 rq_depth;287 u16 rx_buf_sz_idx;288 u16 sq_depth;289};290 291struct hinic_cmd_io_status {292 u8 status;293 u8 version;294 u8 rsvd0[6];295 296 u16 func_idx;297 u8 rsvd1;298 u8 rsvd2;299 u32 io_status;300};301 302struct hinic_cmd_clear_io_res {303 u8 status;304 u8 version;305 u8 rsvd0[6];306 307 u16 func_idx;308 u8 rsvd1;309 u8 rsvd2;310};311 312struct hinic_cmd_set_res_state {313 u8 status;314 u8 version;315 u8 rsvd0[6];316 317 u16 func_idx;318 u8 state;319 u8 rsvd1;320 u32 rsvd2;321};322 323struct hinic_ceq_ctrl_reg {324 u8 status;325 u8 version;326 u8 rsvd0[6];327 328 u16 func_id;329 u16 q_id;330 u32 ctrl0;331 u32 ctrl1;332};333 334struct hinic_cmd_base_qpn {335 u8 status;336 u8 version;337 u8 rsvd0[6];338 339 u16 func_idx;340 u16 qpn;341};342 343struct hinic_cmd_hw_ci {344 u8 status;345 u8 version;346 u8 rsvd0[6];347 348 u16 func_idx;349 350 u8 dma_attr_off;351 u8 pending_limit;352 u8 coalesc_timer;353 354 u8 msix_en;355 u16 msix_entry_idx;356 357 u32 sq_id;358 u32 rsvd1;359 u64 ci_addr;360};361 362struct hinic_cmd_l2nic_reset {363 u8 status;364 u8 version;365 u8 rsvd0[6];366 367 u16 func_id;368 u16 reset_flag;369};370 371struct hinic_msix_config {372 u8 status;373 u8 version;374 u8 rsvd0[6];375 376 u16 func_id;377 u16 msix_index;378 u8 pending_cnt;379 u8 coalesce_timer_cnt;380 u8 lli_timer_cnt;381 u8 lli_credit_cnt;382 u8 resend_timer_cnt;383 u8 rsvd1[3];384};385 386struct hinic_set_random_id {387 u8 status;388 u8 version;389 u8 rsvd0[6];390 391 u8 vf_in_pf;392 u8 rsvd1;393 u16 func_idx;394 u32 random_id;395};396 397struct hinic_board_info {398 u32 board_type;399 u32 port_num;400 u32 port_speed;401 u32 pcie_width;402 u32 host_num;403 u32 pf_num;404 u32 vf_total_num;405 u32 tile_num;406 u32 qcm_num;407 u32 core_num;408 u32 work_mode;409 u32 service_mode;410 u32 pcie_mode;411 u32 cfg_addr;412 u32 boot_sel;413 u32 board_id;414};415 416struct hinic_comm_board_info {417 u8 status;418 u8 version;419 u8 rsvd0[6];420 421 struct hinic_board_info info;422 423 u32 rsvd1[4];424};425 426struct hinic_hwdev {427 struct hinic_hwif *hwif;428 struct msix_entry *msix_entries;429 430 struct hinic_aeqs aeqs;431 struct hinic_func_to_io func_to_io;432 struct hinic_mbox_func_to_func *func_to_func;433 434 struct hinic_cap nic_cap;435 u8 port_id;436 struct hinic_devlink_priv *devlink_dev;437};438 439struct hinic_nic_cb {440 void (*handler)(void *handle, void *buf_in,441 u16 in_size, void *buf_out,442 u16 *out_size);443 444 void *handle;445 unsigned long cb_state;446};447 448#define HINIC_COMM_SELF_CMD_MAX 4449 450typedef void (*comm_mgmt_self_msg_proc)(void *handle, void *buf_in, u16 in_size,451 void *buf_out, u16 *out_size);452 453struct comm_mgmt_self_msg_sub_info {454 u8 cmd;455 comm_mgmt_self_msg_proc proc;456};457 458struct comm_mgmt_self_msg_info {459 u8 cmd_num;460 struct comm_mgmt_self_msg_sub_info info[HINIC_COMM_SELF_CMD_MAX];461};462 463struct hinic_pfhwdev {464 struct hinic_hwdev hwdev;465 466 struct hinic_pf_to_mgmt pf_to_mgmt;467 468 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD];469 470 struct comm_mgmt_self_msg_info proc;471};472 473struct hinic_dev_cap {474 u8 status;475 u8 version;476 u8 rsvd0[6];477 478 u8 rsvd1[5];479 u8 intr_type;480 u8 max_cos_id;481 u8 er_id;482 u8 port_id;483 u8 max_vf;484 u8 rsvd2[62];485 u16 max_sqs;486 u16 max_rqs;487 u16 max_vf_sqs;488 u16 max_vf_rqs;489 u8 rsvd3[204];490};491 492union hinic_fault_hw_mgmt {493 u32 val[4];494 /* valid only type == FAULT_TYPE_CHIP */495 struct {496 u8 node_id;497 u8 err_level;498 u16 err_type;499 u32 err_csr_addr;500 u32 err_csr_value;501 /* func_id valid only if err_level == FAULT_LEVEL_SERIOUS_FLR */502 u16 func_id;503 u16 rsvd2;504 } chip;505 506 /* valid only if type == FAULT_TYPE_UCODE */507 struct {508 u8 cause_id;509 u8 core_id;510 u8 c_id;511 u8 rsvd3;512 u32 epc;513 u32 rsvd4;514 u32 rsvd5;515 } ucode;516 517 /* valid only if type == FAULT_TYPE_MEM_RD_TIMEOUT ||518 * FAULT_TYPE_MEM_WR_TIMEOUT519 */520 struct {521 u32 err_csr_ctrl;522 u32 err_csr_data;523 u32 ctrl_tab;524 u32 mem_index;525 } mem_timeout;526 527 /* valid only if type == FAULT_TYPE_REG_RD_TIMEOUT ||528 * FAULT_TYPE_REG_WR_TIMEOUT529 */530 struct {531 u32 err_csr;532 u32 rsvd6;533 u32 rsvd7;534 u32 rsvd8;535 } reg_timeout;536 537 struct {538 /* 0: read; 1: write */539 u8 op_type;540 u8 port_id;541 u8 dev_ad;542 u8 rsvd9;543 u32 csr_addr;544 u32 op_data;545 u32 rsvd10;546 } phy_fault;547};548 549struct hinic_fault_event {550 u8 type;551 u8 fault_level;552 u8 rsvd0[2];553 union hinic_fault_hw_mgmt event;554};555 556struct hinic_cmd_fault_event {557 u8 status;558 u8 version;559 u8 rsvd0[6];560 561 struct hinic_fault_event event;562};563 564enum hinic_fault_type {565 FAULT_TYPE_CHIP,566 FAULT_TYPE_UCODE,567 FAULT_TYPE_MEM_RD_TIMEOUT,568 FAULT_TYPE_MEM_WR_TIMEOUT,569 FAULT_TYPE_REG_RD_TIMEOUT,570 FAULT_TYPE_REG_WR_TIMEOUT,571 FAULT_TYPE_PHY_FAULT,572 FAULT_TYPE_MAX,573};574 575enum hinic_fault_err_level {576 FAULT_LEVEL_FATAL,577 FAULT_LEVEL_SERIOUS_RESET,578 FAULT_LEVEL_SERIOUS_FLR,579 FAULT_LEVEL_GENERAL,580 FAULT_LEVEL_SUGGESTION,581 FAULT_LEVEL_MAX582};583 584struct hinic_mgmt_watchdog_info {585 u8 status;586 u8 version;587 u8 rsvd0[6];588 589 u32 curr_time_h;590 u32 curr_time_l;591 u32 task_id;592 u32 rsv;593 594 u32 reg[13];595 u32 pc;596 u32 lr;597 u32 cpsr;598 599 u32 stack_top;600 u32 stack_bottom;601 u32 sp;602 u32 curr_used;603 u32 peak_used;604 u32 is_overflow;605 606 u32 stack_actlen;607 u8 data[1024];608};609 610void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,611 enum hinic_mgmt_msg_cmd cmd, void *handle,612 void (*handler)(void *handle, void *buf_in,613 u16 in_size, void *buf_out,614 u16 *out_size));615 616void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,617 enum hinic_mgmt_msg_cmd cmd);618 619int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,620 void *buf_in, u16 in_size, void *buf_out,621 u16 *out_size);622 623int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd,624 void *buf_in, u16 in_size, void *buf_out,625 u16 *out_size);626 627int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth);628 629void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);630 631struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev, struct devlink *devlink);632 633void hinic_free_hwdev(struct hinic_hwdev *hwdev);634 635int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);636 637struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);638 639struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);640 641int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);642 643int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,644 u8 pending_limit, u8 coalesc_timer,645 u8 lli_timer_cfg, u8 lli_credit_limit,646 u8 resend_timer);647 648int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,649 u8 pending_limit, u8 coalesc_timer);650 651void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,652 enum hinic_msix_state flag);653 654int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev,655 struct hinic_msix_config *interrupt_info);656 657int hinic_get_board_info(struct hinic_hwdev *hwdev,658 struct hinic_comm_board_info *board_info);659 660#endif661