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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Huawei HiNIC PCI Express Linux driver4 * Copyright(c) 2017 Huawei Technologies Co., Ltd5 */6 7#ifndef HINIC_HW_IF_H8#define HINIC_HW_IF_H9 10#include <linux/pci.h>11#include <linux/io.h>12#include <linux/types.h>13#include <asm/byteorder.h>14 15#define HINIC_PCIE_LINK_DOWN 0xFFFFFFFF16 17#define HINIC_DMA_ATTR_ST_SHIFT 018#define HINIC_DMA_ATTR_AT_SHIFT 819#define HINIC_DMA_ATTR_PH_SHIFT 1020#define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT 1221#define HINIC_DMA_ATTR_TPH_EN_SHIFT 1322 23#define HINIC_DMA_ATTR_ST_MASK 0xFF24#define HINIC_DMA_ATTR_AT_MASK 0x325#define HINIC_DMA_ATTR_PH_MASK 0x326#define HINIC_DMA_ATTR_NO_SNOOPING_MASK 0x127#define HINIC_DMA_ATTR_TPH_EN_MASK 0x128 29#define HINIC_DMA_ATTR_SET(val, member) \30 (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \31 HINIC_DMA_ATTR_##member##_SHIFT)32 33#define HINIC_DMA_ATTR_CLEAR(val, member) \34 ((val) & (~(HINIC_DMA_ATTR_##member##_MASK \35 << HINIC_DMA_ATTR_##member##_SHIFT)))36 37#define HINIC_FA0_FUNC_IDX_SHIFT 038#define HINIC_FA0_PF_IDX_SHIFT 1039#define HINIC_FA0_PCI_INTF_IDX_SHIFT 1440#define HINIC_FA0_VF_IN_PF_SHIFT 1641/* reserved members - off 16 */42#define HINIC_FA0_FUNC_TYPE_SHIFT 2443 44#define HINIC_FA0_FUNC_IDX_MASK 0x3FF45#define HINIC_FA0_PF_IDX_MASK 0xF46#define HINIC_FA0_PCI_INTF_IDX_MASK 0x347#define HINIC_FA0_FUNC_TYPE_MASK 0x148#define HINIC_FA0_VF_IN_PF_MASK 0xFF49 50#define HINIC_FA0_GET(val, member) \51 (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)52 53#define HINIC_FA1_AEQS_PER_FUNC_SHIFT 854/* reserved members - off 10 */55#define HINIC_FA1_CEQS_PER_FUNC_SHIFT 1256/* reserved members - off 15 */57#define HINIC_FA1_IRQS_PER_FUNC_SHIFT 2058#define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT 2459/* reserved members - off 27 */60#define HINIC_FA1_MGMT_INIT_STATUS_SHIFT 3061#define HINIC_FA1_PF_INIT_STATUS_SHIFT 3162 63#define HINIC_FA1_AEQS_PER_FUNC_MASK 0x364#define HINIC_FA1_CEQS_PER_FUNC_MASK 0x765#define HINIC_FA1_IRQS_PER_FUNC_MASK 0xF66#define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK 0x767#define HINIC_FA1_MGMT_INIT_STATUS_MASK 0x168#define HINIC_FA1_PF_INIT_STATUS_MASK 0x169 70#define HINIC_FA1_GET(val, member) \71 (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)72 73#define HINIC_FA2_GLOBAL_VF_ID_OF_PF_SHIFT 1674#define HINIC_FA2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF75 76#define HINIC_FA2_GET(val, member) \77 (((val) >> HINIC_FA2_##member##_SHIFT) & HINIC_FA2_##member##_MASK)78 79#define HINIC_FA4_OUTBOUND_STATE_SHIFT 080#define HINIC_FA4_DB_STATE_SHIFT 181 82#define HINIC_FA4_OUTBOUND_STATE_MASK 0x183#define HINIC_FA4_DB_STATE_MASK 0x184 85#define HINIC_FA4_GET(val, member) \86 (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK)87 88#define HINIC_FA4_SET(val, member) \89 ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT)90 91#define HINIC_FA4_CLEAR(val, member) \92 ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT)))93 94#define HINIC_FA5_PF_ACTION_SHIFT 095#define HINIC_FA5_PF_ACTION_MASK 0xFFFF96 97#define HINIC_FA5_SET(val, member) \98 (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)99 100#define HINIC_FA5_CLEAR(val, member) \101 ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))102 103#define HINIC_PPF_ELECTION_IDX_SHIFT 0104#define HINIC_PPF_ELECTION_IDX_MASK 0x1F105 106#define HINIC_PPF_ELECTION_SET(val, member) \107 (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \108 HINIC_PPF_ELECTION_##member##_SHIFT)109 110#define HINIC_PPF_ELECTION_GET(val, member) \111 (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \112 HINIC_PPF_ELECTION_##member##_MASK)113 114#define HINIC_PPF_ELECTION_CLEAR(val, member) \115 ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \116 << HINIC_PPF_ELECTION_##member##_SHIFT)))117 118#define HINIC_MSIX_PENDING_LIMIT_SHIFT 0119#define HINIC_MSIX_COALESC_TIMER_SHIFT 8120#define HINIC_MSIX_LLI_TIMER_SHIFT 16121#define HINIC_MSIX_LLI_CREDIT_SHIFT 24122#define HINIC_MSIX_RESEND_TIMER_SHIFT 29123 124#define HINIC_MSIX_PENDING_LIMIT_MASK 0xFF125#define HINIC_MSIX_COALESC_TIMER_MASK 0xFF126#define HINIC_MSIX_LLI_TIMER_MASK 0xFF127#define HINIC_MSIX_LLI_CREDIT_MASK 0x1F128#define HINIC_MSIX_RESEND_TIMER_MASK 0x7129 130#define HINIC_MSIX_ATTR_SET(val, member) \131 (((u32)(val) & HINIC_MSIX_##member##_MASK) << \132 HINIC_MSIX_##member##_SHIFT)133 134#define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29135 136#define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x1137 138#define HINIC_MSIX_CNT_SET(val, member) \139 (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \140 HINIC_MSIX_CNT_##member##_SHIFT)141 142#define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs)143#define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs)144#define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs)145#define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx)146#define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx)147#define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx)148#define HINIC_HWIF_PPF_IDX(hwif) ((hwif)->attr.ppf_idx)149 150#define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type)151#define HINIC_IS_VF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_VF)152#define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF)153#define HINIC_IS_PPF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)154 155#define HINIC_PCI_CFG_REGS_BAR 0156#define HINIC_PCI_INTR_REGS_BAR 2157#define HINIC_PCI_DB_BAR 4158 159#define HINIC_PCIE_ST_DISABLE 0160#define HINIC_PCIE_AT_DISABLE 0161#define HINIC_PCIE_PH_DISABLE 0162 163#define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT 0 /* Disabled */164#define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT 0xFF /* max */165#define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT 0 /* Disabled */166#define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT 0 /* Disabled */167#define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT 7 /* max */168 169#define HINIC_PCI_MSIX_ENTRY_SIZE 16170#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12171#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1172 173enum hinic_pcie_nosnoop {174 HINIC_PCIE_SNOOP = 0,175 HINIC_PCIE_NO_SNOOP = 1,176};177 178enum hinic_pcie_tph {179 HINIC_PCIE_TPH_DISABLE = 0,180 HINIC_PCIE_TPH_ENABLE = 1,181};182 183enum hinic_func_type {184 HINIC_PF = 0,185 HINIC_VF = 1,186 HINIC_PPF = 2,187};188 189enum hinic_mod_type {190 HINIC_MOD_COMM = 0, /* HW communication module */191 HINIC_MOD_L2NIC = 1, /* L2NIC module */192 HINIC_MOD_CFGM = 7, /* Configuration module */193 HINIC_MOD_HILINK = 14, /* Hilink module */194 HINIC_MOD_MAX = 15195};196 197enum hinic_node_id {198 HINIC_NODE_ID_MGMT = 21,199};200 201enum hinic_pf_action {202 HINIC_PF_MGMT_INIT = 0x0,203 204 HINIC_PF_MGMT_ACTIVE = 0x11,205};206 207enum hinic_outbound_state {208 HINIC_OUTBOUND_ENABLE = 0,209 HINIC_OUTBOUND_DISABLE = 1,210};211 212enum hinic_db_state {213 HINIC_DB_ENABLE = 0,214 HINIC_DB_DISABLE = 1,215};216 217enum hinic_msix_state {218 HINIC_MSIX_ENABLE,219 HINIC_MSIX_DISABLE,220};221 222struct hinic_func_attr {223 u16 func_idx;224 u8 pf_idx;225 u8 pci_intf_idx;226 227 enum hinic_func_type func_type;228 229 u8 ppf_idx;230 231 u16 num_irqs;232 u8 num_aeqs;233 u8 num_ceqs;234 235 u8 num_dma_attr;236 237 u16 global_vf_id_of_pf;238};239 240struct hinic_hwif {241 struct pci_dev *pdev;242 void __iomem *cfg_regs_bar;243 void __iomem *intr_regs_base;244 245 struct hinic_func_attr attr;246};247 248static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)249{250 u32 out = readl(hwif->cfg_regs_bar + reg);251 252 return be32_to_cpu(*(__be32 *)&out);253}254 255static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,256 u32 val)257{258 __be32 in = cpu_to_be32(val);259 260 writel(*(u32 *)&in, hwif->cfg_regs_bar + reg);261}262 263int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,264 u8 pending_limit, u8 coalesc_timer,265 u8 lli_timer_cfg, u8 lli_credit_limit,266 u8 resend_timer);267 268void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,269 enum hinic_msix_state flag);270 271int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);272 273void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);274 275enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif);276 277void hinic_outbound_state_set(struct hinic_hwif *hwif,278 enum hinic_outbound_state outbound_state);279 280enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif);281 282void hinic_db_state_set(struct hinic_hwif *hwif,283 enum hinic_db_state db_state);284 285u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif);286 287u16 hinic_global_func_id_hw(struct hinic_hwif *hwif);288 289u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif);290 291int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev);292 293void hinic_free_hwif(struct hinic_hwif *hwif);294 295#endif296