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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Huawei HiNIC PCI Express Linux driver4 * Copyright(c) 2017 Huawei Technologies Co., Ltd5 */6 7#ifndef HINIC_HW_QP_CTXT_H8#define HINIC_HW_QP_CTXT_H9 10#include <linux/types.h>11 12#include "hinic_hw_cmdq.h"13 14#define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT 1315#define HINIC_SQ_CTXT_CEQ_ATTR_EN_SHIFT 2316 17#define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FF18#define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK 0x119 20#define HINIC_SQ_CTXT_CEQ_ATTR_SET(val, member) \21 (((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \22 << HINIC_SQ_CTXT_CEQ_ATTR_##member##_SHIFT)23 24#define HINIC_SQ_CTXT_CI_IDX_SHIFT 1125#define HINIC_SQ_CTXT_CI_WRAPPED_SHIFT 2326 27#define HINIC_SQ_CTXT_CI_IDX_MASK 0xFFF28#define HINIC_SQ_CTXT_CI_WRAPPED_MASK 0x129 30#define HINIC_SQ_CTXT_CI_SET(val, member) \31 (((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \32 << HINIC_SQ_CTXT_CI_##member##_SHIFT)33 34#define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 035#define HINIC_SQ_CTXT_WQ_PAGE_PI_SHIFT 2036 37#define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF38#define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK 0xFFF39 40#define HINIC_SQ_CTXT_WQ_PAGE_SET(val, member) \41 (((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \42 << HINIC_SQ_CTXT_WQ_PAGE_##member##_SHIFT)43 44#define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 045#define HINIC_SQ_CTXT_PREF_CACHE_MAX_SHIFT 1446#define HINIC_SQ_CTXT_PREF_CACHE_MIN_SHIFT 2547 48#define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF49#define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF50#define HINIC_SQ_CTXT_PREF_CACHE_MIN_MASK 0x7F51 52#define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_SHIFT 053#define HINIC_SQ_CTXT_PREF_CI_SHIFT 2054 55#define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_MASK 0xFFFFF56#define HINIC_SQ_CTXT_PREF_CI_MASK 0xFFF57 58#define HINIC_SQ_CTXT_PREF_SET(val, member) \59 (((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \60 << HINIC_SQ_CTXT_PREF_##member##_SHIFT)61 62#define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT 063 64#define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_MASK 0x7FFFFF65 66#define HINIC_SQ_CTXT_WQ_BLOCK_SET(val, member) \67 (((u32)(val) & HINIC_SQ_CTXT_WQ_BLOCK_##member##_MASK) \68 << HINIC_SQ_CTXT_WQ_BLOCK_##member##_SHIFT)69 70#define HINIC_RQ_CTXT_CEQ_ATTR_EN_SHIFT 071#define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_SHIFT 172 73#define HINIC_RQ_CTXT_CEQ_ATTR_EN_MASK 0x174#define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_MASK 0x175 76#define HINIC_RQ_CTXT_CEQ_ATTR_SET(val, member) \77 (((u32)(val) & HINIC_RQ_CTXT_CEQ_ATTR_##member##_MASK) \78 << HINIC_RQ_CTXT_CEQ_ATTR_##member##_SHIFT)79 80#define HINIC_RQ_CTXT_PI_IDX_SHIFT 081#define HINIC_RQ_CTXT_PI_INTR_SHIFT 2282 83#define HINIC_RQ_CTXT_PI_IDX_MASK 0xFFF84#define HINIC_RQ_CTXT_PI_INTR_MASK 0x3FF85 86#define HINIC_RQ_CTXT_PI_SET(val, member) \87 (((u32)(val) & HINIC_RQ_CTXT_PI_##member##_MASK) << \88 HINIC_RQ_CTXT_PI_##member##_SHIFT)89 90#define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 091#define HINIC_RQ_CTXT_WQ_PAGE_CI_SHIFT 2092 93#define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF94#define HINIC_RQ_CTXT_WQ_PAGE_CI_MASK 0xFFF95 96#define HINIC_RQ_CTXT_WQ_PAGE_SET(val, member) \97 (((u32)(val) & HINIC_RQ_CTXT_WQ_PAGE_##member##_MASK) << \98 HINIC_RQ_CTXT_WQ_PAGE_##member##_SHIFT)99 100#define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0101#define HINIC_RQ_CTXT_PREF_CACHE_MAX_SHIFT 14102#define HINIC_RQ_CTXT_PREF_CACHE_MIN_SHIFT 25103 104#define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF105#define HINIC_RQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF106#define HINIC_RQ_CTXT_PREF_CACHE_MIN_MASK 0x7F107 108#define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_SHIFT 0109#define HINIC_RQ_CTXT_PREF_CI_SHIFT 20110 111#define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_MASK 0xFFFFF112#define HINIC_RQ_CTXT_PREF_CI_MASK 0xFFF113 114#define HINIC_RQ_CTXT_PREF_SET(val, member) \115 (((u32)(val) & HINIC_RQ_CTXT_PREF_##member##_MASK) << \116 HINIC_RQ_CTXT_PREF_##member##_SHIFT)117 118#define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT 0119 120#define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_MASK 0x7FFFFF121 122#define HINIC_RQ_CTXT_WQ_BLOCK_SET(val, member) \123 (((u32)(val) & HINIC_RQ_CTXT_WQ_BLOCK_##member##_MASK) << \124 HINIC_RQ_CTXT_WQ_BLOCK_##member##_SHIFT)125 126#define HINIC_SQ_CTXT_SIZE(num_sqs) (sizeof(struct hinic_qp_ctxt_header) \127 + (num_sqs) * sizeof(struct hinic_sq_ctxt))128 129#define HINIC_RQ_CTXT_SIZE(num_rqs) (sizeof(struct hinic_qp_ctxt_header) \130 + (num_rqs) * sizeof(struct hinic_rq_ctxt))131 132#define HINIC_WQ_PAGE_PFN_SHIFT 12133#define HINIC_WQ_BLOCK_PFN_SHIFT 9134 135#define HINIC_WQ_PAGE_PFN(page_addr) ((page_addr) >> HINIC_WQ_PAGE_PFN_SHIFT)136#define HINIC_WQ_BLOCK_PFN(page_addr) ((page_addr) >> \137 HINIC_WQ_BLOCK_PFN_SHIFT)138 139#define HINIC_Q_CTXT_MAX \140 ((HINIC_CMDQ_BUF_SIZE - sizeof(struct hinic_qp_ctxt_header)) \141 / sizeof(struct hinic_sq_ctxt))142 143enum hinic_qp_ctxt_type {144 HINIC_QP_CTXT_TYPE_SQ,145 HINIC_QP_CTXT_TYPE_RQ146};147 148struct hinic_qp_ctxt_header {149 u16 num_queues;150 u16 queue_type;151 u32 addr_offset;152};153 154struct hinic_sq_ctxt {155 u32 ceq_attr;156 157 u32 ci_wrapped;158 159 u32 wq_hi_pfn_pi;160 u32 wq_lo_pfn;161 162 u32 pref_cache;163 u32 pref_wrapped;164 u32 pref_wq_hi_pfn_ci;165 u32 pref_wq_lo_pfn;166 167 u32 rsvd0;168 u32 rsvd1;169 170 u32 wq_block_hi_pfn;171 u32 wq_block_lo_pfn;172};173 174struct hinic_rq_ctxt {175 u32 ceq_attr;176 177 u32 pi_intr_attr;178 179 u32 wq_hi_pfn_ci;180 u32 wq_lo_pfn;181 182 u32 pref_cache;183 u32 pref_wrapped;184 185 u32 pref_wq_hi_pfn_ci;186 u32 pref_wq_lo_pfn;187 188 u32 pi_paddr_hi;189 u32 pi_paddr_lo;190 191 u32 wq_block_hi_pfn;192 u32 wq_block_lo_pfn;193};194 195struct hinic_clean_queue_ctxt {196 struct hinic_qp_ctxt_header cmdq_hdr;197 u32 ctxt_size;198};199 200struct hinic_sq_ctxt_block {201 struct hinic_qp_ctxt_header hdr;202 struct hinic_sq_ctxt sq_ctxt[HINIC_Q_CTXT_MAX];203};204 205struct hinic_rq_ctxt_block {206 struct hinic_qp_ctxt_header hdr;207 struct hinic_rq_ctxt rq_ctxt[HINIC_Q_CTXT_MAX];208};209 210#endif211