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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * linux/drivers/net/ethernet/ibm/ehea/ehea_phyp.h4 *5 * eHEA ethernet device driver for IBM eServer System p6 *7 * (C) Copyright IBM Corp. 20068 *9 * Authors:10 * Christoph Raisch <raisch@de.ibm.com>11 * Jan-Bernd Themann <themann@de.ibm.com>12 * Thomas Klein <tklein@de.ibm.com>13 */14 15#ifndef __EHEA_PHYP_H__16#define __EHEA_PHYP_H__17 18#include <linux/delay.h>19#include <asm/hvcall.h>20#include "ehea.h"21#include "ehea_hw.h"22 23/* Some abbreviations used here:24 *25 * hcp_* - structures, variables and functions releated to Hypervisor Calls26 */27 28/* Number of pages which can be registered at once by H_REGISTER_HEA_RPAGES */29#define EHEA_MAX_RPAGE 51230 31/* Notification Event Queue (NEQ) Entry bit masks */32#define NEQE_EVENT_CODE EHEA_BMASK_IBM(2, 7)33#define NEQE_PORTNUM EHEA_BMASK_IBM(32, 47)34#define NEQE_PORT_UP EHEA_BMASK_IBM(16, 16)35#define NEQE_EXTSWITCH_PORT_UP EHEA_BMASK_IBM(17, 17)36#define NEQE_EXTSWITCH_PRIMARY EHEA_BMASK_IBM(18, 18)37#define NEQE_PLID EHEA_BMASK_IBM(16, 47)38 39/* Notification Event Codes */40#define EHEA_EC_PORTSTATE_CHG 0x3041#define EHEA_EC_ADAPTER_MALFUNC 0x3242#define EHEA_EC_PORT_MALFUNC 0x3343 44/* Notification Event Log Register (NELR) bit masks */45#define NELR_PORT_MALFUNC EHEA_BMASK_IBM(61, 61)46#define NELR_ADAPTER_MALFUNC EHEA_BMASK_IBM(62, 62)47#define NELR_PORTSTATE_CHG EHEA_BMASK_IBM(63, 63)48 49static inline void hcp_epas_ctor(struct h_epas *epas, u64 paddr_kernel,50 u64 paddr_user)51{52 /* To support 64k pages we must round to 64k page boundary */53 epas->kernel.addr = ioremap((paddr_kernel & PAGE_MASK), PAGE_SIZE) +54 (paddr_kernel & ~PAGE_MASK);55 epas->user.addr = paddr_user;56}57 58static inline void hcp_epas_dtor(struct h_epas *epas)59{60 if (epas->kernel.addr)61 iounmap((void __iomem *)((u64)epas->kernel.addr & PAGE_MASK));62 63 epas->user.addr = 0;64 epas->kernel.addr = 0;65}66 67struct hcp_modify_qp_cb0 {68 u64 qp_ctl_reg; /* 00 */69 u32 max_swqe; /* 02 */70 u32 max_rwqe; /* 03 */71 u32 port_nb; /* 04 */72 u32 reserved0; /* 05 */73 u64 qp_aer; /* 06 */74 u64 qp_tenure; /* 08 */75};76 77/* Hcall Query/Modify Queue Pair Control Block 0 Selection Mask Bits */78#define H_QPCB0_ALL EHEA_BMASK_IBM(0, 5)79#define H_QPCB0_QP_CTL_REG EHEA_BMASK_IBM(0, 0)80#define H_QPCB0_MAX_SWQE EHEA_BMASK_IBM(1, 1)81#define H_QPCB0_MAX_RWQE EHEA_BMASK_IBM(2, 2)82#define H_QPCB0_PORT_NB EHEA_BMASK_IBM(3, 3)83#define H_QPCB0_QP_AER EHEA_BMASK_IBM(4, 4)84#define H_QPCB0_QP_TENURE EHEA_BMASK_IBM(5, 5)85 86/* Queue Pair Control Register Status Bits */87#define H_QP_CR_ENABLED 0x8000000000000000ULL /* QP enabled */88 /* QP States: */89#define H_QP_CR_STATE_RESET 0x0000010000000000ULL /* Reset */90#define H_QP_CR_STATE_INITIALIZED 0x0000020000000000ULL /* Initialized */91#define H_QP_CR_STATE_RDY2RCV 0x0000030000000000ULL /* Ready to recv */92#define H_QP_CR_STATE_RDY2SND 0x0000050000000000ULL /* Ready to send */93#define H_QP_CR_STATE_ERROR 0x0000800000000000ULL /* Error */94#define H_QP_CR_RES_STATE 0x0000007F00000000ULL /* Resultant state */95 96struct hcp_modify_qp_cb1 {97 u32 qpn; /* 00 */98 u32 qp_asyn_ev_eq_nb; /* 01 */99 u64 sq_cq_handle; /* 02 */100 u64 rq_cq_handle; /* 04 */101 /* sgel = scatter gather element */102 u32 sgel_nb_sq; /* 06 */103 u32 sgel_nb_rq1; /* 07 */104 u32 sgel_nb_rq2; /* 08 */105 u32 sgel_nb_rq3; /* 09 */106};107 108/* Hcall Query/Modify Queue Pair Control Block 1 Selection Mask Bits */109#define H_QPCB1_ALL EHEA_BMASK_IBM(0, 7)110#define H_QPCB1_QPN EHEA_BMASK_IBM(0, 0)111#define H_QPCB1_ASYN_EV_EQ_NB EHEA_BMASK_IBM(1, 1)112#define H_QPCB1_SQ_CQ_HANDLE EHEA_BMASK_IBM(2, 2)113#define H_QPCB1_RQ_CQ_HANDLE EHEA_BMASK_IBM(3, 3)114#define H_QPCB1_SGEL_NB_SQ EHEA_BMASK_IBM(4, 4)115#define H_QPCB1_SGEL_NB_RQ1 EHEA_BMASK_IBM(5, 5)116#define H_QPCB1_SGEL_NB_RQ2 EHEA_BMASK_IBM(6, 6)117#define H_QPCB1_SGEL_NB_RQ3 EHEA_BMASK_IBM(7, 7)118 119struct hcp_query_ehea {120 u32 cur_num_qps; /* 00 */121 u32 cur_num_cqs; /* 01 */122 u32 cur_num_eqs; /* 02 */123 u32 cur_num_mrs; /* 03 */124 u32 auth_level; /* 04 */125 u32 max_num_qps; /* 05 */126 u32 max_num_cqs; /* 06 */127 u32 max_num_eqs; /* 07 */128 u32 max_num_mrs; /* 08 */129 u32 reserved0; /* 09 */130 u32 int_clock_freq; /* 10 */131 u32 max_num_pds; /* 11 */132 u32 max_num_addr_handles; /* 12 */133 u32 max_num_cqes; /* 13 */134 u32 max_num_wqes; /* 14 */135 u32 max_num_sgel_rq1wqe; /* 15 */136 u32 max_num_sgel_rq2wqe; /* 16 */137 u32 max_num_sgel_rq3wqe; /* 17 */138 u32 mr_page_size; /* 18 */139 u32 reserved1; /* 19 */140 u64 max_mr_size; /* 20 */141 u64 reserved2; /* 22 */142 u32 num_ports; /* 24 */143 u32 reserved3; /* 25 */144 u32 reserved4; /* 26 */145 u32 reserved5; /* 27 */146 u64 max_mc_mac; /* 28 */147 u64 ehea_cap; /* 30 */148 u32 max_isn_per_eq; /* 32 */149 u32 max_num_neq; /* 33 */150 u64 max_num_vlan_ids; /* 34 */151 u32 max_num_port_group; /* 36 */152 u32 max_num_phys_port; /* 37 */153 154};155 156/* Hcall Query/Modify Port Control Block defines */157#define H_PORT_CB0 0158#define H_PORT_CB1 1159#define H_PORT_CB2 2160#define H_PORT_CB3 3161#define H_PORT_CB4 4162#define H_PORT_CB5 5163#define H_PORT_CB6 6164#define H_PORT_CB7 7165 166struct hcp_ehea_port_cb0 {167 u64 port_mac_addr;168 u64 port_rc;169 u64 reserved0;170 u32 port_op_state;171 u32 port_speed;172 u32 ext_swport_op_state;173 u32 neg_tpf_prpf;174 u32 num_default_qps;175 u32 reserved1;176 u64 default_qpn_arr[16];177};178 179/* Hcall Query/Modify Port Control Block 0 Selection Mask Bits */180#define H_PORT_CB0_ALL EHEA_BMASK_IBM(0, 7) /* Set all bits */181#define H_PORT_CB0_MAC EHEA_BMASK_IBM(0, 0) /* MAC address */182#define H_PORT_CB0_PRC EHEA_BMASK_IBM(1, 1) /* Port Recv Control */183#define H_PORT_CB0_DEFQPNARRAY EHEA_BMASK_IBM(7, 7) /* Default QPN Array */184 185/* Hcall Query Port: Returned port speed values */186#define H_SPEED_10M_H 1 /* 10 Mbps, Half Duplex */187#define H_SPEED_10M_F 2 /* 10 Mbps, Full Duplex */188#define H_SPEED_100M_H 3 /* 100 Mbps, Half Duplex */189#define H_SPEED_100M_F 4 /* 100 Mbps, Full Duplex */190#define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */191#define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */192 193/* Port Receive Control Status Bits */194#define PXLY_RC_VALID EHEA_BMASK_IBM(49, 49)195#define PXLY_RC_VLAN_XTRACT EHEA_BMASK_IBM(50, 50)196#define PXLY_RC_TCP_6_TUPLE EHEA_BMASK_IBM(51, 51)197#define PXLY_RC_UDP_6_TUPLE EHEA_BMASK_IBM(52, 52)198#define PXLY_RC_TCP_3_TUPLE EHEA_BMASK_IBM(53, 53)199#define PXLY_RC_TCP_2_TUPLE EHEA_BMASK_IBM(54, 54)200#define PXLY_RC_LLC_SNAP EHEA_BMASK_IBM(55, 55)201#define PXLY_RC_JUMBO_FRAME EHEA_BMASK_IBM(56, 56)202#define PXLY_RC_FRAG_IP_PKT EHEA_BMASK_IBM(57, 57)203#define PXLY_RC_TCP_UDP_CHKSUM EHEA_BMASK_IBM(58, 58)204#define PXLY_RC_IP_CHKSUM EHEA_BMASK_IBM(59, 59)205#define PXLY_RC_MAC_FILTER EHEA_BMASK_IBM(60, 60)206#define PXLY_RC_UNTAG_FILTER EHEA_BMASK_IBM(61, 61)207#define PXLY_RC_VLAN_TAG_FILTER EHEA_BMASK_IBM(62, 63)208 209#define PXLY_RC_VLAN_FILTER 2210#define PXLY_RC_VLAN_PERM 0211 212 213#define H_PORT_CB1_ALL 0x8000000000000000ULL214 215struct hcp_ehea_port_cb1 {216 u64 vlan_filter[64];217};218 219#define H_PORT_CB2_ALL 0xFFE0000000000000ULL220 221struct hcp_ehea_port_cb2 {222 u64 rxo;223 u64 rxucp;224 u64 rxufd;225 u64 rxuerr;226 u64 rxftl;227 u64 rxmcp;228 u64 rxbcp;229 u64 txo;230 u64 txucp;231 u64 txmcp;232 u64 txbcp;233};234 235struct hcp_ehea_port_cb3 {236 u64 vlan_bc_filter[64];237 u64 vlan_mc_filter[64];238 u64 vlan_un_filter[64];239 u64 port_mac_hash_array[64];240};241 242#define H_PORT_CB4_ALL 0xF000000000000000ULL243#define H_PORT_CB4_JUMBO 0x1000000000000000ULL244#define H_PORT_CB4_SPEED 0x8000000000000000ULL245 246struct hcp_ehea_port_cb4 {247 u32 port_speed;248 u32 pause_frame;249 u32 ens_port_op_state;250 u32 jumbo_frame;251 u32 ens_port_wrap;252};253 254/* Hcall Query/Modify Port Control Block 5 Selection Mask Bits */255#define H_PORT_CB5_RCU 0x0001000000000000ULL256#define PXS_RCU EHEA_BMASK_IBM(61, 63)257 258struct hcp_ehea_port_cb5 {259 u64 prc; /* 00 */260 u64 uaa; /* 01 */261 u64 macvc; /* 02 */262 u64 xpcsc; /* 03 */263 u64 xpcsp; /* 04 */264 u64 pcsid; /* 05 */265 u64 xpcsst; /* 06 */266 u64 pthlb; /* 07 */267 u64 pthrb; /* 08 */268 u64 pqu; /* 09 */269 u64 pqd; /* 10 */270 u64 prt; /* 11 */271 u64 wsth; /* 12 */272 u64 rcb; /* 13 */273 u64 rcm; /* 14 */274 u64 rcu; /* 15 */275 u64 macc; /* 16 */276 u64 pc; /* 17 */277 u64 pst; /* 18 */278 u64 ducqpn; /* 19 */279 u64 mcqpn; /* 20 */280 u64 mma; /* 21 */281 u64 pmc0h; /* 22 */282 u64 pmc0l; /* 23 */283 u64 lbc; /* 24 */284};285 286#define H_PORT_CB6_ALL 0xFFFFFE7FFFFF8000ULL287 288struct hcp_ehea_port_cb6 {289 u64 rxo; /* 00 */290 u64 rx64; /* 01 */291 u64 rx65; /* 02 */292 u64 rx128; /* 03 */293 u64 rx256; /* 04 */294 u64 rx512; /* 05 */295 u64 rx1024; /* 06 */296 u64 rxbfcs; /* 07 */297 u64 rxime; /* 08 */298 u64 rxrle; /* 09 */299 u64 rxorle; /* 10 */300 u64 rxftl; /* 11 */301 u64 rxjab; /* 12 */302 u64 rxse; /* 13 */303 u64 rxce; /* 14 */304 u64 rxrf; /* 15 */305 u64 rxfrag; /* 16 */306 u64 rxuoc; /* 17 */307 u64 rxcpf; /* 18 */308 u64 rxsb; /* 19 */309 u64 rxfd; /* 20 */310 u64 rxoerr; /* 21 */311 u64 rxaln; /* 22 */312 u64 ducqpn; /* 23 */313 u64 reserved0; /* 24 */314 u64 rxmcp; /* 25 */315 u64 rxbcp; /* 26 */316 u64 txmcp; /* 27 */317 u64 txbcp; /* 28 */318 u64 txo; /* 29 */319 u64 tx64; /* 30 */320 u64 tx65; /* 31 */321 u64 tx128; /* 32 */322 u64 tx256; /* 33 */323 u64 tx512; /* 34 */324 u64 tx1024; /* 35 */325 u64 txbfcs; /* 36 */326 u64 txcpf; /* 37 */327 u64 txlf; /* 38 */328 u64 txrf; /* 39 */329 u64 txime; /* 40 */330 u64 txsc; /* 41 */331 u64 txmc; /* 42 */332 u64 txsqe; /* 43 */333 u64 txdef; /* 44 */334 u64 txlcol; /* 45 */335 u64 txexcol; /* 46 */336 u64 txcse; /* 47 */337 u64 txbor; /* 48 */338};339 340#define H_PORT_CB7_DUCQPN 0x8000000000000000ULL341 342struct hcp_ehea_port_cb7 {343 u64 def_uc_qpn;344};345 346u64 ehea_h_query_ehea_qp(const u64 adapter_handle,347 const u8 qp_category,348 const u64 qp_handle, const u64 sel_mask,349 void *cb_addr);350 351u64 ehea_h_modify_ehea_qp(const u64 adapter_handle,352 const u8 cat,353 const u64 qp_handle,354 const u64 sel_mask,355 void *cb_addr,356 u64 *inv_attr_id,357 u64 *proc_mask, u16 *out_swr, u16 *out_rwr);358 359u64 ehea_h_alloc_resource_eq(const u64 adapter_handle,360 struct ehea_eq_attr *eq_attr, u64 *eq_handle);361 362u64 ehea_h_alloc_resource_cq(const u64 adapter_handle,363 struct ehea_cq_attr *cq_attr,364 u64 *cq_handle, struct h_epas *epas);365 366u64 ehea_h_alloc_resource_qp(const u64 adapter_handle,367 struct ehea_qp_init_attr *init_attr,368 const u32 pd,369 u64 *qp_handle, struct h_epas *h_epas);370 371#define H_REG_RPAGE_PAGE_SIZE EHEA_BMASK_IBM(48, 55)372#define H_REG_RPAGE_QT EHEA_BMASK_IBM(62, 63)373 374u64 ehea_h_register_rpage(const u64 adapter_handle,375 const u8 pagesize,376 const u8 queue_type,377 const u64 resource_handle,378 const u64 log_pageaddr, u64 count);379 380#define H_DISABLE_GET_EHEA_WQE_P 1381#define H_DISABLE_GET_SQ_WQE_P 2382#define H_DISABLE_GET_RQC 3383 384u64 ehea_h_disable_and_get_hea(const u64 adapter_handle, const u64 qp_handle);385 386#define FORCE_FREE 1387#define NORMAL_FREE 0388 389u64 ehea_h_free_resource(const u64 adapter_handle, const u64 res_handle,390 u64 force_bit);391 392u64 ehea_h_alloc_resource_mr(const u64 adapter_handle, const u64 vaddr,393 const u64 length, const u32 access_ctrl,394 const u32 pd, u64 *mr_handle, u32 *lkey);395 396u64 ehea_h_register_rpage_mr(const u64 adapter_handle, const u64 mr_handle,397 const u8 pagesize, const u8 queue_type,398 const u64 log_pageaddr, const u64 count);399 400u64 ehea_h_register_smr(const u64 adapter_handle, const u64 orig_mr_handle,401 const u64 vaddr_in, const u32 access_ctrl, const u32 pd,402 struct ehea_mr *mr);403 404u64 ehea_h_query_ehea(const u64 adapter_handle, void *cb_addr);405 406/* output param R5 */407#define H_MEHEAPORT_CAT EHEA_BMASK_IBM(40, 47)408#define H_MEHEAPORT_PN EHEA_BMASK_IBM(48, 63)409 410u64 ehea_h_query_ehea_port(const u64 adapter_handle, const u16 port_num,411 const u8 cb_cat, const u64 select_mask,412 void *cb_addr);413 414u64 ehea_h_modify_ehea_port(const u64 adapter_handle, const u16 port_num,415 const u8 cb_cat, const u64 select_mask,416 void *cb_addr);417 418#define H_REGBCMC_PN EHEA_BMASK_IBM(48, 63)419#define H_REGBCMC_REGTYPE EHEA_BMASK_IBM(60, 63)420#define H_REGBCMC_MACADDR EHEA_BMASK_IBM(16, 63)421#define H_REGBCMC_VLANID EHEA_BMASK_IBM(52, 63)422 423u64 ehea_h_reg_dereg_bcmc(const u64 adapter_handle, const u16 port_num,424 const u8 reg_type, const u64 mc_mac_addr,425 const u16 vlan_id, const u32 hcall_id);426 427u64 ehea_h_reset_events(const u64 adapter_handle, const u64 neq_handle,428 const u64 event_mask);429 430u64 ehea_h_error_data(const u64 adapter_handle, const u64 ressource_handle,431 void *rblock);432 433#endif /* __EHEA_PHYP_H__ */434