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1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 1999 - 2006 Intel Corporation. */3 4/* e1000_hw.c5 * Shared functions for accessing and configuring the MAC6 */7 8#include <linux/bitfield.h>9#include "e1000.h"10 11static s32 e1000_check_downshift(struct e1000_hw *hw);12static s32 e1000_check_polarity(struct e1000_hw *hw,13 e1000_rev_polarity *polarity);14static void e1000_clear_hw_cntrs(struct e1000_hw *hw);15static void e1000_clear_vfta(struct e1000_hw *hw);16static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,17 bool link_up);18static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);19static s32 e1000_detect_gig_phy(struct e1000_hw *hw);20static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);21static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,22 u16 *max_length);23static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);24static s32 e1000_id_led_init(struct e1000_hw *hw);25static void e1000_init_rx_addrs(struct e1000_hw *hw);26static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,27 struct e1000_phy_info *phy_info);28static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,29 struct e1000_phy_info *phy_info);30static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);31static s32 e1000_wait_autoneg(struct e1000_hw *hw);32static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);33static s32 e1000_set_phy_type(struct e1000_hw *hw);34static void e1000_phy_init_script(struct e1000_hw *hw);35static s32 e1000_setup_copper_link(struct e1000_hw *hw);36static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);37static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);38static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);39static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);40static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);41static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);42static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);43static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);44static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);45static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,46 u16 words, u16 *data);47static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,48 u16 words, u16 *data);49static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);50static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);51static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);52static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);53static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,54 u16 phy_data);55static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,56 u16 *phy_data);57static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);58static s32 e1000_acquire_eeprom(struct e1000_hw *hw);59static void e1000_release_eeprom(struct e1000_hw *hw);60static void e1000_standby_eeprom(struct e1000_hw *hw);61static s32 e1000_set_vco_speed(struct e1000_hw *hw);62static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);63static s32 e1000_set_phy_mode(struct e1000_hw *hw);64static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,65 u16 *data);66static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,67 u16 *data);68 69/* IGP cable length table */70static const71u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {72 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,73 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,74 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,75 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,76 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,77 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,78 100,79 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,80 110, 110,81 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,82 120, 12083};84 85static DEFINE_MUTEX(e1000_eeprom_lock);86static DEFINE_SPINLOCK(e1000_phy_lock);87 88/**89 * e1000_set_phy_type - Set the phy type member in the hw struct.90 * @hw: Struct containing variables accessed by shared code91 */92static s32 e1000_set_phy_type(struct e1000_hw *hw)93{94 if (hw->mac_type == e1000_undefined)95 return -E1000_ERR_PHY_TYPE;96 97 switch (hw->phy_id) {98 case M88E1000_E_PHY_ID:99 case M88E1000_I_PHY_ID:100 case M88E1011_I_PHY_ID:101 case M88E1111_I_PHY_ID:102 case M88E1118_E_PHY_ID:103 hw->phy_type = e1000_phy_m88;104 break;105 case IGP01E1000_I_PHY_ID:106 if (hw->mac_type == e1000_82541 ||107 hw->mac_type == e1000_82541_rev_2 ||108 hw->mac_type == e1000_82547 ||109 hw->mac_type == e1000_82547_rev_2)110 hw->phy_type = e1000_phy_igp;111 break;112 case RTL8211B_PHY_ID:113 hw->phy_type = e1000_phy_8211;114 break;115 case RTL8201N_PHY_ID:116 hw->phy_type = e1000_phy_8201;117 break;118 default:119 /* Should never have loaded on this device */120 hw->phy_type = e1000_phy_undefined;121 return -E1000_ERR_PHY_TYPE;122 }123 124 return E1000_SUCCESS;125}126 127/**128 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY129 * @hw: Struct containing variables accessed by shared code130 */131static void e1000_phy_init_script(struct e1000_hw *hw)132{133 u16 phy_saved_data;134 135 if (hw->phy_init_script) {136 msleep(20);137 138 /* Save off the current value of register 0x2F5B to be restored139 * at the end of this routine.140 */141 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);142 143 /* Disabled the PHY transmitter */144 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);145 msleep(20);146 147 e1000_write_phy_reg(hw, 0x0000, 0x0140);148 msleep(5);149 150 switch (hw->mac_type) {151 case e1000_82541:152 case e1000_82547:153 e1000_write_phy_reg(hw, 0x1F95, 0x0001);154 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);155 e1000_write_phy_reg(hw, 0x1F79, 0x0018);156 e1000_write_phy_reg(hw, 0x1F30, 0x1600);157 e1000_write_phy_reg(hw, 0x1F31, 0x0014);158 e1000_write_phy_reg(hw, 0x1F32, 0x161C);159 e1000_write_phy_reg(hw, 0x1F94, 0x0003);160 e1000_write_phy_reg(hw, 0x1F96, 0x003F);161 e1000_write_phy_reg(hw, 0x2010, 0x0008);162 break;163 164 case e1000_82541_rev_2:165 case e1000_82547_rev_2:166 e1000_write_phy_reg(hw, 0x1F73, 0x0099);167 break;168 default:169 break;170 }171 172 e1000_write_phy_reg(hw, 0x0000, 0x3300);173 msleep(20);174 175 /* Now enable the transmitter */176 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);177 178 if (hw->mac_type == e1000_82547) {179 u16 fused, fine, coarse;180 181 /* Move to analog registers page */182 e1000_read_phy_reg(hw,183 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,184 &fused);185 186 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {187 e1000_read_phy_reg(hw,188 IGP01E1000_ANALOG_FUSE_STATUS,189 &fused);190 191 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;192 coarse =193 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;194 195 if (coarse >196 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {197 coarse -=198 IGP01E1000_ANALOG_FUSE_COARSE_10;199 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;200 } else if (coarse ==201 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)202 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;203 204 fused =205 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |206 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |207 (coarse &208 IGP01E1000_ANALOG_FUSE_COARSE_MASK);209 210 e1000_write_phy_reg(hw,211 IGP01E1000_ANALOG_FUSE_CONTROL,212 fused);213 e1000_write_phy_reg(hw,214 IGP01E1000_ANALOG_FUSE_BYPASS,215 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);216 }217 }218 }219}220 221/**222 * e1000_set_mac_type - Set the mac type member in the hw struct.223 * @hw: Struct containing variables accessed by shared code224 */225s32 e1000_set_mac_type(struct e1000_hw *hw)226{227 switch (hw->device_id) {228 case E1000_DEV_ID_82542:229 switch (hw->revision_id) {230 case E1000_82542_2_0_REV_ID:231 hw->mac_type = e1000_82542_rev2_0;232 break;233 case E1000_82542_2_1_REV_ID:234 hw->mac_type = e1000_82542_rev2_1;235 break;236 default:237 /* Invalid 82542 revision ID */238 return -E1000_ERR_MAC_TYPE;239 }240 break;241 case E1000_DEV_ID_82543GC_FIBER:242 case E1000_DEV_ID_82543GC_COPPER:243 hw->mac_type = e1000_82543;244 break;245 case E1000_DEV_ID_82544EI_COPPER:246 case E1000_DEV_ID_82544EI_FIBER:247 case E1000_DEV_ID_82544GC_COPPER:248 case E1000_DEV_ID_82544GC_LOM:249 hw->mac_type = e1000_82544;250 break;251 case E1000_DEV_ID_82540EM:252 case E1000_DEV_ID_82540EM_LOM:253 case E1000_DEV_ID_82540EP:254 case E1000_DEV_ID_82540EP_LOM:255 case E1000_DEV_ID_82540EP_LP:256 hw->mac_type = e1000_82540;257 break;258 case E1000_DEV_ID_82545EM_COPPER:259 case E1000_DEV_ID_82545EM_FIBER:260 hw->mac_type = e1000_82545;261 break;262 case E1000_DEV_ID_82545GM_COPPER:263 case E1000_DEV_ID_82545GM_FIBER:264 case E1000_DEV_ID_82545GM_SERDES:265 hw->mac_type = e1000_82545_rev_3;266 break;267 case E1000_DEV_ID_82546EB_COPPER:268 case E1000_DEV_ID_82546EB_FIBER:269 case E1000_DEV_ID_82546EB_QUAD_COPPER:270 hw->mac_type = e1000_82546;271 break;272 case E1000_DEV_ID_82546GB_COPPER:273 case E1000_DEV_ID_82546GB_FIBER:274 case E1000_DEV_ID_82546GB_SERDES:275 case E1000_DEV_ID_82546GB_PCIE:276 case E1000_DEV_ID_82546GB_QUAD_COPPER:277 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:278 hw->mac_type = e1000_82546_rev_3;279 break;280 case E1000_DEV_ID_82541EI:281 case E1000_DEV_ID_82541EI_MOBILE:282 case E1000_DEV_ID_82541ER_LOM:283 hw->mac_type = e1000_82541;284 break;285 case E1000_DEV_ID_82541ER:286 case E1000_DEV_ID_82541GI:287 case E1000_DEV_ID_82541GI_LF:288 case E1000_DEV_ID_82541GI_MOBILE:289 hw->mac_type = e1000_82541_rev_2;290 break;291 case E1000_DEV_ID_82547EI:292 case E1000_DEV_ID_82547EI_MOBILE:293 hw->mac_type = e1000_82547;294 break;295 case E1000_DEV_ID_82547GI:296 hw->mac_type = e1000_82547_rev_2;297 break;298 case E1000_DEV_ID_INTEL_CE4100_GBE:299 hw->mac_type = e1000_ce4100;300 break;301 default:302 /* Should never have loaded on this device */303 return -E1000_ERR_MAC_TYPE;304 }305 306 switch (hw->mac_type) {307 case e1000_82541:308 case e1000_82547:309 case e1000_82541_rev_2:310 case e1000_82547_rev_2:311 hw->asf_firmware_present = true;312 break;313 default:314 break;315 }316 317 /* The 82543 chip does not count tx_carrier_errors properly in318 * FD mode319 */320 if (hw->mac_type == e1000_82543)321 hw->bad_tx_carr_stats_fd = true;322 323 if (hw->mac_type > e1000_82544)324 hw->has_smbus = true;325 326 return E1000_SUCCESS;327}328 329/**330 * e1000_set_media_type - Set media type and TBI compatibility.331 * @hw: Struct containing variables accessed by shared code332 */333void e1000_set_media_type(struct e1000_hw *hw)334{335 u32 status;336 337 if (hw->mac_type != e1000_82543) {338 /* tbi_compatibility is only valid on 82543 */339 hw->tbi_compatibility_en = false;340 }341 342 switch (hw->device_id) {343 case E1000_DEV_ID_82545GM_SERDES:344 case E1000_DEV_ID_82546GB_SERDES:345 hw->media_type = e1000_media_type_internal_serdes;346 break;347 default:348 switch (hw->mac_type) {349 case e1000_82542_rev2_0:350 case e1000_82542_rev2_1:351 hw->media_type = e1000_media_type_fiber;352 break;353 case e1000_ce4100:354 hw->media_type = e1000_media_type_copper;355 break;356 default:357 status = er32(STATUS);358 if (status & E1000_STATUS_TBIMODE) {359 hw->media_type = e1000_media_type_fiber;360 /* tbi_compatibility not valid on fiber */361 hw->tbi_compatibility_en = false;362 } else {363 hw->media_type = e1000_media_type_copper;364 }365 break;366 }367 }368}369 370/**371 * e1000_reset_hw - reset the hardware completely372 * @hw: Struct containing variables accessed by shared code373 *374 * Reset the transmit and receive units; mask and clear all interrupts.375 */376s32 e1000_reset_hw(struct e1000_hw *hw)377{378 u32 ctrl;379 u32 ctrl_ext;380 u32 manc;381 u32 led_ctrl;382 s32 ret_val;383 384 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */385 if (hw->mac_type == e1000_82542_rev2_0) {386 e_dbg("Disabling MWI on 82542 rev 2.0\n");387 e1000_pci_clear_mwi(hw);388 }389 390 /* Clear interrupt mask to stop board from generating interrupts */391 e_dbg("Masking off all interrupts\n");392 ew32(IMC, 0xffffffff);393 394 /* Disable the Transmit and Receive units. Then delay to allow395 * any pending transactions to complete before we hit the MAC with396 * the global reset.397 */398 ew32(RCTL, 0);399 ew32(TCTL, E1000_TCTL_PSP);400 E1000_WRITE_FLUSH();401 402 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */403 hw->tbi_compatibility_on = false;404 405 /* Delay to allow any outstanding PCI transactions to complete before406 * resetting the device407 */408 msleep(10);409 410 ctrl = er32(CTRL);411 412 /* Must reset the PHY before resetting the MAC */413 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {414 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));415 E1000_WRITE_FLUSH();416 msleep(5);417 }418 419 /* Issue a global reset to the MAC. This will reset the chip's420 * transmit, receive, DMA, and link units. It will not effect421 * the current PCI configuration. The global reset bit is self-422 * clearing, and should clear within a microsecond.423 */424 e_dbg("Issuing a global reset to MAC\n");425 426 switch (hw->mac_type) {427 case e1000_82544:428 case e1000_82540:429 case e1000_82545:430 case e1000_82546:431 case e1000_82541:432 case e1000_82541_rev_2:433 /* These controllers can't ack the 64-bit write when issuing the434 * reset, so use IO-mapping as a workaround to issue the reset435 */436 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));437 break;438 case e1000_82545_rev_3:439 case e1000_82546_rev_3:440 /* Reset is performed on a shadow of the control register */441 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));442 break;443 case e1000_ce4100:444 default:445 ew32(CTRL, (ctrl | E1000_CTRL_RST));446 break;447 }448 449 /* After MAC reset, force reload of EEPROM to restore power-on settings450 * to device. Later controllers reload the EEPROM automatically, so451 * just wait for reload to complete.452 */453 switch (hw->mac_type) {454 case e1000_82542_rev2_0:455 case e1000_82542_rev2_1:456 case e1000_82543:457 case e1000_82544:458 /* Wait for reset to complete */459 udelay(10);460 ctrl_ext = er32(CTRL_EXT);461 ctrl_ext |= E1000_CTRL_EXT_EE_RST;462 ew32(CTRL_EXT, ctrl_ext);463 E1000_WRITE_FLUSH();464 /* Wait for EEPROM reload */465 msleep(2);466 break;467 case e1000_82541:468 case e1000_82541_rev_2:469 case e1000_82547:470 case e1000_82547_rev_2:471 /* Wait for EEPROM reload */472 msleep(20);473 break;474 default:475 /* Auto read done will delay 5ms or poll based on mac type */476 ret_val = e1000_get_auto_rd_done(hw);477 if (ret_val)478 return ret_val;479 break;480 }481 482 /* Disable HW ARPs on ASF enabled adapters */483 if (hw->mac_type >= e1000_82540) {484 manc = er32(MANC);485 manc &= ~(E1000_MANC_ARP_EN);486 ew32(MANC, manc);487 }488 489 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {490 e1000_phy_init_script(hw);491 492 /* Configure activity LED after PHY reset */493 led_ctrl = er32(LEDCTL);494 led_ctrl &= IGP_ACTIVITY_LED_MASK;495 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);496 ew32(LEDCTL, led_ctrl);497 }498 499 /* Clear interrupt mask to stop board from generating interrupts */500 e_dbg("Masking off all interrupts\n");501 ew32(IMC, 0xffffffff);502 503 /* Clear any pending interrupt events. */504 er32(ICR);505 506 /* If MWI was previously enabled, reenable it. */507 if (hw->mac_type == e1000_82542_rev2_0) {508 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)509 e1000_pci_set_mwi(hw);510 }511 512 return E1000_SUCCESS;513}514 515/**516 * e1000_init_hw - Performs basic configuration of the adapter.517 * @hw: Struct containing variables accessed by shared code518 *519 * Assumes that the controller has previously been reset and is in a520 * post-reset uninitialized state. Initializes the receive address registers,521 * multicast table, and VLAN filter table. Calls routines to setup link522 * configuration and flow control settings. Clears all on-chip counters. Leaves523 * the transmit and receive units disabled and uninitialized.524 */525s32 e1000_init_hw(struct e1000_hw *hw)526{527 u32 ctrl;528 u32 i;529 s32 ret_val;530 u32 mta_size;531 u32 ctrl_ext;532 533 /* Initialize Identification LED */534 ret_val = e1000_id_led_init(hw);535 if (ret_val) {536 e_dbg("Error Initializing Identification LED\n");537 return ret_val;538 }539 540 /* Set the media type and TBI compatibility */541 e1000_set_media_type(hw);542 543 /* Disabling VLAN filtering. */544 e_dbg("Initializing the IEEE VLAN\n");545 if (hw->mac_type < e1000_82545_rev_3)546 ew32(VET, 0);547 e1000_clear_vfta(hw);548 549 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */550 if (hw->mac_type == e1000_82542_rev2_0) {551 e_dbg("Disabling MWI on 82542 rev 2.0\n");552 e1000_pci_clear_mwi(hw);553 ew32(RCTL, E1000_RCTL_RST);554 E1000_WRITE_FLUSH();555 msleep(5);556 }557 558 /* Setup the receive address. This involves initializing all of the559 * Receive Address Registers (RARs 0 - 15).560 */561 e1000_init_rx_addrs(hw);562 563 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */564 if (hw->mac_type == e1000_82542_rev2_0) {565 ew32(RCTL, 0);566 E1000_WRITE_FLUSH();567 msleep(1);568 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)569 e1000_pci_set_mwi(hw);570 }571 572 /* Zero out the Multicast HASH table */573 e_dbg("Zeroing the MTA\n");574 mta_size = E1000_MC_TBL_SIZE;575 for (i = 0; i < mta_size; i++) {576 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);577 /* use write flush to prevent Memory Write Block (MWB) from578 * occurring when accessing our register space579 */580 E1000_WRITE_FLUSH();581 }582 583 /* Set the PCI priority bit correctly in the CTRL register. This584 * determines if the adapter gives priority to receives, or if it585 * gives equal priority to transmits and receives. Valid only on586 * 82542 and 82543 silicon.587 */588 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {589 ctrl = er32(CTRL);590 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);591 }592 593 switch (hw->mac_type) {594 case e1000_82545_rev_3:595 case e1000_82546_rev_3:596 break;597 default:598 /* Workaround for PCI-X problem when BIOS sets MMRBC599 * incorrectly.600 */601 if (hw->bus_type == e1000_bus_type_pcix &&602 e1000_pcix_get_mmrbc(hw) > 2048)603 e1000_pcix_set_mmrbc(hw, 2048);604 break;605 }606 607 /* Call a subroutine to configure the link and setup flow control. */608 ret_val = e1000_setup_link(hw);609 610 /* Set the transmit descriptor write-back policy */611 if (hw->mac_type > e1000_82544) {612 ctrl = er32(TXDCTL);613 ctrl =614 (ctrl & ~E1000_TXDCTL_WTHRESH) |615 E1000_TXDCTL_FULL_TX_DESC_WB;616 ew32(TXDCTL, ctrl);617 }618 619 /* Clear all of the statistics registers (clear on read). It is620 * important that we do this after we have tried to establish link621 * because the symbol error count will increment wildly if there622 * is no link.623 */624 e1000_clear_hw_cntrs(hw);625 626 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||627 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {628 ctrl_ext = er32(CTRL_EXT);629 /* Relaxed ordering must be disabled to avoid a parity630 * error crash in a PCI slot.631 */632 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;633 ew32(CTRL_EXT, ctrl_ext);634 }635 636 return ret_val;637}638 639/**640 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.641 * @hw: Struct containing variables accessed by shared code.642 */643static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)644{645 u16 eeprom_data;646 s32 ret_val;647 648 if (hw->media_type != e1000_media_type_internal_serdes)649 return E1000_SUCCESS;650 651 switch (hw->mac_type) {652 case e1000_82545_rev_3:653 case e1000_82546_rev_3:654 break;655 default:656 return E1000_SUCCESS;657 }658 659 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,660 &eeprom_data);661 if (ret_val)662 return ret_val;663 664 if (eeprom_data != EEPROM_RESERVED_WORD) {665 /* Adjust SERDES output amplitude only. */666 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;667 ret_val =668 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);669 if (ret_val)670 return ret_val;671 }672 673 return E1000_SUCCESS;674}675 676/**677 * e1000_setup_link - Configures flow control and link settings.678 * @hw: Struct containing variables accessed by shared code679 *680 * Determines which flow control settings to use. Calls the appropriate media-681 * specific link configuration function. Configures the flow control settings.682 * Assuming the adapter has a valid link partner, a valid link should be683 * established. Assumes the hardware has previously been reset and the684 * transmitter and receiver are not enabled.685 */686s32 e1000_setup_link(struct e1000_hw *hw)687{688 u32 ctrl_ext;689 s32 ret_val;690 u16 eeprom_data;691 692 /* Read and store word 0x0F of the EEPROM. This word contains bits693 * that determine the hardware's default PAUSE (flow control) mode,694 * a bit that determines whether the HW defaults to enabling or695 * disabling auto-negotiation, and the direction of the696 * SW defined pins. If there is no SW over-ride of the flow697 * control setting, then the variable hw->fc will698 * be initialized based on a value in the EEPROM.699 */700 if (hw->fc == E1000_FC_DEFAULT) {701 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,702 1, &eeprom_data);703 if (ret_val) {704 e_dbg("EEPROM Read Error\n");705 return -E1000_ERR_EEPROM;706 }707 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)708 hw->fc = E1000_FC_NONE;709 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==710 EEPROM_WORD0F_ASM_DIR)711 hw->fc = E1000_FC_TX_PAUSE;712 else713 hw->fc = E1000_FC_FULL;714 }715 716 /* We want to save off the original Flow Control configuration just717 * in case we get disconnected and then reconnected into a different718 * hub or switch with different Flow Control capabilities.719 */720 if (hw->mac_type == e1000_82542_rev2_0)721 hw->fc &= (~E1000_FC_TX_PAUSE);722 723 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))724 hw->fc &= (~E1000_FC_RX_PAUSE);725 726 hw->original_fc = hw->fc;727 728 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);729 730 /* Take the 4 bits from EEPROM word 0x0F that determine the initial731 * polarity value for the SW controlled pins, and setup the732 * Extended Device Control reg with that info.733 * This is needed because one of the SW controlled pins is used for734 * signal detection. So this should be done before e1000_setup_pcs_link()735 * or e1000_phy_setup() is called.736 */737 if (hw->mac_type == e1000_82543) {738 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,739 1, &eeprom_data);740 if (ret_val) {741 e_dbg("EEPROM Read Error\n");742 return -E1000_ERR_EEPROM;743 }744 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<745 SWDPIO__EXT_SHIFT);746 ew32(CTRL_EXT, ctrl_ext);747 }748 749 /* Call the necessary subroutine to configure the link. */750 ret_val = (hw->media_type == e1000_media_type_copper) ?751 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);752 753 /* Initialize the flow control address, type, and PAUSE timer754 * registers to their default values. This is done even if flow755 * control is disabled, because it does not hurt anything to756 * initialize these registers.757 */758 e_dbg("Initializing the Flow Control address, type and timer regs\n");759 760 ew32(FCT, FLOW_CONTROL_TYPE);761 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);762 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);763 764 ew32(FCTTV, hw->fc_pause_time);765 766 /* Set the flow control receive threshold registers. Normally,767 * these registers will be set to a default threshold that may be768 * adjusted later by the driver's runtime code. However, if the769 * ability to transmit pause frames in not enabled, then these770 * registers will be set to 0.771 */772 if (!(hw->fc & E1000_FC_TX_PAUSE)) {773 ew32(FCRTL, 0);774 ew32(FCRTH, 0);775 } else {776 /* We need to set up the Receive Threshold high and low water777 * marks as well as (optionally) enabling the transmission of778 * XON frames.779 */780 if (hw->fc_send_xon) {781 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));782 ew32(FCRTH, hw->fc_high_water);783 } else {784 ew32(FCRTL, hw->fc_low_water);785 ew32(FCRTH, hw->fc_high_water);786 }787 }788 return ret_val;789}790 791/**792 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link793 * @hw: Struct containing variables accessed by shared code794 *795 * Manipulates Physical Coding Sublayer functions in order to configure796 * link. Assumes the hardware has been previously reset and the transmitter797 * and receiver are not enabled.798 */799static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)800{801 u32 ctrl;802 u32 status;803 u32 txcw = 0;804 u32 i;805 u32 signal = 0;806 s32 ret_val;807 808 /* On adapters with a MAC newer than 82544, SWDP 1 will be809 * set when the optics detect a signal. On older adapters, it will be810 * cleared when there is a signal. This applies to fiber media only.811 * If we're on serdes media, adjust the output amplitude to value812 * set in the EEPROM.813 */814 ctrl = er32(CTRL);815 if (hw->media_type == e1000_media_type_fiber)816 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;817 818 ret_val = e1000_adjust_serdes_amplitude(hw);819 if (ret_val)820 return ret_val;821 822 /* Take the link out of reset */823 ctrl &= ~(E1000_CTRL_LRST);824 825 /* Adjust VCO speed to improve BER performance */826 ret_val = e1000_set_vco_speed(hw);827 if (ret_val)828 return ret_val;829 830 e1000_config_collision_dist(hw);831 832 /* Check for a software override of the flow control settings, and setup833 * the device accordingly. If auto-negotiation is enabled, then834 * software will have to set the "PAUSE" bits to the correct value in835 * the Tranmsit Config Word Register (TXCW) and re-start836 * auto-negotiation. However, if auto-negotiation is disabled, then837 * software will have to manually configure the two flow control enable838 * bits in the CTRL register.839 *840 * The possible values of the "fc" parameter are:841 * 0: Flow control is completely disabled842 * 1: Rx flow control is enabled (we can receive pause frames, but843 * not send pause frames).844 * 2: Tx flow control is enabled (we can send pause frames but we do845 * not support receiving pause frames).846 * 3: Both Rx and TX flow control (symmetric) are enabled.847 */848 switch (hw->fc) {849 case E1000_FC_NONE:850 /* Flow ctrl is completely disabled by a software over-ride */851 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);852 break;853 case E1000_FC_RX_PAUSE:854 /* Rx Flow control is enabled and Tx Flow control is disabled by855 * a software over-ride. Since there really isn't a way to856 * advertise that we are capable of Rx Pause ONLY, we will857 * advertise that we support both symmetric and asymmetric Rx858 * PAUSE. Later, we will disable the adapter's ability to send859 * PAUSE frames.860 */861 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);862 break;863 case E1000_FC_TX_PAUSE:864 /* Tx Flow control is enabled, and Rx Flow control is disabled,865 * by a software over-ride.866 */867 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);868 break;869 case E1000_FC_FULL:870 /* Flow control (both Rx and Tx) is enabled by a software871 * over-ride.872 */873 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);874 break;875 default:876 e_dbg("Flow control param set incorrectly\n");877 return -E1000_ERR_CONFIG;878 }879 880 /* Since auto-negotiation is enabled, take the link out of reset (the881 * link will be in reset, because we previously reset the chip). This882 * will restart auto-negotiation. If auto-negotiation is successful883 * then the link-up status bit will be set and the flow control enable884 * bits (RFCE and TFCE) will be set according to their negotiated value.885 */886 e_dbg("Auto-negotiation enabled\n");887 888 ew32(TXCW, txcw);889 ew32(CTRL, ctrl);890 E1000_WRITE_FLUSH();891 892 hw->txcw = txcw;893 msleep(1);894 895 /* If we have a signal (the cable is plugged in) then poll for a896 * "Link-Up" indication in the Device Status Register. Time-out if a897 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should898 * complete in less than 500 milliseconds even if the other end is doing899 * it in SW). For internal serdes, we just assume a signal is present,900 * then poll.901 */902 if (hw->media_type == e1000_media_type_internal_serdes ||903 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {904 e_dbg("Looking for Link\n");905 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {906 msleep(10);907 status = er32(STATUS);908 if (status & E1000_STATUS_LU)909 break;910 }911 if (i == (LINK_UP_TIMEOUT / 10)) {912 e_dbg("Never got a valid link from auto-neg!!!\n");913 hw->autoneg_failed = 1;914 /* AutoNeg failed to achieve a link, so we'll call915 * e1000_check_for_link. This routine will force the916 * link up if we detect a signal. This will allow us to917 * communicate with non-autonegotiating link partners.918 */919 ret_val = e1000_check_for_link(hw);920 if (ret_val) {921 e_dbg("Error while checking for link\n");922 return ret_val;923 }924 hw->autoneg_failed = 0;925 } else {926 hw->autoneg_failed = 0;927 e_dbg("Valid Link Found\n");928 }929 } else {930 e_dbg("No Signal Detected\n");931 }932 return E1000_SUCCESS;933}934 935/**936 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.937 * @hw: Struct containing variables accessed by shared code938 *939 * Commits changes to PHY configuration by calling e1000_phy_reset().940 */941static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)942{943 s32 ret_val;944 945 /* SW reset the PHY so all changes take effect */946 ret_val = e1000_phy_reset(hw);947 if (ret_val) {948 e_dbg("Error Resetting the PHY\n");949 return ret_val;950 }951 952 return E1000_SUCCESS;953}954 955static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)956{957 s32 ret_val;958 u32 ctrl_aux;959 960 switch (hw->phy_type) {961 case e1000_phy_8211:962 ret_val = e1000_copper_link_rtl_setup(hw);963 if (ret_val) {964 e_dbg("e1000_copper_link_rtl_setup failed!\n");965 return ret_val;966 }967 break;968 case e1000_phy_8201:969 /* Set RMII mode */970 ctrl_aux = er32(CTL_AUX);971 ctrl_aux |= E1000_CTL_AUX_RMII;972 ew32(CTL_AUX, ctrl_aux);973 E1000_WRITE_FLUSH();974 975 /* Disable the J/K bits required for receive */976 ctrl_aux = er32(CTL_AUX);977 ctrl_aux |= 0x4;978 ctrl_aux &= ~0x2;979 ew32(CTL_AUX, ctrl_aux);980 E1000_WRITE_FLUSH();981 ret_val = e1000_copper_link_rtl_setup(hw);982 983 if (ret_val) {984 e_dbg("e1000_copper_link_rtl_setup failed!\n");985 return ret_val;986 }987 break;988 default:989 e_dbg("Error Resetting the PHY\n");990 return E1000_ERR_PHY_TYPE;991 }992 993 return E1000_SUCCESS;994}995 996/**997 * e1000_copper_link_preconfig - early configuration for copper998 * @hw: Struct containing variables accessed by shared code999 *1000 * Make sure we have a valid PHY and change PHY mode before link setup.1001 */1002static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)1003{1004 u32 ctrl;1005 s32 ret_val;1006 u16 phy_data;1007 1008 ctrl = er32(CTRL);1009 /* With 82543, we need to force speed and duplex on the MAC equal to1010 * what the PHY speed and duplex configuration is. In addition, we need1011 * to perform a hardware reset on the PHY to take it out of reset.1012 */1013 if (hw->mac_type > e1000_82543) {1014 ctrl |= E1000_CTRL_SLU;1015 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);1016 ew32(CTRL, ctrl);1017 } else {1018 ctrl |=1019 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);1020 ew32(CTRL, ctrl);1021 ret_val = e1000_phy_hw_reset(hw);1022 if (ret_val)1023 return ret_val;1024 }1025 1026 /* Make sure we have a valid PHY */1027 ret_val = e1000_detect_gig_phy(hw);1028 if (ret_val) {1029 e_dbg("Error, did not detect valid phy.\n");1030 return ret_val;1031 }1032 e_dbg("Phy ID = %x\n", hw->phy_id);1033 1034 /* Set PHY to class A mode (if necessary) */1035 ret_val = e1000_set_phy_mode(hw);1036 if (ret_val)1037 return ret_val;1038 1039 if ((hw->mac_type == e1000_82545_rev_3) ||1040 (hw->mac_type == e1000_82546_rev_3)) {1041 ret_val =1042 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);1043 phy_data |= 0x00000008;1044 ret_val =1045 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);1046 }1047 1048 if (hw->mac_type <= e1000_82543 ||1049 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||1050 hw->mac_type == e1000_82541_rev_2 ||1051 hw->mac_type == e1000_82547_rev_2)1052 hw->phy_reset_disable = false;1053 1054 return E1000_SUCCESS;1055}1056 1057/**1058 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.1059 * @hw: Struct containing variables accessed by shared code1060 */1061static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)1062{1063 u32 led_ctrl;1064 s32 ret_val;1065 u16 phy_data;1066 1067 if (hw->phy_reset_disable)1068 return E1000_SUCCESS;1069 1070 ret_val = e1000_phy_reset(hw);1071 if (ret_val) {1072 e_dbg("Error Resetting the PHY\n");1073 return ret_val;1074 }1075 1076 /* Wait 15ms for MAC to configure PHY from eeprom settings */1077 msleep(15);1078 /* Configure activity LED after PHY reset */1079 led_ctrl = er32(LEDCTL);1080 led_ctrl &= IGP_ACTIVITY_LED_MASK;1081 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);1082 ew32(LEDCTL, led_ctrl);1083 1084 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */1085 if (hw->phy_type == e1000_phy_igp) {1086 /* disable lplu d3 during driver init */1087 ret_val = e1000_set_d3_lplu_state(hw, false);1088 if (ret_val) {1089 e_dbg("Error Disabling LPLU D3\n");1090 return ret_val;1091 }1092 }1093 1094 /* Configure mdi-mdix settings */1095 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);1096 if (ret_val)1097 return ret_val;1098 1099 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {1100 hw->dsp_config_state = e1000_dsp_config_disabled;1101 /* Force MDI for earlier revs of the IGP PHY */1102 phy_data &=1103 ~(IGP01E1000_PSCR_AUTO_MDIX |1104 IGP01E1000_PSCR_FORCE_MDI_MDIX);1105 hw->mdix = 1;1106 1107 } else {1108 hw->dsp_config_state = e1000_dsp_config_enabled;1109 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;1110 1111 switch (hw->mdix) {1112 case 1:1113 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;1114 break;1115 case 2:1116 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;1117 break;1118 case 0:1119 default:1120 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;1121 break;1122 }1123 }1124 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);1125 if (ret_val)1126 return ret_val;1127 1128 /* set auto-master slave resolution settings */1129 if (hw->autoneg) {1130 e1000_ms_type phy_ms_setting = hw->master_slave;1131 1132 if (hw->ffe_config_state == e1000_ffe_config_active)1133 hw->ffe_config_state = e1000_ffe_config_enabled;1134 1135 if (hw->dsp_config_state == e1000_dsp_config_activated)1136 hw->dsp_config_state = e1000_dsp_config_enabled;1137 1138 /* when autonegotiation advertisement is only 1000Mbps then we1139 * should disable SmartSpeed and enable Auto MasterSlave1140 * resolution as hardware default.1141 */1142 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {1143 /* Disable SmartSpeed */1144 ret_val =1145 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,1146 &phy_data);1147 if (ret_val)1148 return ret_val;1149 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;1150 ret_val =1151 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,1152 phy_data);1153 if (ret_val)1154 return ret_val;1155 /* Set auto Master/Slave resolution process */1156 ret_val =1157 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);1158 if (ret_val)1159 return ret_val;1160 phy_data &= ~CR_1000T_MS_ENABLE;1161 ret_val =1162 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);1163 if (ret_val)1164 return ret_val;1165 }1166 1167 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);1168 if (ret_val)1169 return ret_val;1170 1171 /* load defaults for future use */1172 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?1173 ((phy_data & CR_1000T_MS_VALUE) ?1174 e1000_ms_force_master :1175 e1000_ms_force_slave) : e1000_ms_auto;1176 1177 switch (phy_ms_setting) {1178 case e1000_ms_force_master:1179 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);1180 break;1181 case e1000_ms_force_slave:1182 phy_data |= CR_1000T_MS_ENABLE;1183 phy_data &= ~(CR_1000T_MS_VALUE);1184 break;1185 case e1000_ms_auto:1186 phy_data &= ~CR_1000T_MS_ENABLE;1187 break;1188 default:1189 break;1190 }1191 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);1192 if (ret_val)1193 return ret_val;1194 }1195 1196 return E1000_SUCCESS;1197}1198 1199/**1200 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.1201 * @hw: Struct containing variables accessed by shared code1202 */1203static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)1204{1205 s32 ret_val;1206 u16 phy_data;1207 1208 if (hw->phy_reset_disable)1209 return E1000_SUCCESS;1210 1211 /* Enable CRS on TX. This must be set for half-duplex operation. */1212 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);1213 if (ret_val)1214 return ret_val;1215 1216 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;1217 1218 /* Options:1219 * MDI/MDI-X = 0 (default)1220 * 0 - Auto for all speeds1221 * 1 - MDI mode1222 * 2 - MDI-X mode1223 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)1224 */1225 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;1226 1227 switch (hw->mdix) {1228 case 1:1229 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;1230 break;1231 case 2:1232 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;1233 break;1234 case 3:1235 phy_data |= M88E1000_PSCR_AUTO_X_1000T;1236 break;1237 case 0:1238 default:1239 phy_data |= M88E1000_PSCR_AUTO_X_MODE;1240 break;1241 }1242 1243 /* Options:1244 * disable_polarity_correction = 0 (default)1245 * Automatic Correction for Reversed Cable Polarity1246 * 0 - Disabled1247 * 1 - Enabled1248 */1249 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;1250 if (hw->disable_polarity_correction == 1)1251 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;1252 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);1253 if (ret_val)1254 return ret_val;1255 1256 if (hw->phy_revision < M88E1011_I_REV_4) {1257 /* Force TX_CLK in the Extended PHY Specific Control Register1258 * to 25MHz clock.1259 */1260 ret_val =1261 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,1262 &phy_data);1263 if (ret_val)1264 return ret_val;1265 1266 phy_data |= M88E1000_EPSCR_TX_CLK_25;1267 1268 if ((hw->phy_revision == E1000_REVISION_2) &&1269 (hw->phy_id == M88E1111_I_PHY_ID)) {1270 /* Vidalia Phy, set the downshift counter to 5x */1271 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);1272 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;1273 ret_val = e1000_write_phy_reg(hw,1274 M88E1000_EXT_PHY_SPEC_CTRL,1275 phy_data);1276 if (ret_val)1277 return ret_val;1278 } else {1279 /* Configure Master and Slave downshift values */1280 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |1281 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);1282 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |1283 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);1284 ret_val = e1000_write_phy_reg(hw,1285 M88E1000_EXT_PHY_SPEC_CTRL,1286 phy_data);1287 if (ret_val)1288 return ret_val;1289 }1290 }1291 1292 /* SW Reset the PHY so all changes take effect */1293 ret_val = e1000_phy_reset(hw);1294 if (ret_val) {1295 e_dbg("Error Resetting the PHY\n");1296 return ret_val;1297 }1298 1299 return E1000_SUCCESS;1300}1301 1302/**1303 * e1000_copper_link_autoneg - setup auto-neg1304 * @hw: Struct containing variables accessed by shared code1305 *1306 * Setup auto-negotiation and flow control advertisements,1307 * and then perform auto-negotiation.1308 */1309static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)1310{1311 s32 ret_val;1312 u16 phy_data;1313 1314 /* Perform some bounds checking on the hw->autoneg_advertised1315 * parameter. If this variable is zero, then set it to the default.1316 */1317 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;1318 1319 /* If autoneg_advertised is zero, we assume it was not defaulted1320 * by the calling code so we set to advertise full capability.1321 */1322 if (hw->autoneg_advertised == 0)1323 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;1324 1325 /* IFE/RTL8201N PHY only supports 10/100 */1326 if (hw->phy_type == e1000_phy_8201)1327 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;1328 1329 e_dbg("Reconfiguring auto-neg advertisement params\n");1330 ret_val = e1000_phy_setup_autoneg(hw);1331 if (ret_val) {1332 e_dbg("Error Setting up Auto-Negotiation\n");1333 return ret_val;1334 }1335 e_dbg("Restarting Auto-Neg\n");1336 1337 /* Restart auto-negotiation by setting the Auto Neg Enable bit and1338 * the Auto Neg Restart bit in the PHY control register.1339 */1340 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);1341 if (ret_val)1342 return ret_val;1343 1344 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);1345 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);1346 if (ret_val)1347 return ret_val;1348 1349 /* Does the user want to wait for Auto-Neg to complete here, or1350 * check at a later time (for example, callback routine).1351 */1352 if (hw->wait_autoneg_complete) {1353 ret_val = e1000_wait_autoneg(hw);1354 if (ret_val) {1355 e_dbg1356 ("Error while waiting for autoneg to complete\n");1357 return ret_val;1358 }1359 }1360 1361 hw->get_link_status = true;1362 1363 return E1000_SUCCESS;1364}1365 1366/**1367 * e1000_copper_link_postconfig - post link setup1368 * @hw: Struct containing variables accessed by shared code1369 *1370 * Config the MAC and the PHY after link is up.1371 * 1) Set up the MAC to the current PHY speed/duplex1372 * if we are on 82543. If we1373 * are on newer silicon, we only need to configure1374 * collision distance in the Transmit Control Register.1375 * 2) Set up flow control on the MAC to that established with1376 * the link partner.1377 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.1378 */1379static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)1380{1381 s32 ret_val;1382 1383 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {1384 e1000_config_collision_dist(hw);1385 } else {1386 ret_val = e1000_config_mac_to_phy(hw);1387 if (ret_val) {1388 e_dbg("Error configuring MAC to PHY settings\n");1389 return ret_val;1390 }1391 }1392 ret_val = e1000_config_fc_after_link_up(hw);1393 if (ret_val) {1394 e_dbg("Error Configuring Flow Control\n");1395 return ret_val;1396 }1397 1398 /* Config DSP to improve Giga link quality */1399 if (hw->phy_type == e1000_phy_igp) {1400 ret_val = e1000_config_dsp_after_link_change(hw, true);1401 if (ret_val) {1402 e_dbg("Error Configuring DSP after link up\n");1403 return ret_val;1404 }1405 }1406 1407 return E1000_SUCCESS;1408}1409 1410/**1411 * e1000_setup_copper_link - phy/speed/duplex setting1412 * @hw: Struct containing variables accessed by shared code1413 *1414 * Detects which PHY is present and sets up the speed and duplex1415 */1416static s32 e1000_setup_copper_link(struct e1000_hw *hw)1417{1418 s32 ret_val;1419 u16 i;1420 u16 phy_data;1421 1422 /* Check if it is a valid PHY and set PHY mode if necessary. */1423 ret_val = e1000_copper_link_preconfig(hw);1424 if (ret_val)1425 return ret_val;1426 1427 if (hw->phy_type == e1000_phy_igp) {1428 ret_val = e1000_copper_link_igp_setup(hw);1429 if (ret_val)1430 return ret_val;1431 } else if (hw->phy_type == e1000_phy_m88) {1432 ret_val = e1000_copper_link_mgp_setup(hw);1433 if (ret_val)1434 return ret_val;1435 } else {1436 ret_val = gbe_dhg_phy_setup(hw);1437 if (ret_val) {1438 e_dbg("gbe_dhg_phy_setup failed!\n");1439 return ret_val;1440 }1441 }1442 1443 if (hw->autoneg) {1444 /* Setup autoneg and flow control advertisement1445 * and perform autonegotiation1446 */1447 ret_val = e1000_copper_link_autoneg(hw);1448 if (ret_val)1449 return ret_val;1450 } else {1451 /* PHY will be set to 10H, 10F, 100H,or 100F1452 * depending on value from forced_speed_duplex.1453 */1454 e_dbg("Forcing speed and duplex\n");1455 ret_val = e1000_phy_force_speed_duplex(hw);1456 if (ret_val) {1457 e_dbg("Error Forcing Speed and Duplex\n");1458 return ret_val;1459 }1460 }1461 1462 /* Check link status. Wait up to 100 microseconds for link to become1463 * valid.1464 */1465 for (i = 0; i < 10; i++) {1466 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);1467 if (ret_val)1468 return ret_val;1469 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);1470 if (ret_val)1471 return ret_val;1472 1473 if (phy_data & MII_SR_LINK_STATUS) {1474 /* Config the MAC and PHY after link is up */1475 ret_val = e1000_copper_link_postconfig(hw);1476 if (ret_val)1477 return ret_val;1478 1479 e_dbg("Valid link established!!!\n");1480 return E1000_SUCCESS;1481 }1482 udelay(10);1483 }1484 1485 e_dbg("Unable to establish link!!!\n");1486 return E1000_SUCCESS;1487}1488 1489/**1490 * e1000_phy_setup_autoneg - phy settings1491 * @hw: Struct containing variables accessed by shared code1492 *1493 * Configures PHY autoneg and flow control advertisement settings1494 */1495s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)1496{1497 s32 ret_val;1498 u16 mii_autoneg_adv_reg;1499 u16 mii_1000t_ctrl_reg;1500 1501 /* Read the MII Auto-Neg Advertisement Register (Address 4). */1502 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);1503 if (ret_val)1504 return ret_val;1505 1506 /* Read the MII 1000Base-T Control Register (Address 9). */1507 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);1508 if (ret_val)1509 return ret_val;1510 else if (hw->phy_type == e1000_phy_8201)1511 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;1512 1513 /* Need to parse both autoneg_advertised and fc and set up1514 * the appropriate PHY registers. First we will parse for1515 * autoneg_advertised software override. Since we can advertise1516 * a plethora of combinations, we need to check each bit1517 * individually.1518 */1519 1520 /* First we clear all the 10/100 mb speed bits in the Auto-Neg1521 * Advertisement Register (Address 4) and the 1000 mb speed bits in1522 * the 1000Base-T Control Register (Address 9).1523 */1524 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;1525 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;1526 1527 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);1528 1529 /* Do we want to advertise 10 Mb Half Duplex? */1530 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {1531 e_dbg("Advertise 10mb Half duplex\n");1532 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;1533 }1534 1535 /* Do we want to advertise 10 Mb Full Duplex? */1536 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {1537 e_dbg("Advertise 10mb Full duplex\n");1538 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;1539 }1540 1541 /* Do we want to advertise 100 Mb Half Duplex? */1542 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {1543 e_dbg("Advertise 100mb Half duplex\n");1544 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;1545 }1546 1547 /* Do we want to advertise 100 Mb Full Duplex? */1548 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {1549 e_dbg("Advertise 100mb Full duplex\n");1550 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;1551 }1552 1553 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */1554 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {1555 e_dbg1556 ("Advertise 1000mb Half duplex requested, request denied!\n");1557 }1558 1559 /* Do we want to advertise 1000 Mb Full Duplex? */1560 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {1561 e_dbg("Advertise 1000mb Full duplex\n");1562 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;1563 }1564 1565 /* Check for a software override of the flow control settings, and1566 * setup the PHY advertisement registers accordingly. If1567 * auto-negotiation is enabled, then software will have to set the1568 * "PAUSE" bits to the correct value in the Auto-Negotiation1569 * Advertisement Register (PHY_AUTONEG_ADV) and re-start1570 * auto-negotiation.1571 *1572 * The possible values of the "fc" parameter are:1573 * 0: Flow control is completely disabled1574 * 1: Rx flow control is enabled (we can receive pause frames1575 * but not send pause frames).1576 * 2: Tx flow control is enabled (we can send pause frames1577 * but we do not support receiving pause frames).1578 * 3: Both Rx and TX flow control (symmetric) are enabled.1579 * other: No software override. The flow control configuration1580 * in the EEPROM is used.1581 */1582 switch (hw->fc) {1583 case E1000_FC_NONE: /* 0 */1584 /* Flow control (RX & TX) is completely disabled by a1585 * software over-ride.1586 */1587 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);1588 break;1589 case E1000_FC_RX_PAUSE: /* 1 */1590 /* RX Flow control is enabled, and TX Flow control is1591 * disabled, by a software over-ride.1592 */1593 /* Since there really isn't a way to advertise that we are1594 * capable of RX Pause ONLY, we will advertise that we1595 * support both symmetric and asymmetric RX PAUSE. Later1596 * (in e1000_config_fc_after_link_up) we will disable the1597 * hw's ability to send PAUSE frames.1598 */1599 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);1600 break;1601 case E1000_FC_TX_PAUSE: /* 2 */1602 /* TX Flow control is enabled, and RX Flow control is1603 * disabled, by a software over-ride.1604 */1605 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;1606 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;1607 break;1608 case E1000_FC_FULL: /* 3 */1609 /* Flow control (both RX and TX) is enabled by a software1610 * over-ride.1611 */1612 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);1613 break;1614 default:1615 e_dbg("Flow control param set incorrectly\n");1616 return -E1000_ERR_CONFIG;1617 }1618 1619 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);1620 if (ret_val)1621 return ret_val;1622 1623 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);1624 1625 if (hw->phy_type == e1000_phy_8201) {1626 mii_1000t_ctrl_reg = 0;1627 } else {1628 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,1629 mii_1000t_ctrl_reg);1630 if (ret_val)1631 return ret_val;1632 }1633 1634 return E1000_SUCCESS;1635}1636 1637/**1638 * e1000_phy_force_speed_duplex - force link settings1639 * @hw: Struct containing variables accessed by shared code1640 *1641 * Force PHY speed and duplex settings to hw->forced_speed_duplex1642 */1643static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)1644{1645 u32 ctrl;1646 s32 ret_val;1647 u16 mii_ctrl_reg;1648 u16 mii_status_reg;1649 u16 phy_data;1650 u16 i;1651 1652 /* Turn off Flow control if we are forcing speed and duplex. */1653 hw->fc = E1000_FC_NONE;1654 1655 e_dbg("hw->fc = %d\n", hw->fc);1656 1657 /* Read the Device Control Register. */1658 ctrl = er32(CTRL);1659 1660 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */1661 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);1662 ctrl &= ~(DEVICE_SPEED_MASK);1663 1664 /* Clear the Auto Speed Detect Enable bit. */1665 ctrl &= ~E1000_CTRL_ASDE;1666 1667 /* Read the MII Control Register. */1668 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);1669 if (ret_val)1670 return ret_val;1671 1672 /* We need to disable autoneg in order to force link and duplex. */1673 1674 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;1675 1676 /* Are we forcing Full or Half Duplex? */1677 if (hw->forced_speed_duplex == e1000_100_full ||1678 hw->forced_speed_duplex == e1000_10_full) {1679 /* We want to force full duplex so we SET the full duplex bits1680 * in the Device and MII Control Registers.1681 */1682 ctrl |= E1000_CTRL_FD;1683 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;1684 e_dbg("Full Duplex\n");1685 } else {1686 /* We want to force half duplex so we CLEAR the full duplex bits1687 * in the Device and MII Control Registers.1688 */1689 ctrl &= ~E1000_CTRL_FD;1690 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;1691 e_dbg("Half Duplex\n");1692 }1693 1694 /* Are we forcing 100Mbps??? */1695 if (hw->forced_speed_duplex == e1000_100_full ||1696 hw->forced_speed_duplex == e1000_100_half) {1697 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */1698 ctrl |= E1000_CTRL_SPD_100;1699 mii_ctrl_reg |= MII_CR_SPEED_100;1700 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);1701 e_dbg("Forcing 100mb ");1702 } else {1703 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */1704 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);1705 mii_ctrl_reg |= MII_CR_SPEED_10;1706 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);1707 e_dbg("Forcing 10mb ");1708 }1709 1710 e1000_config_collision_dist(hw);1711 1712 /* Write the configured values back to the Device Control Reg. */1713 ew32(CTRL, ctrl);1714 1715 if (hw->phy_type == e1000_phy_m88) {1716 ret_val =1717 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);1718 if (ret_val)1719 return ret_val;1720 1721 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires1722 * MDI forced whenever speed are duplex are forced.1723 */1724 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;1725 ret_val =1726 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);1727 if (ret_val)1728 return ret_val;1729 1730 e_dbg("M88E1000 PSCR: %x\n", phy_data);1731 1732 /* Need to reset the PHY or these changes will be ignored */1733 mii_ctrl_reg |= MII_CR_RESET;1734 1735 /* Disable MDI-X support for 10/100 */1736 } else {1737 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI1738 * forced whenever speed or duplex are forced.1739 */1740 ret_val =1741 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);1742 if (ret_val)1743 return ret_val;1744 1745 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;1746 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;1747 1748 ret_val =1749 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);1750 if (ret_val)1751 return ret_val;1752 }1753 1754 /* Write back the modified PHY MII control register. */1755 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);1756 if (ret_val)1757 return ret_val;1758 1759 udelay(1);1760 1761 /* The wait_autoneg_complete flag may be a little misleading here.1762 * Since we are forcing speed and duplex, Auto-Neg is not enabled.1763 * But we do want to delay for a period while forcing only so we1764 * don't generate false No Link messages. So we will wait here1765 * only if the user has set wait_autoneg_complete to 1, which is1766 * the default.1767 */1768 if (hw->wait_autoneg_complete) {1769 /* We will wait for autoneg to complete. */1770 e_dbg("Waiting for forced speed/duplex link.\n");1771 mii_status_reg = 0;1772 1773 /* Wait for autoneg to complete or 4.5 seconds to expire */1774 for (i = PHY_FORCE_TIME; i > 0; i--) {1775 /* Read the MII Status Register and wait for Auto-Neg1776 * Complete bit to be set.1777 */1778 ret_val =1779 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);1780 if (ret_val)1781 return ret_val;1782 1783 ret_val =1784 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);1785 if (ret_val)1786 return ret_val;1787 1788 if (mii_status_reg & MII_SR_LINK_STATUS)1789 break;1790 msleep(100);1791 }1792 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {1793 /* We didn't get link. Reset the DSP and wait again1794 * for link.1795 */1796 ret_val = e1000_phy_reset_dsp(hw);1797 if (ret_val) {1798 e_dbg("Error Resetting PHY DSP\n");1799 return ret_val;1800 }1801 }1802 /* This loop will early-out if the link condition has been1803 * met1804 */1805 for (i = PHY_FORCE_TIME; i > 0; i--) {1806 if (mii_status_reg & MII_SR_LINK_STATUS)1807 break;1808 msleep(100);1809 /* Read the MII Status Register and wait for Auto-Neg1810 * Complete bit to be set.1811 */1812 ret_val =1813 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);1814 if (ret_val)1815 return ret_val;1816 1817 ret_val =1818 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);1819 if (ret_val)1820 return ret_val;1821 }1822 }1823 1824 if (hw->phy_type == e1000_phy_m88) {1825 /* Because we reset the PHY above, we need to re-force TX_CLK in1826 * the Extended PHY Specific Control Register to 25MHz clock.1827 * This value defaults back to a 2.5MHz clock when the PHY is1828 * reset.1829 */1830 ret_val =1831 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,1832 &phy_data);1833 if (ret_val)1834 return ret_val;1835 1836 phy_data |= M88E1000_EPSCR_TX_CLK_25;1837 ret_val =1838 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,1839 phy_data);1840 if (ret_val)1841 return ret_val;1842 1843 /* In addition, because of the s/w reset above, we need to1844 * enable CRS on Tx. This must be set for both full and half1845 * duplex operation.1846 */1847 ret_val =1848 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);1849 if (ret_val)1850 return ret_val;1851 1852 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;1853 ret_val =1854 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);1855 if (ret_val)1856 return ret_val;1857 1858 if ((hw->mac_type == e1000_82544 ||1859 hw->mac_type == e1000_82543) &&1860 (!hw->autoneg) &&1861 (hw->forced_speed_duplex == e1000_10_full ||1862 hw->forced_speed_duplex == e1000_10_half)) {1863 ret_val = e1000_polarity_reversal_workaround(hw);1864 if (ret_val)1865 return ret_val;1866 }1867 }1868 return E1000_SUCCESS;1869}1870 1871/**1872 * e1000_config_collision_dist - set collision distance register1873 * @hw: Struct containing variables accessed by shared code1874 *1875 * Sets the collision distance in the Transmit Control register.1876 * Link should have been established previously. Reads the speed and duplex1877 * information from the Device Status register.1878 */1879void e1000_config_collision_dist(struct e1000_hw *hw)1880{1881 u32 tctl, coll_dist;1882 1883 if (hw->mac_type < e1000_82543)1884 coll_dist = E1000_COLLISION_DISTANCE_82542;1885 else1886 coll_dist = E1000_COLLISION_DISTANCE;1887 1888 tctl = er32(TCTL);1889 1890 tctl &= ~E1000_TCTL_COLD;1891 tctl |= coll_dist << E1000_COLD_SHIFT;1892 1893 ew32(TCTL, tctl);1894 E1000_WRITE_FLUSH();1895}1896 1897/**1898 * e1000_config_mac_to_phy - sync phy and mac settings1899 * @hw: Struct containing variables accessed by shared code1900 *1901 * Sets MAC speed and duplex settings to reflect the those in the PHY1902 * The contents of the PHY register containing the needed information need to1903 * be passed in.1904 */1905static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)1906{1907 u32 ctrl;1908 s32 ret_val;1909 u16 phy_data;1910 1911 /* 82544 or newer MAC, Auto Speed Detection takes care of1912 * MAC speed/duplex configuration.1913 */1914 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))1915 return E1000_SUCCESS;1916 1917 /* Read the Device Control Register and set the bits to Force Speed1918 * and Duplex.1919 */1920 ctrl = er32(CTRL);1921 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);1922 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);1923 1924 switch (hw->phy_type) {1925 case e1000_phy_8201:1926 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);1927 if (ret_val)1928 return ret_val;1929 1930 if (phy_data & RTL_PHY_CTRL_FD)1931 ctrl |= E1000_CTRL_FD;1932 else1933 ctrl &= ~E1000_CTRL_FD;1934 1935 if (phy_data & RTL_PHY_CTRL_SPD_100)1936 ctrl |= E1000_CTRL_SPD_100;1937 else1938 ctrl |= E1000_CTRL_SPD_10;1939 1940 e1000_config_collision_dist(hw);1941 break;1942 default:1943 /* Set up duplex in the Device Control and Transmit Control1944 * registers depending on negotiated values.1945 */1946 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,1947 &phy_data);1948 if (ret_val)1949 return ret_val;1950 1951 if (phy_data & M88E1000_PSSR_DPLX)1952 ctrl |= E1000_CTRL_FD;1953 else1954 ctrl &= ~E1000_CTRL_FD;1955 1956 e1000_config_collision_dist(hw);1957 1958 /* Set up speed in the Device Control register depending on1959 * negotiated values.1960 */1961 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)1962 ctrl |= E1000_CTRL_SPD_1000;1963 else if ((phy_data & M88E1000_PSSR_SPEED) ==1964 M88E1000_PSSR_100MBS)1965 ctrl |= E1000_CTRL_SPD_100;1966 }1967 1968 /* Write the configured values back to the Device Control Reg. */1969 ew32(CTRL, ctrl);1970 return E1000_SUCCESS;1971}1972 1973/**1974 * e1000_force_mac_fc - force flow control settings1975 * @hw: Struct containing variables accessed by shared code1976 *1977 * Forces the MAC's flow control settings.1978 * Sets the TFCE and RFCE bits in the device control register to reflect1979 * the adapter settings. TFCE and RFCE need to be explicitly set by1980 * software when a Copper PHY is used because autonegotiation is managed1981 * by the PHY rather than the MAC. Software must also configure these1982 * bits when link is forced on a fiber connection.1983 */1984s32 e1000_force_mac_fc(struct e1000_hw *hw)1985{1986 u32 ctrl;1987 1988 /* Get the current configuration of the Device Control Register */1989 ctrl = er32(CTRL);1990 1991 /* Because we didn't get link via the internal auto-negotiation1992 * mechanism (we either forced link or we got link via PHY1993 * auto-neg), we have to manually enable/disable transmit an1994 * receive flow control.1995 *1996 * The "Case" statement below enables/disable flow control1997 * according to the "hw->fc" parameter.1998 *1999 * The possible values of the "fc" parameter are:2000 * 0: Flow control is completely disabled2001 * 1: Rx flow control is enabled (we can receive pause2002 * frames but not send pause frames).2003 * 2: Tx flow control is enabled (we can send pause frames2004 * but we do not receive pause frames).2005 * 3: Both Rx and TX flow control (symmetric) is enabled.2006 * other: No other values should be possible at this point.2007 */2008 2009 switch (hw->fc) {2010 case E1000_FC_NONE:2011 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));2012 break;2013 case E1000_FC_RX_PAUSE:2014 ctrl &= (~E1000_CTRL_TFCE);2015 ctrl |= E1000_CTRL_RFCE;2016 break;2017 case E1000_FC_TX_PAUSE:2018 ctrl &= (~E1000_CTRL_RFCE);2019 ctrl |= E1000_CTRL_TFCE;2020 break;2021 case E1000_FC_FULL:2022 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);2023 break;2024 default:2025 e_dbg("Flow control param set incorrectly\n");2026 return -E1000_ERR_CONFIG;2027 }2028 2029 /* Disable TX Flow Control for 82542 (rev 2.0) */2030 if (hw->mac_type == e1000_82542_rev2_0)2031 ctrl &= (~E1000_CTRL_TFCE);2032 2033 ew32(CTRL, ctrl);2034 return E1000_SUCCESS;2035}2036 2037/**2038 * e1000_config_fc_after_link_up - configure flow control after autoneg2039 * @hw: Struct containing variables accessed by shared code2040 *2041 * Configures flow control settings after link is established2042 * Should be called immediately after a valid link has been established.2043 * Forces MAC flow control settings if link was forced. When in MII/GMII mode2044 * and autonegotiation is enabled, the MAC flow control settings will be set2045 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE2046 * and RFCE bits will be automatically set to the negotiated flow control mode.2047 */2048static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)2049{2050 s32 ret_val;2051 u16 mii_status_reg;2052 u16 mii_nway_adv_reg;2053 u16 mii_nway_lp_ability_reg;2054 u16 speed;2055 u16 duplex;2056 2057 /* Check for the case where we have fiber media and auto-neg failed2058 * so we had to force link. In this case, we need to force the2059 * configuration of the MAC to match the "fc" parameter.2060 */2061 if (((hw->media_type == e1000_media_type_fiber) &&2062 (hw->autoneg_failed)) ||2063 ((hw->media_type == e1000_media_type_internal_serdes) &&2064 (hw->autoneg_failed)) ||2065 ((hw->media_type == e1000_media_type_copper) &&2066 (!hw->autoneg))) {2067 ret_val = e1000_force_mac_fc(hw);2068 if (ret_val) {2069 e_dbg("Error forcing flow control settings\n");2070 return ret_val;2071 }2072 }2073 2074 /* Check for the case where we have copper media and auto-neg is2075 * enabled. In this case, we need to check and see if Auto-Neg2076 * has completed, and if so, how the PHY and link partner has2077 * flow control configured.2078 */2079 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {2080 /* Read the MII Status Register and check to see if AutoNeg2081 * has completed. We read this twice because this reg has2082 * some "sticky" (latched) bits.2083 */2084 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);2085 if (ret_val)2086 return ret_val;2087 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);2088 if (ret_val)2089 return ret_val;2090 2091 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {2092 /* The AutoNeg process has completed, so we now need to2093 * read both the Auto Negotiation Advertisement Register2094 * (Address 4) and the Auto_Negotiation Base Page2095 * Ability Register (Address 5) to determine how flow2096 * control was negotiated.2097 */2098 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,2099 &mii_nway_adv_reg);2100 if (ret_val)2101 return ret_val;2102 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,2103 &mii_nway_lp_ability_reg);2104 if (ret_val)2105 return ret_val;2106 2107 /* Two bits in the Auto Negotiation Advertisement2108 * Register (Address 4) and two bits in the Auto2109 * Negotiation Base Page Ability Register (Address 5)2110 * determine flow control for both the PHY and the link2111 * partner. The following table, taken out of the IEEE2112 * 802.3ab/D6.0 dated March 25, 1999, describes these2113 * PAUSE resolution bits and how flow control is2114 * determined based upon these settings.2115 * NOTE: DC = Don't Care2116 *2117 * LOCAL DEVICE | LINK PARTNER2118 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution2119 *-------|---------|-------|---------|------------------2120 * 0 | 0 | DC | DC | E1000_FC_NONE2121 * 0 | 1 | 0 | DC | E1000_FC_NONE2122 * 0 | 1 | 1 | 0 | E1000_FC_NONE2123 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE2124 * 1 | 0 | 0 | DC | E1000_FC_NONE2125 * 1 | DC | 1 | DC | E1000_FC_FULL2126 * 1 | 1 | 0 | 0 | E1000_FC_NONE2127 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE2128 *2129 */2130 /* Are both PAUSE bits set to 1? If so, this implies2131 * Symmetric Flow Control is enabled at both ends. The2132 * ASM_DIR bits are irrelevant per the spec.2133 *2134 * For Symmetric Flow Control:2135 *2136 * LOCAL DEVICE | LINK PARTNER2137 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result2138 *-------|---------|-------|---------|------------------2139 * 1 | DC | 1 | DC | E1000_FC_FULL2140 *2141 */2142 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&2143 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {2144 /* Now we need to check if the user selected Rx2145 * ONLY of pause frames. In this case, we had2146 * to advertise FULL flow control because we2147 * could not advertise Rx ONLY. Hence, we must2148 * now check to see if we need to turn OFF the2149 * TRANSMISSION of PAUSE frames.2150 */2151 if (hw->original_fc == E1000_FC_FULL) {2152 hw->fc = E1000_FC_FULL;2153 e_dbg("Flow Control = FULL.\n");2154 } else {2155 hw->fc = E1000_FC_RX_PAUSE;2156 e_dbg2157 ("Flow Control = RX PAUSE frames only.\n");2158 }2159 }2160 /* For receiving PAUSE frames ONLY.2161 *2162 * LOCAL DEVICE | LINK PARTNER2163 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result2164 *-------|---------|-------|---------|------------------2165 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE2166 *2167 */2168 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&2169 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&2170 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&2171 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {2172 hw->fc = E1000_FC_TX_PAUSE;2173 e_dbg2174 ("Flow Control = TX PAUSE frames only.\n");2175 }2176 /* For transmitting PAUSE frames ONLY.2177 *2178 * LOCAL DEVICE | LINK PARTNER2179 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result2180 *-------|---------|-------|---------|------------------2181 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE2182 *2183 */2184 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&2185 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&2186 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&2187 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {2188 hw->fc = E1000_FC_RX_PAUSE;2189 e_dbg2190 ("Flow Control = RX PAUSE frames only.\n");2191 }2192 /* Per the IEEE spec, at this point flow control should2193 * be disabled. However, we want to consider that we2194 * could be connected to a legacy switch that doesn't2195 * advertise desired flow control, but can be forced on2196 * the link partner. So if we advertised no flow2197 * control, that is what we will resolve to. If we2198 * advertised some kind of receive capability (Rx Pause2199 * Only or Full Flow Control) and the link partner2200 * advertised none, we will configure ourselves to2201 * enable Rx Flow Control only. We can do this safely2202 * for two reasons: If the link partner really2203 * didn't want flow control enabled, and we enable Rx,2204 * no harm done since we won't be receiving any PAUSE2205 * frames anyway. If the intent on the link partner was2206 * to have flow control enabled, then by us enabling Rx2207 * only, we can at least receive pause frames and2208 * process them. This is a good idea because in most2209 * cases, since we are predominantly a server NIC, more2210 * times than not we will be asked to delay transmission2211 * of packets than asking our link partner to pause2212 * transmission of frames.2213 */2214 else if ((hw->original_fc == E1000_FC_NONE ||2215 hw->original_fc == E1000_FC_TX_PAUSE) ||2216 hw->fc_strict_ieee) {2217 hw->fc = E1000_FC_NONE;2218 e_dbg("Flow Control = NONE.\n");2219 } else {2220 hw->fc = E1000_FC_RX_PAUSE;2221 e_dbg2222 ("Flow Control = RX PAUSE frames only.\n");2223 }2224 2225 /* Now we need to do one last check... If we auto-2226 * negotiated to HALF DUPLEX, flow control should not be2227 * enabled per IEEE 802.3 spec.2228 */2229 ret_val =2230 e1000_get_speed_and_duplex(hw, &speed, &duplex);2231 if (ret_val) {2232 e_dbg2233 ("Error getting link speed and duplex\n");2234 return ret_val;2235 }2236 2237 if (duplex == HALF_DUPLEX)2238 hw->fc = E1000_FC_NONE;2239 2240 /* Now we call a subroutine to actually force the MAC2241 * controller to use the correct flow control settings.2242 */2243 ret_val = e1000_force_mac_fc(hw);2244 if (ret_val) {2245 e_dbg2246 ("Error forcing flow control settings\n");2247 return ret_val;2248 }2249 } else {2250 e_dbg2251 ("Copper PHY and Auto Neg has not completed.\n");2252 }2253 }2254 return E1000_SUCCESS;2255}2256 2257/**2258 * e1000_check_for_serdes_link_generic - Check for link (Serdes)2259 * @hw: pointer to the HW structure2260 *2261 * Checks for link up on the hardware. If link is not up and we have2262 * a signal, then we need to force link up.2263 */2264static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)2265{2266 u32 rxcw;2267 u32 ctrl;2268 u32 status;2269 s32 ret_val = E1000_SUCCESS;2270 2271 ctrl = er32(CTRL);2272 status = er32(STATUS);2273 rxcw = er32(RXCW);2274 2275 /* If we don't have link (auto-negotiation failed or link partner2276 * cannot auto-negotiate), and our link partner is not trying to2277 * auto-negotiate with us (we are receiving idles or data),2278 * we need to force link up. We also need to give auto-negotiation2279 * time to complete.2280 */2281 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */2282 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {2283 if (hw->autoneg_failed == 0) {2284 hw->autoneg_failed = 1;2285 goto out;2286 }2287 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");2288 2289 /* Disable auto-negotiation in the TXCW register */2290 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));2291 2292 /* Force link-up and also force full-duplex. */2293 ctrl = er32(CTRL);2294 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);2295 ew32(CTRL, ctrl);2296 2297 /* Configure Flow Control after forcing link up. */2298 ret_val = e1000_config_fc_after_link_up(hw);2299 if (ret_val) {2300 e_dbg("Error configuring flow control\n");2301 goto out;2302 }2303 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {2304 /* If we are forcing link and we are receiving /C/ ordered2305 * sets, re-enable auto-negotiation in the TXCW register2306 * and disable forced link in the Device Control register2307 * in an attempt to auto-negotiate with our link partner.2308 */2309 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");2310 ew32(TXCW, hw->txcw);2311 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));2312 2313 hw->serdes_has_link = true;2314 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {2315 /* If we force link for non-auto-negotiation switch, check2316 * link status based on MAC synchronization for internal2317 * serdes media type.2318 */2319 /* SYNCH bit and IV bit are sticky. */2320 udelay(10);2321 rxcw = er32(RXCW);2322 if (rxcw & E1000_RXCW_SYNCH) {2323 if (!(rxcw & E1000_RXCW_IV)) {2324 hw->serdes_has_link = true;2325 e_dbg("SERDES: Link up - forced.\n");2326 }2327 } else {2328 hw->serdes_has_link = false;2329 e_dbg("SERDES: Link down - force failed.\n");2330 }2331 }2332 2333 if (E1000_TXCW_ANE & er32(TXCW)) {2334 status = er32(STATUS);2335 if (status & E1000_STATUS_LU) {2336 /* SYNCH bit and IV bit are sticky, so reread rxcw. */2337 udelay(10);2338 rxcw = er32(RXCW);2339 if (rxcw & E1000_RXCW_SYNCH) {2340 if (!(rxcw & E1000_RXCW_IV)) {2341 hw->serdes_has_link = true;2342 e_dbg("SERDES: Link up - autoneg "2343 "completed successfully.\n");2344 } else {2345 hw->serdes_has_link = false;2346 e_dbg("SERDES: Link down - invalid"2347 "codewords detected in autoneg.\n");2348 }2349 } else {2350 hw->serdes_has_link = false;2351 e_dbg("SERDES: Link down - no sync.\n");2352 }2353 } else {2354 hw->serdes_has_link = false;2355 e_dbg("SERDES: Link down - autoneg failed\n");2356 }2357 }2358 2359 out:2360 return ret_val;2361}2362 2363/**2364 * e1000_check_for_link2365 * @hw: Struct containing variables accessed by shared code2366 *2367 * Checks to see if the link status of the hardware has changed.2368 * Called by any function that needs to check the link status of the adapter.2369 */2370s32 e1000_check_for_link(struct e1000_hw *hw)2371{2372 u32 status;2373 u32 rctl;2374 u32 icr;2375 s32 ret_val;2376 u16 phy_data;2377 2378 er32(CTRL);2379 status = er32(STATUS);2380 2381 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be2382 * set when the optics detect a signal. On older adapters, it will be2383 * cleared when there is a signal. This applies to fiber media only.2384 */2385 if ((hw->media_type == e1000_media_type_fiber) ||2386 (hw->media_type == e1000_media_type_internal_serdes)) {2387 er32(RXCW);2388 2389 if (hw->media_type == e1000_media_type_fiber) {2390 if (status & E1000_STATUS_LU)2391 hw->get_link_status = false;2392 }2393 }2394 2395 /* If we have a copper PHY then we only want to go out to the PHY2396 * registers to see if Auto-Neg has completed and/or if our link2397 * status has changed. The get_link_status flag will be set if we2398 * receive a Link Status Change interrupt or we have Rx Sequence2399 * Errors.2400 */2401 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {2402 /* First we want to see if the MII Status Register reports2403 * link. If so, then we want to get the current speed/duplex2404 * of the PHY.2405 * Read the register twice since the link bit is sticky.2406 */2407 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);2408 if (ret_val)2409 return ret_val;2410 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);2411 if (ret_val)2412 return ret_val;2413 2414 if (phy_data & MII_SR_LINK_STATUS) {2415 hw->get_link_status = false;2416 /* Check if there was DownShift, must be checked2417 * immediately after link-up2418 */2419 e1000_check_downshift(hw);2420 2421 /* If we are on 82544 or 82543 silicon and speed/duplex2422 * are forced to 10H or 10F, then we will implement the2423 * polarity reversal workaround. We disable interrupts2424 * first, and upon returning, place the devices2425 * interrupt state to its previous value except for the2426 * link status change interrupt which will2427 * happen due to the execution of this workaround.2428 */2429 2430 if ((hw->mac_type == e1000_82544 ||2431 hw->mac_type == e1000_82543) &&2432 (!hw->autoneg) &&2433 (hw->forced_speed_duplex == e1000_10_full ||2434 hw->forced_speed_duplex == e1000_10_half)) {2435 ew32(IMC, 0xffffffff);2436 ret_val =2437 e1000_polarity_reversal_workaround(hw);2438 icr = er32(ICR);2439 ew32(ICS, (icr & ~E1000_ICS_LSC));2440 ew32(IMS, IMS_ENABLE_MASK);2441 }2442 2443 } else {2444 /* No link detected */2445 e1000_config_dsp_after_link_change(hw, false);2446 return 0;2447 }2448 2449 /* If we are forcing speed/duplex, then we simply return since2450 * we have already determined whether we have link or not.2451 */2452 if (!hw->autoneg)2453 return -E1000_ERR_CONFIG;2454 2455 /* optimize the dsp settings for the igp phy */2456 e1000_config_dsp_after_link_change(hw, true);2457 2458 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we2459 * have Si on board that is 82544 or newer, Auto2460 * Speed Detection takes care of MAC speed/duplex2461 * configuration. So we only need to configure Collision2462 * Distance in the MAC. Otherwise, we need to force2463 * speed/duplex on the MAC to the current PHY speed/duplex2464 * settings.2465 */2466 if ((hw->mac_type >= e1000_82544) &&2467 (hw->mac_type != e1000_ce4100))2468 e1000_config_collision_dist(hw);2469 else {2470 ret_val = e1000_config_mac_to_phy(hw);2471 if (ret_val) {2472 e_dbg2473 ("Error configuring MAC to PHY settings\n");2474 return ret_val;2475 }2476 }2477 2478 /* Configure Flow Control now that Auto-Neg has completed.2479 * First, we need to restore the desired flow control settings2480 * because we may have had to re-autoneg with a different link2481 * partner.2482 */2483 ret_val = e1000_config_fc_after_link_up(hw);2484 if (ret_val) {2485 e_dbg("Error configuring flow control\n");2486 return ret_val;2487 }2488 2489 /* At this point we know that we are on copper and we have2490 * auto-negotiated link. These are conditions for checking the2491 * link partner capability register. We use the link speed to2492 * determine if TBI compatibility needs to be turned on or off.2493 * If the link is not at gigabit speed, then TBI compatibility2494 * is not needed. If we are at gigabit speed, we turn on TBI2495 * compatibility.2496 */2497 if (hw->tbi_compatibility_en) {2498 u16 speed, duplex;2499 2500 ret_val =2501 e1000_get_speed_and_duplex(hw, &speed, &duplex);2502 2503 if (ret_val) {2504 e_dbg2505 ("Error getting link speed and duplex\n");2506 return ret_val;2507 }2508 if (speed != SPEED_1000) {2509 /* If link speed is not set to gigabit speed, we2510 * do not need to enable TBI compatibility.2511 */2512 if (hw->tbi_compatibility_on) {2513 /* If we previously were in the mode,2514 * turn it off.2515 */2516 rctl = er32(RCTL);2517 rctl &= ~E1000_RCTL_SBP;2518 ew32(RCTL, rctl);2519 hw->tbi_compatibility_on = false;2520 }2521 } else {2522 /* If TBI compatibility is was previously off,2523 * turn it on. For compatibility with a TBI link2524 * partner, we will store bad packets. Some2525 * frames have an additional byte on the end and2526 * will look like CRC errors to the hardware.2527 */2528 if (!hw->tbi_compatibility_on) {2529 hw->tbi_compatibility_on = true;2530 rctl = er32(RCTL);2531 rctl |= E1000_RCTL_SBP;2532 ew32(RCTL, rctl);2533 }2534 }2535 }2536 }2537 2538 if ((hw->media_type == e1000_media_type_fiber) ||2539 (hw->media_type == e1000_media_type_internal_serdes))2540 e1000_check_for_serdes_link_generic(hw);2541 2542 return E1000_SUCCESS;2543}2544 2545/**2546 * e1000_get_speed_and_duplex2547 * @hw: Struct containing variables accessed by shared code2548 * @speed: Speed of the connection2549 * @duplex: Duplex setting of the connection2550 *2551 * Detects the current speed and duplex settings of the hardware.2552 */2553s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)2554{2555 u32 status;2556 s32 ret_val;2557 u16 phy_data;2558 2559 if (hw->mac_type >= e1000_82543) {2560 status = er32(STATUS);2561 if (status & E1000_STATUS_SPEED_1000) {2562 *speed = SPEED_1000;2563 e_dbg("1000 Mbs, ");2564 } else if (status & E1000_STATUS_SPEED_100) {2565 *speed = SPEED_100;2566 e_dbg("100 Mbs, ");2567 } else {2568 *speed = SPEED_10;2569 e_dbg("10 Mbs, ");2570 }2571 2572 if (status & E1000_STATUS_FD) {2573 *duplex = FULL_DUPLEX;2574 e_dbg("Full Duplex\n");2575 } else {2576 *duplex = HALF_DUPLEX;2577 e_dbg(" Half Duplex\n");2578 }2579 } else {2580 e_dbg("1000 Mbs, Full Duplex\n");2581 *speed = SPEED_1000;2582 *duplex = FULL_DUPLEX;2583 }2584 2585 /* IGP01 PHY may advertise full duplex operation after speed downgrade2586 * even if it is operating at half duplex. Here we set the duplex2587 * settings to match the duplex in the link partner's capabilities.2588 */2589 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {2590 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);2591 if (ret_val)2592 return ret_val;2593 2594 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))2595 *duplex = HALF_DUPLEX;2596 else {2597 ret_val =2598 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);2599 if (ret_val)2600 return ret_val;2601 if ((*speed == SPEED_100 &&2602 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||2603 (*speed == SPEED_10 &&2604 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))2605 *duplex = HALF_DUPLEX;2606 }2607 }2608 2609 return E1000_SUCCESS;2610}2611 2612/**2613 * e1000_wait_autoneg2614 * @hw: Struct containing variables accessed by shared code2615 *2616 * Blocks until autoneg completes or times out (~4.5 seconds)2617 */2618static s32 e1000_wait_autoneg(struct e1000_hw *hw)2619{2620 s32 ret_val;2621 u16 i;2622 u16 phy_data;2623 2624 e_dbg("Waiting for Auto-Neg to complete.\n");2625 2626 /* We will wait for autoneg to complete or 4.5 seconds to expire. */2627 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {2628 /* Read the MII Status Register and wait for Auto-Neg2629 * Complete bit to be set.2630 */2631 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);2632 if (ret_val)2633 return ret_val;2634 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);2635 if (ret_val)2636 return ret_val;2637 if (phy_data & MII_SR_AUTONEG_COMPLETE)2638 return E1000_SUCCESS;2639 2640 msleep(100);2641 }2642 return E1000_SUCCESS;2643}2644 2645/**2646 * e1000_raise_mdi_clk - Raises the Management Data Clock2647 * @hw: Struct containing variables accessed by shared code2648 * @ctrl: Device control register's current value2649 */2650static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)2651{2652 /* Raise the clock input to the Management Data Clock (by setting the2653 * MDC bit), and then delay 10 microseconds.2654 */2655 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));2656 E1000_WRITE_FLUSH();2657 udelay(10);2658}2659 2660/**2661 * e1000_lower_mdi_clk - Lowers the Management Data Clock2662 * @hw: Struct containing variables accessed by shared code2663 * @ctrl: Device control register's current value2664 */2665static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)2666{2667 /* Lower the clock input to the Management Data Clock (by clearing the2668 * MDC bit), and then delay 10 microseconds.2669 */2670 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));2671 E1000_WRITE_FLUSH();2672 udelay(10);2673}2674 2675/**2676 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY2677 * @hw: Struct containing variables accessed by shared code2678 * @data: Data to send out to the PHY2679 * @count: Number of bits to shift out2680 *2681 * Bits are shifted out in MSB to LSB order.2682 */2683static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)2684{2685 u32 ctrl;2686 u32 mask;2687 2688 /* We need to shift "count" number of bits out to the PHY. So, the value2689 * in the "data" parameter will be shifted out to the PHY one bit at a2690 * time. In order to do this, "data" must be broken down into bits.2691 */2692 mask = 0x01;2693 mask <<= (count - 1);2694 2695 ctrl = er32(CTRL);2696 2697 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */2698 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);2699 2700 while (mask) {2701 /* A "1" is shifted out to the PHY by setting the MDIO bit to2702 * "1" and then raising and lowering the Management Data Clock.2703 * A "0" is shifted out to the PHY by setting the MDIO bit to2704 * "0" and then raising and lowering the clock.2705 */2706 if (data & mask)2707 ctrl |= E1000_CTRL_MDIO;2708 else2709 ctrl &= ~E1000_CTRL_MDIO;2710 2711 ew32(CTRL, ctrl);2712 E1000_WRITE_FLUSH();2713 2714 udelay(10);2715 2716 e1000_raise_mdi_clk(hw, &ctrl);2717 e1000_lower_mdi_clk(hw, &ctrl);2718 2719 mask = mask >> 1;2720 }2721}2722 2723/**2724 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY2725 * @hw: Struct containing variables accessed by shared code2726 *2727 * Bits are shifted in MSB to LSB order.2728 */2729static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)2730{2731 u32 ctrl;2732 u16 data = 0;2733 u8 i;2734 2735 /* In order to read a register from the PHY, we need to shift in a total2736 * of 18 bits from the PHY. The first two bit (turnaround) times are2737 * used to avoid contention on the MDIO pin when a read operation is2738 * performed. These two bits are ignored by us and thrown away. Bits are2739 * "shifted in" by raising the input to the Management Data Clock2740 * (setting the MDC bit), and then reading the value of the MDIO bit.2741 */2742 ctrl = er32(CTRL);2743 2744 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as2745 * input.2746 */2747 ctrl &= ~E1000_CTRL_MDIO_DIR;2748 ctrl &= ~E1000_CTRL_MDIO;2749 2750 ew32(CTRL, ctrl);2751 E1000_WRITE_FLUSH();2752 2753 /* Raise and Lower the clock before reading in the data. This accounts2754 * for the turnaround bits. The first clock occurred when we clocked out2755 * the last bit of the Register Address.2756 */2757 e1000_raise_mdi_clk(hw, &ctrl);2758 e1000_lower_mdi_clk(hw, &ctrl);2759 2760 for (data = 0, i = 0; i < 16; i++) {2761 data = data << 1;2762 e1000_raise_mdi_clk(hw, &ctrl);2763 ctrl = er32(CTRL);2764 /* Check to see if we shifted in a "1". */2765 if (ctrl & E1000_CTRL_MDIO)2766 data |= 1;2767 e1000_lower_mdi_clk(hw, &ctrl);2768 }2769 2770 e1000_raise_mdi_clk(hw, &ctrl);2771 e1000_lower_mdi_clk(hw, &ctrl);2772 2773 return data;2774}2775 2776/**2777 * e1000_read_phy_reg - read a phy register2778 * @hw: Struct containing variables accessed by shared code2779 * @reg_addr: address of the PHY register to read2780 * @phy_data: pointer to the value on the PHY register2781 *2782 * Reads the value from a PHY register, if the value is on a specific non zero2783 * page, sets the page first.2784 */2785s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)2786{2787 u32 ret_val;2788 unsigned long flags;2789 2790 spin_lock_irqsave(&e1000_phy_lock, flags);2791 2792 if ((hw->phy_type == e1000_phy_igp) &&2793 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {2794 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,2795 (u16) reg_addr);2796 if (ret_val)2797 goto out;2798 }2799 2800 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,2801 phy_data);2802out:2803 spin_unlock_irqrestore(&e1000_phy_lock, flags);2804 2805 return ret_val;2806}2807 2808static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,2809 u16 *phy_data)2810{2811 u32 i;2812 u32 mdic = 0;2813 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;2814 2815 if (reg_addr > MAX_PHY_REG_ADDRESS) {2816 e_dbg("PHY Address %d is out of range\n", reg_addr);2817 return -E1000_ERR_PARAM;2818 }2819 2820 if (hw->mac_type > e1000_82543) {2821 /* Set up Op-code, Phy Address, and register address in the MDI2822 * Control register. The MAC will take care of interfacing with2823 * the PHY to retrieve the desired data.2824 */2825 if (hw->mac_type == e1000_ce4100) {2826 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |2827 (phy_addr << E1000_MDIC_PHY_SHIFT) |2828 (INTEL_CE_GBE_MDIC_OP_READ) |2829 (INTEL_CE_GBE_MDIC_GO));2830 2831 writel(mdic, E1000_MDIO_CMD);2832 2833 /* Poll the ready bit to see if the MDI read2834 * completed2835 */2836 for (i = 0; i < 64; i++) {2837 udelay(50);2838 mdic = readl(E1000_MDIO_CMD);2839 if (!(mdic & INTEL_CE_GBE_MDIC_GO))2840 break;2841 }2842 2843 if (mdic & INTEL_CE_GBE_MDIC_GO) {2844 e_dbg("MDI Read did not complete\n");2845 return -E1000_ERR_PHY;2846 }2847 2848 mdic = readl(E1000_MDIO_STS);2849 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {2850 e_dbg("MDI Read Error\n");2851 return -E1000_ERR_PHY;2852 }2853 *phy_data = (u16)mdic;2854 } else {2855 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |2856 (phy_addr << E1000_MDIC_PHY_SHIFT) |2857 (E1000_MDIC_OP_READ));2858 2859 ew32(MDIC, mdic);2860 2861 /* Poll the ready bit to see if the MDI read2862 * completed2863 */2864 for (i = 0; i < 64; i++) {2865 udelay(50);2866 mdic = er32(MDIC);2867 if (mdic & E1000_MDIC_READY)2868 break;2869 }2870 if (!(mdic & E1000_MDIC_READY)) {2871 e_dbg("MDI Read did not complete\n");2872 return -E1000_ERR_PHY;2873 }2874 if (mdic & E1000_MDIC_ERROR) {2875 e_dbg("MDI Error\n");2876 return -E1000_ERR_PHY;2877 }2878 *phy_data = (u16)mdic;2879 }2880 } else {2881 /* We must first send a preamble through the MDIO pin to signal2882 * the beginning of an MII instruction. This is done by sending2883 * 32 consecutive "1" bits.2884 */2885 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);2886 2887 /* Now combine the next few fields that are required for a read2888 * operation. We use this method instead of calling the2889 * e1000_shift_out_mdi_bits routine five different times. The2890 * format of a MII read instruction consists of a shift out of2891 * 14 bits and is defined as follows:2892 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>2893 * followed by a shift in of 18 bits. This first two bits2894 * shifted in are TurnAround bits used to avoid contention on2895 * the MDIO pin when a READ operation is performed. These two2896 * bits are thrown away followed by a shift in of 16 bits which2897 * contains the desired data.2898 */2899 mdic = ((reg_addr) | (phy_addr << 5) |2900 (PHY_OP_READ << 10) | (PHY_SOF << 12));2901 2902 e1000_shift_out_mdi_bits(hw, mdic, 14);2903 2904 /* Now that we've shifted out the read command to the MII, we2905 * need to "shift in" the 16-bit value (18 total bits) of the2906 * requested PHY register address.2907 */2908 *phy_data = e1000_shift_in_mdi_bits(hw);2909 }2910 return E1000_SUCCESS;2911}2912 2913/**2914 * e1000_write_phy_reg - write a phy register2915 *2916 * @hw: Struct containing variables accessed by shared code2917 * @reg_addr: address of the PHY register to write2918 * @phy_data: data to write to the PHY2919 *2920 * Writes a value to a PHY register2921 */2922s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)2923{2924 u32 ret_val;2925 unsigned long flags;2926 2927 spin_lock_irqsave(&e1000_phy_lock, flags);2928 2929 if ((hw->phy_type == e1000_phy_igp) &&2930 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {2931 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,2932 (u16)reg_addr);2933 if (ret_val) {2934 spin_unlock_irqrestore(&e1000_phy_lock, flags);2935 return ret_val;2936 }2937 }2938 2939 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,2940 phy_data);2941 spin_unlock_irqrestore(&e1000_phy_lock, flags);2942 2943 return ret_val;2944}2945 2946static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,2947 u16 phy_data)2948{2949 u32 i;2950 u32 mdic = 0;2951 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;2952 2953 if (reg_addr > MAX_PHY_REG_ADDRESS) {2954 e_dbg("PHY Address %d is out of range\n", reg_addr);2955 return -E1000_ERR_PARAM;2956 }2957 2958 if (hw->mac_type > e1000_82543) {2959 /* Set up Op-code, Phy Address, register address, and data2960 * intended for the PHY register in the MDI Control register.2961 * The MAC will take care of interfacing with the PHY to send2962 * the desired data.2963 */2964 if (hw->mac_type == e1000_ce4100) {2965 mdic = (((u32)phy_data) |2966 (reg_addr << E1000_MDIC_REG_SHIFT) |2967 (phy_addr << E1000_MDIC_PHY_SHIFT) |2968 (INTEL_CE_GBE_MDIC_OP_WRITE) |2969 (INTEL_CE_GBE_MDIC_GO));2970 2971 writel(mdic, E1000_MDIO_CMD);2972 2973 /* Poll the ready bit to see if the MDI read2974 * completed2975 */2976 for (i = 0; i < 640; i++) {2977 udelay(5);2978 mdic = readl(E1000_MDIO_CMD);2979 if (!(mdic & INTEL_CE_GBE_MDIC_GO))2980 break;2981 }2982 if (mdic & INTEL_CE_GBE_MDIC_GO) {2983 e_dbg("MDI Write did not complete\n");2984 return -E1000_ERR_PHY;2985 }2986 } else {2987 mdic = (((u32)phy_data) |2988 (reg_addr << E1000_MDIC_REG_SHIFT) |2989 (phy_addr << E1000_MDIC_PHY_SHIFT) |2990 (E1000_MDIC_OP_WRITE));2991 2992 ew32(MDIC, mdic);2993 2994 /* Poll the ready bit to see if the MDI read2995 * completed2996 */2997 for (i = 0; i < 641; i++) {2998 udelay(5);2999 mdic = er32(MDIC);3000 if (mdic & E1000_MDIC_READY)3001 break;3002 }3003 if (!(mdic & E1000_MDIC_READY)) {3004 e_dbg("MDI Write did not complete\n");3005 return -E1000_ERR_PHY;3006 }3007 }3008 } else {3009 /* We'll need to use the SW defined pins to shift the write3010 * command out to the PHY. We first send a preamble to the PHY3011 * to signal the beginning of the MII instruction. This is done3012 * by sending 32 consecutive "1" bits.3013 */3014 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);3015 3016 /* Now combine the remaining required fields that will indicate3017 * a write operation. We use this method instead of calling the3018 * e1000_shift_out_mdi_bits routine for each field in the3019 * command. The format of a MII write instruction is as follows:3020 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>.3021 */3022 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |3023 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));3024 mdic <<= 16;3025 mdic |= (u32)phy_data;3026 3027 e1000_shift_out_mdi_bits(hw, mdic, 32);3028 }3029 3030 return E1000_SUCCESS;3031}3032 3033/**3034 * e1000_phy_hw_reset - reset the phy, hardware style3035 * @hw: Struct containing variables accessed by shared code3036 *3037 * Returns the PHY to the power-on reset state3038 */3039s32 e1000_phy_hw_reset(struct e1000_hw *hw)3040{3041 u32 ctrl, ctrl_ext;3042 u32 led_ctrl;3043 3044 e_dbg("Resetting Phy...\n");3045 3046 if (hw->mac_type > e1000_82543) {3047 /* Read the device control register and assert the3048 * E1000_CTRL_PHY_RST bit. Then, take it out of reset.3049 * For e1000 hardware, we delay for 10ms between the assert3050 * and de-assert.3051 */3052 ctrl = er32(CTRL);3053 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);3054 E1000_WRITE_FLUSH();3055 3056 msleep(10);3057 3058 ew32(CTRL, ctrl);3059 E1000_WRITE_FLUSH();3060 3061 } else {3062 /* Read the Extended Device Control Register, assert the3063 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it3064 * out of reset.3065 */3066 ctrl_ext = er32(CTRL_EXT);3067 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;3068 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;3069 ew32(CTRL_EXT, ctrl_ext);3070 E1000_WRITE_FLUSH();3071 msleep(10);3072 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;3073 ew32(CTRL_EXT, ctrl_ext);3074 E1000_WRITE_FLUSH();3075 }3076 udelay(150);3077 3078 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {3079 /* Configure activity LED after PHY reset */3080 led_ctrl = er32(LEDCTL);3081 led_ctrl &= IGP_ACTIVITY_LED_MASK;3082 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);3083 ew32(LEDCTL, led_ctrl);3084 }3085 3086 /* Wait for FW to finish PHY configuration. */3087 return e1000_get_phy_cfg_done(hw);3088}3089 3090/**3091 * e1000_phy_reset - reset the phy to commit settings3092 * @hw: Struct containing variables accessed by shared code3093 *3094 * Resets the PHY3095 * Sets bit 15 of the MII Control register3096 */3097s32 e1000_phy_reset(struct e1000_hw *hw)3098{3099 s32 ret_val;3100 u16 phy_data;3101 3102 switch (hw->phy_type) {3103 case e1000_phy_igp:3104 ret_val = e1000_phy_hw_reset(hw);3105 if (ret_val)3106 return ret_val;3107 break;3108 default:3109 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);3110 if (ret_val)3111 return ret_val;3112 3113 phy_data |= MII_CR_RESET;3114 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);3115 if (ret_val)3116 return ret_val;3117 3118 udelay(1);3119 break;3120 }3121 3122 if (hw->phy_type == e1000_phy_igp)3123 e1000_phy_init_script(hw);3124 3125 return E1000_SUCCESS;3126}3127 3128/**3129 * e1000_detect_gig_phy - check the phy type3130 * @hw: Struct containing variables accessed by shared code3131 *3132 * Probes the expected PHY address for known PHY IDs3133 */3134static s32 e1000_detect_gig_phy(struct e1000_hw *hw)3135{3136 s32 phy_init_status, ret_val;3137 u16 phy_id_high, phy_id_low;3138 bool match = false;3139 3140 if (hw->phy_id != 0)3141 return E1000_SUCCESS;3142 3143 /* Read the PHY ID Registers to identify which PHY is onboard. */3144 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);3145 if (ret_val)3146 return ret_val;3147 3148 hw->phy_id = (u32)(phy_id_high << 16);3149 udelay(20);3150 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);3151 if (ret_val)3152 return ret_val;3153 3154 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);3155 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;3156 3157 switch (hw->mac_type) {3158 case e1000_82543:3159 if (hw->phy_id == M88E1000_E_PHY_ID)3160 match = true;3161 break;3162 case e1000_82544:3163 if (hw->phy_id == M88E1000_I_PHY_ID)3164 match = true;3165 break;3166 case e1000_82540:3167 case e1000_82545:3168 case e1000_82545_rev_3:3169 case e1000_82546:3170 case e1000_82546_rev_3:3171 if (hw->phy_id == M88E1011_I_PHY_ID)3172 match = true;3173 break;3174 case e1000_ce4100:3175 if ((hw->phy_id == RTL8211B_PHY_ID) ||3176 (hw->phy_id == RTL8201N_PHY_ID) ||3177 (hw->phy_id == M88E1118_E_PHY_ID))3178 match = true;3179 break;3180 case e1000_82541:3181 case e1000_82541_rev_2:3182 case e1000_82547:3183 case e1000_82547_rev_2:3184 if (hw->phy_id == IGP01E1000_I_PHY_ID)3185 match = true;3186 break;3187 default:3188 e_dbg("Invalid MAC type %d\n", hw->mac_type);3189 return -E1000_ERR_CONFIG;3190 }3191 phy_init_status = e1000_set_phy_type(hw);3192 3193 if ((match) && (phy_init_status == E1000_SUCCESS)) {3194 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);3195 return E1000_SUCCESS;3196 }3197 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);3198 return -E1000_ERR_PHY;3199}3200 3201/**3202 * e1000_phy_reset_dsp - reset DSP3203 * @hw: Struct containing variables accessed by shared code3204 *3205 * Resets the PHY's DSP3206 */3207static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)3208{3209 s32 ret_val;3210 3211 do {3212 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);3213 if (ret_val)3214 break;3215 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);3216 if (ret_val)3217 break;3218 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);3219 if (ret_val)3220 break;3221 ret_val = E1000_SUCCESS;3222 } while (0);3223 3224 return ret_val;3225}3226 3227/**3228 * e1000_phy_igp_get_info - get igp specific registers3229 * @hw: Struct containing variables accessed by shared code3230 * @phy_info: PHY information structure3231 *3232 * Get PHY information from various PHY registers for igp PHY only.3233 */3234static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,3235 struct e1000_phy_info *phy_info)3236{3237 s32 ret_val;3238 u16 phy_data, min_length, max_length, average;3239 e1000_rev_polarity polarity;3240 3241 /* The downshift status is checked only once, after link is established,3242 * and it stored in the hw->speed_downgraded parameter.3243 */3244 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;3245 3246 /* IGP01E1000 does not need to support it. */3247 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;3248 3249 /* IGP01E1000 always correct polarity reversal */3250 phy_info->polarity_correction = e1000_polarity_reversal_enabled;3251 3252 /* Check polarity status */3253 ret_val = e1000_check_polarity(hw, &polarity);3254 if (ret_val)3255 return ret_val;3256 3257 phy_info->cable_polarity = polarity;3258 3259 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);3260 if (ret_val)3261 return ret_val;3262 3263 phy_info->mdix_mode =3264 (e1000_auto_x_mode)FIELD_GET(IGP01E1000_PSSR_MDIX, phy_data);3265 3266 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==3267 IGP01E1000_PSSR_SPEED_1000MBPS) {3268 /* Local/Remote Receiver Information are only valid @ 10003269 * Mbps3270 */3271 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);3272 if (ret_val)3273 return ret_val;3274 3275 phy_info->local_rx = FIELD_GET(SR_1000T_LOCAL_RX_STATUS,3276 phy_data) ?3277 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;3278 phy_info->remote_rx = FIELD_GET(SR_1000T_REMOTE_RX_STATUS,3279 phy_data) ?3280 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;3281 3282 /* Get cable length */3283 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);3284 if (ret_val)3285 return ret_val;3286 3287 /* Translate to old method */3288 average = (max_length + min_length) / 2;3289 3290 if (average <= e1000_igp_cable_length_50)3291 phy_info->cable_length = e1000_cable_length_50;3292 else if (average <= e1000_igp_cable_length_80)3293 phy_info->cable_length = e1000_cable_length_50_80;3294 else if (average <= e1000_igp_cable_length_110)3295 phy_info->cable_length = e1000_cable_length_80_110;3296 else if (average <= e1000_igp_cable_length_140)3297 phy_info->cable_length = e1000_cable_length_110_140;3298 else3299 phy_info->cable_length = e1000_cable_length_140;3300 }3301 3302 return E1000_SUCCESS;3303}3304 3305/**3306 * e1000_phy_m88_get_info - get m88 specific registers3307 * @hw: Struct containing variables accessed by shared code3308 * @phy_info: PHY information structure3309 *3310 * Get PHY information from various PHY registers for m88 PHY only.3311 */3312static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,3313 struct e1000_phy_info *phy_info)3314{3315 s32 ret_val;3316 u16 phy_data;3317 e1000_rev_polarity polarity;3318 3319 /* The downshift status is checked only once, after link is established,3320 * and it stored in the hw->speed_downgraded parameter.3321 */3322 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;3323 3324 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);3325 if (ret_val)3326 return ret_val;3327 3328 phy_info->extended_10bt_distance =3329 FIELD_GET(M88E1000_PSCR_10BT_EXT_DIST_ENABLE, phy_data) ?3330 e1000_10bt_ext_dist_enable_lower :3331 e1000_10bt_ext_dist_enable_normal;3332 3333 phy_info->polarity_correction =3334 FIELD_GET(M88E1000_PSCR_POLARITY_REVERSAL, phy_data) ?3335 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;3336 3337 /* Check polarity status */3338 ret_val = e1000_check_polarity(hw, &polarity);3339 if (ret_val)3340 return ret_val;3341 phy_info->cable_polarity = polarity;3342 3343 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);3344 if (ret_val)3345 return ret_val;3346 3347 phy_info->mdix_mode =3348 (e1000_auto_x_mode)FIELD_GET(M88E1000_PSSR_MDIX, phy_data);3349 3350 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {3351 /* Cable Length Estimation and Local/Remote Receiver Information3352 * are only valid at 1000 Mbps.3353 */3354 phy_info->cable_length =3355 (e1000_cable_length)FIELD_GET(M88E1000_PSSR_CABLE_LENGTH,3356 phy_data);3357 3358 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);3359 if (ret_val)3360 return ret_val;3361 3362 phy_info->local_rx = FIELD_GET(SR_1000T_LOCAL_RX_STATUS,3363 phy_data) ?3364 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;3365 phy_info->remote_rx = FIELD_GET(SR_1000T_REMOTE_RX_STATUS,3366 phy_data) ?3367 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;3368 }3369 3370 return E1000_SUCCESS;3371}3372 3373/**3374 * e1000_phy_get_info - request phy info3375 * @hw: Struct containing variables accessed by shared code3376 * @phy_info: PHY information structure3377 *3378 * Get PHY information from various PHY registers3379 */3380s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)3381{3382 s32 ret_val;3383 u16 phy_data;3384 3385 phy_info->cable_length = e1000_cable_length_undefined;3386 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;3387 phy_info->cable_polarity = e1000_rev_polarity_undefined;3388 phy_info->downshift = e1000_downshift_undefined;3389 phy_info->polarity_correction = e1000_polarity_reversal_undefined;3390 phy_info->mdix_mode = e1000_auto_x_mode_undefined;3391 phy_info->local_rx = e1000_1000t_rx_status_undefined;3392 phy_info->remote_rx = e1000_1000t_rx_status_undefined;3393 3394 if (hw->media_type != e1000_media_type_copper) {3395 e_dbg("PHY info is only valid for copper media\n");3396 return -E1000_ERR_CONFIG;3397 }3398 3399 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);3400 if (ret_val)3401 return ret_val;3402 3403 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);3404 if (ret_val)3405 return ret_val;3406 3407 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {3408 e_dbg("PHY info is only valid if link is up\n");3409 return -E1000_ERR_CONFIG;3410 }3411 3412 if (hw->phy_type == e1000_phy_igp)3413 return e1000_phy_igp_get_info(hw, phy_info);3414 else if ((hw->phy_type == e1000_phy_8211) ||3415 (hw->phy_type == e1000_phy_8201))3416 return E1000_SUCCESS;3417 else3418 return e1000_phy_m88_get_info(hw, phy_info);3419}3420 3421s32 e1000_validate_mdi_setting(struct e1000_hw *hw)3422{3423 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {3424 e_dbg("Invalid MDI setting detected\n");3425 hw->mdix = 1;3426 return -E1000_ERR_CONFIG;3427 }3428 return E1000_SUCCESS;3429}3430 3431/**3432 * e1000_init_eeprom_params - initialize sw eeprom vars3433 * @hw: Struct containing variables accessed by shared code3434 *3435 * Sets up eeprom variables in the hw struct. Must be called after mac_type3436 * is configured.3437 */3438s32 e1000_init_eeprom_params(struct e1000_hw *hw)3439{3440 struct e1000_eeprom_info *eeprom = &hw->eeprom;3441 u32 eecd = er32(EECD);3442 s32 ret_val = E1000_SUCCESS;3443 u16 eeprom_size;3444 3445 switch (hw->mac_type) {3446 case e1000_82542_rev2_0:3447 case e1000_82542_rev2_1:3448 case e1000_82543:3449 case e1000_82544:3450 eeprom->type = e1000_eeprom_microwire;3451 eeprom->word_size = 64;3452 eeprom->opcode_bits = 3;3453 eeprom->address_bits = 6;3454 eeprom->delay_usec = 50;3455 break;3456 case e1000_82540:3457 case e1000_82545:3458 case e1000_82545_rev_3:3459 case e1000_82546:3460 case e1000_82546_rev_3:3461 eeprom->type = e1000_eeprom_microwire;3462 eeprom->opcode_bits = 3;3463 eeprom->delay_usec = 50;3464 if (eecd & E1000_EECD_SIZE) {3465 eeprom->word_size = 256;3466 eeprom->address_bits = 8;3467 } else {3468 eeprom->word_size = 64;3469 eeprom->address_bits = 6;3470 }3471 break;3472 case e1000_82541:3473 case e1000_82541_rev_2:3474 case e1000_82547:3475 case e1000_82547_rev_2:3476 if (eecd & E1000_EECD_TYPE) {3477 eeprom->type = e1000_eeprom_spi;3478 eeprom->opcode_bits = 8;3479 eeprom->delay_usec = 1;3480 if (eecd & E1000_EECD_ADDR_BITS) {3481 eeprom->page_size = 32;3482 eeprom->address_bits = 16;3483 } else {3484 eeprom->page_size = 8;3485 eeprom->address_bits = 8;3486 }3487 } else {3488 eeprom->type = e1000_eeprom_microwire;3489 eeprom->opcode_bits = 3;3490 eeprom->delay_usec = 50;3491 if (eecd & E1000_EECD_ADDR_BITS) {3492 eeprom->word_size = 256;3493 eeprom->address_bits = 8;3494 } else {3495 eeprom->word_size = 64;3496 eeprom->address_bits = 6;3497 }3498 }3499 break;3500 default:3501 break;3502 }3503 3504 if (eeprom->type == e1000_eeprom_spi) {3505 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes3506 * 128B to 32KB (incremented by powers of 2).3507 */3508 /* Set to default value for initial eeprom read. */3509 eeprom->word_size = 64;3510 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);3511 if (ret_val)3512 return ret_val;3513 eeprom_size =3514 FIELD_GET(EEPROM_SIZE_MASK, eeprom_size);3515 /* 256B eeprom size was not supported in earlier hardware, so we3516 * bump eeprom_size up one to ensure that "1" (which maps to3517 * 256B) is never the result used in the shifting logic below.3518 */3519 if (eeprom_size)3520 eeprom_size++;3521 3522 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);3523 }3524 return ret_val;3525}3526 3527/**3528 * e1000_raise_ee_clk - Raises the EEPROM's clock input.3529 * @hw: Struct containing variables accessed by shared code3530 * @eecd: EECD's current value3531 */3532static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)3533{3534 /* Raise the clock input to the EEPROM (by setting the SK bit), and then3535 * wait <delay> microseconds.3536 */3537 *eecd = *eecd | E1000_EECD_SK;3538 ew32(EECD, *eecd);3539 E1000_WRITE_FLUSH();3540 udelay(hw->eeprom.delay_usec);3541}3542 3543/**3544 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.3545 * @hw: Struct containing variables accessed by shared code3546 * @eecd: EECD's current value3547 */3548static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)3549{3550 /* Lower the clock input to the EEPROM (by clearing the SK bit), and3551 * then wait 50 microseconds.3552 */3553 *eecd = *eecd & ~E1000_EECD_SK;3554 ew32(EECD, *eecd);3555 E1000_WRITE_FLUSH();3556 udelay(hw->eeprom.delay_usec);3557}3558 3559/**3560 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.3561 * @hw: Struct containing variables accessed by shared code3562 * @data: data to send to the EEPROM3563 * @count: number of bits to shift out3564 */3565static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)3566{3567 struct e1000_eeprom_info *eeprom = &hw->eeprom;3568 u32 eecd;3569 u32 mask;3570 3571 /* We need to shift "count" bits out to the EEPROM. So, value in the3572 * "data" parameter will be shifted out to the EEPROM one bit at a time.3573 * In order to do this, "data" must be broken down into bits.3574 */3575 mask = 0x01 << (count - 1);3576 eecd = er32(EECD);3577 if (eeprom->type == e1000_eeprom_microwire)3578 eecd &= ~E1000_EECD_DO;3579 else if (eeprom->type == e1000_eeprom_spi)3580 eecd |= E1000_EECD_DO;3581 3582 do {3583 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a3584 * "1", and then raising and then lowering the clock (the SK bit3585 * controls the clock input to the EEPROM). A "0" is shifted3586 * out to the EEPROM by setting "DI" to "0" and then raising and3587 * then lowering the clock.3588 */3589 eecd &= ~E1000_EECD_DI;3590 3591 if (data & mask)3592 eecd |= E1000_EECD_DI;3593 3594 ew32(EECD, eecd);3595 E1000_WRITE_FLUSH();3596 3597 udelay(eeprom->delay_usec);3598 3599 e1000_raise_ee_clk(hw, &eecd);3600 e1000_lower_ee_clk(hw, &eecd);3601 3602 mask = mask >> 1;3603 3604 } while (mask);3605 3606 /* We leave the "DI" bit set to "0" when we leave this routine. */3607 eecd &= ~E1000_EECD_DI;3608 ew32(EECD, eecd);3609}3610 3611/**3612 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM3613 * @hw: Struct containing variables accessed by shared code3614 * @count: number of bits to shift in3615 */3616static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)3617{3618 u32 eecd;3619 u32 i;3620 u16 data;3621 3622 /* In order to read a register from the EEPROM, we need to shift 'count'3623 * bits in from the EEPROM. Bits are "shifted in" by raising the clock3624 * input to the EEPROM (setting the SK bit), and then reading the value3625 * of the "DO" bit. During this "shifting in" process the "DI" bit3626 * should always be clear.3627 */3628 3629 eecd = er32(EECD);3630 3631 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);3632 data = 0;3633 3634 for (i = 0; i < count; i++) {3635 data = data << 1;3636 e1000_raise_ee_clk(hw, &eecd);3637 3638 eecd = er32(EECD);3639 3640 eecd &= ~(E1000_EECD_DI);3641 if (eecd & E1000_EECD_DO)3642 data |= 1;3643 3644 e1000_lower_ee_clk(hw, &eecd);3645 }3646 3647 return data;3648}3649 3650/**3651 * e1000_acquire_eeprom - Prepares EEPROM for access3652 * @hw: Struct containing variables accessed by shared code3653 *3654 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This3655 * function should be called before issuing a command to the EEPROM.3656 */3657static s32 e1000_acquire_eeprom(struct e1000_hw *hw)3658{3659 struct e1000_eeprom_info *eeprom = &hw->eeprom;3660 u32 eecd, i = 0;3661 3662 eecd = er32(EECD);3663 3664 /* Request EEPROM Access */3665 if (hw->mac_type > e1000_82544) {3666 eecd |= E1000_EECD_REQ;3667 ew32(EECD, eecd);3668 eecd = er32(EECD);3669 while ((!(eecd & E1000_EECD_GNT)) &&3670 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {3671 i++;3672 udelay(5);3673 eecd = er32(EECD);3674 }3675 if (!(eecd & E1000_EECD_GNT)) {3676 eecd &= ~E1000_EECD_REQ;3677 ew32(EECD, eecd);3678 e_dbg("Could not acquire EEPROM grant\n");3679 return -E1000_ERR_EEPROM;3680 }3681 }3682 3683 /* Setup EEPROM for Read/Write */3684 3685 if (eeprom->type == e1000_eeprom_microwire) {3686 /* Clear SK and DI */3687 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);3688 ew32(EECD, eecd);3689 3690 /* Set CS */3691 eecd |= E1000_EECD_CS;3692 ew32(EECD, eecd);3693 } else if (eeprom->type == e1000_eeprom_spi) {3694 /* Clear SK and CS */3695 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);3696 ew32(EECD, eecd);3697 E1000_WRITE_FLUSH();3698 udelay(1);3699 }3700 3701 return E1000_SUCCESS;3702}3703 3704/**3705 * e1000_standby_eeprom - Returns EEPROM to a "standby" state3706 * @hw: Struct containing variables accessed by shared code3707 */3708static void e1000_standby_eeprom(struct e1000_hw *hw)3709{3710 struct e1000_eeprom_info *eeprom = &hw->eeprom;3711 u32 eecd;3712 3713 eecd = er32(EECD);3714 3715 if (eeprom->type == e1000_eeprom_microwire) {3716 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);3717 ew32(EECD, eecd);3718 E1000_WRITE_FLUSH();3719 udelay(eeprom->delay_usec);3720 3721 /* Clock high */3722 eecd |= E1000_EECD_SK;3723 ew32(EECD, eecd);3724 E1000_WRITE_FLUSH();3725 udelay(eeprom->delay_usec);3726 3727 /* Select EEPROM */3728 eecd |= E1000_EECD_CS;3729 ew32(EECD, eecd);3730 E1000_WRITE_FLUSH();3731 udelay(eeprom->delay_usec);3732 3733 /* Clock low */3734 eecd &= ~E1000_EECD_SK;3735 ew32(EECD, eecd);3736 E1000_WRITE_FLUSH();3737 udelay(eeprom->delay_usec);3738 } else if (eeprom->type == e1000_eeprom_spi) {3739 /* Toggle CS to flush commands */3740 eecd |= E1000_EECD_CS;3741 ew32(EECD, eecd);3742 E1000_WRITE_FLUSH();3743 udelay(eeprom->delay_usec);3744 eecd &= ~E1000_EECD_CS;3745 ew32(EECD, eecd);3746 E1000_WRITE_FLUSH();3747 udelay(eeprom->delay_usec);3748 }3749}3750 3751/**3752 * e1000_release_eeprom - drop chip select3753 * @hw: Struct containing variables accessed by shared code3754 *3755 * Terminates a command by inverting the EEPROM's chip select pin3756 */3757static void e1000_release_eeprom(struct e1000_hw *hw)3758{3759 u32 eecd;3760 3761 eecd = er32(EECD);3762 3763 if (hw->eeprom.type == e1000_eeprom_spi) {3764 eecd |= E1000_EECD_CS; /* Pull CS high */3765 eecd &= ~E1000_EECD_SK; /* Lower SCK */3766 3767 ew32(EECD, eecd);3768 E1000_WRITE_FLUSH();3769 3770 udelay(hw->eeprom.delay_usec);3771 } else if (hw->eeprom.type == e1000_eeprom_microwire) {3772 /* cleanup eeprom */3773 3774 /* CS on Microwire is active-high */3775 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);3776 3777 ew32(EECD, eecd);3778 3779 /* Rising edge of clock */3780 eecd |= E1000_EECD_SK;3781 ew32(EECD, eecd);3782 E1000_WRITE_FLUSH();3783 udelay(hw->eeprom.delay_usec);3784 3785 /* Falling edge of clock */3786 eecd &= ~E1000_EECD_SK;3787 ew32(EECD, eecd);3788 E1000_WRITE_FLUSH();3789 udelay(hw->eeprom.delay_usec);3790 }3791 3792 /* Stop requesting EEPROM access */3793 if (hw->mac_type > e1000_82544) {3794 eecd &= ~E1000_EECD_REQ;3795 ew32(EECD, eecd);3796 }3797}3798 3799/**3800 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.3801 * @hw: Struct containing variables accessed by shared code3802 */3803static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)3804{3805 u16 retry_count = 0;3806 u8 spi_stat_reg;3807 3808 /* Read "Status Register" repeatedly until the LSB is cleared. The3809 * EEPROM will signal that the command has been completed by clearing3810 * bit 0 of the internal status register. If it's not cleared within3811 * 5 milliseconds, then error out.3812 */3813 retry_count = 0;3814 do {3815 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,3816 hw->eeprom.opcode_bits);3817 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);3818 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))3819 break;3820 3821 udelay(5);3822 retry_count += 5;3823 3824 e1000_standby_eeprom(hw);3825 } while (retry_count < EEPROM_MAX_RETRY_SPI);3826 3827 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and3828 * only 0-5mSec on 5V devices)3829 */3830 if (retry_count >= EEPROM_MAX_RETRY_SPI) {3831 e_dbg("SPI EEPROM Status error\n");3832 return -E1000_ERR_EEPROM;3833 }3834 3835 return E1000_SUCCESS;3836}3837 3838/**3839 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.3840 * @hw: Struct containing variables accessed by shared code3841 * @offset: offset of word in the EEPROM to read3842 * @data: word read from the EEPROM3843 * @words: number of words to read3844 */3845s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)3846{3847 s32 ret;3848 3849 mutex_lock(&e1000_eeprom_lock);3850 ret = e1000_do_read_eeprom(hw, offset, words, data);3851 mutex_unlock(&e1000_eeprom_lock);3852 return ret;3853}3854 3855static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,3856 u16 *data)3857{3858 struct e1000_eeprom_info *eeprom = &hw->eeprom;3859 u32 i = 0;3860 3861 if (hw->mac_type == e1000_ce4100) {3862 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,3863 data);3864 return E1000_SUCCESS;3865 }3866 3867 /* A check for invalid values: offset too large, too many words, and3868 * not enough words.3869 */3870 if ((offset >= eeprom->word_size) ||3871 (words > eeprom->word_size - offset) ||3872 (words == 0)) {3873 e_dbg("\"words\" parameter out of bounds. Words = %d,"3874 "size = %d\n", offset, eeprom->word_size);3875 return -E1000_ERR_EEPROM;3876 }3877 3878 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI3879 * directly. In this case, we need to acquire the EEPROM so that3880 * FW or other port software does not interrupt.3881 */3882 /* Prepare the EEPROM for bit-bang reading */3883 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)3884 return -E1000_ERR_EEPROM;3885 3886 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have3887 * acquired the EEPROM at this point, so any returns should release it3888 */3889 if (eeprom->type == e1000_eeprom_spi) {3890 u16 word_in;3891 u8 read_opcode = EEPROM_READ_OPCODE_SPI;3892 3893 if (e1000_spi_eeprom_ready(hw)) {3894 e1000_release_eeprom(hw);3895 return -E1000_ERR_EEPROM;3896 }3897 3898 e1000_standby_eeprom(hw);3899 3900 /* Some SPI eeproms use the 8th address bit embedded in the3901 * opcode3902 */3903 if ((eeprom->address_bits == 8) && (offset >= 128))3904 read_opcode |= EEPROM_A8_OPCODE_SPI;3905 3906 /* Send the READ command (opcode + addr) */3907 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);3908 e1000_shift_out_ee_bits(hw, (u16)(offset * 2),3909 eeprom->address_bits);3910 3911 /* Read the data. The address of the eeprom internally3912 * increments with each byte (spi) being read, saving on the3913 * overhead of eeprom setup and tear-down. The address counter3914 * will roll over if reading beyond the size of the eeprom, thus3915 * allowing the entire memory to be read starting from any3916 * offset.3917 */3918 for (i = 0; i < words; i++) {3919 word_in = e1000_shift_in_ee_bits(hw, 16);3920 data[i] = (word_in >> 8) | (word_in << 8);3921 }3922 } else if (eeprom->type == e1000_eeprom_microwire) {3923 for (i = 0; i < words; i++) {3924 /* Send the READ command (opcode + addr) */3925 e1000_shift_out_ee_bits(hw,3926 EEPROM_READ_OPCODE_MICROWIRE,3927 eeprom->opcode_bits);3928 e1000_shift_out_ee_bits(hw, (u16)(offset + i),3929 eeprom->address_bits);3930 3931 /* Read the data. For microwire, each word requires the3932 * overhead of eeprom setup and tear-down.3933 */3934 data[i] = e1000_shift_in_ee_bits(hw, 16);3935 e1000_standby_eeprom(hw);3936 cond_resched();3937 }3938 }3939 3940 /* End this read operation */3941 e1000_release_eeprom(hw);3942 3943 return E1000_SUCCESS;3944}3945 3946/**3947 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum3948 * @hw: Struct containing variables accessed by shared code3949 *3950 * Reads the first 64 16 bit words of the EEPROM and sums the values read.3951 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is3952 * valid.3953 */3954s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)3955{3956 u16 checksum = 0;3957 u16 i, eeprom_data;3958 3959 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {3960 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {3961 e_dbg("EEPROM Read Error\n");3962 return -E1000_ERR_EEPROM;3963 }3964 checksum += eeprom_data;3965 }3966 3967#ifdef CONFIG_PARISC3968 /* This is a signature and not a checksum on HP c8000 */3969 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))3970 return E1000_SUCCESS;3971 3972#endif3973 if (checksum == (u16)EEPROM_SUM)3974 return E1000_SUCCESS;3975 else {3976 e_dbg("EEPROM Checksum Invalid\n");3977 return -E1000_ERR_EEPROM;3978 }3979}3980 3981/**3982 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum3983 * @hw: Struct containing variables accessed by shared code3984 *3985 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.3986 * Writes the difference to word offset 63 of the EEPROM.3987 */3988s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)3989{3990 u16 checksum = 0;3991 u16 i, eeprom_data;3992 3993 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {3994 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {3995 e_dbg("EEPROM Read Error\n");3996 return -E1000_ERR_EEPROM;3997 }3998 checksum += eeprom_data;3999 }4000 checksum = (u16)EEPROM_SUM - checksum;4001 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {4002 e_dbg("EEPROM Write Error\n");4003 return -E1000_ERR_EEPROM;4004 }4005 return E1000_SUCCESS;4006}4007 4008/**4009 * e1000_write_eeprom - write words to the different EEPROM types.4010 * @hw: Struct containing variables accessed by shared code4011 * @offset: offset within the EEPROM to be written to4012 * @words: number of words to write4013 * @data: 16 bit word to be written to the EEPROM4014 *4015 * If e1000_update_eeprom_checksum is not called after this function, the4016 * EEPROM will most likely contain an invalid checksum.4017 */4018s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)4019{4020 s32 ret;4021 4022 mutex_lock(&e1000_eeprom_lock);4023 ret = e1000_do_write_eeprom(hw, offset, words, data);4024 mutex_unlock(&e1000_eeprom_lock);4025 return ret;4026}4027 4028static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,4029 u16 *data)4030{4031 struct e1000_eeprom_info *eeprom = &hw->eeprom;4032 s32 status = 0;4033 4034 if (hw->mac_type == e1000_ce4100) {4035 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,4036 data);4037 return E1000_SUCCESS;4038 }4039 4040 /* A check for invalid values: offset too large, too many words, and4041 * not enough words.4042 */4043 if ((offset >= eeprom->word_size) ||4044 (words > eeprom->word_size - offset) ||4045 (words == 0)) {4046 e_dbg("\"words\" parameter out of bounds\n");4047 return -E1000_ERR_EEPROM;4048 }4049 4050 /* Prepare the EEPROM for writing */4051 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)4052 return -E1000_ERR_EEPROM;4053 4054 if (eeprom->type == e1000_eeprom_microwire) {4055 status = e1000_write_eeprom_microwire(hw, offset, words, data);4056 } else {4057 status = e1000_write_eeprom_spi(hw, offset, words, data);4058 msleep(10);4059 }4060 4061 /* Done with writing */4062 e1000_release_eeprom(hw);4063 4064 return status;4065}4066 4067/**4068 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.4069 * @hw: Struct containing variables accessed by shared code4070 * @offset: offset within the EEPROM to be written to4071 * @words: number of words to write4072 * @data: pointer to array of 8 bit words to be written to the EEPROM4073 */4074static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,4075 u16 *data)4076{4077 struct e1000_eeprom_info *eeprom = &hw->eeprom;4078 u16 widx = 0;4079 4080 while (widx < words) {4081 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;4082 4083 if (e1000_spi_eeprom_ready(hw))4084 return -E1000_ERR_EEPROM;4085 4086 e1000_standby_eeprom(hw);4087 cond_resched();4088 4089 /* Send the WRITE ENABLE command (8 bit opcode ) */4090 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,4091 eeprom->opcode_bits);4092 4093 e1000_standby_eeprom(hw);4094 4095 /* Some SPI eeproms use the 8th address bit embedded in the4096 * opcode4097 */4098 if ((eeprom->address_bits == 8) && (offset >= 128))4099 write_opcode |= EEPROM_A8_OPCODE_SPI;4100 4101 /* Send the Write command (8-bit opcode + addr) */4102 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);4103 4104 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),4105 eeprom->address_bits);4106 4107 /* Send the data */4108 4109 /* Loop to allow for up to whole page write (32 bytes) of4110 * eeprom4111 */4112 while (widx < words) {4113 u16 word_out = data[widx];4114 4115 word_out = (word_out >> 8) | (word_out << 8);4116 e1000_shift_out_ee_bits(hw, word_out, 16);4117 widx++;4118 4119 /* Some larger eeprom sizes are capable of a 32-byte4120 * PAGE WRITE operation, while the smaller eeproms are4121 * capable of an 8-byte PAGE WRITE operation. Break the4122 * inner loop to pass new address4123 */4124 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {4125 e1000_standby_eeprom(hw);4126 break;4127 }4128 }4129 }4130 4131 return E1000_SUCCESS;4132}4133 4134/**4135 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.4136 * @hw: Struct containing variables accessed by shared code4137 * @offset: offset within the EEPROM to be written to4138 * @words: number of words to write4139 * @data: pointer to array of 8 bit words to be written to the EEPROM4140 */4141static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,4142 u16 words, u16 *data)4143{4144 struct e1000_eeprom_info *eeprom = &hw->eeprom;4145 u32 eecd;4146 u16 words_written = 0;4147 u16 i = 0;4148 4149 /* Send the write enable command to the EEPROM (3-bit opcode plus4150 * 6/8-bit dummy address beginning with 11). It's less work to include4151 * the 11 of the dummy address as part of the opcode than it is to shift4152 * it over the correct number of bits for the address. This puts the4153 * EEPROM into write/erase mode.4154 */4155 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,4156 (u16)(eeprom->opcode_bits + 2));4157 4158 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));4159 4160 /* Prepare the EEPROM */4161 e1000_standby_eeprom(hw);4162 4163 while (words_written < words) {4164 /* Send the Write command (3-bit opcode + addr) */4165 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,4166 eeprom->opcode_bits);4167 4168 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),4169 eeprom->address_bits);4170 4171 /* Send the data */4172 e1000_shift_out_ee_bits(hw, data[words_written], 16);4173 4174 /* Toggle the CS line. This in effect tells the EEPROM to4175 * execute the previous command.4176 */4177 e1000_standby_eeprom(hw);4178 4179 /* Read DO repeatedly until it is high (equal to '1'). The4180 * EEPROM will signal that the command has been completed by4181 * raising the DO signal. If DO does not go high in 104182 * milliseconds, then error out.4183 */4184 for (i = 0; i < 200; i++) {4185 eecd = er32(EECD);4186 if (eecd & E1000_EECD_DO)4187 break;4188 udelay(50);4189 }4190 if (i == 200) {4191 e_dbg("EEPROM Write did not complete\n");4192 return -E1000_ERR_EEPROM;4193 }4194 4195 /* Recover from write */4196 e1000_standby_eeprom(hw);4197 cond_resched();4198 4199 words_written++;4200 }4201 4202 /* Send the write disable command to the EEPROM (3-bit opcode plus4203 * 6/8-bit dummy address beginning with 10). It's less work to include4204 * the 10 of the dummy address as part of the opcode than it is to shift4205 * it over the correct number of bits for the address. This takes the4206 * EEPROM out of write/erase mode.4207 */4208 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,4209 (u16)(eeprom->opcode_bits + 2));4210 4211 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));4212 4213 return E1000_SUCCESS;4214}4215 4216/**4217 * e1000_read_mac_addr - read the adapters MAC from eeprom4218 * @hw: Struct containing variables accessed by shared code4219 *4220 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the4221 * second function of dual function devices4222 */4223s32 e1000_read_mac_addr(struct e1000_hw *hw)4224{4225 u16 offset;4226 u16 eeprom_data, i;4227 4228 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {4229 offset = i >> 1;4230 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {4231 e_dbg("EEPROM Read Error\n");4232 return -E1000_ERR_EEPROM;4233 }4234 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);4235 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);4236 }4237 4238 switch (hw->mac_type) {4239 default:4240 break;4241 case e1000_82546:4242 case e1000_82546_rev_3:4243 if (er32(STATUS) & E1000_STATUS_FUNC_1)4244 hw->perm_mac_addr[5] ^= 0x01;4245 break;4246 }4247 4248 for (i = 0; i < NODE_ADDRESS_SIZE; i++)4249 hw->mac_addr[i] = hw->perm_mac_addr[i];4250 return E1000_SUCCESS;4251}4252 4253/**4254 * e1000_init_rx_addrs - Initializes receive address filters.4255 * @hw: Struct containing variables accessed by shared code4256 *4257 * Places the MAC address in receive address register 0 and clears the rest4258 * of the receive address registers. Clears the multicast table. Assumes4259 * the receiver is in reset when the routine is called.4260 */4261static void e1000_init_rx_addrs(struct e1000_hw *hw)4262{4263 u32 i;4264 u32 rar_num;4265 4266 /* Setup the receive address. */4267 e_dbg("Programming MAC Address into RAR[0]\n");4268 4269 e1000_rar_set(hw, hw->mac_addr, 0);4270 4271 rar_num = E1000_RAR_ENTRIES;4272 4273 /* Zero out the following 14 receive addresses. RAR[15] is for4274 * manageability4275 */4276 e_dbg("Clearing RAR[1-14]\n");4277 for (i = 1; i < rar_num; i++) {4278 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);4279 E1000_WRITE_FLUSH();4280 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);4281 E1000_WRITE_FLUSH();4282 }4283}4284 4285/**4286 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table4287 * @hw: Struct containing variables accessed by shared code4288 * @mc_addr: the multicast address to hash4289 */4290u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)4291{4292 u32 hash_value = 0;4293 4294 /* The portion of the address that is used for the hash table is4295 * determined by the mc_filter_type setting.4296 */4297 switch (hw->mc_filter_type) {4298 /* [0] [1] [2] [3] [4] [5]4299 * 01 AA 00 12 34 564300 * LSB MSB4301 */4302 case 0:4303 /* [47:36] i.e. 0x563 for above example address */4304 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));4305 break;4306 case 1:4307 /* [46:35] i.e. 0xAC6 for above example address */4308 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));4309 break;4310 case 2:4311 /* [45:34] i.e. 0x5D8 for above example address */4312 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));4313 break;4314 case 3:4315 /* [43:32] i.e. 0x634 for above example address */4316 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));4317 break;4318 }4319 4320 hash_value &= 0xFFF;4321 return hash_value;4322}4323 4324/**4325 * e1000_rar_set - Puts an ethernet address into a receive address register.4326 * @hw: Struct containing variables accessed by shared code4327 * @addr: Address to put into receive address register4328 * @index: Receive address register to write4329 */4330void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)4331{4332 u32 rar_low, rar_high;4333 4334 /* HW expects these in little endian so we reverse the byte order4335 * from network order (big endian) to little endian4336 */4337 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |4338 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));4339 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));4340 4341 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx4342 * unit hang.4343 *4344 * Description:4345 * If there are any Rx frames queued up or otherwise present in the HW4346 * before RSS is enabled, and then we enable RSS, the HW Rx unit will4347 * hang. To work around this issue, we have to disable receives and4348 * flush out all Rx frames before we enable RSS. To do so, we modify we4349 * redirect all Rx traffic to manageability and then reset the HW.4350 * This flushes away Rx frames, and (since the redirections to4351 * manageability persists across resets) keeps new ones from coming in4352 * while we work. Then, we clear the Address Valid AV bit for all MAC4353 * addresses and undo the re-direction to manageability.4354 * Now, frames are coming in again, but the MAC won't accept them, so4355 * far so good. We now proceed to initialize RSS (if necessary) and4356 * configure the Rx unit. Last, we re-enable the AV bits and continue4357 * on our merry way.4358 */4359 switch (hw->mac_type) {4360 default:4361 /* Indicate to hardware the Address is Valid. */4362 rar_high |= E1000_RAH_AV;4363 break;4364 }4365 4366 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);4367 E1000_WRITE_FLUSH();4368 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);4369 E1000_WRITE_FLUSH();4370}4371 4372/**4373 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.4374 * @hw: Struct containing variables accessed by shared code4375 * @offset: Offset in VLAN filter table to write4376 * @value: Value to write into VLAN filter table4377 */4378void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)4379{4380 u32 temp;4381 4382 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {4383 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));4384 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);4385 E1000_WRITE_FLUSH();4386 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);4387 E1000_WRITE_FLUSH();4388 } else {4389 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);4390 E1000_WRITE_FLUSH();4391 }4392}4393 4394/**4395 * e1000_clear_vfta - Clears the VLAN filter table4396 * @hw: Struct containing variables accessed by shared code4397 */4398static void e1000_clear_vfta(struct e1000_hw *hw)4399{4400 u32 offset;4401 4402 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {4403 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);4404 E1000_WRITE_FLUSH();4405 }4406}4407 4408static s32 e1000_id_led_init(struct e1000_hw *hw)4409{4410 u32 ledctl;4411 const u32 ledctl_mask = 0x000000FF;4412 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;4413 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;4414 u16 eeprom_data, i, temp;4415 const u16 led_mask = 0x0F;4416 4417 if (hw->mac_type < e1000_82540) {4418 /* Nothing to do */4419 return E1000_SUCCESS;4420 }4421 4422 ledctl = er32(LEDCTL);4423 hw->ledctl_default = ledctl;4424 hw->ledctl_mode1 = hw->ledctl_default;4425 hw->ledctl_mode2 = hw->ledctl_default;4426 4427 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {4428 e_dbg("EEPROM Read Error\n");4429 return -E1000_ERR_EEPROM;4430 }4431 4432 if ((eeprom_data == ID_LED_RESERVED_0000) ||4433 (eeprom_data == ID_LED_RESERVED_FFFF)) {4434 eeprom_data = ID_LED_DEFAULT;4435 }4436 4437 for (i = 0; i < 4; i++) {4438 temp = (eeprom_data >> (i << 2)) & led_mask;4439 switch (temp) {4440 case ID_LED_ON1_DEF2:4441 case ID_LED_ON1_ON2:4442 case ID_LED_ON1_OFF2:4443 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));4444 hw->ledctl_mode1 |= ledctl_on << (i << 3);4445 break;4446 case ID_LED_OFF1_DEF2:4447 case ID_LED_OFF1_ON2:4448 case ID_LED_OFF1_OFF2:4449 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));4450 hw->ledctl_mode1 |= ledctl_off << (i << 3);4451 break;4452 default:4453 /* Do nothing */4454 break;4455 }4456 switch (temp) {4457 case ID_LED_DEF1_ON2:4458 case ID_LED_ON1_ON2:4459 case ID_LED_OFF1_ON2:4460 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));4461 hw->ledctl_mode2 |= ledctl_on << (i << 3);4462 break;4463 case ID_LED_DEF1_OFF2:4464 case ID_LED_ON1_OFF2:4465 case ID_LED_OFF1_OFF2:4466 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));4467 hw->ledctl_mode2 |= ledctl_off << (i << 3);4468 break;4469 default:4470 /* Do nothing */4471 break;4472 }4473 }4474 return E1000_SUCCESS;4475}4476 4477/**4478 * e1000_setup_led4479 * @hw: Struct containing variables accessed by shared code4480 *4481 * Prepares SW controlable LED for use and saves the current state of the LED.4482 */4483s32 e1000_setup_led(struct e1000_hw *hw)4484{4485 u32 ledctl;4486 s32 ret_val = E1000_SUCCESS;4487 4488 switch (hw->mac_type) {4489 case e1000_82542_rev2_0:4490 case e1000_82542_rev2_1:4491 case e1000_82543:4492 case e1000_82544:4493 /* No setup necessary */4494 break;4495 case e1000_82541:4496 case e1000_82547:4497 case e1000_82541_rev_2:4498 case e1000_82547_rev_2:4499 /* Turn off PHY Smart Power Down (if enabled) */4500 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,4501 &hw->phy_spd_default);4502 if (ret_val)4503 return ret_val;4504 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,4505 (u16)(hw->phy_spd_default &4506 ~IGP01E1000_GMII_SPD));4507 if (ret_val)4508 return ret_val;4509 fallthrough;4510 default:4511 if (hw->media_type == e1000_media_type_fiber) {4512 ledctl = er32(LEDCTL);4513 /* Save current LEDCTL settings */4514 hw->ledctl_default = ledctl;4515 /* Turn off LED0 */4516 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |4517 E1000_LEDCTL_LED0_BLINK |4518 E1000_LEDCTL_LED0_MODE_MASK);4519 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<4520 E1000_LEDCTL_LED0_MODE_SHIFT);4521 ew32(LEDCTL, ledctl);4522 } else if (hw->media_type == e1000_media_type_copper)4523 ew32(LEDCTL, hw->ledctl_mode1);4524 break;4525 }4526 4527 return E1000_SUCCESS;4528}4529 4530/**4531 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.4532 * @hw: Struct containing variables accessed by shared code4533 */4534s32 e1000_cleanup_led(struct e1000_hw *hw)4535{4536 s32 ret_val = E1000_SUCCESS;4537 4538 switch (hw->mac_type) {4539 case e1000_82542_rev2_0:4540 case e1000_82542_rev2_1:4541 case e1000_82543:4542 case e1000_82544:4543 /* No cleanup necessary */4544 break;4545 case e1000_82541:4546 case e1000_82547:4547 case e1000_82541_rev_2:4548 case e1000_82547_rev_2:4549 /* Turn on PHY Smart Power Down (if previously enabled) */4550 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,4551 hw->phy_spd_default);4552 if (ret_val)4553 return ret_val;4554 fallthrough;4555 default:4556 /* Restore LEDCTL settings */4557 ew32(LEDCTL, hw->ledctl_default);4558 break;4559 }4560 4561 return E1000_SUCCESS;4562}4563 4564/**4565 * e1000_led_on - Turns on the software controllable LED4566 * @hw: Struct containing variables accessed by shared code4567 */4568s32 e1000_led_on(struct e1000_hw *hw)4569{4570 u32 ctrl = er32(CTRL);4571 4572 switch (hw->mac_type) {4573 case e1000_82542_rev2_0:4574 case e1000_82542_rev2_1:4575 case e1000_82543:4576 /* Set SW Defineable Pin 0 to turn on the LED */4577 ctrl |= E1000_CTRL_SWDPIN0;4578 ctrl |= E1000_CTRL_SWDPIO0;4579 break;4580 case e1000_82544:4581 if (hw->media_type == e1000_media_type_fiber) {4582 /* Set SW Defineable Pin 0 to turn on the LED */4583 ctrl |= E1000_CTRL_SWDPIN0;4584 ctrl |= E1000_CTRL_SWDPIO0;4585 } else {4586 /* Clear SW Defineable Pin 0 to turn on the LED */4587 ctrl &= ~E1000_CTRL_SWDPIN0;4588 ctrl |= E1000_CTRL_SWDPIO0;4589 }4590 break;4591 default:4592 if (hw->media_type == e1000_media_type_fiber) {4593 /* Clear SW Defineable Pin 0 to turn on the LED */4594 ctrl &= ~E1000_CTRL_SWDPIN0;4595 ctrl |= E1000_CTRL_SWDPIO0;4596 } else if (hw->media_type == e1000_media_type_copper) {4597 ew32(LEDCTL, hw->ledctl_mode2);4598 return E1000_SUCCESS;4599 }4600 break;4601 }4602 4603 ew32(CTRL, ctrl);4604 4605 return E1000_SUCCESS;4606}4607 4608/**4609 * e1000_led_off - Turns off the software controllable LED4610 * @hw: Struct containing variables accessed by shared code4611 */4612s32 e1000_led_off(struct e1000_hw *hw)4613{4614 u32 ctrl = er32(CTRL);4615 4616 switch (hw->mac_type) {4617 case e1000_82542_rev2_0:4618 case e1000_82542_rev2_1:4619 case e1000_82543:4620 /* Clear SW Defineable Pin 0 to turn off the LED */4621 ctrl &= ~E1000_CTRL_SWDPIN0;4622 ctrl |= E1000_CTRL_SWDPIO0;4623 break;4624 case e1000_82544:4625 if (hw->media_type == e1000_media_type_fiber) {4626 /* Clear SW Defineable Pin 0 to turn off the LED */4627 ctrl &= ~E1000_CTRL_SWDPIN0;4628 ctrl |= E1000_CTRL_SWDPIO0;4629 } else {4630 /* Set SW Defineable Pin 0 to turn off the LED */4631 ctrl |= E1000_CTRL_SWDPIN0;4632 ctrl |= E1000_CTRL_SWDPIO0;4633 }4634 break;4635 default:4636 if (hw->media_type == e1000_media_type_fiber) {4637 /* Set SW Defineable Pin 0 to turn off the LED */4638 ctrl |= E1000_CTRL_SWDPIN0;4639 ctrl |= E1000_CTRL_SWDPIO0;4640 } else if (hw->media_type == e1000_media_type_copper) {4641 ew32(LEDCTL, hw->ledctl_mode1);4642 return E1000_SUCCESS;4643 }4644 break;4645 }4646 4647 ew32(CTRL, ctrl);4648 4649 return E1000_SUCCESS;4650}4651 4652/**4653 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.4654 * @hw: Struct containing variables accessed by shared code4655 */4656static void e1000_clear_hw_cntrs(struct e1000_hw *hw)4657{4658 er32(CRCERRS);4659 er32(SYMERRS);4660 er32(MPC);4661 er32(SCC);4662 er32(ECOL);4663 er32(MCC);4664 er32(LATECOL);4665 er32(COLC);4666 er32(DC);4667 er32(SEC);4668 er32(RLEC);4669 er32(XONRXC);4670 er32(XONTXC);4671 er32(XOFFRXC);4672 er32(XOFFTXC);4673 er32(FCRUC);4674 4675 er32(PRC64);4676 er32(PRC127);4677 er32(PRC255);4678 er32(PRC511);4679 er32(PRC1023);4680 er32(PRC1522);4681 4682 er32(GPRC);4683 er32(BPRC);4684 er32(MPRC);4685 er32(GPTC);4686 er32(GORCL);4687 er32(GORCH);4688 er32(GOTCL);4689 er32(GOTCH);4690 er32(RNBC);4691 er32(RUC);4692 er32(RFC);4693 er32(ROC);4694 er32(RJC);4695 er32(TORL);4696 er32(TORH);4697 er32(TOTL);4698 er32(TOTH);4699 er32(TPR);4700 er32(TPT);4701 4702 er32(PTC64);4703 er32(PTC127);4704 er32(PTC255);4705 er32(PTC511);4706 er32(PTC1023);4707 er32(PTC1522);4708 4709 er32(MPTC);4710 er32(BPTC);4711 4712 if (hw->mac_type < e1000_82543)4713 return;4714 4715 er32(ALGNERRC);4716 er32(RXERRC);4717 er32(TNCRS);4718 er32(CEXTERR);4719 er32(TSCTC);4720 er32(TSCTFC);4721 4722 if (hw->mac_type <= e1000_82544)4723 return;4724 4725 er32(MGTPRC);4726 er32(MGTPDC);4727 er32(MGTPTC);4728}4729 4730/**4731 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.4732 * @hw: Struct containing variables accessed by shared code4733 *4734 * Call this after e1000_init_hw. You may override the IFS defaults by setting4735 * hw->ifs_params_forced to true. However, you must initialize hw->4736 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio4737 * before calling this function.4738 */4739void e1000_reset_adaptive(struct e1000_hw *hw)4740{4741 if (hw->adaptive_ifs) {4742 if (!hw->ifs_params_forced) {4743 hw->current_ifs_val = 0;4744 hw->ifs_min_val = IFS_MIN;4745 hw->ifs_max_val = IFS_MAX;4746 hw->ifs_step_size = IFS_STEP;4747 hw->ifs_ratio = IFS_RATIO;4748 }4749 hw->in_ifs_mode = false;4750 ew32(AIT, 0);4751 } else {4752 e_dbg("Not in Adaptive IFS mode!\n");4753 }4754}4755 4756/**4757 * e1000_update_adaptive - update adaptive IFS4758 * @hw: Struct containing variables accessed by shared code4759 *4760 * Called during the callback/watchdog routine to update IFS value based on4761 * the ratio of transmits to collisions.4762 */4763void e1000_update_adaptive(struct e1000_hw *hw)4764{4765 if (hw->adaptive_ifs) {4766 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {4767 if (hw->tx_packet_delta > MIN_NUM_XMITS) {4768 hw->in_ifs_mode = true;4769 if (hw->current_ifs_val < hw->ifs_max_val) {4770 if (hw->current_ifs_val == 0)4771 hw->current_ifs_val =4772 hw->ifs_min_val;4773 else4774 hw->current_ifs_val +=4775 hw->ifs_step_size;4776 ew32(AIT, hw->current_ifs_val);4777 }4778 }4779 } else {4780 if (hw->in_ifs_mode &&4781 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {4782 hw->current_ifs_val = 0;4783 hw->in_ifs_mode = false;4784 ew32(AIT, 0);4785 }4786 }4787 } else {4788 e_dbg("Not in Adaptive IFS mode!\n");4789 }4790}4791 4792/**4793 * e1000_get_bus_info4794 * @hw: Struct containing variables accessed by shared code4795 *4796 * Gets the current PCI bus type, speed, and width of the hardware4797 */4798void e1000_get_bus_info(struct e1000_hw *hw)4799{4800 u32 status;4801 4802 switch (hw->mac_type) {4803 case e1000_82542_rev2_0:4804 case e1000_82542_rev2_1:4805 hw->bus_type = e1000_bus_type_pci;4806 hw->bus_speed = e1000_bus_speed_unknown;4807 hw->bus_width = e1000_bus_width_unknown;4808 break;4809 default:4810 status = er32(STATUS);4811 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?4812 e1000_bus_type_pcix : e1000_bus_type_pci;4813 4814 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {4815 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?4816 e1000_bus_speed_66 : e1000_bus_speed_120;4817 } else if (hw->bus_type == e1000_bus_type_pci) {4818 hw->bus_speed = (status & E1000_STATUS_PCI66) ?4819 e1000_bus_speed_66 : e1000_bus_speed_33;4820 } else {4821 switch (status & E1000_STATUS_PCIX_SPEED) {4822 case E1000_STATUS_PCIX_SPEED_66:4823 hw->bus_speed = e1000_bus_speed_66;4824 break;4825 case E1000_STATUS_PCIX_SPEED_100:4826 hw->bus_speed = e1000_bus_speed_100;4827 break;4828 case E1000_STATUS_PCIX_SPEED_133:4829 hw->bus_speed = e1000_bus_speed_133;4830 break;4831 default:4832 hw->bus_speed = e1000_bus_speed_reserved;4833 break;4834 }4835 }4836 hw->bus_width = (status & E1000_STATUS_BUS64) ?4837 e1000_bus_width_64 : e1000_bus_width_32;4838 break;4839 }4840}4841 4842/**4843 * e1000_write_reg_io4844 * @hw: Struct containing variables accessed by shared code4845 * @offset: offset to write to4846 * @value: value to write4847 *4848 * Writes a value to one of the devices registers using port I/O (as opposed to4849 * memory mapped I/O). Only 82544 and newer devices support port I/O.4850 */4851static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)4852{4853 unsigned long io_addr = hw->io_base;4854 unsigned long io_data = hw->io_base + 4;4855 4856 e1000_io_write(hw, io_addr, offset);4857 e1000_io_write(hw, io_data, value);4858}4859 4860/**4861 * e1000_get_cable_length - Estimates the cable length.4862 * @hw: Struct containing variables accessed by shared code4863 * @min_length: The estimated minimum length4864 * @max_length: The estimated maximum length4865 *4866 * returns: - E1000_ERR_XXX4867 * E1000_SUCCESS4868 *4869 * This function always returns a ranged length (minimum & maximum).4870 * So for M88 phy's, this function interprets the one value returned from the4871 * register to the minimum and maximum range.4872 * For IGP phy's, the function calculates the range by the AGC registers.4873 */4874static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,4875 u16 *max_length)4876{4877 s32 ret_val;4878 u16 agc_value = 0;4879 u16 i, phy_data;4880 u16 cable_length;4881 4882 *min_length = *max_length = 0;4883 4884 /* Use old method for Phy older than IGP */4885 if (hw->phy_type == e1000_phy_m88) {4886 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,4887 &phy_data);4888 if (ret_val)4889 return ret_val;4890 cable_length = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);4891 4892 /* Convert the enum value to ranged values */4893 switch (cable_length) {4894 case e1000_cable_length_50:4895 *min_length = 0;4896 *max_length = e1000_igp_cable_length_50;4897 break;4898 case e1000_cable_length_50_80:4899 *min_length = e1000_igp_cable_length_50;4900 *max_length = e1000_igp_cable_length_80;4901 break;4902 case e1000_cable_length_80_110:4903 *min_length = e1000_igp_cable_length_80;4904 *max_length = e1000_igp_cable_length_110;4905 break;4906 case e1000_cable_length_110_140:4907 *min_length = e1000_igp_cable_length_110;4908 *max_length = e1000_igp_cable_length_140;4909 break;4910 case e1000_cable_length_140:4911 *min_length = e1000_igp_cable_length_140;4912 *max_length = e1000_igp_cable_length_170;4913 break;4914 default:4915 return -E1000_ERR_PHY;4916 }4917 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */4918 u16 cur_agc_value;4919 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;4920 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {4921 IGP01E1000_PHY_AGC_A,4922 IGP01E1000_PHY_AGC_B,4923 IGP01E1000_PHY_AGC_C,4924 IGP01E1000_PHY_AGC_D4925 };4926 /* Read the AGC registers for all channels */4927 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {4928 ret_val =4929 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);4930 if (ret_val)4931 return ret_val;4932 4933 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;4934 4935 /* Value bound check. */4936 if ((cur_agc_value >=4937 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||4938 (cur_agc_value == 0))4939 return -E1000_ERR_PHY;4940 4941 agc_value += cur_agc_value;4942 4943 /* Update minimal AGC value. */4944 if (min_agc_value > cur_agc_value)4945 min_agc_value = cur_agc_value;4946 }4947 4948 /* Remove the minimal AGC result for length < 50m */4949 if (agc_value <4950 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {4951 agc_value -= min_agc_value;4952 4953 /* Get the average length of the remaining 3 channels */4954 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);4955 } else {4956 /* Get the average length of all the 4 channels. */4957 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;4958 }4959 4960 /* Set the range of the calculated length. */4961 *min_length = ((e1000_igp_cable_length_table[agc_value] -4962 IGP01E1000_AGC_RANGE) > 0) ?4963 (e1000_igp_cable_length_table[agc_value] -4964 IGP01E1000_AGC_RANGE) : 0;4965 *max_length = e1000_igp_cable_length_table[agc_value] +4966 IGP01E1000_AGC_RANGE;4967 }4968 4969 return E1000_SUCCESS;4970}4971 4972/**4973 * e1000_check_polarity - Check the cable polarity4974 * @hw: Struct containing variables accessed by shared code4975 * @polarity: output parameter : 0 - Polarity is not reversed4976 * 1 - Polarity is reversed.4977 *4978 * returns: - E1000_ERR_XXX4979 * E1000_SUCCESS4980 *4981 * For phy's older than IGP, this function simply reads the polarity bit in the4982 * Phy Status register. For IGP phy's, this bit is valid only if link speed is4983 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will4984 * return 0. If the link speed is 1000 Mbps the polarity status is in the4985 * IGP01E1000_PHY_PCS_INIT_REG.4986 */4987static s32 e1000_check_polarity(struct e1000_hw *hw,4988 e1000_rev_polarity *polarity)4989{4990 s32 ret_val;4991 u16 phy_data;4992 4993 if (hw->phy_type == e1000_phy_m88) {4994 /* return the Polarity bit in the Status register. */4995 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,4996 &phy_data);4997 if (ret_val)4998 return ret_val;4999 *polarity = FIELD_GET(M88E1000_PSSR_REV_POLARITY, phy_data) ?5000 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;5001 5002 } else if (hw->phy_type == e1000_phy_igp) {5003 /* Read the Status register to check the speed */5004 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,5005 &phy_data);5006 if (ret_val)5007 return ret_val;5008 5009 /* If speed is 1000 Mbps, must read the5010 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status5011 */5012 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==5013 IGP01E1000_PSSR_SPEED_1000MBPS) {5014 /* Read the GIG initialization PCS register (0x00B4) */5015 ret_val =5016 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,5017 &phy_data);5018 if (ret_val)5019 return ret_val;5020 5021 /* Check the polarity bits */5022 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?5023 e1000_rev_polarity_reversed :5024 e1000_rev_polarity_normal;5025 } else {5026 /* For 10 Mbps, read the polarity bit in the status5027 * register. (for 100 Mbps this bit is always 0)5028 */5029 *polarity =5030 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?5031 e1000_rev_polarity_reversed :5032 e1000_rev_polarity_normal;5033 }5034 }5035 return E1000_SUCCESS;5036}5037 5038/**5039 * e1000_check_downshift - Check if Downshift occurred5040 * @hw: Struct containing variables accessed by shared code5041 *5042 * returns: - E1000_ERR_XXX5043 * E1000_SUCCESS5044 *5045 * For phy's older than IGP, this function reads the Downshift bit in the Phy5046 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the5047 * Link Health register. In IGP this bit is latched high, so the driver must5048 * read it immediately after link is established.5049 */5050static s32 e1000_check_downshift(struct e1000_hw *hw)5051{5052 s32 ret_val;5053 u16 phy_data;5054 5055 if (hw->phy_type == e1000_phy_igp) {5056 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,5057 &phy_data);5058 if (ret_val)5059 return ret_val;5060 5061 hw->speed_downgraded =5062 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;5063 } else if (hw->phy_type == e1000_phy_m88) {5064 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,5065 &phy_data);5066 if (ret_val)5067 return ret_val;5068 5069 hw->speed_downgraded = FIELD_GET(M88E1000_PSSR_DOWNSHIFT,5070 phy_data);5071 }5072 5073 return E1000_SUCCESS;5074}5075 5076static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {5077 IGP01E1000_PHY_AGC_PARAM_A,5078 IGP01E1000_PHY_AGC_PARAM_B,5079 IGP01E1000_PHY_AGC_PARAM_C,5080 IGP01E1000_PHY_AGC_PARAM_D5081};5082 5083static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)5084{5085 u16 min_length, max_length;5086 u16 phy_data, i;5087 s32 ret_val;5088 5089 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);5090 if (ret_val)5091 return ret_val;5092 5093 if (hw->dsp_config_state != e1000_dsp_config_enabled)5094 return 0;5095 5096 if (min_length >= e1000_igp_cable_length_50) {5097 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {5098 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],5099 &phy_data);5100 if (ret_val)5101 return ret_val;5102 5103 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;5104 5105 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],5106 phy_data);5107 if (ret_val)5108 return ret_val;5109 }5110 hw->dsp_config_state = e1000_dsp_config_activated;5111 } else {5112 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;5113 u32 idle_errs = 0;5114 5115 /* clear previous idle error counts */5116 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);5117 if (ret_val)5118 return ret_val;5119 5120 for (i = 0; i < ffe_idle_err_timeout; i++) {5121 udelay(1000);5122 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,5123 &phy_data);5124 if (ret_val)5125 return ret_val;5126 5127 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);5128 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {5129 hw->ffe_config_state = e1000_ffe_config_active;5130 5131 ret_val = e1000_write_phy_reg(hw,5132 IGP01E1000_PHY_DSP_FFE,5133 IGP01E1000_PHY_DSP_FFE_CM_CP);5134 if (ret_val)5135 return ret_val;5136 break;5137 }5138 5139 if (idle_errs)5140 ffe_idle_err_timeout =5141 FFE_IDLE_ERR_COUNT_TIMEOUT_100;5142 }5143 }5144 5145 return 0;5146}5147 5148/**5149 * e1000_config_dsp_after_link_change5150 * @hw: Struct containing variables accessed by shared code5151 * @link_up: was link up at the time this was called5152 *5153 * returns: - E1000_ERR_PHY if fail to read/write the PHY5154 * E1000_SUCCESS at any other case.5155 *5156 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a5157 * gigabit link is achieved to improve link quality.5158 */5159 5160static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)5161{5162 s32 ret_val;5163 u16 phy_data, phy_saved_data, speed, duplex, i;5164 5165 if (hw->phy_type != e1000_phy_igp)5166 return E1000_SUCCESS;5167 5168 if (link_up) {5169 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);5170 if (ret_val) {5171 e_dbg("Error getting link speed and duplex\n");5172 return ret_val;5173 }5174 5175 if (speed == SPEED_1000) {5176 ret_val = e1000_1000Mb_check_cable_length(hw);5177 if (ret_val)5178 return ret_val;5179 }5180 } else {5181 if (hw->dsp_config_state == e1000_dsp_config_activated) {5182 /* Save off the current value of register 0x2F5B to be5183 * restored at the end of the routines.5184 */5185 ret_val =5186 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);5187 5188 if (ret_val)5189 return ret_val;5190 5191 /* Disable the PHY transmitter */5192 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);5193 5194 if (ret_val)5195 return ret_val;5196 5197 msleep(20);5198 5199 ret_val = e1000_write_phy_reg(hw, 0x0000,5200 IGP01E1000_IEEE_FORCE_GIGA);5201 if (ret_val)5202 return ret_val;5203 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {5204 ret_val =5205 e1000_read_phy_reg(hw, dsp_reg_array[i],5206 &phy_data);5207 if (ret_val)5208 return ret_val;5209 5210 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;5211 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;5212 5213 ret_val =5214 e1000_write_phy_reg(hw, dsp_reg_array[i],5215 phy_data);5216 if (ret_val)5217 return ret_val;5218 }5219 5220 ret_val = e1000_write_phy_reg(hw, 0x0000,5221 IGP01E1000_IEEE_RESTART_AUTONEG);5222 if (ret_val)5223 return ret_val;5224 5225 msleep(20);5226 5227 /* Now enable the transmitter */5228 ret_val =5229 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);5230 5231 if (ret_val)5232 return ret_val;5233 5234 hw->dsp_config_state = e1000_dsp_config_enabled;5235 }5236 5237 if (hw->ffe_config_state == e1000_ffe_config_active) {5238 /* Save off the current value of register 0x2F5B to be5239 * restored at the end of the routines.5240 */5241 ret_val =5242 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);5243 5244 if (ret_val)5245 return ret_val;5246 5247 /* Disable the PHY transmitter */5248 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);5249 5250 if (ret_val)5251 return ret_val;5252 5253 msleep(20);5254 5255 ret_val = e1000_write_phy_reg(hw, 0x0000,5256 IGP01E1000_IEEE_FORCE_GIGA);5257 if (ret_val)5258 return ret_val;5259 ret_val =5260 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,5261 IGP01E1000_PHY_DSP_FFE_DEFAULT);5262 if (ret_val)5263 return ret_val;5264 5265 ret_val = e1000_write_phy_reg(hw, 0x0000,5266 IGP01E1000_IEEE_RESTART_AUTONEG);5267 if (ret_val)5268 return ret_val;5269 5270 msleep(20);5271 5272 /* Now enable the transmitter */5273 ret_val =5274 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);5275 5276 if (ret_val)5277 return ret_val;5278 5279 hw->ffe_config_state = e1000_ffe_config_enabled;5280 }5281 }5282 return E1000_SUCCESS;5283}5284 5285/**5286 * e1000_set_phy_mode - Set PHY to class A mode5287 * @hw: Struct containing variables accessed by shared code5288 *5289 * Assumes the following operations will follow to enable the new class mode.5290 * 1. Do a PHY soft reset5291 * 2. Restart auto-negotiation or force link.5292 */5293static s32 e1000_set_phy_mode(struct e1000_hw *hw)5294{5295 s32 ret_val;5296 u16 eeprom_data;5297 5298 if ((hw->mac_type == e1000_82545_rev_3) &&5299 (hw->media_type == e1000_media_type_copper)) {5300 ret_val =5301 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,5302 &eeprom_data);5303 if (ret_val)5304 return ret_val;5305 5306 if ((eeprom_data != EEPROM_RESERVED_WORD) &&5307 (eeprom_data & EEPROM_PHY_CLASS_A)) {5308 ret_val =5309 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,5310 0x000B);5311 if (ret_val)5312 return ret_val;5313 ret_val =5314 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,5315 0x8104);5316 if (ret_val)5317 return ret_val;5318 5319 hw->phy_reset_disable = false;5320 }5321 }5322 5323 return E1000_SUCCESS;5324}5325 5326/**5327 * e1000_set_d3_lplu_state - set d3 link power state5328 * @hw: Struct containing variables accessed by shared code5329 * @active: true to enable lplu false to disable lplu.5330 *5331 * This function sets the lplu state according to the active flag. When5332 * activating lplu this function also disables smart speed and vise versa.5333 * lplu will not be activated unless the device autonegotiation advertisement5334 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.5335 *5336 * returns: - E1000_ERR_PHY if fail to read/write the PHY5337 * E1000_SUCCESS at any other case.5338 */5339static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)5340{5341 s32 ret_val;5342 u16 phy_data;5343 5344 if (hw->phy_type != e1000_phy_igp)5345 return E1000_SUCCESS;5346 5347 /* During driver activity LPLU should not be used or it will attain link5348 * from the lowest speeds starting from 10Mbps. The capability is used5349 * for Dx transitions and states5350 */5351 if (hw->mac_type == e1000_82541_rev_2 ||5352 hw->mac_type == e1000_82547_rev_2) {5353 ret_val =5354 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);5355 if (ret_val)5356 return ret_val;5357 }5358 5359 if (!active) {5360 if (hw->mac_type == e1000_82541_rev_2 ||5361 hw->mac_type == e1000_82547_rev_2) {5362 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;5363 ret_val =5364 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,5365 phy_data);5366 if (ret_val)5367 return ret_val;5368 }5369 5370 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used5371 * during Dx states where the power conservation is most5372 * important. During driver activity we should enable5373 * SmartSpeed, so performance is maintained.5374 */5375 if (hw->smart_speed == e1000_smart_speed_on) {5376 ret_val =5377 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,5378 &phy_data);5379 if (ret_val)5380 return ret_val;5381 5382 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;5383 ret_val =5384 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,5385 phy_data);5386 if (ret_val)5387 return ret_val;5388 } else if (hw->smart_speed == e1000_smart_speed_off) {5389 ret_val =5390 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,5391 &phy_data);5392 if (ret_val)5393 return ret_val;5394 5395 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;5396 ret_val =5397 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,5398 phy_data);5399 if (ret_val)5400 return ret_val;5401 }5402 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||5403 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||5404 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {5405 if (hw->mac_type == e1000_82541_rev_2 ||5406 hw->mac_type == e1000_82547_rev_2) {5407 phy_data |= IGP01E1000_GMII_FLEX_SPD;5408 ret_val =5409 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,5410 phy_data);5411 if (ret_val)5412 return ret_val;5413 }5414 5415 /* When LPLU is enabled we should disable SmartSpeed */5416 ret_val =5417 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,5418 &phy_data);5419 if (ret_val)5420 return ret_val;5421 5422 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;5423 ret_val =5424 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,5425 phy_data);5426 if (ret_val)5427 return ret_val;5428 }5429 return E1000_SUCCESS;5430}5431 5432/**5433 * e1000_set_vco_speed5434 * @hw: Struct containing variables accessed by shared code5435 *5436 * Change VCO speed register to improve Bit Error Rate performance of SERDES.5437 */5438static s32 e1000_set_vco_speed(struct e1000_hw *hw)5439{5440 s32 ret_val;5441 u16 default_page = 0;5442 u16 phy_data;5443 5444 switch (hw->mac_type) {5445 case e1000_82545_rev_3:5446 case e1000_82546_rev_3:5447 break;5448 default:5449 return E1000_SUCCESS;5450 }5451 5452 /* Set PHY register 30, page 5, bit 8 to 0 */5453 5454 ret_val =5455 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);5456 if (ret_val)5457 return ret_val;5458 5459 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);5460 if (ret_val)5461 return ret_val;5462 5463 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);5464 if (ret_val)5465 return ret_val;5466 5467 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;5468 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);5469 if (ret_val)5470 return ret_val;5471 5472 /* Set PHY register 30, page 4, bit 11 to 1 */5473 5474 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);5475 if (ret_val)5476 return ret_val;5477 5478 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);5479 if (ret_val)5480 return ret_val;5481 5482 phy_data |= M88E1000_PHY_VCO_REG_BIT11;5483 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);5484 if (ret_val)5485 return ret_val;5486 5487 ret_val =5488 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);5489 if (ret_val)5490 return ret_val;5491 5492 return E1000_SUCCESS;5493}5494 5495/**5496 * e1000_enable_mng_pass_thru - check for bmc pass through5497 * @hw: Struct containing variables accessed by shared code5498 *5499 * Verifies the hardware needs to allow ARPs to be processed by the host5500 * returns: - true/false5501 */5502u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)5503{5504 u32 manc;5505 5506 if (hw->asf_firmware_present) {5507 manc = er32(MANC);5508 5509 if (!(manc & E1000_MANC_RCV_TCO_EN) ||5510 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))5511 return false;5512 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))5513 return true;5514 }5515 return false;5516}5517 5518static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)5519{5520 s32 ret_val;5521 u16 mii_status_reg;5522 u16 i;5523 5524 /* Polarity reversal workaround for forced 10F/10H links. */5525 5526 /* Disable the transmitter on the PHY */5527 5528 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);5529 if (ret_val)5530 return ret_val;5531 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);5532 if (ret_val)5533 return ret_val;5534 5535 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);5536 if (ret_val)5537 return ret_val;5538 5539 /* This loop will early-out if the NO link condition has been met. */5540 for (i = PHY_FORCE_TIME; i > 0; i--) {5541 /* Read the MII Status Register and wait for Link Status bit5542 * to be clear.5543 */5544 5545 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);5546 if (ret_val)5547 return ret_val;5548 5549 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);5550 if (ret_val)5551 return ret_val;5552 5553 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)5554 break;5555 msleep(100);5556 }5557 5558 /* Recommended delay time after link has been lost */5559 msleep(1000);5560 5561 /* Now we will re-enable th transmitter on the PHY */5562 5563 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);5564 if (ret_val)5565 return ret_val;5566 msleep(50);5567 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);5568 if (ret_val)5569 return ret_val;5570 msleep(50);5571 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);5572 if (ret_val)5573 return ret_val;5574 msleep(50);5575 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);5576 if (ret_val)5577 return ret_val;5578 5579 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);5580 if (ret_val)5581 return ret_val;5582 5583 /* This loop will early-out if the link condition has been met. */5584 for (i = PHY_FORCE_TIME; i > 0; i--) {5585 /* Read the MII Status Register and wait for Link Status bit5586 * to be set.5587 */5588 5589 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);5590 if (ret_val)5591 return ret_val;5592 5593 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);5594 if (ret_val)5595 return ret_val;5596 5597 if (mii_status_reg & MII_SR_LINK_STATUS)5598 break;5599 msleep(100);5600 }5601 return E1000_SUCCESS;5602}5603 5604/**5605 * e1000_get_auto_rd_done5606 * @hw: Struct containing variables accessed by shared code5607 *5608 * Check for EEPROM Auto Read bit done.5609 * returns: - E1000_ERR_RESET if fail to reset MAC5610 * E1000_SUCCESS at any other case.5611 */5612static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)5613{5614 msleep(5);5615 return E1000_SUCCESS;5616}5617 5618/**5619 * e1000_get_phy_cfg_done5620 * @hw: Struct containing variables accessed by shared code5621 *5622 * Checks if the PHY configuration is done5623 * returns: - E1000_ERR_RESET if fail to reset MAC5624 * E1000_SUCCESS at any other case.5625 */5626static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)5627{5628 msleep(10);5629 return E1000_SUCCESS;5630}5631