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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 1999 - 2018 Intel Corporation. */3 4#ifndef _E1000E_80003ES2LAN_H_5#define _E1000E_80003ES2LAN_H_6 7#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x008#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x029#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x1010#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F11 12#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x000813#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x080014#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x001015 16#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x000417#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x000018#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x200019 20#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C21#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x000422 23#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */24#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x0001000025 26#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x827#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x928 29/* GG82563 PHY Specific Status Register (Page 0, Register 16 */30#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */31#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x006032#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */33#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */34#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */35 36/* PHY Specific Control Register 2 (Page 0, Register 26) */37#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */38 39/* MAC Specific Control Register (Page 2, Register 21) */40/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */41#define GG82563_MSCR_TX_CLK_MASK 0x000742#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x000443#define GG82563_MSCR_TX_CLK_100MBPS_25 0x000544#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x000745 46#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */47 48/* DSP Distance Register (Page 5, Register 26)49 * 0 = <50M50 * 1 = 50-80M51 * 2 = 80-100M52 * 3 = 110-140M53 * 4 = >140M54 */55#define GG82563_DSPD_CABLE_LENGTH 0x000756 57/* Kumeran Mode Control Register (Page 193, Register 16) */58#define GG82563_KMCR_PASS_FALSE_CARRIER 0x080059 60/* Max number of times Kumeran read/write should be validated */61#define GG82563_MAX_KMRN_RETRY 0x562 63/* Power Management Control Register (Page 193, Register 20) */64/* 1=Enable SERDES Electrical Idle */65#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x000166 67/* In-Band Control Register (Page 194, Register 18) */68#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */69 70#endif71