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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 1999 - 2018 Intel Corporation. */3 4#ifndef _E1000_DEFINES_H_5#define _E1000_DEFINES_H_6 7/* Number of Transmit and Receive Descriptors must be a multiple of 8 */8#define REQ_TX_DESCRIPTOR_MULTIPLE 89#define REQ_RX_DESCRIPTOR_MULTIPLE 810 11/* Definitions for power management and wakeup registers */12/* Wake Up Control */13#define E1000_WUC_APME 0x00000001 /* APM Enable */14#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */15#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */16#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */17#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */18 19/* Wake Up Filter Control */20#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */21#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */22#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */23#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */24#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */25#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */26 27/* Wake Up Status */28#define E1000_WUS_LNKC E1000_WUFC_LNKC29#define E1000_WUS_MAG E1000_WUFC_MAG30#define E1000_WUS_EX E1000_WUFC_EX31#define E1000_WUS_MC E1000_WUFC_MC32#define E1000_WUS_BC E1000_WUFC_BC33 34/* Extended Device Control */35#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */36#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */37#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */38#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */39#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */40#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */41#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */42#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C0000043#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C0000044#define E1000_CTRL_EXT_EIAME 0x0100000045#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */46#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */47#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */48#define E1000_CTRL_EXT_LSECCK 0x0000100049#define E1000_CTRL_EXT_PHYPDEN 0x0010000050 51/* Receive Descriptor bit definitions */52#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */53#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */54#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */55#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */56#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */57#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */58#define E1000_RXD_ERR_CE 0x01 /* CRC Error */59#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */60#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */61#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */62#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */63#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */64#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */65#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */66 67#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */68#define E1000_RXDEXT_STATERR_CE 0x0100000069#define E1000_RXDEXT_STATERR_SE 0x0200000070#define E1000_RXDEXT_STATERR_SEQ 0x0400000071#define E1000_RXDEXT_STATERR_CXE 0x1000000072#define E1000_RXDEXT_STATERR_RXE 0x8000000073 74/* mask to determine if packets should be dropped due to frame errors */75#define E1000_RXD_ERR_FRAME_ERR_MASK ( \76 E1000_RXD_ERR_CE | \77 E1000_RXD_ERR_SE | \78 E1000_RXD_ERR_SEQ | \79 E1000_RXD_ERR_CXE | \80 E1000_RXD_ERR_RXE)81 82/* Same mask, but for extended and packet split descriptors */83#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \84 E1000_RXDEXT_STATERR_CE | \85 E1000_RXDEXT_STATERR_SE | \86 E1000_RXDEXT_STATERR_SEQ | \87 E1000_RXDEXT_STATERR_CXE | \88 E1000_RXDEXT_STATERR_RXE)89 90#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF000091#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x0001000092#define E1000_MRQC_RSS_FIELD_IPV4 0x0002000093#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x0004000094#define E1000_MRQC_RSS_FIELD_IPV6 0x0010000095#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x0020000096 97#define E1000_RXDPS_HDRSTAT_HDRSP 0x0000800098 99/* Management Control */100#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */101#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */102#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */103#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */104#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */105/* Enable MAC address filtering */106#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000107/* Enable MNG packets to host memory */108#define E1000_MANC_EN_MNG2HOST 0x00200000109 110#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */111#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */112#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */113#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */114 115/* Receive Control */116#define E1000_RCTL_EN 0x00000002 /* enable */117#define E1000_RCTL_SBP 0x00000004 /* store bad packet */118#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */119#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */120#define E1000_RCTL_LPE 0x00000020 /* long packet enable */121#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */122#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */123#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */124#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */125#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */126#define E1000_RCTL_RDMTS_HEX 0x00010000127#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */128#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */129#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */130/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */131#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */132#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */133#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */134#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */135/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */136#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */137#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */138#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */139#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */140#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */141#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */142#define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */143#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */144#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */145#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */146 147/* Use byte values for the following shift parameters148 * Usage:149 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &150 * E1000_PSRCTL_BSIZE0_MASK) |151 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &152 * E1000_PSRCTL_BSIZE1_MASK) |153 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &154 * E1000_PSRCTL_BSIZE2_MASK) |155 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;156 * E1000_PSRCTL_BSIZE3_MASK))157 * where value0 = [128..16256], default=256158 * value1 = [1024..64512], default=4096159 * value2 = [0..64512], default=4096160 * value3 = [0..64512], default=0161 */162 163#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F164#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00165#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000166#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000167 168#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */169#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */170#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */171#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */172 173/* SWFW_SYNC Definitions */174#define E1000_SWFW_EEP_SM 0x1175#define E1000_SWFW_PHY0_SM 0x2176#define E1000_SWFW_PHY1_SM 0x4177#define E1000_SWFW_CSR_SM 0x8178 179/* Device Control */180#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */181#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */182#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */183#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */184#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */185#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */186#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */187#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */188#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */189#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */190#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */191#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */192#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */193#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */194#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */195#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */196#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */197#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */198#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */199#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */200#define E1000_CTRL_RST 0x04000000 /* Global reset */201#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */202#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */203#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */204#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */205 206#define E1000_PCS_LCTL_FORCE_FCTRL 0x80207 208#define E1000_PCS_LSTS_AN_COMPLETE 0x10000209 210/* Device Status */211#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */212#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */213#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */214#define E1000_STATUS_FUNC_SHIFT 2215#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */216#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */217#define E1000_STATUS_SPEED_MASK 0x000000C0218#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */219#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */220#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */221#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */222#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */223#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master Req status */224 225/* PCIm function state */226#define E1000_STATUS_PCIM_STATE 0x40000000227 228#define HALF_DUPLEX 1229#define FULL_DUPLEX 2230 231#define ADVERTISE_10_HALF 0x0001232#define ADVERTISE_10_FULL 0x0002233#define ADVERTISE_100_HALF 0x0004234#define ADVERTISE_100_FULL 0x0008235#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */236#define ADVERTISE_1000_FULL 0x0020237 238/* 1000/H is not supported, nor spec-compliant. */239#define E1000_ALL_SPEED_DUPLEX ( \240 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \241 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)242#define E1000_ALL_NOT_GIG ( \243 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \244 ADVERTISE_100_FULL)245#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)246#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)247#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)248 249#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX250 251/* LED Control */252#define E1000_PHY_LED0_MODE_MASK 0x00000007253#define E1000_PHY_LED0_IVRT 0x00000008254#define E1000_PHY_LED0_MASK 0x0000001F255 256#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F257#define E1000_LEDCTL_LED0_MODE_SHIFT 0258#define E1000_LEDCTL_LED0_IVRT 0x00000040259#define E1000_LEDCTL_LED0_BLINK 0x00000080260 261#define E1000_LEDCTL_MODE_LINK_UP 0x2262#define E1000_LEDCTL_MODE_LED_ON 0xE263#define E1000_LEDCTL_MODE_LED_OFF 0xF264 265/* Transmit Descriptor bit definitions */266#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */267#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */268#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */269#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */270#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */271#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */272#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */273#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */274#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */275#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */276#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */277#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */278#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */279#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */280#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */281#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */282#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */283#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */284#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */285#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */286 287/* Transmit Control */288#define E1000_TCTL_EN 0x00000002 /* enable Tx */289#define E1000_TCTL_PSP 0x00000008 /* pad short packets */290#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */291#define E1000_TCTL_COLD 0x003ff000 /* collision distance */292#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */293#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */294 295/* SerDes Control */296#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400297#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410298 299/* Receive Checksum Control */300#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */301#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */302#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */303 304/* Header split receive */305#define E1000_RFCTL_NFSW_DIS 0x00000040306#define E1000_RFCTL_NFSR_DIS 0x00000080307#define E1000_RFCTL_ACK_DIS 0x00001000308#define E1000_RFCTL_EXTEN 0x00008000309#define E1000_RFCTL_IPV6_EX_DIS 0x00010000310#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000311 312/* Collision related configuration parameters */313#define E1000_COLLISION_THRESHOLD 15314#define E1000_CT_SHIFT 4315#define E1000_COLLISION_DISTANCE 63316#define E1000_COLD_SHIFT 12317 318/* Default values for the transmit IPG register */319#define DEFAULT_82543_TIPG_IPGT_COPPER 8320 321#define E1000_TIPG_IPGT_MASK 0x000003FF322 323#define DEFAULT_82543_TIPG_IPGR1 8324#define E1000_TIPG_IPGR1_SHIFT 10325 326#define DEFAULT_82543_TIPG_IPGR2 6327#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7328#define E1000_TIPG_IPGR2_SHIFT 20329 330#define MAX_JUMBO_FRAME_SIZE 0x3F00331#define E1000_TX_PTR_GAP 0x1F332 333/* Extended Configuration Control and Size */334#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020335#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001336#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008337#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020338#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080339#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000340#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16341#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000342#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16343 344#define E1000_PHY_CTRL_D0A_LPLU 0x00000002345#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004346#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008347#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040348 349#define E1000_KABGTXD_BGSQLBIAS 0x00050000350 351/* Low Power IDLE Control */352#define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */353 354/* PBA constants */355#define E1000_PBA_8K 0x0008 /* 8KB */356#define E1000_PBA_16K 0x0010 /* 16KB */357 358#define E1000_PBA_RXA_MASK 0xFFFF359 360#define E1000_PBS_16K E1000_PBA_16K361 362/* Uncorrectable/correctable ECC Error counts and enable bits */363#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF364#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00365#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8366#define E1000_PBECCSTS_ECC_ENABLE 0x00010000367 368#define IFS_MAX 80369#define IFS_MIN 40370#define IFS_RATIO 4371#define IFS_STEP 10372#define MIN_NUM_XMITS 1000373 374/* SW Semaphore Register */375#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */376#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */377#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */378 379#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */380 381/* Interrupt Cause Read */382#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */383#define E1000_ICR_LSC 0x00000004 /* Link Status Change */384#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */385#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */386#define E1000_ICR_RXO 0x00000040 /* Receiver Overrun */387#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */388#define E1000_ICR_MDAC 0x00000200 /* MDIO Access Complete */389#define E1000_ICR_SRPD 0x00010000 /* Small Receive Packet Detected */390#define E1000_ICR_ACK 0x00020000 /* Receive ACK Frame Detected */391#define E1000_ICR_MNG 0x00040000 /* Manageability Event Detected */392#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */393/* If this bit asserted, the driver should claim the interrupt */394#define E1000_ICR_INT_ASSERTED 0x80000000395#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */396#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */397#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */398#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */399#define E1000_ICR_OTHER 0x01000000 /* Other Interrupt */400 401/* PBA ECC Register */402#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */403#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */404#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */405#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */406#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */407 408/* This defines the bits that are set in the Interrupt Mask409 * Set/Read Register. Each bit is documented below:410 * o RXT0 = Receiver Timer Interrupt (ring 0)411 * o TXDW = Transmit Descriptor Written Back412 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)413 * o RXSEQ = Receive Sequence Error414 * o LSC = Link Status Change415 */416#define IMS_ENABLE_MASK ( \417 E1000_IMS_RXT0 | \418 E1000_IMS_TXDW | \419 E1000_IMS_RXDMT0 | \420 E1000_IMS_RXSEQ | \421 E1000_IMS_LSC)422 423/* These are all of the events related to the OTHER interrupt.424 */425#define IMS_OTHER_MASK ( \426 E1000_IMS_LSC | \427 E1000_IMS_RXO | \428 E1000_IMS_MDAC | \429 E1000_IMS_SRPD | \430 E1000_IMS_ACK | \431 E1000_IMS_MNG)432 433/* Interrupt Mask Set */434#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */435#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */436#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */437#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */438#define E1000_IMS_RXO E1000_ICR_RXO /* Receiver Overrun */439#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */440#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO Access Complete */441#define E1000_IMS_SRPD E1000_ICR_SRPD /* Small Receive Packet */442#define E1000_IMS_ACK E1000_ICR_ACK /* Receive ACK Frame Detected */443#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability Event */444#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */445#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */446#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */447#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */448#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */449#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupt */450 451/* Interrupt Cause Set */452#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */453#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */454#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */455#define E1000_ICS_OTHER E1000_ICR_OTHER /* Other Interrupt */456 457/* Transmit Descriptor Control */458#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */459#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */460#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */461#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */462#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */463#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */464/* Enable the counting of desc. still to be processed. */465#define E1000_TXDCTL_COUNT_DESC 0x00400000466 467/* Flow Control Constants */468#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001469#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100470#define FLOW_CONTROL_TYPE 0x8808471 472/* 802.1q VLAN Packet Size */473#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */474 475/* Receive Address476 * Number of high/low register pairs in the RAR. The RAR (Receive Address477 * Registers) holds the directed and multicast addresses that we monitor.478 * Technically, we have 16 spots. However, we reserve one of these spots479 * (RAR[15]) for our directed address used by controllers with480 * manageability enabled, allowing us room for 15 multicast addresses.481 */482#define E1000_RAR_ENTRIES 15483#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */484#define E1000_RAL_MAC_ADDR_LEN 4485#define E1000_RAH_MAC_ADDR_LEN 2486 487/* Error Codes */488#define E1000_ERR_NVM 1489#define E1000_ERR_PHY 2490#define E1000_ERR_CONFIG 3491#define E1000_ERR_PARAM 4492#define E1000_ERR_MAC_INIT 5493#define E1000_ERR_PHY_TYPE 6494#define E1000_ERR_RESET 9495#define E1000_ERR_MASTER_REQUESTS_PENDING 10496#define E1000_ERR_HOST_INTERFACE_COMMAND 11497#define E1000_BLK_PHY_RESET 12498#define E1000_ERR_SWFW_SYNC 13499#define E1000_NOT_IMPLEMENTED 14500#define E1000_ERR_INVALID_ARGUMENT 16501#define E1000_ERR_NO_SPACE 17502#define E1000_ERR_NVM_PBA_SECTION 18503 504/* Loop limit on how long we wait for auto-negotiation to complete */505#define FIBER_LINK_UP_LIMIT 50506#define COPPER_LINK_UP_LIMIT 10507#define PHY_AUTO_NEG_LIMIT 45508#define PHY_FORCE_LIMIT 20509/* Number of 100 microseconds we wait for PCI Express master disable */510#define MASTER_DISABLE_TIMEOUT 800511/* Number of milliseconds we wait for PHY configuration done after MAC reset */512#define PHY_CFG_TIMEOUT 100513/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */514#define MDIO_OWNERSHIP_TIMEOUT 10515/* Number of milliseconds for NVM auto read done after MAC reset. */516#define AUTO_READ_DONE_TIMEOUT 10517 518/* Flow Control */519#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */520#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */521#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */522 523/* Transmit Configuration Word */524#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */525#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */526#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */527#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */528#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */529 530/* Receive Configuration Word */531#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */532#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */533#define E1000_RXCW_C 0x20000000 /* Receive config */534#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */535 536/* HH Time Sync */537#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */538#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */539#define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */540 541#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */542#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */543 544#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */545#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */546#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00547#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02548#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04549#define E1000_TSYNCRXCTL_TYPE_ALL 0x08550#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A551#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */552#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */553 554#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000555#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000556 557#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000558#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000559 560#define E1000_TIMINCA_INCPERIOD_SHIFT 24561#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF562 563/* PCI Express Control */564#define E1000_GCR_RXD_NO_SNOOP 0x00000001565#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002566#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004567#define E1000_GCR_TXD_NO_SNOOP 0x00000008568#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010569#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020570 571#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \572 E1000_GCR_RXDSCW_NO_SNOOP | \573 E1000_GCR_RXDSCR_NO_SNOOP | \574 E1000_GCR_TXD_NO_SNOOP | \575 E1000_GCR_TXDSCW_NO_SNOOP | \576 E1000_GCR_TXDSCR_NO_SNOOP)577 578/* NVM Control */579#define E1000_EECD_SK 0x00000001 /* NVM Clock */580#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */581#define E1000_EECD_DI 0x00000004 /* NVM Data In */582#define E1000_EECD_DO 0x00000008 /* NVM Data Out */583#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */584#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */585#define E1000_EECD_PRES 0x00000100 /* NVM Present */586#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */587/* NVM Addressing bits based on type (0-small, 1-large) */588#define E1000_EECD_ADDR_BITS 0x00000400589#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */590#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */591#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */592#define E1000_EECD_SIZE_EX_SHIFT 11593#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */594#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */595#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */596#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)597 598#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM r/w regs */599#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */600#define E1000_NVM_RW_REG_START 1 /* Start operation */601#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */602#define E1000_NVM_POLL_WRITE 1 /* Flag for polling write complete */603#define E1000_NVM_POLL_READ 0 /* Flag for polling read complete */604#define E1000_FLASH_UPDATES 2000605 606/* NVM Word Offsets */607#define NVM_COMPAT 0x0003608#define NVM_ID_LED_SETTINGS 0x0004609#define NVM_FUTURE_INIT_WORD1 0x0019610#define NVM_COMPAT_VALID_CSUM 0x0001611#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040612 613#define NVM_INIT_CONTROL2_REG 0x000F614#define NVM_INIT_CONTROL3_PORT_B 0x0014615#define NVM_INIT_3GIO_3 0x001A616#define NVM_INIT_CONTROL3_PORT_A 0x0024617#define NVM_CFG 0x0012618#define NVM_ALT_MAC_ADDR_PTR 0x0037619#define NVM_CHECKSUM_REG 0x003F620 621#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */622#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */623 624/* Mask bits for fields in Word 0x0f of the NVM */625#define NVM_WORD0F_PAUSE_MASK 0x3000626#define NVM_WORD0F_PAUSE 0x1000627#define NVM_WORD0F_ASM_DIR 0x2000628 629/* Mask bits for fields in Word 0x1a of the NVM */630#define NVM_WORD1A_ASPM_MASK 0x000C631 632/* Mask bits for fields in Word 0x03 of the EEPROM */633#define NVM_COMPAT_LOM 0x0800634 635/* length of string needed to store PBA number */636#define E1000_PBANUM_LENGTH 11637 638/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */639#define NVM_SUM 0xBABA640 641/* PBA (printed board assembly) number words */642#define NVM_PBA_OFFSET_0 8643#define NVM_PBA_OFFSET_1 9644#define NVM_PBA_PTR_GUARD 0xFAFA645#define NVM_WORD_SIZE_BASE_SHIFT 6646 647/* NVM Commands - SPI */648#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */649#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */650#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */651#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */652#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */653#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */654 655/* SPI NVM Status Register */656#define NVM_STATUS_RDY_SPI 0x01657 658/* Word definitions for ID LED Settings */659#define ID_LED_RESERVED_0000 0x0000660#define ID_LED_RESERVED_FFFF 0xFFFF661#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \662 (ID_LED_OFF1_OFF2 << 8) | \663 (ID_LED_DEF1_DEF2 << 4) | \664 (ID_LED_DEF1_DEF2))665#define ID_LED_DEF1_DEF2 0x1666#define ID_LED_DEF1_ON2 0x2667#define ID_LED_DEF1_OFF2 0x3668#define ID_LED_ON1_DEF2 0x4669#define ID_LED_ON1_ON2 0x5670#define ID_LED_ON1_OFF2 0x6671#define ID_LED_OFF1_DEF2 0x7672#define ID_LED_OFF1_ON2 0x8673#define ID_LED_OFF1_OFF2 0x9674 675#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF676#define IGP_ACTIVITY_LED_ENABLE 0x0300677#define IGP_LED3_MODE 0x07000000678 679/* PCI/PCI-X/PCI-EX Config space */680#define PCI_HEADER_TYPE_REGISTER 0x0E681 682#define PHY_REVISION_MASK 0xFFFFFFF0683#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */684#define MAX_PHY_MULTI_PAGE_REG 0xF685 686/* Bit definitions for valid PHY IDs.687 * I = Integrated688 * E = External689 */690#define M88E1000_E_PHY_ID 0x01410C50691#define M88E1000_I_PHY_ID 0x01410C30692#define M88E1011_I_PHY_ID 0x01410C20693#define IGP01E1000_I_PHY_ID 0x02A80380694#define M88E1111_I_PHY_ID 0x01410CC0695#define GG82563_E_PHY_ID 0x01410CA0696#define IGP03E1000_E_PHY_ID 0x02A80390697#define IFE_E_PHY_ID 0x02A80330698#define IFE_PLUS_E_PHY_ID 0x02A80320699#define IFE_C_E_PHY_ID 0x02A80310700#define BME1000_E_PHY_ID 0x01410CB0701#define BME1000_E_PHY_ID_R2 0x01410CB1702#define I82577_E_PHY_ID 0x01540050703#define I82578_E_PHY_ID 0x004DD040704#define I82579_E_PHY_ID 0x01540090705#define I217_E_PHY_ID 0x015400A0706 707/* M88E1000 Specific Registers */708#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */709#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */710#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */711 712#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */713#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */714 715/* M88E1000 PHY Specific Control Register */716#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */717#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */718 /* Manual MDI configuration */719#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */720/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */721#define M88E1000_PSCR_AUTO_X_1000T 0x0040722/* Auto crossover enabled all speeds */723#define M88E1000_PSCR_AUTO_X_MODE 0x0060724#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */725 726/* M88E1000 PHY Specific Status Register */727#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */728#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */729#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */730/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */731#define M88E1000_PSSR_CABLE_LENGTH 0x0380732#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */733#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */734 735#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7736 737/* Number of times we will attempt to autonegotiate before downshifting if we738 * are the master739 */740#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00741#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000742/* Number of times we will attempt to autonegotiate before downshifting if we743 * are the slave744 */745#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300746#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100747#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */748 749/* M88EC018 Rev 2 specific DownShift settings */750#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00751#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800752 753#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020754#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C755 756/* BME1000 PHY Specific Control Register */757#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */758 759/* Bits...760 * 15-5: page761 * 4-0: register offset762 */763#define GG82563_PAGE_SHIFT 5764#define GG82563_REG(page, reg) \765 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))766#define GG82563_MIN_ALT_REG 30767 768/* GG82563 Specific Registers */769#define GG82563_PHY_SPEC_CTRL \770 GG82563_REG(0, 16) /* PHY Specific Control */771#define GG82563_PHY_PAGE_SELECT \772 GG82563_REG(0, 22) /* Page Select */773#define GG82563_PHY_SPEC_CTRL_2 \774 GG82563_REG(0, 26) /* PHY Specific Control 2 */775#define GG82563_PHY_PAGE_SELECT_ALT \776 GG82563_REG(0, 29) /* Alternate Page Select */777 778#define GG82563_PHY_MAC_SPEC_CTRL \779 GG82563_REG(2, 21) /* MAC Specific Control Register */780 781#define GG82563_PHY_DSP_DISTANCE \782 GG82563_REG(5, 26) /* DSP Distance */783 784/* Page 193 - Port Control Registers */785#define GG82563_PHY_KMRN_MODE_CTRL \786 GG82563_REG(193, 16) /* Kumeran Mode Control */787#define GG82563_PHY_PWR_MGMT_CTRL \788 GG82563_REG(193, 20) /* Power Management Control */789 790/* Page 194 - KMRN Registers */791#define GG82563_PHY_INBAND_CTRL \792 GG82563_REG(194, 18) /* Inband Control */793 794/* MDI Control */795#define E1000_MDIC_REG_MASK 0x001F0000796#define E1000_MDIC_REG_SHIFT 16797#define E1000_MDIC_PHY_SHIFT 21798#define E1000_MDIC_OP_WRITE 0x04000000799#define E1000_MDIC_OP_READ 0x08000000800#define E1000_MDIC_READY 0x10000000801#define E1000_MDIC_ERROR 0x40000000802 803/* SerDes Control */804#define E1000_GEN_POLL_TIMEOUT 640805 806#endif /* _E1000_DEFINES_H_ */807