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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2013 - 2018 Intel Corporation. */3 4#ifndef _FM10K_COMMON_H_5#define _FM10K_COMMON_H_6 7#include "fm10k_type.h"8 9#define FM10K_REMOVED(hw_addr) unlikely(!(hw_addr))10 11/* PCI configuration read */12u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg);13 14/* read operations, indexed using DWORDS */15u32 fm10k_read_reg(struct fm10k_hw *hw, int reg);16 17/* write operations, indexed using DWORDS */18#define fm10k_write_reg(hw, reg, val) \19do { \20 u32 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \21 if (!FM10K_REMOVED(hw_addr)) \22 writel((val), &hw_addr[(reg)]); \23} while (0)24 25/* Switch register write operations, index using DWORDS */26#define fm10k_write_sw_reg(hw, reg, val) \27do { \28 u32 __iomem *sw_addr = READ_ONCE((hw)->sw_addr); \29 if (!FM10K_REMOVED(sw_addr)) \30 writel((val), &sw_addr[(reg)]); \31} while (0)32 33/* read ctrl register which has no clear on read fields as PCIe flush */34#define fm10k_write_flush(hw) fm10k_read_reg((hw), FM10K_CTRL)35s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw);36s32 fm10k_get_invariants_generic(struct fm10k_hw *hw);37s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt);38s32 fm10k_start_hw_generic(struct fm10k_hw *hw);39s32 fm10k_stop_hw_generic(struct fm10k_hw *hw);40u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,41 struct fm10k_hw_stat *stat);42#define fm10k_update_hw_base_32b(stat, delta) ((stat)->base_l += (delta))43void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,44 u32 idx, u32 count);45#define fm10k_unbind_hw_stats_32b(s) ((s)->base_h = 0)46void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count);47s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready);48#endif /* _FM10K_COMMON_H_ */49