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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2013 - 2021 Intel Corporation. */3 4#ifndef _I40E_DCB_H_5#define _I40E_DCB_H_6 7#include "i40e_type.h"8 9#define I40E_DCBX_STATUS_NOT_STARTED 010#define I40E_DCBX_STATUS_IN_PROGRESS 111#define I40E_DCBX_STATUS_DONE 212#define I40E_DCBX_STATUS_MULTIPLE_PEERS 313#define I40E_DCBX_STATUS_DISABLED 714 15#define I40E_TLV_TYPE_END 016#define I40E_TLV_TYPE_ORG 12717 18#define I40E_IEEE_8021QAZ_OUI 0x0080C219#define I40E_IEEE_SUBTYPE_ETS_CFG 920#define I40E_IEEE_SUBTYPE_ETS_REC 1021#define I40E_IEEE_SUBTYPE_PFC_CFG 1122#define I40E_IEEE_SUBTYPE_APP_PRI 1223 24#define I40E_CEE_DCBX_OUI 0x001b2125#define I40E_CEE_DCBX_TYPE 226 27#define I40E_CEE_SUBTYPE_CTRL 128#define I40E_CEE_SUBTYPE_PG_CFG 229#define I40E_CEE_SUBTYPE_PFC_CFG 330#define I40E_CEE_SUBTYPE_APP_PRI 431 32#define I40E_CEE_MAX_FEAT_TYPE 333#define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET 0x2B34#define I40E_LLDP_CURRENT_STATUS_X722_OFFSET 0x3135#define I40E_LLDP_CURRENT_STATUS_OFFSET 136#define I40E_LLDP_CURRENT_STATUS_SIZE 137 38/* Defines for LLDP TLV header */39#define I40E_LLDP_TLV_LEN_SHIFT 040#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)41#define I40E_LLDP_TLV_TYPE_SHIFT 942#define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT)43#define I40E_LLDP_TLV_SUBTYPE_SHIFT 044#define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)45#define I40E_LLDP_TLV_OUI_SHIFT 846#define I40E_LLDP_TLV_OUI_MASK (0xFFFFFFU << I40E_LLDP_TLV_OUI_SHIFT)47 48/* Defines for IEEE ETS TLV */49#define I40E_IEEE_ETS_MAXTC_SHIFT 050#define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)51#define I40E_IEEE_ETS_CBS_SHIFT 652#define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)53#define I40E_IEEE_ETS_WILLING_SHIFT 754#define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)55#define I40E_IEEE_ETS_PRIO_0_SHIFT 056#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)57#define I40E_IEEE_ETS_PRIO_1_SHIFT 458#define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)59#define I40E_CEE_PGID_PRIO_0_SHIFT 060#define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT)61#define I40E_CEE_PGID_PRIO_1_SHIFT 462#define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT)63#define I40E_CEE_PGID_STRICT 1564 65/* Defines for IEEE TSA types */66#define I40E_IEEE_TSA_STRICT 067#define I40E_IEEE_TSA_ETS 268 69/* Defines for IEEE PFC TLV */70#define I40E_DCB_PFC_ENABLED 271#define I40E_DCB_PFC_FORCED_NUM_TC 272#define I40E_IEEE_PFC_CAP_SHIFT 073#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)74#define I40E_IEEE_PFC_MBC_SHIFT 675#define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)76#define I40E_IEEE_PFC_WILLING_SHIFT 777#define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)78 79/* Defines for IEEE APP TLV */80#define I40E_IEEE_APP_SEL_SHIFT 081#define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT)82#define I40E_IEEE_APP_PRIO_SHIFT 583#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)84 85/* TLV definitions for preparing MIB */86#define I40E_TLV_ID_CHASSIS_ID 087#define I40E_TLV_ID_PORT_ID 188#define I40E_TLV_ID_TIME_TO_LIVE 289#define I40E_IEEE_TLV_ID_ETS_CFG 390#define I40E_IEEE_TLV_ID_ETS_REC 491#define I40E_IEEE_TLV_ID_PFC_CFG 592#define I40E_IEEE_TLV_ID_APP_PRI 693#define I40E_TLV_ID_END_OF_LLDPPDU 794#define I40E_TLV_ID_START I40E_IEEE_TLV_ID_ETS_CFG95 96#define I40E_IEEE_TLV_HEADER_LENGTH 297#define I40E_IEEE_ETS_TLV_LENGTH 2598#define I40E_IEEE_PFC_TLV_LENGTH 699#define I40E_IEEE_APP_TLV_LENGTH 11100 101/* Defines for default SW DCB config */102#define I40E_IEEE_DEFAULT_ETS_TCBW 100103#define I40E_IEEE_DEFAULT_ETS_WILLING 1104#define I40E_IEEE_DEFAULT_PFC_WILLING 1105#define I40E_IEEE_DEFAULT_NUM_APPS 1106#define I40E_IEEE_DEFAULT_APP_PRIO 3107 108#pragma pack(1)109/* IEEE 802.1AB LLDP Organization specific TLV */110struct i40e_lldp_org_tlv {111 __be16 typelength;112 __be32 ouisubtype;113 u8 tlvinfo[1];114};115 116struct i40e_cee_tlv_hdr {117 __be16 typelen;118 u8 operver;119 u8 maxver;120};121 122struct i40e_cee_ctrl_tlv {123 struct i40e_cee_tlv_hdr hdr;124 __be32 seqno;125 __be32 ackno;126};127 128struct i40e_cee_feat_tlv {129 struct i40e_cee_tlv_hdr hdr;130 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */131#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80132#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40133#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20134 u8 subtype;135 u8 tlvinfo[1];136};137 138struct i40e_cee_app_prio {139 __be16 protocol;140 u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */141#define I40E_CEE_APP_SELECTOR_MASK 0x03142 __be16 lower_oui;143 u8 prio_map;144};145#pragma pack()146 147enum i40e_get_fw_lldp_status_resp {148 I40E_GET_FW_LLDP_STATUS_DISABLED = 0,149 I40E_GET_FW_LLDP_STATUS_ENABLED = 1150};151 152/* Data structures to pass for SW DCBX */153struct i40e_rx_pb_config {154 u32 shared_pool_size;155 u32 shared_pool_high_wm;156 u32 shared_pool_low_wm;157 u32 shared_pool_high_thresh[I40E_MAX_TRAFFIC_CLASS];158 u32 shared_pool_low_thresh[I40E_MAX_TRAFFIC_CLASS];159 u32 tc_pool_size[I40E_MAX_TRAFFIC_CLASS];160 u32 tc_pool_high_wm[I40E_MAX_TRAFFIC_CLASS];161 u32 tc_pool_low_wm[I40E_MAX_TRAFFIC_CLASS];162};163 164enum i40e_dcb_arbiter_mode {165 I40E_DCB_ARB_MODE_STRICT_PRIORITY = 0,166 I40E_DCB_ARB_MODE_ROUND_ROBIN = 1167};168 169#define I40E_DCB_DEFAULT_MAX_EXPONENT 0xB170#define I40E_DEFAULT_PAUSE_TIME 0xffff171#define I40E_MAX_FRAME_SIZE 4608 /* 4.5 KB */172 173#define I40E_DEVICE_RPB_SIZE 968000 /* 968 KB */174 175/* BitTimes (BT) conversion */176#define I40E_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))177#define I40E_B2BT(BT) ((BT) * 8)178#define I40E_BT2B(BT) (((BT) + (8 - 1)) / 8)179 180/* Max Frame(TC) = MFS(max) + MFS(TC) */181#define I40E_MAX_FRAME_TC(mfs_max, mfs_tc) I40E_B2BT((mfs_max) + (mfs_tc))182 183/* EEE Tx LPI Exit time in Bit Times */184#define I40E_EEE_TX_LPI_EXIT_TIME 142500185 186/* PCI Round Trip Time in Bit Times */187#define I40E_PCIRTT_LINK_SPEED_10G 20000188#define I40E_PCIRTT_BYTE_LINK_SPEED_20G 40000189#define I40E_PCIRTT_BYTE_LINK_SPEED_40G 80000190 191/* PFC Frame Delay Bit Times */192#define I40E_PFC_FRAME_DELAY 672193 194/* Worst case Cable (10GBase-T) Delay Bit Times */195#define I40E_CABLE_DELAY 5556196 197/* Higher Layer Delay @10G Bit Times */198#define I40E_HIGHER_LAYER_DELAY_10G 6144199 200/* Interface Delays in Bit Times */201/* TODO: Add for other link speeds 20G/40G/etc. */202#define I40E_INTERFACE_DELAY_10G_MAC_CONTROL 8192203#define I40E_INTERFACE_DELAY_10G_MAC 8192204#define I40E_INTERFACE_DELAY_10G_RS 8192205 206#define I40E_INTERFACE_DELAY_XGXS 2048207#define I40E_INTERFACE_DELAY_XAUI 2048208 209#define I40E_INTERFACE_DELAY_10G_BASEX_PCS 2048210#define I40E_INTERFACE_DELAY_10G_BASER_PCS 3584211#define I40E_INTERFACE_DELAY_LX4_PMD 512212#define I40E_INTERFACE_DELAY_CX4_PMD 512213#define I40E_INTERFACE_DELAY_SERIAL_PMA 512214#define I40E_INTERFACE_DELAY_PMD 512215 216#define I40E_INTERFACE_DELAY_10G_BASET 25600217 218/* Hardware RX DCB config related defines */219#define I40E_DCB_1_PORT_THRESHOLD 0xF220#define I40E_DCB_1_PORT_FIFO_SIZE 0x10221#define I40E_DCB_2_PORT_THRESHOLD_LOW_NUM_TC 0xF222#define I40E_DCB_2_PORT_FIFO_SIZE_LOW_NUM_TC 0x10223#define I40E_DCB_2_PORT_THRESHOLD_HIGH_NUM_TC 0xC224#define I40E_DCB_2_PORT_FIFO_SIZE_HIGH_NUM_TC 0x8225#define I40E_DCB_4_PORT_THRESHOLD_LOW_NUM_TC 0x9226#define I40E_DCB_4_PORT_FIFO_SIZE_LOW_NUM_TC 0x8227#define I40E_DCB_4_PORT_THRESHOLD_HIGH_NUM_TC 0x6228#define I40E_DCB_4_PORT_FIFO_SIZE_HIGH_NUM_TC 0x4229#define I40E_DCB_WATERMARK_START_FACTOR 0x2230 231/* delay values for with 10G BaseT in Bit Times */232#define I40E_INTERFACE_DELAY_10G_COPPER \233 (I40E_INTERFACE_DELAY_10G_MAC + (2 * I40E_INTERFACE_DELAY_XAUI) \234 + I40E_INTERFACE_DELAY_10G_BASET)235#define I40E_DV_TC(mfs_max, mfs_tc) \236 ((2 * I40E_MAX_FRAME_TC(mfs_max, mfs_tc)) \237 + I40E_PFC_FRAME_DELAY \238 + (2 * I40E_CABLE_DELAY) \239 + (2 * I40E_INTERFACE_DELAY_10G_COPPER) \240 + I40E_HIGHER_LAYER_DELAY_10G)241static inline u32 I40E_STD_DV_TC(u32 mfs_max, u32 mfs_tc)242{243 return I40E_DV_TC(mfs_max, mfs_tc) + I40E_B2BT(mfs_max);244}245 246/* APIs for SW DCBX */247void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,248 enum i40e_dcb_arbiter_mode ets_mode,249 enum i40e_dcb_arbiter_mode non_ets_mode,250 u32 max_exponent, u8 lltc_map);251void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,252 u8 num_tc, u8 num_ports);253void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,254 u8 pfc_en, u8 *prio_tc);255void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc);256u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw);257void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,258 u8 *mode, u8 *prio_type);259void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc);260void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,261 u8 num_ports, bool eee_enabled,262 u8 pfc_en, u32 *mfs_tc,263 struct i40e_rx_pb_config *pb_cfg);264void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,265 struct i40e_rx_pb_config *old_pb_cfg,266 struct i40e_rx_pb_config *new_pb_cfg);267int i40e_get_dcbx_status(struct i40e_hw *hw,268 u16 *status);269int i40e_lldp_to_dcb_config(u8 *lldpmib,270 struct i40e_dcbx_config *dcbcfg);271int i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,272 u8 bridgetype,273 struct i40e_dcbx_config *dcbcfg);274int i40e_get_dcb_config(struct i40e_hw *hw);275int i40e_init_dcb(struct i40e_hw *hw,276 bool enable_mib_change);277int278i40e_get_fw_lldp_status(struct i40e_hw *hw,279 enum i40e_get_fw_lldp_status_resp *lldp_status);280int i40e_set_dcb_config(struct i40e_hw *hw);281int i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,282 struct i40e_dcbx_config *dcbcfg);283#endif /* _I40E_DCB_H_ */284