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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018, Intel Corporation. */3 4#ifndef _ICE_ADMINQ_CMD_H_5#define _ICE_ADMINQ_CMD_H_6 7/* This header file defines the Admin Queue commands, error codes and8 * descriptor format. It is shared between Firmware and Software.9 */10 11#define ICE_MAX_VSI 76812#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x913#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 972814 15struct ice_aqc_generic {16 __le32 param0;17 __le32 param1;18 __le32 addr_high;19 __le32 addr_low;20};21 22/* Get version (direct 0x0001) */23struct ice_aqc_get_ver {24 __le32 rom_ver;25 __le32 fw_build;26 u8 fw_branch;27 u8 fw_major;28 u8 fw_minor;29 u8 fw_patch;30 u8 api_branch;31 u8 api_major;32 u8 api_minor;33 u8 api_patch;34};35 36/* Send driver version (indirect 0x0002) */37struct ice_aqc_driver_ver {38 u8 major_ver;39 u8 minor_ver;40 u8 build_ver;41 u8 subbuild_ver;42 u8 reserved[4];43 __le32 addr_high;44 __le32 addr_low;45};46 47/* Queue Shutdown (direct 0x0003) */48struct ice_aqc_q_shutdown {49 u8 driver_unloading;50#define ICE_AQC_DRIVER_UNLOADING BIT(0)51 u8 reserved[15];52};53 54/* Request resource ownership (direct 0x0008)55 * Release resource ownership (direct 0x0009)56 */57struct ice_aqc_req_res {58 __le16 res_id;59#define ICE_AQC_RES_ID_NVM 160#define ICE_AQC_RES_ID_SDP 261#define ICE_AQC_RES_ID_CHNG_LOCK 362#define ICE_AQC_RES_ID_GLBL_LOCK 463 __le16 access_type;64#define ICE_AQC_RES_ACCESS_READ 165#define ICE_AQC_RES_ACCESS_WRITE 266 67 /* Upon successful completion, FW writes this value and driver is68 * expected to release resource before timeout. This value is provided69 * in milliseconds.70 */71 __le32 timeout;72#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 300073#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 18000074#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 100075#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 300076 /* For SDP: pin ID of the SDP */77 __le32 res_number;78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */79 __le16 status;80#define ICE_AQ_RES_GLBL_SUCCESS 081#define ICE_AQ_RES_GLBL_IN_PROG 182#define ICE_AQ_RES_GLBL_DONE 283 u8 reserved[2];84};85 86/* Get function capabilities (indirect 0x000A)87 * Get device capabilities (indirect 0x000B)88 */89struct ice_aqc_list_caps {90 u8 cmd_flags;91 u8 pf_index;92 u8 reserved[2];93 __le32 count;94 __le32 addr_high;95 __le32 addr_low;96};97 98/* Device/Function buffer entry, repeated per reported capability */99struct ice_aqc_list_caps_elem {100 __le16 cap;101#define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005102#define ICE_AQC_CAPS_SRIOV 0x0012103#define ICE_AQC_CAPS_VF 0x0013104#define ICE_AQC_CAPS_VSI 0x0017105#define ICE_AQC_CAPS_DCB 0x0018106#define ICE_AQC_CAPS_RSS 0x0040107#define ICE_AQC_CAPS_RXQS 0x0041108#define ICE_AQC_CAPS_TXQS 0x0042109#define ICE_AQC_CAPS_MSIX 0x0043110#define ICE_AQC_CAPS_FD 0x0045111#define ICE_AQC_CAPS_1588 0x0046112#define ICE_AQC_CAPS_MAX_MTU 0x0047113#define ICE_AQC_CAPS_NVM_VER 0x0048114#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049115#define ICE_AQC_CAPS_OROM_VER 0x004A116#define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B117#define ICE_AQC_CAPS_NET_VER 0x004C118#define ICE_AQC_CAPS_PENDING_NET_VER 0x004D119#define ICE_AQC_CAPS_RDMA 0x0051120#define ICE_AQC_CAPS_SENSOR_READING 0x0067121#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076122#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077123#define ICE_AQC_CAPS_NVM_MGMT 0x0080124#define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085125#define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087126#define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092127#define ICE_AQC_BIT_ROCEV2_LAG 0x01128#define ICE_AQC_BIT_SRIOV_LAG 0x02129 130 u8 major_ver;131 u8 minor_ver;132 /* Number of resources described by this capability */133 __le32 number;134 /* Only meaningful for some types of resources */135 __le32 logical_id;136 /* Only meaningful for some types of resources */137 __le32 phys_id;138 __le64 rsvd1;139 __le64 rsvd2;140};141 142/* Manage MAC address, read command - indirect (0x0107)143 * This struct is also used for the response144 */145struct ice_aqc_manage_mac_read {146 __le16 flags; /* Zeroed by device driver */147#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)148#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)149#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)150#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)151#define ICE_AQC_MAN_MAC_READ_S 4152#define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)153 u8 rsvd[2];154 u8 num_addr; /* Used in response */155 u8 rsvd1[3];156 __le32 addr_high;157 __le32 addr_low;158};159 160/* Response buffer format for manage MAC read command */161struct ice_aqc_manage_mac_read_resp {162 u8 lport_num;163 u8 addr_type;164#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0165#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1166 u8 mac_addr[ETH_ALEN];167};168 169/* Manage MAC address, write command - direct (0x0108) */170struct ice_aqc_manage_mac_write {171 u8 rsvd;172 u8 flags;173#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)174#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)175#define ICE_AQC_MAN_MAC_WR_S 6176#define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)177#define ICE_AQC_MAN_MAC_UPDATE_LAA 0178#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)179 /* byte stream in network order */180 u8 mac_addr[ETH_ALEN];181 __le32 addr_high;182 __le32 addr_low;183};184 185/* Clear PXE Command and response (direct 0x0110) */186struct ice_aqc_clear_pxe {187 u8 rx_cnt;188#define ICE_AQC_CLEAR_PXE_RX_CNT 0x2189 u8 reserved[15];190};191 192/* Get switch configuration (0x0200) */193struct ice_aqc_get_sw_cfg {194 /* Reserved for command and copy of request flags for response */195 __le16 flags;196 /* First desc in case of command and next_elem in case of response197 * In case of response, if it is not zero, means all the configuration198 * was not returned and new command shall be sent with this value in199 * the 'first desc' field200 */201 __le16 element;202 /* Reserved for command, only used for response */203 __le16 num_elems;204 __le16 rsvd;205 __le32 addr_high;206 __le32 addr_low;207};208 209/* Each entry in the response buffer is of the following type: */210struct ice_aqc_get_sw_cfg_resp_elem {211 /* VSI/Port Number */212 __le16 vsi_port_num;213#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0214#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \215 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)216#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14217#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)218#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0219#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1220#define ICE_AQC_GET_SW_CONF_RESP_VSI 2221 222 /* SWID VSI/Port belongs to */223 __le16 swid;224 225 /* Bit 14..0 : PF/VF number VSI belongs to226 * Bit 15 : VF indication bit227 */228 __le16 pf_vf_num;229#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0230#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \231 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)232#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)233};234 235/* Loopback port parameter mode values. */236enum ice_local_fwd_mode {237 ICE_LOCAL_FWD_MODE_ENABLED = 0,238 ICE_LOCAL_FWD_MODE_DISABLED = 1,239 ICE_LOCAL_FWD_MODE_PRIORITIZED = 2,240};241 242/* Set Port parameters, (direct, 0x0203) */243struct ice_aqc_set_port_params {244 __le16 cmd_flags;245#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)246 __le16 bad_frame_vsi;247 __le16 swid;248#define ICE_AQC_PORT_SWID_VALID BIT(15)249#define ICE_AQC_PORT_SWID_M 0xFF250 u8 local_fwd_mode;251#define ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID BIT(2)252 u8 reserved[9];253};254 255/* These resource type defines are used for all switch resource256 * commands where a resource type is required, such as:257 * Get Resource Allocation command (indirect 0x0204)258 * Allocate Resources command (indirect 0x0208)259 * Free Resources command (indirect 0x0209)260 * Get Allocated Resource Descriptors Command (indirect 0x020A)261 * Share Resource command (indirect 0x020B)262 */263#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03264#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04265#define ICE_AQC_RES_TYPE_RECIPE 0x05266#define ICE_AQC_RES_TYPE_SWID 0x07267#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21268#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22269#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23270#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58271#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59272#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60273#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61274 275#define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)276#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)277#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)278#define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14)279#define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15)280 281#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00282 283#define ICE_AQC_RES_TYPE_S 0284#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)285 286/* Allocate Resources command (indirect 0x0208)287 * Free Resources command (indirect 0x0209)288 * Share Resource command (indirect 0x020B)289 */290struct ice_aqc_alloc_free_res_cmd {291 __le16 num_entries; /* Number of Resource entries */292 u8 reserved[6];293 __le32 addr_high;294 __le32 addr_low;295};296 297/* Resource descriptor */298struct ice_aqc_res_elem {299 union {300 __le16 sw_resp;301 __le16 flu_resp;302 } e;303};304 305/* Buffer for Allocate/Free Resources commands */306struct ice_aqc_alloc_free_res_elem {307 __le16 res_type; /* Types defined above cmd 0x0204 */308#define ICE_AQC_RES_TYPE_SHARED_S 7309#define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)310#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8311#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \312 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)313 __le16 num_elems;314 struct ice_aqc_res_elem elem[];315};316 317/* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */318struct ice_aqc_set_vlan_mode {319 u8 reserved;320 u8 l2tag_prio_tagging;321#define ICE_AQ_VLAN_PRIO_TAG_S 0322#define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)323#define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0324#define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1325#define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2326#define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3327#define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4328#define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4329#define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7330 u8 l2tag_reserved[64];331 u8 rdma_packet;332#define ICE_AQ_VLAN_RDMA_TAG_S 0333#define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)334#define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10335#define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A336 u8 rdma_reserved[2];337 u8 mng_vlan_prot_id;338#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10339#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11340 u8 prot_id_reserved[30];341};342 343/* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */344struct ice_aqc_get_vlan_mode {345 u8 vlan_mode;346#define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)347 u8 l2tag_prio_tagging;348 u8 reserved[98];349};350 351/* Add VSI (indirect 0x0210)352 * Update VSI (indirect 0x0211)353 * Get VSI (indirect 0x0212)354 * Free VSI (indirect 0x0213)355 */356struct ice_aqc_add_get_update_free_vsi {357 __le16 vsi_num;358#define ICE_AQ_VSI_NUM_S 0359#define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)360#define ICE_AQ_VSI_IS_VALID BIT(15)361 __le16 cmd_flags;362#define ICE_AQ_VSI_KEEP_ALLOC 0x1363 u8 vf_id;364 u8 reserved;365 __le16 vsi_flags;366#define ICE_AQ_VSI_TYPE_S 0367#define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)368#define ICE_AQ_VSI_TYPE_VF 0x0369#define ICE_AQ_VSI_TYPE_VMDQ2 0x1370#define ICE_AQ_VSI_TYPE_PF 0x2371#define ICE_AQ_VSI_TYPE_EMP_MNG 0x3372 __le32 addr_high;373 __le32 addr_low;374};375 376/* Response descriptor for:377 * Add VSI (indirect 0x0210)378 * Update VSI (indirect 0x0211)379 * Free VSI (indirect 0x0213)380 */381struct ice_aqc_add_update_free_vsi_resp {382 __le16 vsi_num;383 __le16 ext_status;384 __le16 vsi_used;385 __le16 vsi_free;386 __le32 addr_high;387 __le32 addr_low;388};389 390struct ice_aqc_vsi_props {391 __le16 valid_sections;392#define ICE_AQ_VSI_PROP_SW_VALID BIT(0)393#define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)394#define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)395#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)396#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)397#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)398#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)399#define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)400#define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)401#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)402#define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)403 /* switch section */404 u8 sw_id;405 u8 sw_flags;406#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)407#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)408#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)409 u8 sw_flags2;410#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0411#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)412#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)413#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)414 u8 veb_stat_id;415#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0416#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)417#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)418 /* security section */419 u8 sec_flags;420#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)421#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)422#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4423#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)424#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)425 u8 sec_reserved;426 /* VLAN section */427 __le16 port_based_inner_vlan; /* VLANS include priority bits */428 u8 inner_vlan_reserved[2];429 u8 inner_vlan_flags;430#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0431#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)432#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1433#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2434#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3435#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)436#define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3437#define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)438#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U439#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U440#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U441#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U442 u8 inner_vlan_reserved2[3];443 /* ingress egress up sections */444 __le32 ingress_table; /* bitmap, 3 bits per up */445#define ICE_AQ_VSI_UP_TABLE_UP0_S 0446#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)447#define ICE_AQ_VSI_UP_TABLE_UP1_S 3448#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)449#define ICE_AQ_VSI_UP_TABLE_UP2_S 6450#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)451#define ICE_AQ_VSI_UP_TABLE_UP3_S 9452#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)453#define ICE_AQ_VSI_UP_TABLE_UP4_S 12454#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)455#define ICE_AQ_VSI_UP_TABLE_UP5_S 15456#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)457#define ICE_AQ_VSI_UP_TABLE_UP6_S 18458#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)459#define ICE_AQ_VSI_UP_TABLE_UP7_S 21460#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)461 __le32 egress_table; /* same defines as for ingress table */462 /* outer tags section */463 __le16 port_based_outer_vlan;464 u8 outer_vlan_flags;465#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0466#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)467#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0468#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1469#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2470#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3471#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2472#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)473#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0474#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1475#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2476#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3477#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)478#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5479#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)480#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1481#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2482#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3483#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)484 u8 outer_vlan_reserved;485 /* queue mapping section */486 __le16 mapping_flags;487#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0488#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)489 __le16 q_mapping[16];490#define ICE_AQ_VSI_Q_S 0491#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)492 __le16 tc_mapping[8];493#define ICE_AQ_VSI_TC_Q_OFFSET_S 0494#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)495#define ICE_AQ_VSI_TC_Q_NUM_S 11496#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)497 /* queueing option section */498 u8 q_opt_rss;499#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0500#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)501#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0502#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2503#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3504#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2505#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)506#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6507#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6)508#define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U509#define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U510#define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U511#define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U512 u8 q_opt_tc;513#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0514#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)515#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)516 u8 q_opt_flags;517#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)518 u8 q_opt_reserved[3];519 /* outer up section */520 __le32 outer_up_table; /* same structure and defines as ingress tbl */521 /* section 10 */522 __le16 sect_10_reserved;523 /* flow director section */524 __le16 fd_options;525#define ICE_AQ_VSI_FD_ENABLE BIT(0)526#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)527#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)528 __le16 max_fd_fltr_dedicated;529 __le16 max_fd_fltr_shared;530 __le16 fd_def_q;531#define ICE_AQ_VSI_FD_DEF_Q_S 0532#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)533#define ICE_AQ_VSI_FD_DEF_GRP_S 12534#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)535 __le16 fd_report_opt;536#define ICE_AQ_VSI_FD_REPORT_Q_S 0537#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)538#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12539#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)540#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)541 /* PASID section */542 __le32 pasid_id;543#define ICE_AQ_VSI_PASID_ID_S 0544#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)545#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)546 u8 reserved[24];547};548 549#define ICE_MAX_NUM_RECIPES 64550 551/* Add/Get Recipe (indirect 0x0290/0x0292) */552struct ice_aqc_add_get_recipe {553 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */554 __le16 return_index; /* Input, used for Get cmd only */555 u8 reserved[4];556 __le32 addr_high;557 __le32 addr_low;558};559 560struct ice_aqc_recipe_content {561 u8 rid;562#define ICE_AQ_RECIPE_ID_S 0563#define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)564#define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)565#define ICE_AQ_SW_ID_LKUP_IDX 0566 u8 lkup_indx[5];567#define ICE_AQ_RECIPE_LKUP_DATA_S 0568#define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)569#define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)570#define ICE_AQ_SW_ID_LKUP_MASK 0x00FF571 __le16 mask[5];572 u8 result_indx;573#define ICE_AQ_RECIPE_RESULT_DATA_S 0574#define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)575#define ICE_AQ_RECIPE_RESULT_EN BIT(7)576 u8 rsvd0[3];577 u8 act_ctrl_join_priority;578 u8 act_ctrl_fwd_priority;579#define ICE_AQ_RECIPE_FWD_PRIORITY_S 0580#define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)581 u8 act_ctrl;582#define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)583#define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)584#define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)585#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4586#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)587 u8 rsvd1;588 __le32 dflt_act;589#define ICE_AQ_RECIPE_DFLT_ACT_S 0590#define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)591#define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)592};593 594struct ice_aqc_recipe_data_elem {595 u8 recipe_indx;596 u8 resp_bits;597#define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)598 u8 rsvd0[2];599 u8 recipe_bitmap[8];600 u8 rsvd1[4];601 struct ice_aqc_recipe_content content;602 u8 rsvd2[20];603};604 605/* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */606struct ice_aqc_recipe_to_profile {607 __le16 profile_id;608 u8 rsvd[6];609 __le64 recipe_assoc;610};611static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16);612 613/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)614 */615struct ice_aqc_sw_rules {616 /* ops: add switch rules, referring the number of rules.617 * ops: update switch rules, referring the number of filters618 * ops: remove switch rules, referring the entry index.619 * ops: get switch rules, referring to the number of filters.620 */621 __le16 num_rules_fltr_entry_index;622 u8 reserved[6];623 __le32 addr_high;624 __le32 addr_low;625};626 627/* Add switch rule response:628 * Content of return buffer is same as the input buffer. The status field and629 * LUT index are updated as part of the response630 */631struct ice_aqc_sw_rules_elem_hdr {632 __le16 type; /* Switch rule type, one of T_... */633#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0634#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1635#define ICE_AQC_SW_RULES_T_LG_ACT 0x2636#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3637#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4638#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5639#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6640 __le16 status;641} __packed __aligned(sizeof(__le16));642 643/* Add/Update/Get/Remove lookup Rx/Tx command/response entry644 * This structures describes the lookup rules and associated actions. "index"645 * is returned as part of a response to a successful Add command, and can be646 * used to identify the rule for Update/Get/Remove commands.647 */648struct ice_sw_rule_lkup_rx_tx {649 struct ice_aqc_sw_rules_elem_hdr hdr;650 651 __le16 recipe_id;652#define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10653 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */654 __le16 src;655 __le32 act;656 657 /* Bit 0:1 - Action type */658#define ICE_SINGLE_ACT_TYPE_S 0x00659#define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)660 661 /* Bit 2 - Loop back enable662 * Bit 3 - LAN enable663 */664#define ICE_SINGLE_ACT_LB_ENABLE BIT(2)665#define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)666 667 /* Action type = 0 - Forward to VSI or VSI list */668#define ICE_SINGLE_ACT_VSI_FORWARDING 0x0669 670#define ICE_SINGLE_ACT_VSI_ID_S 4671#define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)672#define ICE_SINGLE_ACT_VSI_LIST_ID_S 4673#define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)674 /* This bit needs to be set if action is forward to VSI list */675#define ICE_SINGLE_ACT_VSI_LIST BIT(14)676#define ICE_SINGLE_ACT_VALID_BIT BIT(17)677#define ICE_SINGLE_ACT_DROP BIT(18)678 679 /* Action type = 1 - Forward to Queue of Queue group */680#define ICE_SINGLE_ACT_TO_Q 0x1681#define ICE_SINGLE_ACT_Q_INDEX_S 4682#define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)683#define ICE_SINGLE_ACT_Q_REGION_S 15684#define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)685#define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)686 687 /* Action type = 2 - Prune */688#define ICE_SINGLE_ACT_PRUNE 0x2689#define ICE_SINGLE_ACT_EGRESS BIT(15)690#define ICE_SINGLE_ACT_INGRESS BIT(16)691#define ICE_SINGLE_ACT_PRUNET BIT(17)692 /* Bit 18 should be set to 0 for this action */693 694 /* Action type = 2 - Pointer */695#define ICE_SINGLE_ACT_PTR 0x2696#define ICE_SINGLE_ACT_PTR_VAL_S 4697#define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)698 /* Bit 18 should be set to 1 */699#define ICE_SINGLE_ACT_PTR_BIT BIT(18)700 701 /* Action type = 3 - Other actions. Last two bits702 * are other action identifier703 */704#define ICE_SINGLE_ACT_OTHER_ACTS 0x3705#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17706#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \707 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)708 709 /* Bit 17:18 - Defines other actions */710 /* Other action = 0 - Mirror VSI */711#define ICE_SINGLE_OTHER_ACT_MIRROR 0712#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4713#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \714 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)715 716 /* Other action = 3 - Set Stat count */717#define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3718#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4719#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \720 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)721 722 __le16 index; /* The index of the rule in the lookup table */723 /* Length and values of the header to be matched per recipe or724 * lookup-type725 */726 __le16 hdr_len;727 u8 hdr_data[];728} __packed __aligned(sizeof(__le16));729 730/* Add/Update/Remove large action command/response entry731 * "index" is returned as part of a response to a successful Add command, and732 * can be used to identify the action for Update/Get/Remove commands.733 */734struct ice_sw_rule_lg_act {735 struct ice_aqc_sw_rules_elem_hdr hdr;736 737 __le16 index; /* Index in large action table */738 __le16 size;739 /* Max number of large actions */740#define ICE_MAX_LG_ACT 4741 /* Bit 0:1 - Action type */742#define ICE_LG_ACT_TYPE_S 0743#define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)744 745 /* Action type = 0 - Forward to VSI or VSI list */746#define ICE_LG_ACT_VSI_FORWARDING 0747#define ICE_LG_ACT_VSI_ID_S 3748#define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)749#define ICE_LG_ACT_VSI_LIST_ID_S 3750#define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)751 /* This bit needs to be set if action is forward to VSI list */752#define ICE_LG_ACT_VSI_LIST BIT(13)753 754#define ICE_LG_ACT_VALID_BIT BIT(16)755 756 /* Action type = 1 - Forward to Queue of Queue group */757#define ICE_LG_ACT_TO_Q 0x1758#define ICE_LG_ACT_Q_INDEX_S 3759#define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)760#define ICE_LG_ACT_Q_REGION_S 14761#define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)762#define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)763 764 /* Action type = 2 - Prune */765#define ICE_LG_ACT_PRUNE 0x2766#define ICE_LG_ACT_EGRESS BIT(14)767#define ICE_LG_ACT_INGRESS BIT(15)768#define ICE_LG_ACT_PRUNET BIT(16)769 770 /* Action type = 3 - Mirror VSI */771#define ICE_LG_OTHER_ACT_MIRROR 0x3772#define ICE_LG_ACT_MIRROR_VSI_ID_S 3773#define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)774 775 /* Action type = 5 - Generic Value */776#define ICE_LG_ACT_GENERIC 0x5777#define ICE_LG_ACT_GENERIC_VALUE_S 3778#define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)779#define ICE_LG_ACT_GENERIC_OFFSET_S 19780#define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)781#define ICE_LG_ACT_GENERIC_PRIORITY_S 22782#define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)783#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7784 785 /* Action = 7 - Set Stat count */786#define ICE_LG_ACT_STAT_COUNT 0x7787#define ICE_LG_ACT_STAT_COUNT_S 3788#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)789 __le32 act[]; /* array of size for actions */790} __packed __aligned(sizeof(__le16));791 792/* Add/Update/Remove VSI list command/response entry793 * "index" is returned as part of a response to a successful Add command, and794 * can be used to identify the VSI list for Update/Get/Remove commands.795 */796struct ice_sw_rule_vsi_list {797 struct ice_aqc_sw_rules_elem_hdr hdr;798 799 __le16 index; /* Index of VSI/Prune list */800 __le16 number_vsi;801 __le16 vsi[]; /* Array of number_vsi VSI numbers */802} __packed __aligned(sizeof(__le16));803 804/* Query PFC Mode (direct 0x0302)805 * Set PFC Mode (direct 0x0303)806 */807struct ice_aqc_set_query_pfc_mode {808 u8 pfc_mode;809/* For Query Command response, reserved in all other cases */810#define ICE_AQC_PFC_VLAN_BASED_PFC 1811#define ICE_AQC_PFC_DSCP_BASED_PFC 2812 u8 rsvd[15];813};814/* Get Default Topology (indirect 0x0400) */815struct ice_aqc_get_topo {816 u8 port_num;817 u8 num_branches;818 __le16 reserved1;819 __le32 reserved2;820 __le32 addr_high;821 __le32 addr_low;822};823 824/* Get/Set Tx Topology (indirect 0x0418/0x0417) */825struct ice_aqc_get_set_tx_topo {826 u8 set_flags;827#define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0)828#define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1)829#define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4)830#define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5)831 832 u8 get_flags;833#define ICE_AQC_TX_TOPO_GET_RAM 2834 835 __le16 reserved1;836 __le32 reserved2;837 __le32 addr_high;838 __le32 addr_low;839};840 841/* Update TSE (indirect 0x0403)842 * Get TSE (indirect 0x0404)843 * Add TSE (indirect 0x0401)844 * Delete TSE (indirect 0x040F)845 * Move TSE (indirect 0x0408)846 * Suspend Nodes (indirect 0x0409)847 * Resume Nodes (indirect 0x040A)848 */849struct ice_aqc_sched_elem_cmd {850 __le16 num_elem_req; /* Used by commands */851 __le16 num_elem_resp; /* Used by responses */852 __le32 reserved;853 __le32 addr_high;854 __le32 addr_low;855};856 857struct ice_aqc_txsched_move_grp_info_hdr {858 __le32 src_parent_teid;859 __le32 dest_parent_teid;860 __le16 num_elems;861 u8 mode;862#define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0863#define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1864#define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2865 u8 reserved;866};867 868struct ice_aqc_move_elem {869 struct ice_aqc_txsched_move_grp_info_hdr hdr;870 __le32 teid[];871};872 873struct ice_aqc_elem_info_bw {874 __le16 bw_profile_idx;875 __le16 bw_alloc;876};877 878struct ice_aqc_txsched_elem {879 u8 elem_type; /* Special field, reserved for some aq calls */880#define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0881#define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1882#define ICE_AQC_ELEM_TYPE_TC 0x2883#define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3884#define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4885#define ICE_AQC_ELEM_TYPE_LEAF 0x5886#define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6887 u8 valid_sections;888#define ICE_AQC_ELEM_VALID_GENERIC BIT(0)889#define ICE_AQC_ELEM_VALID_CIR BIT(1)890#define ICE_AQC_ELEM_VALID_EIR BIT(2)891#define ICE_AQC_ELEM_VALID_SHARED BIT(3)892 u8 generic;893#define ICE_AQC_ELEM_GENERIC_MODE_M 0x1894#define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1895#define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1)896#define ICE_AQC_ELEM_GENERIC_SP_S 0x4897#define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4)898#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5899#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \900 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)901 u8 flags; /* Special field, reserved for some aq calls */902#define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1903 struct ice_aqc_elem_info_bw cir_bw;904 struct ice_aqc_elem_info_bw eir_bw;905 __le16 srl_id;906 __le16 reserved2;907};908 909struct ice_aqc_txsched_elem_data {910 __le32 parent_teid;911 __le32 node_teid;912 struct ice_aqc_txsched_elem data;913};914 915struct ice_aqc_txsched_topo_grp_info_hdr {916 __le32 parent_teid;917 __le16 num_elems;918 __le16 reserved2;919};920 921struct ice_aqc_add_elem {922 struct ice_aqc_txsched_topo_grp_info_hdr hdr;923 struct ice_aqc_txsched_elem_data generic[];924};925 926struct ice_aqc_get_topo_elem {927 struct ice_aqc_txsched_topo_grp_info_hdr hdr;928 struct ice_aqc_txsched_elem_data929 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];930};931 932struct ice_aqc_delete_elem {933 struct ice_aqc_txsched_topo_grp_info_hdr hdr;934 __le32 teid[];935};936 937/* Query Port ETS (indirect 0x040E)938 *939 * This indirect command is used to query port TC node configuration.940 */941struct ice_aqc_query_port_ets {942 __le32 port_teid;943 __le32 reserved;944 __le32 addr_high;945 __le32 addr_low;946};947 948struct ice_aqc_port_ets_elem {949 u8 tc_valid_bits;950 u8 reserved[3];951 /* 3 bits for UP per TC 0-7, 4th byte reserved */952 __le32 up2tc;953 u8 tc_bw_share[8];954 __le32 port_eir_prof_id;955 __le32 port_cir_prof_id;956 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */957 __le32 tc_node_prio;958#define ICE_TC_NODE_PRIO_S 0x4959 u8 reserved1[4];960 __le32 tc_node_teid[8]; /* Used for response, reserved in command */961};962 963/* Rate limiting profile for964 * Add RL profile (indirect 0x0410)965 * Query RL profile (indirect 0x0411)966 * Remove RL profile (indirect 0x0415)967 * These indirect commands acts on single or multiple968 * RL profiles with specified data.969 */970struct ice_aqc_rl_profile {971 __le16 num_profiles;972 __le16 num_processed; /* Only for response. Reserved in Command. */973 u8 reserved[4];974 __le32 addr_high;975 __le32 addr_low;976};977 978struct ice_aqc_rl_profile_elem {979 u8 level;980 u8 flags;981#define ICE_AQC_RL_PROFILE_TYPE_S 0x0982#define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)983#define ICE_AQC_RL_PROFILE_TYPE_CIR 0984#define ICE_AQC_RL_PROFILE_TYPE_EIR 1985#define ICE_AQC_RL_PROFILE_TYPE_SRL 2986/* The following flag is used for Query RL Profile Data */987#define ICE_AQC_RL_PROFILE_INVAL_S 0x7988#define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)989 990 __le16 profile_id;991 __le16 max_burst_size;992 __le16 rl_multiply;993 __le16 wake_up_calc;994 __le16 rl_encode;995};996 997/* Query Scheduler Resource Allocation (indirect 0x0412)998 * This indirect command retrieves the scheduler resources allocated by999 * EMP Firmware to the given PF.1000 */1001struct ice_aqc_query_txsched_res {1002 u8 reserved[8];1003 __le32 addr_high;1004 __le32 addr_low;1005};1006 1007struct ice_aqc_generic_sched_props {1008 __le16 phys_levels;1009 __le16 logical_levels;1010 u8 flattening_bitmap;1011 u8 max_device_cgds;1012 u8 max_pf_cgds;1013 u8 rsvd0;1014 __le16 rdma_qsets;1015 u8 rsvd1[22];1016};1017 1018struct ice_aqc_layer_props {1019 u8 logical_layer;1020 u8 chunk_size;1021 __le16 max_device_nodes;1022 __le16 max_pf_nodes;1023 u8 rsvd0[4];1024 __le16 max_sibl_grp_sz;1025 __le16 max_cir_rl_profiles;1026 __le16 max_eir_rl_profiles;1027 __le16 max_srl_profiles;1028 u8 rsvd1[14];1029};1030 1031struct ice_aqc_query_txsched_res_resp {1032 struct ice_aqc_generic_sched_props sched_props;1033 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];1034};1035 1036/* Get PHY capabilities (indirect 0x0600) */1037struct ice_aqc_get_phy_caps {1038 u8 lport_num;1039 u8 reserved;1040 __le16 param0;1041 /* 18.0 - Report qualified modules */1042#define ICE_AQC_GET_PHY_RQM BIT(0)1043 /* 18.1 - 18.3 : Report mode1044 * 000b - Report NVM capabilities1045 * 001b - Report topology capabilities1046 * 010b - Report SW configured1047 * 100b - Report default capabilities1048 */1049#define ICE_AQC_REPORT_MODE_S 11050#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)1051#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 01052#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)1053#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)1054#define ICE_AQC_REPORT_DFLT_CFG BIT(3)1055 __le32 reserved1;1056 __le32 addr_high;1057 __le32 addr_low;1058};1059 1060/* This is #define of PHY type (Extended):1061 * The first set of defines is for phy_type_low.1062 */1063#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)1064#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)1065#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)1066#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)1067#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)1068#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)1069#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)1070#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)1071#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)1072#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)1073#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)1074#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)1075#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)1076#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)1077#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)1078#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)1079#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)1080#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)1081#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)1082#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)1083#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)1084#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)1085#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)1086#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)1087#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)1088#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)1089#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)1090#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)1091#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)1092#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)1093#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)1094#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)1095#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)1096#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)1097#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)1098#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)1099#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)1100#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)1101#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)1102#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)1103#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)1104#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)1105#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)1106#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)1107#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)1108#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)1109#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)1110#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)1111#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)1112#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)1113#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)1114#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)1115#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)1116#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)1117#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)1118#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)1119#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)1120#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)1121#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)1122#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)1123#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)1124#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)1125#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)1126#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)1127#define ICE_PHY_TYPE_LOW_MAX_INDEX 631128/* The second set of defines is for phy_type_high. */1129#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)1130#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)1131#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)1132#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)1133#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)1134#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5)1135#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6)1136#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7)1137#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8)1138#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9)1139#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10)1140#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11)1141#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12)1142#define ICE_PHY_TYPE_HIGH_MAX_INDEX 121143 1144struct ice_aqc_get_phy_caps_data {1145 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */1146 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */1147 u8 caps;1148#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)1149#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)1150#define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)1151#define ICE_AQC_PHY_EN_LINK BIT(3)1152#define ICE_AQC_PHY_AN_MODE BIT(4)1153#define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)1154#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)1155#define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)1156 u8 low_power_ctrl_an;1157#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)1158#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)1159#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)1160#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)1161 __le16 eee_cap;1162#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)1163#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)1164#define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)1165#define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)1166#define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)1167#define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)1168#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)1169 __le16 eeer_value;1170 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */1171 u8 phy_fw_ver[8];1172 u8 link_fec_options;1173#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)1174#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)1175#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)1176#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)1177#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)1178#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)1179#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)1180#define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)1181 u8 module_compliance_enforcement;1182#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)1183 u8 extended_compliance_code;1184#define ICE_MODULE_TYPE_TOTAL_BYTE 31185 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];1186#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA01187#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x801188#define ICE_AQC_MOD_TYPE_IDENT 11189#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)1190#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)1191#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)1192#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)1193#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)1194#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)1195#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA01196#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x861197 u8 qualified_module_count;1198 u8 rsvd2[7]; /* Bytes 47:41 reserved */1199#define ICE_AQC_QUAL_MOD_COUNT_MAX 161200 struct {1201 u8 v_oui[3];1202 u8 rsvd3;1203 u8 v_part[16];1204 __le32 v_rev;1205 __le64 rsvd4;1206 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];1207};1208 1209/* Set PHY capabilities (direct 0x0601)1210 * NOTE: This command must be followed by setup link and restart auto-neg1211 */1212struct ice_aqc_set_phy_cfg {1213 u8 lport_num;1214 u8 reserved[7];1215 __le32 addr_high;1216 __le32 addr_low;1217};1218 1219/* Set PHY config command data structure */1220struct ice_aqc_set_phy_cfg_data {1221 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */1222 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */1223 u8 caps;1224#define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)1225#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)1226#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)1227#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)1228#define ICE_AQ_PHY_ENA_LINK BIT(3)1229#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)1230#define ICE_AQ_PHY_ENA_LESM BIT(6)1231#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)1232 u8 low_power_ctrl_an;1233 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */1234 __le16 eeer_value;1235 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */1236 u8 module_compliance_enforcement;1237};1238 1239/* Set MAC Config command data structure (direct 0x0603) */1240struct ice_aqc_set_mac_cfg {1241 __le16 max_frame_size;1242 u8 params;1243#define ICE_AQ_SET_MAC_PACE_S 31244#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)1245#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)1246#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 01247#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M1248 u8 tx_tmr_priority;1249 __le16 tx_tmr_value;1250 __le16 fc_refresh_threshold;1251 u8 drop_opts;1252#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)1253#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 01254#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)1255 u8 reserved[7];1256};1257 1258/* Restart AN command data structure (direct 0x0605)1259 * Also used for response, with only the lport_num field present.1260 */1261struct ice_aqc_restart_an {1262 u8 lport_num;1263 u8 reserved;1264 u8 cmd_flags;1265#define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)1266#define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)1267 u8 reserved2[13];1268};1269 1270/* Get link status (indirect 0x0607), also used for Link Status Event */1271struct ice_aqc_get_link_status {1272 u8 lport_num;1273 u8 reserved;1274 __le16 cmd_flags;1275#define ICE_AQ_LSE_M 0x31276#define ICE_AQ_LSE_NOP 0x01277#define ICE_AQ_LSE_DIS 0x21278#define ICE_AQ_LSE_ENA 0x31279 /* only response uses this flag */1280#define ICE_AQ_LSE_IS_ENABLED 0x11281 __le32 reserved2;1282 __le32 addr_high;1283 __le32 addr_low;1284};1285 1286/* Get link status response data structure, also used for Link Status Event */1287struct ice_aqc_get_link_status_data {1288 u8 topo_media_conflict;1289#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)1290#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)1291#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)1292#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)1293#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)1294#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)1295#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)1296 u8 link_cfg_err;1297#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)1298#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)1299#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)1300 u8 link_info;1301#define ICE_AQ_LINK_UP BIT(0) /* Link Status */1302#define ICE_AQ_LINK_FAULT BIT(1)1303#define ICE_AQ_LINK_FAULT_TX BIT(2)1304#define ICE_AQ_LINK_FAULT_RX BIT(3)1305#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)1306#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */1307#define ICE_AQ_MEDIA_AVAILABLE BIT(6)1308#define ICE_AQ_SIGNAL_DETECT BIT(7)1309 u8 an_info;1310#define ICE_AQ_AN_COMPLETED BIT(0)1311#define ICE_AQ_LP_AN_ABILITY BIT(1)1312#define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */1313#define ICE_AQ_FEC_EN BIT(3)1314#define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */1315#define ICE_AQ_LINK_PAUSE_TX BIT(5)1316#define ICE_AQ_LINK_PAUSE_RX BIT(6)1317#define ICE_AQ_QUALIFIED_MODULE BIT(7)1318 u8 ext_info;1319#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)1320#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */1321 /* Port Tx Suspended */1322#define ICE_AQ_LINK_TX_S 21323#define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)1324#define ICE_AQ_LINK_TX_ACTIVE 01325#define ICE_AQ_LINK_TX_DRAINED 11326#define ICE_AQ_LINK_TX_FLUSHED 31327 u8 reserved2;1328 __le16 max_frame_size;1329 u8 cfg;1330#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)1331#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)1332#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)1333#define ICE_AQ_FEC_MASK ICE_M(0x7, 0)1334 /* Pacing Config */1335#define ICE_AQ_CFG_PACING_S 31336#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)1337#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)1338#define ICE_AQ_CFG_PACING_TYPE_AVG 01339#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M1340 /* External Device Power Ability */1341 u8 power_desc;1342#define ICE_AQ_PWR_CLASS_M 0x3F1343#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 01344#define ICE_AQ_LINK_PWR_BASET_HIGH 11345#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 01346#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 11347#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 21348#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 31349 __le16 link_speed;1350#define ICE_AQ_LINK_SPEED_M 0x7FF1351#define ICE_AQ_LINK_SPEED_10MB BIT(0)1352#define ICE_AQ_LINK_SPEED_100MB BIT(1)1353#define ICE_AQ_LINK_SPEED_1000MB BIT(2)1354#define ICE_AQ_LINK_SPEED_2500MB BIT(3)1355#define ICE_AQ_LINK_SPEED_5GB BIT(4)1356#define ICE_AQ_LINK_SPEED_10GB BIT(5)1357#define ICE_AQ_LINK_SPEED_20GB BIT(6)1358#define ICE_AQ_LINK_SPEED_25GB BIT(7)1359#define ICE_AQ_LINK_SPEED_40GB BIT(8)1360#define ICE_AQ_LINK_SPEED_50GB BIT(9)1361#define ICE_AQ_LINK_SPEED_100GB BIT(10)1362#define ICE_AQ_LINK_SPEED_200GB BIT(11)1363#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)1364 /* Aligns next field to 8-byte boundary */1365 __le16 reserved3;1366 u8 ext_fec_status;1367 /* RS 272 FEC enabled */1368#define ICE_AQ_LINK_RS_272_FEC_EN BIT(0)1369 u8 reserved4;1370 /* Use values from ICE_PHY_TYPE_LOW_* */1371 __le64 phy_type_low;1372 /* Use values from ICE_PHY_TYPE_HIGH_* */1373 __le64 phy_type_high;1374#define ICE_AQC_LS_DATA_SIZE_V1 \1375 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high)1376 /* Get link status v2 link partner data */1377 __le64 lp_phy_type_low;1378 __le64 lp_phy_type_high;1379 u8 lp_fec_adv;1380#define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0)1381#define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1)1382#define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2)1383#define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3)1384#define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4)1385#define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5)1386 u8 lp_fec_req;1387#define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0)1388#define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1)1389#define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2)1390#define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3)1391 u8 lp_flowcontrol;1392#define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0)1393#define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1)1394 u8 reserved5[5];1395#define ICE_AQC_LS_DATA_SIZE_V2 \1396 offsetofend(struct ice_aqc_get_link_status_data, reserved5)1397} __packed;1398 1399/* Set event mask command (direct 0x0613) */1400struct ice_aqc_set_event_mask {1401 u8 lport_num;1402 u8 reserved[7];1403 __le16 event_mask;1404#define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)1405#define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)1406#define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)1407#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)1408#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)1409#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)1410#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)1411#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)1412#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)1413#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)1414 u8 reserved1[6];1415};1416 1417/* Set MAC Loopback command (direct 0x0620) */1418struct ice_aqc_set_mac_lb {1419 u8 lb_mode;1420#define ICE_AQ_MAC_LB_EN BIT(0)1421#define ICE_AQ_MAC_LB_OSC_CLK BIT(1)1422 u8 reserved[15];1423};1424 1425/* Set PHY recovered clock output (direct 0x0630) */1426struct ice_aqc_set_phy_rec_clk_out {1427 u8 phy_output;1428 u8 port_num;1429#define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF1430 u8 flags;1431#define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0)1432 u8 rsvd;1433 __le32 freq;1434 u8 rsvd2[6];1435 __le16 node_handle;1436};1437 1438/* Get PHY recovered clock output (direct 0x0631) */1439struct ice_aqc_get_phy_rec_clk_out {1440 u8 phy_output;1441 u8 port_num;1442#define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF1443 u8 flags;1444#define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0)1445 u8 rsvd[11];1446 __le16 node_handle;1447};1448 1449/* Get sensor reading (direct 0x0632) */1450struct ice_aqc_get_sensor_reading {1451 u8 sensor;1452 u8 format;1453 u8 reserved[6];1454 __le32 addr_high;1455 __le32 addr_low;1456};1457 1458/* Get sensor reading response (direct 0x0632) */1459struct ice_aqc_get_sensor_reading_resp {1460 union {1461 u8 raw[8];1462 /* Output data for sensor 0x00, format 0x00 */1463 struct _packed {1464 s8 temp;1465 u8 temp_warning_threshold;1466 u8 temp_critical_threshold;1467 u8 temp_fatal_threshold;1468 u8 reserved[4];1469 } s0f0;1470 } data;1471};1472 1473/* DNL call command (indirect 0x0682)1474 * Struct is used for both command and response1475 */1476struct ice_aqc_dnl_call_command {1477 u8 ctx; /* Used in command, reserved in response */1478 u8 reserved;1479 __le16 activity_id;1480#define ICE_AQC_ACT_ID_DNL 0x11291481 __le32 reserved1;1482 __le32 addr_high;1483 __le32 addr_low;1484};1485 1486struct ice_aqc_dnl_equa_param {1487 __le16 data_in;1488#define ICE_AQC_RX_EQU_SHIFT 81489#define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT)1490#define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT)1491#define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT)1492#define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT)1493#define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT)1494#define ICE_AQC_RX_EQU_DRATE (0x15 << ICE_AQC_RX_EQU_SHIFT)1495#define ICE_AQC_TX_EQU_PRE1 0x01496#define ICE_AQC_TX_EQU_PRE3 0x31497#define ICE_AQC_TX_EQU_ATTEN 0x41498#define ICE_AQC_TX_EQU_POST1 0x81499#define ICE_AQC_TX_EQU_PRE2 0xC1500 __le16 op_code_serdes_sel;1501#define ICE_AQC_OP_CODE_SHIFT 41502#define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT)1503#define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT)1504 __le32 reserved[3];1505};1506 1507struct ice_aqc_dnl_equa_respon {1508 /* Equalization value can be negative */1509 int val;1510 __le32 reserved[3];1511};1512 1513/* DNL call command/response buffer (indirect 0x0682) */1514struct ice_aqc_dnl_call {1515 union {1516 struct ice_aqc_dnl_equa_param txrx_equa_reqs;1517 __le32 stores[4];1518 struct ice_aqc_dnl_equa_respon txrx_equa_resp;1519 } sto;1520};1521 1522struct ice_aqc_link_topo_params {1523 u8 lport_num;1524 u8 lport_num_valid;1525#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)1526 u8 node_type_ctx;1527#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 01528#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)1529#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 01530#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 11531#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 21532#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 31533#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 41534#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 51535#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 61536#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 71537#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 81538#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 91539#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 101540#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 111541#define ICE_AQC_LINK_TOPO_NODE_CTX_S 41542#define ICE_AQC_LINK_TOPO_NODE_CTX_M \1543 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)1544#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 01545#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 11546#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 21547#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 31548#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 41549#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 51550 u8 index;1551};1552 1553struct ice_aqc_link_topo_addr {1554 struct ice_aqc_link_topo_params topo_params;1555 __le16 handle;1556#define ICE_AQC_LINK_TOPO_HANDLE_S 01557#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)1558/* Used to decode the handle field */1559#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)1560#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)1561#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 01562#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 01563/* In case of a Mezzanine type */1564#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \1565 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)1566#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 61567#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)1568/* In case of a LOM type */1569#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \1570 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)1571};1572 1573/* Get Link Topology Handle (direct, 0x06E0) */1574struct ice_aqc_get_link_topo {1575 struct ice_aqc_link_topo_addr addr;1576 u8 node_part_num;1577#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x211578#define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x241579#define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x251580#define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x301581#define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x311582#define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x471583#define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x481584 u8 rsvd[9];1585};1586 1587/* Read/Write I2C (direct, 0x06E2/0x06E3) */1588struct ice_aqc_i2c {1589 struct ice_aqc_link_topo_addr topo_addr;1590 __le16 i2c_addr;1591 u8 i2c_params;1592#define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0)1593#define ICE_AQC_I2C_USE_REPEATED_START BIT(7)1594 1595 u8 rsvd;1596 __le16 i2c_bus_addr;1597 u8 i2c_data[4]; /* Used only by write command, reserved in read. */1598};1599 1600/* Read I2C Response (direct, 0x06E2) */1601struct ice_aqc_read_i2c_resp {1602 u8 i2c_data[16];1603};1604 1605/* Set Port Identification LED (direct, 0x06E9) */1606struct ice_aqc_set_port_id_led {1607 u8 lport_num;1608 u8 lport_num_valid;1609 u8 ident_mode;1610#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)1611#define ICE_AQC_PORT_IDENT_LED_ORIG 01612 u8 rsvd[13];1613};1614 1615/* Get Port Options (indirect, 0x06EA) */1616struct ice_aqc_get_port_options {1617 u8 lport_num;1618 u8 lport_num_valid;1619 u8 port_options_count;1620#define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0)1621#define ICE_AQC_PORT_OPT_MAX 161622 1623 u8 innermost_phy_index;1624 u8 port_options;1625#define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0)1626#define ICE_AQC_PORT_OPT_VALID BIT(7)1627 1628 u8 pending_port_option_status;1629#define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0)1630#define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7)1631 1632 u8 rsvd[2];1633 __le32 addr_high;1634 __le32 addr_low;1635};1636 1637struct ice_aqc_get_port_options_elem {1638 u8 pmd;1639#define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0)1640 1641 u8 max_lane_speed;1642#define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0)1643#define ICE_AQC_PORT_OPT_MAX_LANE_100M 01644#define ICE_AQC_PORT_OPT_MAX_LANE_1G 11645#define ICE_AQC_PORT_OPT_MAX_LANE_2500M 21646#define ICE_AQC_PORT_OPT_MAX_LANE_5G 31647#define ICE_AQC_PORT_OPT_MAX_LANE_10G 41648#define ICE_AQC_PORT_OPT_MAX_LANE_25G 51649#define ICE_AQC_PORT_OPT_MAX_LANE_50G 61650#define ICE_AQC_PORT_OPT_MAX_LANE_100G 71651 1652 u8 global_scid[2];1653 u8 phy_scid[2];1654 u8 pf2port_cid[2];1655};1656 1657/* Set Port Option (direct, 0x06EB) */1658struct ice_aqc_set_port_option {1659 u8 lport_num;1660 u8 lport_num_valid;1661 u8 selected_port_option;1662 u8 rsvd[13];1663};1664 1665/* Set/Get GPIO (direct, 0x06EC/0x06ED) */1666struct ice_aqc_gpio {1667 __le16 gpio_ctrl_handle;1668#define ICE_AQC_GPIO_HANDLE_S 01669#define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)1670 u8 gpio_num;1671 u8 gpio_val;1672 u8 rsvd[12];1673};1674 1675/* Read/Write SFF EEPROM command (indirect 0x06EE) */1676struct ice_aqc_sff_eeprom {1677 u8 lport_num;1678 u8 lport_num_valid;1679#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)1680 __le16 i2c_bus_addr;1681#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F1682#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF1683#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)1684#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 01685#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M1686#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 111687#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)1688#define ICE_AQC_SFF_NO_PAGE_CHANGE 01689#define ICE_AQC_SFF_SET_23_ON_MISMATCH 11690#define ICE_AQC_SFF_SET_22_ON_MISMATCH 21691#define ICE_AQC_SFF_IS_WRITE BIT(15)1692 __le16 i2c_mem_addr;1693 __le16 eeprom_page;1694#define ICE_AQC_SFF_EEPROM_BANK_S 01695#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)1696#define ICE_AQC_SFF_EEPROM_PAGE_S 81697#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)1698 __le32 addr_high;1699 __le32 addr_low;1700};1701 1702/* NVM Read command (indirect 0x0701)1703 * NVM Erase commands (direct 0x0702)1704 * NVM Update commands (indirect 0x0703)1705 */1706struct ice_aqc_nvm {1707#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF1708 __le16 offset_low;1709 u8 offset_high;1710 u8 cmd_flags;1711#define ICE_AQC_NVM_LAST_CMD BIT(0)1712#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */1713#define ICE_AQC_NVM_PRESERVATION_S 11714#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)1715#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)1716#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)1717#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)1718#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)1719#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */1720#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)1721#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)1722#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)1723#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */1724#define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)1725#define ICE_AQC_NVM_FLASH_ONLY BIT(7)1726#define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */1727#define ICE_AQC_NVM_POR_FLAG 01728#define ICE_AQC_NVM_PERST_FLAG 11729#define ICE_AQC_NVM_EMPR_FLAG 21730#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */1731 /* For Write Activate, several flags are sent as part of a separate1732 * flags2 field using a separate byte. For simplicity of the software1733 * interface, we pass the flags as a 16 bit value so these flags are1734 * all offset by 8 bits1735 */1736#define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */1737 __le16 module_typeid;1738 __le16 length;1739#define ICE_AQC_NVM_ERASE_LEN 0xFFFF1740 __le32 addr_high;1741 __le32 addr_low;1742};1743 1744#define ICE_AQC_NVM_START_POINT 01745 1746#define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B1747 1748struct ice_aqc_nvm_tx_topo_user_sel {1749 __le16 length;1750 u8 data;1751#define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4)1752 u8 reserved;1753};1754 1755/* NVM Checksum Command (direct, 0x0706) */1756struct ice_aqc_nvm_checksum {1757 u8 flags;1758#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)1759#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)1760 u8 rsvd;1761 __le16 checksum; /* Used only by response */1762#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA1763 u8 rsvd2[12];1764};1765 1766/* Used for NVM Set Package Data command - 0x070A */1767struct ice_aqc_nvm_pkg_data {1768 u8 reserved[3];1769 u8 cmd_flags;1770#define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */1771#define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */1772 1773 u32 reserved1;1774 __le32 addr_high;1775 __le32 addr_low;1776};1777 1778/* Used for Pass Component Table command - 0x070B */1779struct ice_aqc_nvm_pass_comp_tbl {1780 u8 component_response; /* Response only */1781#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x01782#define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x11783#define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x21784 u8 component_response_code; /* Response only */1785#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x01786#define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x11787#define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x21788#define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x31789#define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x41790#define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x51791#define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x61792#define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x71793#define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x81794#define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA1795#define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB1796 u8 reserved;1797 u8 transfer_flag;1798#define ICE_AQ_NVM_PASS_COMP_TBL_START 0x11799#define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x21800#define ICE_AQ_NVM_PASS_COMP_TBL_END 0x41801#define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x51802 __le32 reserved1;1803 __le32 addr_high;1804 __le32 addr_low;1805};1806 1807struct ice_aqc_nvm_comp_tbl {1808 __le16 comp_class;1809#define NVM_COMP_CLASS_ALL_FW 0x000A1810 1811 __le16 comp_id;1812#define NVM_COMP_ID_OROM 0x51813#define NVM_COMP_ID_NVM 0x61814#define NVM_COMP_ID_NETLIST 0x81815 1816 u8 comp_class_idx;1817#define FWU_COMP_CLASS_IDX_NOT_USE 0x01818 1819 __le32 comp_cmp_stamp;1820 u8 cvs_type;1821#define NVM_CVS_TYPE_ASCII 0x11822 1823 u8 cvs_len;1824 u8 cvs[]; /* Component Version String */1825} __packed;1826 1827/* Send to PF command (indirect 0x0801) ID is only used by PF1828 *1829 * Send to VF command (indirect 0x0802) ID is only used by PF1830 *1831 */1832struct ice_aqc_pf_vf_msg {1833 __le32 id;1834 u32 reserved;1835 __le32 addr_high;1836 __le32 addr_low;1837};1838 1839/* Get LLDP MIB (indirect 0x0A00)1840 * Note: This is also used by the LLDP MIB Change Event (0x0A01)1841 * as the format is the same.1842 */1843struct ice_aqc_lldp_get_mib {1844 u8 type;1845#define ICE_AQ_LLDP_MIB_TYPE_S 01846#define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)1847#define ICE_AQ_LLDP_MIB_LOCAL 01848#define ICE_AQ_LLDP_MIB_REMOTE 11849#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 21850#define ICE_AQ_LLDP_BRID_TYPE_S 21851#define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)1852#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 01853#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 11854/* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */1855#define ICE_AQ_LLDP_TX_S 0x41856#define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)1857#define ICE_AQ_LLDP_TX_ACTIVE 01858#define ICE_AQ_LLDP_TX_SUSPENDED 11859#define ICE_AQ_LLDP_TX_FLUSHED 31860/* DCBX mode */1861#define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6)1862#define ICE_AQ_LLDP_DCBX_NA 01863#define ICE_AQ_LLDP_DCBX_CEE 11864#define ICE_AQ_LLDP_DCBX_IEEE 21865 1866 u8 state;1867#define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0)1868#define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 01869#define ICE_AQ_LLDP_MIB_CHANGE_PENDING 11870 1871/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)1872 * and in the LLDP MIB Change Event (0x0A01). They are valid for the1873 * Get LLDP MIB (0x0A00) response only.1874 */1875 __le16 local_len;1876 __le16 remote_len;1877 u8 reserved[2];1878 __le32 addr_high;1879 __le32 addr_low;1880};1881 1882/* Configure LLDP MIB Change Event (direct 0x0A01) */1883/* For MIB Change Event use ice_aqc_lldp_get_mib structure above */1884struct ice_aqc_lldp_set_mib_change {1885 u8 command;1886#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x01887#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x11888#define ICE_AQ_LLDP_MIB_PENDING_M BIT(1)1889#define ICE_AQ_LLDP_MIB_PENDING_DISABLE 01890#define ICE_AQ_LLDP_MIB_PENDING_ENABLE 11891 u8 reserved[15];1892};1893 1894/* Stop LLDP (direct 0x0A05) */1895struct ice_aqc_lldp_stop {1896 u8 command;1897#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)1898#define ICE_AQ_LLDP_AGENT_STOP 0x01899#define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK1900#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)1901 u8 reserved[15];1902};1903 1904/* Start LLDP (direct 0x0A06) */1905struct ice_aqc_lldp_start {1906 u8 command;1907#define ICE_AQ_LLDP_AGENT_START BIT(0)1908#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)1909 u8 reserved[15];1910};1911 1912/* Get CEE DCBX Oper Config (0x0A07)1913 * The command uses the generic descriptor struct and1914 * returns the struct below as an indirect response.1915 */1916struct ice_aqc_get_cee_dcb_cfg_resp {1917 u8 oper_num_tc;1918 u8 oper_prio_tc[4];1919 u8 oper_tc_bw[8];1920 u8 oper_pfc_en;1921 __le16 oper_app_prio;1922#define ICE_AQC_CEE_APP_FCOE_S 01923#define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)1924#define ICE_AQC_CEE_APP_ISCSI_S 31925#define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)1926#define ICE_AQC_CEE_APP_FIP_S 81927#define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)1928 __le32 tlv_status;1929#define ICE_AQC_CEE_PG_STATUS_S 01930#define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)1931#define ICE_AQC_CEE_PFC_STATUS_S 31932#define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)1933#define ICE_AQC_CEE_FCOE_STATUS_S 81934#define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)1935#define ICE_AQC_CEE_ISCSI_STATUS_S 111936#define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)1937#define ICE_AQC_CEE_FIP_STATUS_S 161938#define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)1939 u8 reserved[12];1940};1941 1942/* Set Local LLDP MIB (indirect 0x0A08)1943 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX1944 */1945struct ice_aqc_lldp_set_local_mib {1946 u8 type;1947#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)1948#define SET_LOCAL_MIB_TYPE_LOCAL_MIB 01949#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)1950#define SET_LOCAL_MIB_TYPE_CEE_WILLING 01951#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M1952 u8 reserved0;1953 __le16 length;1954 u8 reserved1[4];1955 __le32 addr_high;1956 __le32 addr_low;1957};1958 1959/* Stop/Start LLDP Agent (direct 0x0A09)1960 * Used for stopping/starting specific LLDP agent. e.g. DCBX.1961 * The same structure is used for the response, with the command field1962 * being used as the status field.1963 */1964struct ice_aqc_lldp_stop_start_specific_agent {1965 u8 command;1966#define ICE_AQC_START_STOP_AGENT_M BIT(0)1967#define ICE_AQC_START_STOP_AGENT_STOP_DCBX 01968#define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M1969 u8 reserved[15];1970};1971 1972/* LLDP Filter Control (direct 0x0A0A) */1973struct ice_aqc_lldp_filter_ctrl {1974 u8 cmd_flags;1975#define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x01976#define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x11977 u8 reserved1;1978 __le16 vsi_num;1979 u8 reserved2[12];1980};1981 1982#define ICE_AQC_RSS_VSI_VALID BIT(15)1983 1984/* Get/Set RSS key (indirect 0x0B04/0x0B02) */1985struct ice_aqc_get_set_rss_key {1986 __le16 vsi_id;1987 u8 reserved[6];1988 __le32 addr_high;1989 __le32 addr_low;1990};1991 1992#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x281993#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC1994#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \1995 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \1996 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)1997 1998struct ice_aqc_get_set_rss_keys {1999 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];2000 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];2001};2002 2003enum ice_lut_type {2004 ICE_LUT_VSI = 0,2005 ICE_LUT_PF = 1,2006 ICE_LUT_GLOBAL = 2,2007};2008 2009enum ice_lut_size {2010 ICE_LUT_VSI_SIZE = 64,2011 ICE_LUT_GLOBAL_SIZE = 512,2012 ICE_LUT_PF_SIZE = 2048,2013};2014 2015/* enum ice_aqc_lut_flags combines constants used to fill2016 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID,2017 * LUT size and LUT type, last of which does not need neither shift nor mask.2018 */2019enum ice_aqc_lut_flags {2020 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */2021 ICE_AQC_LUT_SIZE_512 = BIT(2),2022 ICE_AQC_LUT_SIZE_2K = BIT(3),2023 2024 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4),2025};2026 2027/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */2028struct ice_aqc_get_set_rss_lut {2029 __le16 vsi_id;2030 __le16 flags;2031 __le32 reserved;2032 __le32 addr_high;2033 __le32 addr_low;2034};2035 2036/* Sideband Control Interface Commands */2037/* Neighbor Device Request (indirect 0x0C00); also used for the response. */2038struct ice_aqc_neigh_dev_req {2039 __le16 sb_data_len;2040 u8 reserved[6];2041 __le32 addr_high;2042 __le32 addr_low;2043};2044 2045/* Add Tx LAN Queues (indirect 0x0C30) */2046struct ice_aqc_add_txqs {2047 u8 num_qgrps;2048 u8 reserved[3];2049 __le32 reserved1;2050 __le32 addr_high;2051 __le32 addr_low;2052};2053 2054/* This is the descriptor of each queue entry for the Add Tx LAN Queues2055 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.2056 */2057struct ice_aqc_add_txqs_perq {2058 __le16 txq_id;2059 u8 rsvd[2];2060 __le32 q_teid;2061 u8 txq_ctx[22];2062 u8 rsvd2[2];2063 struct ice_aqc_txsched_elem info;2064};2065 2066/* The format of the command buffer for Add Tx LAN Queues (0x0C30)2067 * is an array of the following structs. Please note that the length of2068 * each struct ice_aqc_add_tx_qgrp is variable due2069 * to the variable number of queues in each group!2070 */2071struct ice_aqc_add_tx_qgrp {2072 __le32 parent_teid;2073 u8 num_txqs;2074 u8 rsvd[3];2075 struct ice_aqc_add_txqs_perq txqs[];2076};2077 2078/* Disable Tx LAN Queues (indirect 0x0C31) */2079struct ice_aqc_dis_txqs {2080 u8 cmd_type;2081#define ICE_AQC_Q_DIS_CMD_S 02082#define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)2083#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)2084#define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)2085#define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)2086#define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)2087#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)2088#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)2089 u8 num_entries;2090 __le16 vmvf_and_timeout;2091#define ICE_AQC_Q_DIS_VMVF_NUM_S 02092#define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)2093#define ICE_AQC_Q_DIS_TIMEOUT_S 102094#define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)2095 __le32 blocked_cgds;2096 __le32 addr_high;2097 __le32 addr_low;2098};2099 2100/* The buffer for Disable Tx LAN Queues (indirect 0x0C31)2101 * contains the following structures, arrayed one after the2102 * other.2103 * Note: Since the q_id is 16 bits wide, if the2104 * number of queues is even, then 2 bytes of alignment MUST be2105 * added before the start of the next group, to allow correct2106 * alignment of the parent_teid field.2107 */2108struct ice_aqc_dis_txq_item {2109 __le32 parent_teid;2110 u8 num_qs;2111 u8 rsvd;2112 /* The length of the q_id array varies according to num_qs */2113#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 152114#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \2115 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)2116#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \2117 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)2118 __le16 q_id[];2119} __packed;2120 2121/* Move/Reconfigure Tx queue (indirect 0x0C32) */2122struct ice_aqc_cfg_txqs {2123 u8 cmd_type;2124#define ICE_AQC_Q_CFG_MOVE_NODE 0x12125#define ICE_AQC_Q_CFG_TC_CHNG 0x22126#define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x32127#define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2)2128#define ICE_AQC_Q_CFG_FLUSH BIT(3)2129 u8 num_qs;2130 u8 port_num_chng;2131#define ICE_AQC_Q_CFG_SRC_PRT_M 0x72132#define ICE_AQC_Q_CFG_DST_PRT_S 32133#define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S)2134 u8 time_out;2135#define ICE_AQC_Q_CFG_TIMEOUT_S 22136#define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S)2137 __le32 blocked_cgds;2138 __le32 addr_high;2139 __le32 addr_low;2140};2141 2142/* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */2143struct ice_aqc_cfg_txq_perq {2144 __le16 q_handle;2145 u8 tc;2146 u8 rsvd;2147 __le32 q_teid;2148};2149 2150/* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */2151struct ice_aqc_cfg_txqs_buf {2152 __le32 src_parent_teid;2153 __le32 dst_parent_teid;2154 struct ice_aqc_cfg_txq_perq queue_info[];2155};2156 2157/* Add Tx RDMA Queue Set (indirect 0x0C33) */2158struct ice_aqc_add_rdma_qset {2159 u8 num_qset_grps;2160 u8 reserved[7];2161 __le32 addr_high;2162 __le32 addr_low;2163};2164 2165/* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set2166 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.2167 */2168struct ice_aqc_add_tx_rdma_qset_entry {2169 __le16 tx_qset_id;2170 u8 rsvd[2];2171 __le32 qset_teid;2172 struct ice_aqc_txsched_elem info;2173};2174 2175/* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)2176 * is an array of the following structs. Please note that the length of2177 * each struct ice_aqc_add_rdma_qset is variable due to the variable2178 * number of queues in each group!2179 */2180struct ice_aqc_add_rdma_qset_data {2181 __le32 parent_teid;2182 __le16 num_qsets;2183 u8 rsvd[2];2184 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];2185};2186 2187/* Download Package (indirect 0x0C40) */2188/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */2189struct ice_aqc_download_pkg {2190 u8 flags;2191#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x012192 u8 reserved[3];2193 __le32 reserved1;2194 __le32 addr_high;2195 __le32 addr_low;2196};2197 2198struct ice_aqc_download_pkg_resp {2199 __le32 error_offset;2200 __le32 error_info;2201 __le32 addr_high;2202 __le32 addr_low;2203};2204 2205/* Get Package Info List (indirect 0x0C43) */2206struct ice_aqc_get_pkg_info_list {2207 __le32 reserved1;2208 __le32 reserved2;2209 __le32 addr_high;2210 __le32 addr_low;2211};2212 2213/* Version format for packages */2214struct ice_pkg_ver {2215 u8 major;2216 u8 minor;2217 u8 update;2218 u8 draft;2219};2220 2221#define ICE_PKG_NAME_SIZE 322222#define ICE_SEG_ID_SIZE 282223#define ICE_SEG_NAME_SIZE 282224 2225struct ice_aqc_get_pkg_info {2226 struct ice_pkg_ver ver;2227 char name[ICE_SEG_NAME_SIZE];2228 __le32 track_id;2229 u8 is_in_nvm;2230 u8 is_active;2231 u8 is_active_at_boot;2232 u8 is_modified;2233};2234 2235/* Get Package Info List response buffer format (0x0C43) */2236struct ice_aqc_get_pkg_info_resp {2237 __le32 count;2238 struct ice_aqc_get_pkg_info pkg_info[];2239};2240 2241/* Get CGU abilities command response data structure (indirect 0x0C61) */2242struct ice_aqc_get_cgu_abilities {2243 u8 num_inputs;2244 u8 num_outputs;2245 u8 pps_dpll_idx;2246 u8 eec_dpll_idx;2247 __le32 max_in_freq;2248 __le32 max_in_phase_adj;2249 __le32 max_out_freq;2250 __le32 max_out_phase_adj;2251 u8 cgu_part_num;2252 u8 rsvd[3];2253};2254 2255/* Set CGU input config (direct 0x0C62) */2256struct ice_aqc_set_cgu_input_config {2257 u8 input_idx;2258 u8 flags1;2259#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6)2260#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7)2261 u8 flags2;2262#define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)2263#define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)2264 u8 rsvd;2265 __le32 freq;2266 __le32 phase_delay;2267 u8 rsvd2[2];2268 __le16 node_handle;2269};2270 2271/* Get CGU input config response descriptor structure (direct 0x0C63) */2272struct ice_aqc_get_cgu_input_config {2273 u8 input_idx;2274 u8 status;2275#define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0)2276#define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1)2277#define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2)2278#define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3)2279#define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4)2280#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6)2281#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7)2282 u8 type;2283#define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0)2284#define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4)2285#define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5)2286#define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6)2287 u8 flags1;2288#define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0)2289#define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2)2290#define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3)2291#define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7)2292 __le32 freq;2293 __le32 phase_delay;2294 u8 flags2;2295#define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)2296#define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)2297 u8 rsvd[1];2298 __le16 node_handle;2299};2300 2301/* Set CGU output config (direct 0x0C64) */2302struct ice_aqc_set_cgu_output_config {2303 u8 output_idx;2304 u8 flags;2305#define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0)2306#define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1)2307#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2)2308#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3)2309#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4)2310 u8 src_sel;2311#define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0)2312 u8 rsvd;2313 __le32 freq;2314 __le32 phase_delay;2315 u8 rsvd2[2];2316 __le16 node_handle;2317};2318 2319/* Get CGU output config (direct 0x0C65) */2320struct ice_aqc_get_cgu_output_config {2321 u8 output_idx;2322 u8 flags;2323#define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0)2324#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1)2325#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2)2326 u8 src_sel;2327#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 02328#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \2329 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)2330#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 52331#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \2332 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)2333 u8 rsvd;2334 __le32 freq;2335 __le32 src_freq;2336 u8 rsvd2[2];2337 __le16 node_handle;2338};2339 2340/* Get CGU DPLL status (direct 0x0C66) */2341struct ice_aqc_get_cgu_dpll_status {2342 u8 dpll_num;2343 u8 ref_state;2344#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0)2345#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1)2346#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2)2347#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3)2348#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4)2349#define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5)2350#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6)2351 u8 dpll_state;2352#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0)2353#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1)2354#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2)2355#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5)2356#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7)2357 u8 config;2358#define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)2359#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 52360#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \2361 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)2362#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 02363#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \2364 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)2365 __le32 phase_offset_h;2366 __le32 phase_offset_l;2367 u8 eec_mode;2368#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA2369#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB2370#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF2371 u8 rsvd[1];2372 __le16 node_handle;2373};2374 2375/* Set CGU DPLL config (direct 0x0C67) */2376struct ice_aqc_set_cgu_dpll_config {2377 u8 dpll_num;2378 u8 ref_state;2379#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0)2380#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1)2381#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2)2382#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3)2383#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4)2384#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5)2385#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6)2386 u8 rsvd;2387 u8 config;2388#define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)2389#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 52390#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \2391 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)2392#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 02393#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \2394 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)2395 u8 rsvd2[8];2396 u8 eec_mode;2397 u8 rsvd3[1];2398 __le16 node_handle;2399};2400 2401/* Set CGU reference priority (direct 0x0C68) */2402struct ice_aqc_set_cgu_ref_prio {2403 u8 dpll_num;2404 u8 ref_idx;2405 u8 ref_priority;2406 u8 rsvd[11];2407 __le16 node_handle;2408};2409 2410/* Get CGU reference priority (direct 0x0C69) */2411struct ice_aqc_get_cgu_ref_prio {2412 u8 dpll_num;2413 u8 ref_idx;2414 u8 ref_priority; /* Valid only in response */2415 u8 rsvd[13];2416};2417 2418/* Get CGU info (direct 0x0C6A) */2419struct ice_aqc_get_cgu_info {2420 __le32 cgu_id;2421 __le32 cgu_cfg_ver;2422 __le32 cgu_fw_ver;2423 u8 node_part_num;2424 u8 dev_rev;2425 __le16 node_handle;2426};2427 2428/* Driver Shared Parameters (direct, 0x0C90) */2429struct ice_aqc_driver_shared_params {2430 u8 set_or_get_op;2431#define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)2432#define ICE_AQC_DRIVER_PARAM_SET 02433#define ICE_AQC_DRIVER_PARAM_GET 12434 u8 param_indx;2435#define ICE_AQC_DRIVER_PARAM_MAX_IDX 152436 u8 rsvd[2];2437 __le32 param_val;2438 __le32 addr_high;2439 __le32 addr_low;2440};2441 2442/* Lan Queue Overflow Event (direct, 0x1001) */2443struct ice_aqc_event_lan_overflow {2444 __le32 prtdcb_ruptq;2445 __le32 qtx_ctl;2446 u8 reserved[8];2447};2448 2449enum ice_aqc_fw_logging_mod {2450 ICE_AQC_FW_LOG_ID_GENERAL = 0,2451 ICE_AQC_FW_LOG_ID_CTRL,2452 ICE_AQC_FW_LOG_ID_LINK,2453 ICE_AQC_FW_LOG_ID_LINK_TOPO,2454 ICE_AQC_FW_LOG_ID_DNL,2455 ICE_AQC_FW_LOG_ID_I2C,2456 ICE_AQC_FW_LOG_ID_SDP,2457 ICE_AQC_FW_LOG_ID_MDIO,2458 ICE_AQC_FW_LOG_ID_ADMINQ,2459 ICE_AQC_FW_LOG_ID_HDMA,2460 ICE_AQC_FW_LOG_ID_LLDP,2461 ICE_AQC_FW_LOG_ID_DCBX,2462 ICE_AQC_FW_LOG_ID_DCB,2463 ICE_AQC_FW_LOG_ID_XLR,2464 ICE_AQC_FW_LOG_ID_NVM,2465 ICE_AQC_FW_LOG_ID_AUTH,2466 ICE_AQC_FW_LOG_ID_VPD,2467 ICE_AQC_FW_LOG_ID_IOSF,2468 ICE_AQC_FW_LOG_ID_PARSER,2469 ICE_AQC_FW_LOG_ID_SW,2470 ICE_AQC_FW_LOG_ID_SCHEDULER,2471 ICE_AQC_FW_LOG_ID_TXQ,2472 ICE_AQC_FW_LOG_ID_RSVD,2473 ICE_AQC_FW_LOG_ID_POST,2474 ICE_AQC_FW_LOG_ID_WATCHDOG,2475 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,2476 ICE_AQC_FW_LOG_ID_MNG,2477 ICE_AQC_FW_LOG_ID_SYNCE,2478 ICE_AQC_FW_LOG_ID_HEALTH,2479 ICE_AQC_FW_LOG_ID_TSDRV,2480 ICE_AQC_FW_LOG_ID_PFREG,2481 ICE_AQC_FW_LOG_ID_MDLVER,2482 ICE_AQC_FW_LOG_ID_MAX,2483};2484 2485/* Set FW Logging configuration (indirect 0xFF30)2486 * Register for FW Logging (indirect 0xFF31)2487 * Query FW Logging (indirect 0xFF32)2488 * FW Log Event (indirect 0xFF33)2489 */2490struct ice_aqc_fw_log {2491 u8 cmd_flags;2492#define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)2493#define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)2494#define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2)2495#define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)2496#define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)2497#define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)2498 2499 u8 rsp_flag;2500 __le16 fw_rt_msb;2501 union {2502 struct {2503 __le32 fw_rt_lsb;2504 } sync;2505 struct {2506 __le16 log_resolution;2507#define ICE_AQC_FW_LOG_MIN_RESOLUTION (1)2508#define ICE_AQC_FW_LOG_MAX_RESOLUTION (128)2509 2510 __le16 mdl_cnt;2511 } cfg;2512 } ops;2513 __le32 addr_high;2514 __le32 addr_low;2515};2516 2517/* Response Buffer for:2518 * Set Firmware Logging Configuration (0xFF30)2519 * Query FW Logging (0xFF32)2520 */2521struct ice_aqc_fw_log_cfg_resp {2522 __le16 module_identifier;2523 u8 log_level;2524 u8 rsvd0;2525};2526 2527/**2528 * struct ice_aq_desc - Admin Queue (AQ) descriptor2529 * @flags: ICE_AQ_FLAG_* flags2530 * @opcode: AQ command opcode2531 * @datalen: length in bytes of indirect/external data buffer2532 * @retval: return value from firmware2533 * @cookie_high: opaque data high-half2534 * @cookie_low: opaque data low-half2535 * @params: command-specific parameters2536 *2537 * Descriptor format for commands the driver posts on the Admin Transmit Queue2538 * (ATQ). The firmware writes back onto the command descriptor and returns2539 * the result of the command. Asynchronous events that are not an immediate2540 * result of the command are written to the Admin Receive Queue (ARQ) using2541 * the same descriptor format. Descriptors are in little-endian notation with2542 * 32-bit words.2543 */2544struct ice_aq_desc {2545 __le16 flags;2546 __le16 opcode;2547 __le16 datalen;2548 __le16 retval;2549 __le32 cookie_high;2550 __le32 cookie_low;2551 union {2552 u8 raw[16];2553 struct ice_aqc_generic generic;2554 struct ice_aqc_get_ver get_ver;2555 struct ice_aqc_driver_ver driver_ver;2556 struct ice_aqc_q_shutdown q_shutdown;2557 struct ice_aqc_req_res res_owner;2558 struct ice_aqc_manage_mac_read mac_read;2559 struct ice_aqc_manage_mac_write mac_write;2560 struct ice_aqc_clear_pxe clear_pxe;2561 struct ice_aqc_list_caps get_cap;2562 struct ice_aqc_get_phy_caps get_phy;2563 struct ice_aqc_set_phy_cfg set_phy;2564 struct ice_aqc_restart_an restart_an;2565 struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out;2566 struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out;2567 struct ice_aqc_get_sensor_reading get_sensor_reading;2568 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;2569 struct ice_aqc_gpio read_write_gpio;2570 struct ice_aqc_sff_eeprom read_write_sff_param;2571 struct ice_aqc_set_port_id_led set_port_id_led;2572 struct ice_aqc_get_port_options get_port_options;2573 struct ice_aqc_set_port_option set_port_option;2574 struct ice_aqc_get_sw_cfg get_sw_conf;2575 struct ice_aqc_set_port_params set_port_params;2576 struct ice_aqc_sw_rules sw_rules;2577 struct ice_aqc_add_get_recipe add_get_recipe;2578 struct ice_aqc_recipe_to_profile recipe_to_profile;2579 struct ice_aqc_get_topo get_topo;2580 struct ice_aqc_sched_elem_cmd sched_elem_cmd;2581 struct ice_aqc_query_txsched_res query_sched_res;2582 struct ice_aqc_query_port_ets port_ets;2583 struct ice_aqc_rl_profile rl_profile;2584 struct ice_aqc_nvm nvm;2585 struct ice_aqc_nvm_checksum nvm_checksum;2586 struct ice_aqc_nvm_pkg_data pkg_data;2587 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;2588 struct ice_aqc_pf_vf_msg virt;2589 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;2590 struct ice_aqc_lldp_get_mib lldp_get_mib;2591 struct ice_aqc_lldp_set_mib_change lldp_set_event;2592 struct ice_aqc_lldp_stop lldp_stop;2593 struct ice_aqc_lldp_start lldp_start;2594 struct ice_aqc_lldp_set_local_mib lldp_set_mib;2595 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;2596 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;2597 struct ice_aqc_get_set_rss_lut get_set_rss_lut;2598 struct ice_aqc_get_set_rss_key get_set_rss_key;2599 struct ice_aqc_neigh_dev_req neigh_dev;2600 struct ice_aqc_add_txqs add_txqs;2601 struct ice_aqc_dis_txqs dis_txqs;2602 struct ice_aqc_cfg_txqs cfg_txqs;2603 struct ice_aqc_add_rdma_qset add_rdma_qset;2604 struct ice_aqc_add_get_update_free_vsi vsi_cmd;2605 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;2606 struct ice_aqc_download_pkg download_pkg;2607 struct ice_aqc_set_cgu_input_config set_cgu_input_config;2608 struct ice_aqc_get_cgu_input_config get_cgu_input_config;2609 struct ice_aqc_set_cgu_output_config set_cgu_output_config;2610 struct ice_aqc_get_cgu_output_config get_cgu_output_config;2611 struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status;2612 struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config;2613 struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio;2614 struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio;2615 struct ice_aqc_get_cgu_info get_cgu_info;2616 struct ice_aqc_driver_shared_params drv_shared_params;2617 struct ice_aqc_fw_log fw_log;2618 struct ice_aqc_set_mac_lb set_mac_lb;2619 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;2620 struct ice_aqc_set_mac_cfg set_mac_cfg;2621 struct ice_aqc_set_event_mask set_event_mask;2622 struct ice_aqc_get_link_status get_link_status;2623 struct ice_aqc_event_lan_overflow lan_overflow;2624 struct ice_aqc_get_link_topo get_link_topo;2625 struct ice_aqc_dnl_call_command dnl_call;2626 struct ice_aqc_i2c read_write_i2c;2627 struct ice_aqc_read_i2c_resp read_i2c_resp;2628 struct ice_aqc_get_set_tx_topo get_set_tx_topo;2629 } params;2630};2631 2632/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */2633#define ICE_AQ_LG_BUF 5122634 2635#define ICE_AQ_FLAG_DD_S 02636#define ICE_AQ_FLAG_CMP_S 12637#define ICE_AQ_FLAG_ERR_S 22638#define ICE_AQ_FLAG_LB_S 92639#define ICE_AQ_FLAG_RD_S 102640#define ICE_AQ_FLAG_BUF_S 122641#define ICE_AQ_FLAG_SI_S 132642 2643#define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */2644#define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */2645#define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */2646#define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */2647#define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */2648#define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */2649#define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */2650 2651/* error codes */2652enum ice_aq_err {2653 ICE_AQ_RC_OK = 0, /* Success */2654 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */2655 ICE_AQ_RC_ENOENT = 2, /* No such element */2656 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */2657 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */2658 ICE_AQ_RC_EEXIST = 13, /* Object already exists */2659 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */2660 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */2661 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */2662 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */2663 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */2664 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */2665 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */2666 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */2667 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */2668};2669 2670/* Admin Queue command opcodes */2671enum ice_adminq_opc {2672 /* AQ commands */2673 ice_aqc_opc_get_ver = 0x0001,2674 ice_aqc_opc_driver_ver = 0x0002,2675 ice_aqc_opc_q_shutdown = 0x0003,2676 2677 /* resource ownership */2678 ice_aqc_opc_req_res = 0x0008,2679 ice_aqc_opc_release_res = 0x0009,2680 2681 /* device/function capabilities */2682 ice_aqc_opc_list_func_caps = 0x000A,2683 ice_aqc_opc_list_dev_caps = 0x000B,2684 2685 /* manage MAC address */2686 ice_aqc_opc_manage_mac_read = 0x0107,2687 ice_aqc_opc_manage_mac_write = 0x0108,2688 2689 /* PXE */2690 ice_aqc_opc_clear_pxe_mode = 0x0110,2691 2692 /* internal switch commands */2693 ice_aqc_opc_get_sw_cfg = 0x0200,2694 ice_aqc_opc_set_port_params = 0x0203,2695 2696 /* Alloc/Free/Get Resources */2697 ice_aqc_opc_alloc_res = 0x0208,2698 ice_aqc_opc_free_res = 0x0209,2699 ice_aqc_opc_share_res = 0x020B,2700 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,2701 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,2702 2703 /* VSI commands */2704 ice_aqc_opc_add_vsi = 0x0210,2705 ice_aqc_opc_update_vsi = 0x0211,2706 ice_aqc_opc_free_vsi = 0x0213,2707 2708 /* recipe commands */2709 ice_aqc_opc_add_recipe = 0x0290,2710 ice_aqc_opc_recipe_to_profile = 0x0291,2711 ice_aqc_opc_get_recipe = 0x0292,2712 ice_aqc_opc_get_recipe_to_profile = 0x0293,2713 2714 /* switch rules population commands */2715 ice_aqc_opc_add_sw_rules = 0x02A0,2716 ice_aqc_opc_update_sw_rules = 0x02A1,2717 ice_aqc_opc_remove_sw_rules = 0x02A2,2718 2719 ice_aqc_opc_clear_pf_cfg = 0x02A4,2720 2721 /* DCB commands */2722 ice_aqc_opc_query_pfc_mode = 0x0302,2723 ice_aqc_opc_set_pfc_mode = 0x0303,2724 2725 /* transmit scheduler commands */2726 ice_aqc_opc_get_dflt_topo = 0x0400,2727 ice_aqc_opc_add_sched_elems = 0x0401,2728 ice_aqc_opc_cfg_sched_elems = 0x0403,2729 ice_aqc_opc_get_sched_elems = 0x0404,2730 ice_aqc_opc_move_sched_elems = 0x0408,2731 ice_aqc_opc_suspend_sched_elems = 0x0409,2732 ice_aqc_opc_resume_sched_elems = 0x040A,2733 ice_aqc_opc_query_port_ets = 0x040E,2734 ice_aqc_opc_delete_sched_elems = 0x040F,2735 ice_aqc_opc_add_rl_profiles = 0x0410,2736 ice_aqc_opc_query_sched_res = 0x0412,2737 ice_aqc_opc_remove_rl_profiles = 0x0415,2738 2739 /* tx topology commands */2740 ice_aqc_opc_set_tx_topo = 0x0417,2741 ice_aqc_opc_get_tx_topo = 0x0418,2742 2743 /* PHY commands */2744 ice_aqc_opc_get_phy_caps = 0x0600,2745 ice_aqc_opc_set_phy_cfg = 0x0601,2746 ice_aqc_opc_set_mac_cfg = 0x0603,2747 ice_aqc_opc_restart_an = 0x0605,2748 ice_aqc_opc_get_link_status = 0x0607,2749 ice_aqc_opc_set_event_mask = 0x0613,2750 ice_aqc_opc_set_mac_lb = 0x0620,2751 ice_aqc_opc_set_phy_rec_clk_out = 0x0630,2752 ice_aqc_opc_get_phy_rec_clk_out = 0x0631,2753 ice_aqc_opc_get_sensor_reading = 0x0632,2754 ice_aqc_opc_dnl_call = 0x0682,2755 ice_aqc_opc_get_link_topo = 0x06E0,2756 ice_aqc_opc_read_i2c = 0x06E2,2757 ice_aqc_opc_write_i2c = 0x06E3,2758 ice_aqc_opc_set_port_id_led = 0x06E9,2759 ice_aqc_opc_get_port_options = 0x06EA,2760 ice_aqc_opc_set_port_option = 0x06EB,2761 ice_aqc_opc_set_gpio = 0x06EC,2762 ice_aqc_opc_get_gpio = 0x06ED,2763 ice_aqc_opc_sff_eeprom = 0x06EE,2764 2765 /* NVM commands */2766 ice_aqc_opc_nvm_read = 0x0701,2767 ice_aqc_opc_nvm_erase = 0x0702,2768 ice_aqc_opc_nvm_write = 0x0703,2769 ice_aqc_opc_nvm_checksum = 0x0706,2770 ice_aqc_opc_nvm_write_activate = 0x0707,2771 ice_aqc_opc_nvm_update_empr = 0x0709,2772 ice_aqc_opc_nvm_pkg_data = 0x070A,2773 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,2774 2775 /* PF/VF mailbox commands */2776 ice_mbx_opc_send_msg_to_pf = 0x0801,2777 ice_mbx_opc_send_msg_to_vf = 0x0802,2778 /* LLDP commands */2779 ice_aqc_opc_lldp_get_mib = 0x0A00,2780 ice_aqc_opc_lldp_set_mib_change = 0x0A01,2781 ice_aqc_opc_lldp_stop = 0x0A05,2782 ice_aqc_opc_lldp_start = 0x0A06,2783 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,2784 ice_aqc_opc_lldp_set_local_mib = 0x0A08,2785 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,2786 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,2787 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B,2788 2789 /* RSS commands */2790 ice_aqc_opc_set_rss_key = 0x0B02,2791 ice_aqc_opc_set_rss_lut = 0x0B03,2792 ice_aqc_opc_get_rss_key = 0x0B04,2793 ice_aqc_opc_get_rss_lut = 0x0B05,2794 2795 /* Sideband Control Interface commands */2796 ice_aqc_opc_neighbour_device_request = 0x0C00,2797 2798 /* Tx queue handling commands/events */2799 ice_aqc_opc_add_txqs = 0x0C30,2800 ice_aqc_opc_dis_txqs = 0x0C31,2801 ice_aqc_opc_cfg_txqs = 0x0C32,2802 ice_aqc_opc_add_rdma_qset = 0x0C33,2803 2804 /* package commands */2805 ice_aqc_opc_download_pkg = 0x0C40,2806 ice_aqc_opc_upload_section = 0x0C41,2807 ice_aqc_opc_update_pkg = 0x0C42,2808 ice_aqc_opc_get_pkg_info_list = 0x0C43,2809 2810 /* 1588/SyncE commands/events */2811 ice_aqc_opc_get_cgu_abilities = 0x0C61,2812 ice_aqc_opc_set_cgu_input_config = 0x0C62,2813 ice_aqc_opc_get_cgu_input_config = 0x0C63,2814 ice_aqc_opc_set_cgu_output_config = 0x0C64,2815 ice_aqc_opc_get_cgu_output_config = 0x0C65,2816 ice_aqc_opc_get_cgu_dpll_status = 0x0C66,2817 ice_aqc_opc_set_cgu_dpll_config = 0x0C67,2818 ice_aqc_opc_set_cgu_ref_prio = 0x0C68,2819 ice_aqc_opc_get_cgu_ref_prio = 0x0C69,2820 ice_aqc_opc_get_cgu_info = 0x0C6A,2821 2822 ice_aqc_opc_driver_shared_params = 0x0C90,2823 2824 /* Standalone Commands/Events */2825 ice_aqc_opc_event_lan_overflow = 0x1001,2826 2827 /* FW Logging Commands */2828 ice_aqc_opc_fw_logs_config = 0xFF30,2829 ice_aqc_opc_fw_logs_register = 0xFF31,2830 ice_aqc_opc_fw_logs_query = 0xFF32,2831 ice_aqc_opc_fw_logs_event = 0xFF33,2832};2833 2834#endif /* _ICE_ADMINQ_CMD_H_ */2835