1207 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright (c) 2019, Intel Corporation. */3 4#include <net/xdp_sock_drv.h>5#include "ice_base.h"6#include "ice_lib.h"7#include "ice_dcb_lib.h"8#include "ice_sriov.h"9 10/**11 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI12 * @qs_cfg: gathered variables needed for PF->VSI queues assignment13 *14 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap15 */16static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)17{18 unsigned int offset, i;19 20 mutex_lock(qs_cfg->qs_mutex);21 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,22 0, qs_cfg->q_count, 0);23 if (offset >= qs_cfg->pf_map_size) {24 mutex_unlock(qs_cfg->qs_mutex);25 return -ENOMEM;26 }27 28 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);29 for (i = 0; i < qs_cfg->q_count; i++)30 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset);31 mutex_unlock(qs_cfg->qs_mutex);32 33 return 0;34}35 36/**37 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI38 * @qs_cfg: gathered variables needed for pf->vsi queues assignment39 *40 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap41 */42static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)43{44 unsigned int i, index = 0;45 46 mutex_lock(qs_cfg->qs_mutex);47 for (i = 0; i < qs_cfg->q_count; i++) {48 index = find_next_zero_bit(qs_cfg->pf_map,49 qs_cfg->pf_map_size, index);50 if (index >= qs_cfg->pf_map_size)51 goto err_scatter;52 set_bit(index, qs_cfg->pf_map);53 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index;54 }55 mutex_unlock(qs_cfg->qs_mutex);56 57 return 0;58err_scatter:59 for (index = 0; index < i; index++) {60 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);61 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;62 }63 mutex_unlock(qs_cfg->qs_mutex);64 65 return -ENOMEM;66}67 68/**69 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled70 * @pf: the PF being configured71 * @pf_q: the PF queue72 * @ena: enable or disable state of the queue73 *74 * This routine will wait for the given Rx queue of the PF to reach the75 * enabled or disabled state.76 * Returns -ETIMEDOUT in case of failing to reach the requested state after77 * multiple retries; else will return 0 in case of success.78 */79static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)80{81 int i;82 83 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {84 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &85 QRX_CTRL_QENA_STAT_M))86 return 0;87 88 usleep_range(20, 40);89 }90 91 return -ETIMEDOUT;92}93 94/**95 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector96 * @vsi: the VSI being configured97 * @v_idx: index of the vector in the VSI struct98 *99 * We allocate one q_vector and set default value for ITR setting associated100 * with this q_vector. If allocation fails we return -ENOMEM.101 */102static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx)103{104 struct ice_pf *pf = vsi->back;105 struct ice_q_vector *q_vector;106 int err;107 108 /* allocate q_vector */109 q_vector = kzalloc(sizeof(*q_vector), GFP_KERNEL);110 if (!q_vector)111 return -ENOMEM;112 113 q_vector->vsi = vsi;114 q_vector->v_idx = v_idx;115 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR;116 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR;117 q_vector->tx.itr_mode = ITR_DYNAMIC;118 q_vector->rx.itr_mode = ITR_DYNAMIC;119 q_vector->tx.type = ICE_TX_CONTAINER;120 q_vector->rx.type = ICE_RX_CONTAINER;121 q_vector->irq.index = -ENOENT;122 123 if (vsi->type == ICE_VSI_VF) {124 ice_calc_vf_reg_idx(vsi->vf, q_vector);125 goto out;126 } else if (vsi->type == ICE_VSI_CTRL && vsi->vf) {127 struct ice_vsi *ctrl_vsi = ice_get_vf_ctrl_vsi(pf, vsi);128 129 if (ctrl_vsi) {130 if (unlikely(!ctrl_vsi->q_vectors)) {131 err = -ENOENT;132 goto err_free_q_vector;133 }134 135 q_vector->irq = ctrl_vsi->q_vectors[0]->irq;136 goto skip_alloc;137 }138 }139 140 q_vector->irq = ice_alloc_irq(pf, vsi->irq_dyn_alloc);141 if (q_vector->irq.index < 0) {142 err = -ENOMEM;143 goto err_free_q_vector;144 }145 146skip_alloc:147 q_vector->reg_idx = q_vector->irq.index;148 q_vector->vf_reg_idx = q_vector->irq.index;149 150 /* only set affinity_mask if the CPU is online */151 if (cpu_online(v_idx))152 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);153 154 /* This will not be called in the driver load path because the netdev155 * will not be created yet. All other cases with register the NAPI156 * handler here (i.e. resume, reset/rebuild, etc.)157 */158 if (vsi->netdev)159 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll);160 161out:162 /* tie q_vector and VSI together */163 vsi->q_vectors[v_idx] = q_vector;164 165 return 0;166 167err_free_q_vector:168 kfree(q_vector);169 170 return err;171}172 173/**174 * ice_free_q_vector - Free memory allocated for a specific interrupt vector175 * @vsi: VSI having the memory freed176 * @v_idx: index of the vector to be freed177 */178static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)179{180 struct ice_q_vector *q_vector;181 struct ice_pf *pf = vsi->back;182 struct ice_tx_ring *tx_ring;183 struct ice_rx_ring *rx_ring;184 struct device *dev;185 186 dev = ice_pf_to_dev(pf);187 if (!vsi->q_vectors[v_idx]) {188 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx);189 return;190 }191 q_vector = vsi->q_vectors[v_idx];192 193 ice_for_each_tx_ring(tx_ring, vsi->q_vectors[v_idx]->tx)194 tx_ring->q_vector = NULL;195 196 ice_for_each_rx_ring(rx_ring, vsi->q_vectors[v_idx]->rx)197 rx_ring->q_vector = NULL;198 199 /* only VSI with an associated netdev is set up with NAPI */200 if (vsi->netdev)201 netif_napi_del(&q_vector->napi);202 203 /* release MSIX interrupt if q_vector had interrupt allocated */204 if (q_vector->irq.index < 0)205 goto free_q_vector;206 207 /* only free last VF ctrl vsi interrupt */208 if (vsi->type == ICE_VSI_CTRL && vsi->vf &&209 ice_get_vf_ctrl_vsi(pf, vsi))210 goto free_q_vector;211 212 ice_free_irq(pf, q_vector->irq);213 214free_q_vector:215 kfree(q_vector);216 vsi->q_vectors[v_idx] = NULL;217}218 219/**220 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set221 * @hw: board specific structure222 */223static void ice_cfg_itr_gran(struct ice_hw *hw)224{225 u32 regval = rd32(hw, GLINT_CTL);226 227 /* no need to update global register if ITR gran is already set */228 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&229 (FIELD_GET(GLINT_CTL_ITR_GRAN_200_M, regval) == ICE_ITR_GRAN_US) &&230 (FIELD_GET(GLINT_CTL_ITR_GRAN_100_M, regval) == ICE_ITR_GRAN_US) &&231 (FIELD_GET(GLINT_CTL_ITR_GRAN_50_M, regval) == ICE_ITR_GRAN_US) &&232 (FIELD_GET(GLINT_CTL_ITR_GRAN_25_M, regval) == ICE_ITR_GRAN_US))233 return;234 235 regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) |236 FIELD_PREP(GLINT_CTL_ITR_GRAN_100_M, ICE_ITR_GRAN_US) |237 FIELD_PREP(GLINT_CTL_ITR_GRAN_50_M, ICE_ITR_GRAN_US) |238 FIELD_PREP(GLINT_CTL_ITR_GRAN_25_M, ICE_ITR_GRAN_US);239 wr32(hw, GLINT_CTL, regval);240}241 242/**243 * ice_calc_txq_handle - calculate the queue handle244 * @vsi: VSI that ring belongs to245 * @ring: ring to get the absolute queue index246 * @tc: traffic class number247 */248static u16 ice_calc_txq_handle(struct ice_vsi *vsi, struct ice_tx_ring *ring, u8 tc)249{250 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n");251 252 if (ring->ch)253 return ring->q_index - ring->ch->base_q;254 255 /* Idea here for calculation is that we subtract the number of queue256 * count from TC that ring belongs to from it's absolute queue index257 * and as a result we get the queue's index within TC.258 */259 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset;260}261 262/**263 * ice_cfg_xps_tx_ring - Configure XPS for a Tx ring264 * @ring: The Tx ring to configure265 *266 * This enables/disables XPS for a given Tx descriptor ring267 * based on the TCs enabled for the VSI that ring belongs to.268 */269static void ice_cfg_xps_tx_ring(struct ice_tx_ring *ring)270{271 if (!ring->q_vector || !ring->netdev)272 return;273 274 /* We only initialize XPS once, so as not to overwrite user settings */275 if (test_and_set_bit(ICE_TX_XPS_INIT_DONE, ring->xps_state))276 return;277 278 netif_set_xps_queue(ring->netdev, &ring->q_vector->affinity_mask,279 ring->q_index);280}281 282/**283 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance284 * @ring: The Tx ring to configure285 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized286 * @pf_q: queue index in the PF space287 *288 * Configure the Tx descriptor ring in TLAN context.289 */290static void291ice_setup_tx_ctx(struct ice_tx_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)292{293 struct ice_vsi *vsi = ring->vsi;294 struct ice_hw *hw = &vsi->back->hw;295 296 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;297 298 tlan_ctx->port_num = vsi->port_info->lport;299 300 /* Transmit Queue Length */301 tlan_ctx->qlen = ring->count;302 303 ice_set_cgd_num(tlan_ctx, ring->dcb_tc);304 305 /* PF number */306 tlan_ctx->pf_num = hw->pf_id;307 308 /* queue belongs to a specific VSI type309 * VF / VM index should be programmed per vmvf_type setting:310 * for vmvf_type = VF, it is VF number between 0-256311 * for vmvf_type = VM, it is VM number between 0-767312 * for PF or EMP this field should be set to zero313 */314 switch (vsi->type) {315 case ICE_VSI_LB:316 case ICE_VSI_CTRL:317 case ICE_VSI_PF:318 if (ring->ch)319 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ;320 else321 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;322 break;323 case ICE_VSI_VF:324 /* Firmware expects vmvf_num to be absolute VF ID */325 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf->vf_id;326 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;327 break;328 case ICE_VSI_SF:329 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ;330 break;331 default:332 return;333 }334 335 /* make sure the context is associated with the right VSI */336 if (ring->ch)337 tlan_ctx->src_vsi = ring->ch->vsi_num;338 else339 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);340 341 /* Restrict Tx timestamps to the PF VSI */342 switch (vsi->type) {343 case ICE_VSI_PF:344 tlan_ctx->tsyn_ena = 1;345 break;346 default:347 break;348 }349 350 tlan_ctx->tso_ena = ICE_TX_LEGACY;351 tlan_ctx->tso_qnum = pf_q;352 353 /* Legacy or Advanced Host Interface:354 * 0: Advanced Host Interface355 * 1: Legacy Host Interface356 */357 tlan_ctx->legacy_int = ICE_TX_LEGACY;358}359 360/**361 * ice_rx_offset - Return expected offset into page to access data362 * @rx_ring: Ring we are requesting offset of363 *364 * Returns the offset value for ring into the data buffer.365 */366static unsigned int ice_rx_offset(struct ice_rx_ring *rx_ring)367{368 if (ice_ring_uses_build_skb(rx_ring))369 return ICE_SKB_PAD;370 return 0;371}372 373/**374 * ice_setup_rx_ctx - Configure a receive ring context375 * @ring: The Rx ring to configure376 *377 * Configure the Rx descriptor ring in RLAN context.378 */379static int ice_setup_rx_ctx(struct ice_rx_ring *ring)380{381 struct ice_vsi *vsi = ring->vsi;382 u32 rxdid = ICE_RXDID_FLEX_NIC;383 struct ice_rlan_ctx rlan_ctx;384 struct ice_hw *hw;385 u16 pf_q;386 int err;387 388 hw = &vsi->back->hw;389 390 /* what is Rx queue number in global space of 2K Rx queues */391 pf_q = vsi->rxq_map[ring->q_index];392 393 /* clear the context structure first */394 memset(&rlan_ctx, 0, sizeof(rlan_ctx));395 396 /* Receive Queue Base Address.397 * Indicates the starting address of the descriptor queue defined in398 * 128 Byte units.399 */400 rlan_ctx.base = ring->dma >> ICE_RLAN_BASE_S;401 402 rlan_ctx.qlen = ring->count;403 404 /* Receive Packet Data Buffer Size.405 * The Packet Data Buffer Size is defined in 128 byte units.406 */407 rlan_ctx.dbuf = DIV_ROUND_UP(ring->rx_buf_len,408 BIT_ULL(ICE_RLAN_CTX_DBUF_S));409 410 /* use 32 byte descriptors */411 rlan_ctx.dsize = 1;412 413 /* Strip the Ethernet CRC bytes before the packet is posted to host414 * memory.415 */416 rlan_ctx.crcstrip = !(ring->flags & ICE_RX_FLAGS_CRC_STRIP_DIS);417 418 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor419 * and it needs to remain 1 for non-DVM capable configurations to not420 * break backward compatibility for VF drivers. Setting this field to 0421 * will cause the single/outer VLAN tag to be stripped to the L2TAG2_2ND422 * field in the Rx descriptor. Setting it to 1 allows the VLAN tag to423 * be stripped in L2TAG1 of the Rx descriptor, which is where VFs will424 * check for the tag425 */426 if (ice_is_dvm_ena(hw))427 if (vsi->type == ICE_VSI_VF &&428 ice_vf_is_port_vlan_ena(vsi->vf))429 rlan_ctx.l2tsel = 1;430 else431 rlan_ctx.l2tsel = 0;432 else433 rlan_ctx.l2tsel = 1;434 435 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;436 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;437 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;438 439 /* This controls whether VLAN is stripped from inner headers440 * The VLAN in the inner L2 header is stripped to the receive441 * descriptor if enabled by this flag.442 */443 rlan_ctx.showiv = 0;444 445 /* Max packet size for this queue - must not be set to a larger value446 * than 5 x DBUF447 */448 rlan_ctx.rxmax = min_t(u32, vsi->max_frame,449 ICE_MAX_CHAINED_RX_BUFS * ring->rx_buf_len);450 451 /* Rx queue threshold in units of 64 */452 rlan_ctx.lrxqthresh = 1;453 454 /* PF acts as uplink for switchdev; set flex descriptor with src_vsi455 * metadata and flags to allow redirecting to PR netdev456 */457 if (ice_is_eswitch_mode_switchdev(vsi->back)) {458 ring->flags |= ICE_RX_FLAGS_MULTIDEV;459 rxdid = ICE_RXDID_FLEX_NIC_2;460 }461 462 /* Enable Flexible Descriptors in the queue context which463 * allows this driver to select a specific receive descriptor format464 * increasing context priority to pick up profile ID; default is 0x01;465 * setting to 0x03 to ensure profile is programming if prev context is466 * of same priority467 */468 if (vsi->type != ICE_VSI_VF)469 ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3, true);470 else471 ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3,472 false);473 474 /* Absolute queue number out of 2K needs to be passed */475 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);476 if (err) {477 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",478 pf_q, err);479 return -EIO;480 }481 482 if (vsi->type == ICE_VSI_VF)483 return 0;484 485 /* configure Rx buffer alignment */486 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags))487 ice_clear_ring_build_skb_ena(ring);488 else489 ice_set_ring_build_skb_ena(ring);490 491 ring->rx_offset = ice_rx_offset(ring);492 493 /* init queue specific tail register */494 ring->tail = hw->hw_addr + QRX_TAIL(pf_q);495 writel(0, ring->tail);496 497 return 0;498}499 500static void ice_xsk_pool_fill_cb(struct ice_rx_ring *ring)501{502 void *ctx_ptr = &ring->pkt_ctx;503 struct xsk_cb_desc desc = {};504 505 XSK_CHECK_PRIV_TYPE(struct ice_xdp_buff);506 desc.src = &ctx_ptr;507 desc.off = offsetof(struct ice_xdp_buff, pkt_ctx) -508 sizeof(struct xdp_buff);509 desc.bytes = sizeof(ctx_ptr);510 xsk_pool_fill_cb(ring->xsk_pool, &desc);511}512 513/**514 * ice_get_frame_sz - calculate xdp_buff::frame_sz515 * @rx_ring: the ring being configured516 *517 * Return frame size based on underlying PAGE_SIZE518 */519static unsigned int ice_get_frame_sz(struct ice_rx_ring *rx_ring)520{521 unsigned int frame_sz;522 523#if (PAGE_SIZE >= 8192)524 frame_sz = rx_ring->rx_buf_len;525#else526 frame_sz = ice_rx_pg_size(rx_ring) / 2;527#endif528 529 return frame_sz;530}531 532/**533 * ice_vsi_cfg_rxq - Configure an Rx queue534 * @ring: the ring being configured535 *536 * Return 0 on success and a negative value on error.537 */538static int ice_vsi_cfg_rxq(struct ice_rx_ring *ring)539{540 struct device *dev = ice_pf_to_dev(ring->vsi->back);541 u32 num_bufs = ICE_RX_DESC_UNUSED(ring);542 int err;543 544 ring->rx_buf_len = ring->vsi->rx_buf_len;545 546 if (ring->vsi->type == ICE_VSI_PF || ring->vsi->type == ICE_VSI_SF) {547 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) {548 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,549 ring->q_index,550 ring->q_vector->napi.napi_id,551 ring->rx_buf_len);552 if (err)553 return err;554 }555 556 ice_rx_xsk_pool(ring);557 if (ring->xsk_pool) {558 xdp_rxq_info_unreg(&ring->xdp_rxq);559 560 ring->rx_buf_len =561 xsk_pool_get_rx_frame_size(ring->xsk_pool);562 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,563 ring->q_index,564 ring->q_vector->napi.napi_id,565 ring->rx_buf_len);566 if (err)567 return err;568 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,569 MEM_TYPE_XSK_BUFF_POOL,570 NULL);571 if (err)572 return err;573 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);574 ice_xsk_pool_fill_cb(ring);575 576 dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n",577 ring->q_index);578 } else {579 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) {580 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,581 ring->q_index,582 ring->q_vector->napi.napi_id,583 ring->rx_buf_len);584 if (err)585 return err;586 }587 588 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,589 MEM_TYPE_PAGE_SHARED,590 NULL);591 if (err)592 return err;593 }594 }595 596 xdp_init_buff(&ring->xdp, ice_get_frame_sz(ring), &ring->xdp_rxq);597 ring->xdp.data = NULL;598 ring->xdp_ext.pkt_ctx = &ring->pkt_ctx;599 err = ice_setup_rx_ctx(ring);600 if (err) {601 dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n",602 ring->q_index, err);603 return err;604 }605 606 if (ring->xsk_pool) {607 bool ok;608 609 if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) {610 dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n",611 num_bufs, ring->q_index);612 dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n");613 614 return 0;615 }616 617 ok = ice_alloc_rx_bufs_zc(ring, ring->xsk_pool, num_bufs);618 if (!ok) {619 u16 pf_q = ring->vsi->rxq_map[ring->q_index];620 621 dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n",622 ring->q_index, pf_q);623 }624 625 return 0;626 }627 628 ice_alloc_rx_bufs(ring, num_bufs);629 630 return 0;631}632 633int ice_vsi_cfg_single_rxq(struct ice_vsi *vsi, u16 q_idx)634{635 if (q_idx >= vsi->num_rxq)636 return -EINVAL;637 638 return ice_vsi_cfg_rxq(vsi->rx_rings[q_idx]);639}640 641/**642 * ice_vsi_cfg_frame_size - setup max frame size and Rx buffer length643 * @vsi: VSI644 */645static void ice_vsi_cfg_frame_size(struct ice_vsi *vsi)646{647 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) {648 vsi->max_frame = ICE_MAX_FRAME_LEGACY_RX;649 vsi->rx_buf_len = ICE_RXBUF_1664;650#if (PAGE_SIZE < 8192)651 } else if (!ICE_2K_TOO_SMALL_WITH_PADDING &&652 (vsi->netdev->mtu <= ETH_DATA_LEN)) {653 vsi->max_frame = ICE_RXBUF_1536 - NET_IP_ALIGN;654 vsi->rx_buf_len = ICE_RXBUF_1536 - NET_IP_ALIGN;655#endif656 } else {657 vsi->max_frame = ICE_AQ_SET_MAC_FRAME_SIZE_MAX;658 vsi->rx_buf_len = ICE_RXBUF_3072;659 }660}661 662/**663 * ice_vsi_cfg_rxqs - Configure the VSI for Rx664 * @vsi: the VSI being configured665 *666 * Return 0 on success and a negative value on error667 * Configure the Rx VSI for operation.668 */669int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)670{671 u16 i;672 673 if (vsi->type == ICE_VSI_VF)674 goto setup_rings;675 676 ice_vsi_cfg_frame_size(vsi);677setup_rings:678 /* set up individual rings */679 ice_for_each_rxq(vsi, i) {680 int err = ice_vsi_cfg_rxq(vsi->rx_rings[i]);681 682 if (err)683 return err;684 }685 686 return 0;687}688 689/**690 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI691 * @qs_cfg: gathered variables needed for pf->vsi queues assignment692 *693 * This function first tries to find contiguous space. If it is not successful,694 * it tries with the scatter approach.695 *696 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap697 */698int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)699{700 int ret = 0;701 702 ret = __ice_vsi_get_qs_contig(qs_cfg);703 if (ret) {704 /* contig failed, so try with scatter approach */705 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;706 qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count,707 qs_cfg->scatter_count);708 ret = __ice_vsi_get_qs_sc(qs_cfg);709 }710 return ret;711}712 713/**714 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait715 * @vsi: the VSI being configured716 * @ena: start or stop the Rx ring717 * @rxq_idx: 0-based Rx queue index for the VSI passed in718 * @wait: wait or don't wait for configuration to finish in hardware719 *720 * Return 0 on success and negative on error.721 */722int723ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait)724{725 int pf_q = vsi->rxq_map[rxq_idx];726 struct ice_pf *pf = vsi->back;727 struct ice_hw *hw = &pf->hw;728 u32 rx_reg;729 730 rx_reg = rd32(hw, QRX_CTRL(pf_q));731 732 /* Skip if the queue is already in the requested state */733 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))734 return 0;735 736 /* turn on/off the queue */737 if (ena)738 rx_reg |= QRX_CTRL_QENA_REQ_M;739 else740 rx_reg &= ~QRX_CTRL_QENA_REQ_M;741 wr32(hw, QRX_CTRL(pf_q), rx_reg);742 743 if (!wait)744 return 0;745 746 ice_flush(hw);747 return ice_pf_rxq_wait(pf, pf_q, ena);748}749 750/**751 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started752 * @vsi: the VSI being configured753 * @ena: true/false to verify Rx ring has been enabled/disabled respectively754 * @rxq_idx: 0-based Rx queue index for the VSI passed in755 *756 * This routine will wait for the given Rx queue of the VSI to reach the757 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach758 * the requested state after multiple retries; else will return 0 in case of759 * success.760 */761int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx)762{763 int pf_q = vsi->rxq_map[rxq_idx];764 struct ice_pf *pf = vsi->back;765 766 return ice_pf_rxq_wait(pf, pf_q, ena);767}768 769/**770 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors771 * @vsi: the VSI being configured772 *773 * We allocate one q_vector per queue interrupt. If allocation fails we774 * return -ENOMEM.775 */776int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)777{778 struct device *dev = ice_pf_to_dev(vsi->back);779 u16 v_idx;780 int err;781 782 if (vsi->q_vectors[0]) {783 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num);784 return -EEXIST;785 }786 787 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) {788 err = ice_vsi_alloc_q_vector(vsi, v_idx);789 if (err)790 goto err_out;791 }792 793 return 0;794 795err_out:796 while (v_idx--)797 ice_free_q_vector(vsi, v_idx);798 799 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n",800 vsi->num_q_vectors, vsi->vsi_num, err);801 vsi->num_q_vectors = 0;802 return err;803}804 805/**806 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors807 * @vsi: the VSI being configured808 *809 * This function maps descriptor rings to the queue-specific vectors allotted810 * through the MSI-X enabling code. On a constrained vector budget, we map Tx811 * and Rx rings to the vector as "efficiently" as possible.812 */813void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)814{815 int q_vectors = vsi->num_q_vectors;816 u16 tx_rings_rem, rx_rings_rem;817 int v_id;818 819 /* initially assigning remaining rings count to VSIs num queue value */820 tx_rings_rem = vsi->num_txq;821 rx_rings_rem = vsi->num_rxq;822 823 for (v_id = 0; v_id < q_vectors; v_id++) {824 struct ice_q_vector *q_vector = vsi->q_vectors[v_id];825 u8 tx_rings_per_v, rx_rings_per_v;826 u16 q_id, q_base;827 828 /* Tx rings mapping to vector */829 tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem,830 q_vectors - v_id);831 q_vector->num_ring_tx = tx_rings_per_v;832 q_vector->tx.tx_ring = NULL;833 q_vector->tx.itr_idx = ICE_TX_ITR;834 q_base = vsi->num_txq - tx_rings_rem;835 836 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {837 struct ice_tx_ring *tx_ring = vsi->tx_rings[q_id];838 839 tx_ring->q_vector = q_vector;840 tx_ring->next = q_vector->tx.tx_ring;841 q_vector->tx.tx_ring = tx_ring;842 }843 tx_rings_rem -= tx_rings_per_v;844 845 /* Rx rings mapping to vector */846 rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem,847 q_vectors - v_id);848 q_vector->num_ring_rx = rx_rings_per_v;849 q_vector->rx.rx_ring = NULL;850 q_vector->rx.itr_idx = ICE_RX_ITR;851 q_base = vsi->num_rxq - rx_rings_rem;852 853 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {854 struct ice_rx_ring *rx_ring = vsi->rx_rings[q_id];855 856 rx_ring->q_vector = q_vector;857 rx_ring->next = q_vector->rx.rx_ring;858 q_vector->rx.rx_ring = rx_ring;859 }860 rx_rings_rem -= rx_rings_per_v;861 }862 863 if (ice_is_xdp_ena_vsi(vsi))864 ice_map_xdp_rings(vsi);865}866 867/**868 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors869 * @vsi: the VSI having memory freed870 */871void ice_vsi_free_q_vectors(struct ice_vsi *vsi)872{873 int v_idx;874 875 ice_for_each_q_vector(vsi, v_idx)876 ice_free_q_vector(vsi, v_idx);877 878 vsi->num_q_vectors = 0;879}880 881/**882 * ice_vsi_cfg_txq - Configure single Tx queue883 * @vsi: the VSI that queue belongs to884 * @ring: Tx ring to be configured885 * @qg_buf: queue group buffer886 */887static int888ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_tx_ring *ring,889 struct ice_aqc_add_tx_qgrp *qg_buf)890{891 u8 buf_len = struct_size(qg_buf, txqs, 1);892 struct ice_tlan_ctx tlan_ctx = { 0 };893 struct ice_aqc_add_txqs_perq *txq;894 struct ice_channel *ch = ring->ch;895 struct ice_pf *pf = vsi->back;896 struct ice_hw *hw = &pf->hw;897 int status;898 u16 pf_q;899 u8 tc;900 901 /* Configure XPS */902 ice_cfg_xps_tx_ring(ring);903 904 pf_q = ring->reg_idx;905 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);906 /* copy context contents into the qg_buf */907 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);908 ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,909 ice_tlan_ctx_info);910 911 /* init queue specific tail reg. It is referred as912 * transmit comm scheduler queue doorbell.913 */914 ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q);915 916 if (IS_ENABLED(CONFIG_DCB))917 tc = ring->dcb_tc;918 else919 tc = 0;920 921 /* Add unique software queue handle of the Tx queue per922 * TC into the VSI Tx ring923 */924 ring->q_handle = ice_calc_txq_handle(vsi, ring, tc);925 926 if (ch)927 status = ice_ena_vsi_txq(vsi->port_info, ch->ch_vsi->idx, 0,928 ring->q_handle, 1, qg_buf, buf_len,929 NULL);930 else931 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc,932 ring->q_handle, 1, qg_buf, buf_len,933 NULL);934 if (status) {935 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %d\n",936 status);937 return status;938 }939 940 /* Add Tx Queue TEID into the VSI Tx ring from the941 * response. This will complete configuring and942 * enabling the queue.943 */944 txq = &qg_buf->txqs[0];945 if (pf_q == le16_to_cpu(txq->txq_id))946 ring->txq_teid = le32_to_cpu(txq->q_teid);947 948 return 0;949}950 951int ice_vsi_cfg_single_txq(struct ice_vsi *vsi, struct ice_tx_ring **tx_rings,952 u16 q_idx)953{954 DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1);955 956 if (q_idx >= vsi->alloc_txq || !tx_rings || !tx_rings[q_idx])957 return -EINVAL;958 959 qg_buf->num_txqs = 1;960 961 return ice_vsi_cfg_txq(vsi, tx_rings[q_idx], qg_buf);962}963 964/**965 * ice_vsi_cfg_txqs - Configure the VSI for Tx966 * @vsi: the VSI being configured967 * @rings: Tx ring array to be configured968 * @count: number of Tx ring array elements969 *970 * Return 0 on success and a negative value on error971 * Configure the Tx VSI for operation.972 */973static int974ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_tx_ring **rings, u16 count)975{976 DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1);977 int err = 0;978 u16 q_idx;979 980 qg_buf->num_txqs = 1;981 982 for (q_idx = 0; q_idx < count; q_idx++) {983 err = ice_vsi_cfg_txq(vsi, rings[q_idx], qg_buf);984 if (err)985 break;986 }987 988 return err;989}990 991/**992 * ice_vsi_cfg_lan_txqs - Configure the VSI for Tx993 * @vsi: the VSI being configured994 *995 * Return 0 on success and a negative value on error996 * Configure the Tx VSI for operation.997 */998int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi)999{1000 return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, vsi->num_txq);1001}1002 1003/**1004 * ice_vsi_cfg_xdp_txqs - Configure Tx queues dedicated for XDP in given VSI1005 * @vsi: the VSI being configured1006 *1007 * Return 0 on success and a negative value on error1008 * Configure the Tx queues dedicated for XDP in given VSI for operation.1009 */1010int ice_vsi_cfg_xdp_txqs(struct ice_vsi *vsi)1011{1012 int ret;1013 int i;1014 1015 ret = ice_vsi_cfg_txqs(vsi, vsi->xdp_rings, vsi->num_xdp_txq);1016 if (ret)1017 return ret;1018 1019 ice_for_each_rxq(vsi, i)1020 ice_tx_xsk_pool(vsi, i);1021 1022 return 0;1023}1024 1025/**1026 * ice_cfg_itr - configure the initial interrupt throttle values1027 * @hw: pointer to the HW structure1028 * @q_vector: interrupt vector that's being configured1029 *1030 * Configure interrupt throttling values for the ring containers that are1031 * associated with the interrupt vector passed in.1032 */1033void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)1034{1035 ice_cfg_itr_gran(hw);1036 1037 if (q_vector->num_ring_rx)1038 ice_write_itr(&q_vector->rx, q_vector->rx.itr_setting);1039 1040 if (q_vector->num_ring_tx)1041 ice_write_itr(&q_vector->tx, q_vector->tx.itr_setting);1042 1043 ice_write_intrl(q_vector, q_vector->intrl);1044}1045 1046/**1047 * ice_cfg_txq_interrupt - configure interrupt on Tx queue1048 * @vsi: the VSI being configured1049 * @txq: Tx queue being mapped to MSI-X vector1050 * @msix_idx: MSI-X vector index within the function1051 * @itr_idx: ITR index of the interrupt cause1052 *1053 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector1054 * within the function space.1055 */1056void1057ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)1058{1059 struct ice_pf *pf = vsi->back;1060 struct ice_hw *hw = &pf->hw;1061 u32 val;1062 1063 itr_idx = FIELD_PREP(QINT_TQCTL_ITR_INDX_M, itr_idx);1064 1065 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |1066 FIELD_PREP(QINT_TQCTL_MSIX_INDX_M, msix_idx);1067 1068 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);1069 if (ice_is_xdp_ena_vsi(vsi)) {1070 u32 xdp_txq = txq + vsi->num_xdp_txq;1071 1072 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]),1073 val);1074 }1075 ice_flush(hw);1076}1077 1078/**1079 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue1080 * @vsi: the VSI being configured1081 * @rxq: Rx queue being mapped to MSI-X vector1082 * @msix_idx: MSI-X vector index within the function1083 * @itr_idx: ITR index of the interrupt cause1084 *1085 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector1086 * within the function space.1087 */1088void1089ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)1090{1091 struct ice_pf *pf = vsi->back;1092 struct ice_hw *hw = &pf->hw;1093 u32 val;1094 1095 itr_idx = FIELD_PREP(QINT_RQCTL_ITR_INDX_M, itr_idx);1096 1097 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |1098 FIELD_PREP(QINT_RQCTL_MSIX_INDX_M, msix_idx);1099 1100 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);1101 1102 ice_flush(hw);1103}1104 1105/**1106 * ice_trigger_sw_intr - trigger a software interrupt1107 * @hw: pointer to the HW structure1108 * @q_vector: interrupt vector to trigger the software interrupt for1109 */1110void ice_trigger_sw_intr(struct ice_hw *hw, const struct ice_q_vector *q_vector)1111{1112 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),1113 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |1114 GLINT_DYN_CTL_SWINT_TRIG_M |1115 GLINT_DYN_CTL_INTENA_M);1116}1117 1118/**1119 * ice_vsi_stop_tx_ring - Disable single Tx ring1120 * @vsi: the VSI being configured1121 * @rst_src: reset source1122 * @rel_vmvf_num: Relative ID of VF/VM1123 * @ring: Tx ring to be stopped1124 * @txq_meta: Meta data of Tx ring to be stopped1125 */1126int1127ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,1128 u16 rel_vmvf_num, struct ice_tx_ring *ring,1129 struct ice_txq_meta *txq_meta)1130{1131 struct ice_pf *pf = vsi->back;1132 struct ice_q_vector *q_vector;1133 struct ice_hw *hw = &pf->hw;1134 int status;1135 u32 val;1136 1137 /* clear cause_ena bit for disabled queues */1138 val = rd32(hw, QINT_TQCTL(ring->reg_idx));1139 val &= ~QINT_TQCTL_CAUSE_ENA_M;1140 wr32(hw, QINT_TQCTL(ring->reg_idx), val);1141 1142 /* software is expected to wait for 100 ns */1143 ndelay(100);1144 1145 /* trigger a software interrupt for the vector1146 * associated to the queue to schedule NAPI handler1147 */1148 q_vector = ring->q_vector;1149 if (q_vector && !(vsi->vf && ice_is_vf_disabled(vsi->vf)))1150 ice_trigger_sw_intr(hw, q_vector);1151 1152 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,1153 txq_meta->tc, 1, &txq_meta->q_handle,1154 &txq_meta->q_id, &txq_meta->q_teid, rst_src,1155 rel_vmvf_num, NULL);1156 1157 /* if the disable queue command was exercised during an1158 * active reset flow, -EBUSY is returned.1159 * This is not an error as the reset operation disables1160 * queues at the hardware level anyway.1161 */1162 if (status == -EBUSY) {1163 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n");1164 } else if (status == -ENOENT) {1165 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n");1166 } else if (status) {1167 dev_dbg(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %d\n",1168 status);1169 return status;1170 }1171 1172 return 0;1173}1174 1175/**1176 * ice_fill_txq_meta - Prepare the Tx queue's meta data1177 * @vsi: VSI that ring belongs to1178 * @ring: ring that txq_meta will be based on1179 * @txq_meta: a helper struct that wraps Tx queue's information1180 *1181 * Set up a helper struct that will contain all the necessary fields that1182 * are needed for stopping Tx queue1183 */1184void1185ice_fill_txq_meta(const struct ice_vsi *vsi, struct ice_tx_ring *ring,1186 struct ice_txq_meta *txq_meta)1187{1188 struct ice_channel *ch = ring->ch;1189 u8 tc;1190 1191 if (IS_ENABLED(CONFIG_DCB))1192 tc = ring->dcb_tc;1193 else1194 tc = 0;1195 1196 txq_meta->q_id = ring->reg_idx;1197 txq_meta->q_teid = ring->txq_teid;1198 txq_meta->q_handle = ring->q_handle;1199 if (ch) {1200 txq_meta->vsi_idx = ch->ch_vsi->idx;1201 txq_meta->tc = 0;1202 } else {1203 txq_meta->vsi_idx = vsi->idx;1204 txq_meta->tc = tc;1205 }1206}1207