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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018, Intel Corporation. */3 4#ifndef _ICE_COMMON_H_5#define _ICE_COMMON_H_6 7#include <linux/bitfield.h>8 9#include "ice.h"10#include "ice_type.h"11#include "ice_nvm.h"12#include "ice_flex_pipe.h"13#include "ice_parser.h"14#include <linux/avf/virtchnl.h>15#include "ice_switch.h"16#include "ice_fdir.h"17 18#define ICE_SQ_SEND_DELAY_TIME_MS 1019#define ICE_SQ_SEND_MAX_EXECUTE 320 21#define FEC_REG_SHIFT 222#define FEC_RECV_ID_SHIFT 423#define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT)24#define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT)25#define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT)26#define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT)27#define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT)28#define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT)29#define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT)30#define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT)31#define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT)32#define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT)33#define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT)34#define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT)35#define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT)36#define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT)37#define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT)38#define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT)39#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)40#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)41 42int ice_init_hw(struct ice_hw *hw);43void ice_deinit_hw(struct ice_hw *hw);44int ice_check_reset(struct ice_hw *hw);45int ice_reset(struct ice_hw *hw, enum ice_reset_req req);46int ice_create_all_ctrlq(struct ice_hw *hw);47int ice_init_all_ctrlq(struct ice_hw *hw);48void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading);49void ice_destroy_all_ctrlq(struct ice_hw *hw);50int51ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,52 struct ice_rq_event_info *e, u16 *pending);53int54ice_get_link_status(struct ice_port_info *pi, bool *link_up);55int ice_update_link_info(struct ice_port_info *pi);56int57ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,58 enum ice_aq_res_access_type access, u32 timeout);59void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);60int61ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);62int63ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);64int ice_aq_alloc_free_res(struct ice_hw *hw,65 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,66 enum ice_adminq_opc opc);67bool ice_is_sbq_supported(struct ice_hw *hw);68struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw);69int70ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,71 struct ice_aq_desc *desc, void *buf, u16 buf_size,72 struct ice_sq_cd *cd);73void ice_clear_pxe_mode(struct ice_hw *hw);74int ice_get_caps(struct ice_hw *hw);75 76void ice_set_safe_mode_caps(struct ice_hw *hw);77 78int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,79 u32 rxq_index);80 81int82ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);83int84ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);85int86ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,87 struct ice_aqc_get_set_rss_keys *keys);88int89ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,90 struct ice_aqc_get_set_rss_keys *keys);91 92bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);93int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);94void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);95extern const struct ice_ctx_ele ice_tlan_ctx_info[];96int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,97 const struct ice_ctx_ele *ce_info);98 99extern struct mutex ice_global_cfg_lock_sw;100 101int102ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,103 void *buf, u16 buf_size, struct ice_sq_cd *cd);104int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);105 106int107ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,108 struct ice_sq_cd *cd);109int110ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,111 struct ice_sq_cd *cd);112int113ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,114 struct ice_aqc_get_phy_caps_data *caps,115 struct ice_sq_cd *cd);116bool ice_is_pf_c827(struct ice_hw *hw);117bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw);118bool ice_is_clock_mux_in_netlist(struct ice_hw *hw);119bool ice_is_cgu_in_netlist(struct ice_hw *hw);120bool ice_is_gps_in_netlist(struct ice_hw *hw);121int122ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,123 u8 *node_part_number, u16 *node_handle);124int125ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,126 enum ice_adminq_opc opc, struct ice_sq_cd *cd);127int128ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps);129void130ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,131 u16 link_speeds_bitmap);132int133ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,134 struct ice_sq_cd *cd);135bool ice_is_generic_mac(struct ice_hw *hw);136bool ice_is_e810(struct ice_hw *hw);137int ice_clear_pf_cfg(struct ice_hw *hw);138int139ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,140 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);141bool ice_fw_supports_link_override(struct ice_hw *hw);142int143ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,144 struct ice_port_info *pi);145bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);146int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,147 u8 serdes_num, int *output);148int149ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,150 enum ice_fec_stats_types fec_type, u32 *output);151 152enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);153enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);154int155ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,156 bool ena_auto_link_update);157int158ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,159 enum ice_fc_mode req_mode);160bool161ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,162 struct ice_aqc_set_phy_cfg_data *cfg);163void164ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,165 struct ice_aqc_get_phy_caps_data *caps,166 struct ice_aqc_set_phy_cfg_data *cfg);167int168ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,169 enum ice_fec_mode fec);170int171ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,172 struct ice_sq_cd *cd);173int174ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);175int176ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,177 struct ice_link_status *link, struct ice_sq_cd *cd);178int179ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,180 struct ice_sq_cd *cd);181int182ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);183 184int185ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,186 struct ice_sq_cd *cd);187int188ice_aq_get_port_options(struct ice_hw *hw,189 struct ice_aqc_get_port_options_elem *options,190 u8 *option_count, u8 lport, bool lport_valid,191 u8 *active_option_idx, bool *active_option_valid,192 u8 *pending_option_idx, bool *pending_option_valid);193int194ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,195 u8 new_option);196int197ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,198 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,199 bool write, struct ice_sq_cd *cd);200u32 ice_get_link_speed(u16 index);201 202int203ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,204 u16 *max_rdmaqs);205int206ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,207 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid);208int209ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,210 u16 *q_id);211int212ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,213 u16 *q_handle, u16 *q_ids, u32 *q_teids,214 enum ice_disq_rst_src rst_src, u16 vmvf_num,215 struct ice_sq_cd *cd);216int217ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,218 u16 *max_lanqs);219int220ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,221 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,222 struct ice_sq_cd *cd);223int224ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,225 u16 buf_size, u16 num_qs, u8 oldport, u8 newport,226 struct ice_sq_cd *cd);227int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);228void ice_replay_post(struct ice_hw *hw);229struct ice_q_ctx *230ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);231int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag);232int233ice_aq_get_cgu_abilities(struct ice_hw *hw,234 struct ice_aqc_get_cgu_abilities *abilities);235int236ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,237 u32 freq, s32 phase_delay);238int239ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,240 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay);241int242ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,243 u8 src_sel, u32 freq, s32 phase_delay);244int245ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,246 u8 *src_sel, u32 *freq, u32 *src_freq);247int248ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,249 u8 *dpll_state, u8 *config, s64 *phase_offset,250 u8 *eec_mode);251int252ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,253 u8 config, u8 eec_mode);254int255ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,256 u8 ref_priority);257int258ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,259 u8 *ref_prio);260int261ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,262 u32 *cgu_fw_ver);263 264int265ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,266 u32 *freq);267int268ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,269 u8 *flags, u16 *node_handle);270int ice_aq_get_sensor_reading(struct ice_hw *hw,271 struct ice_aqc_get_sensor_reading_resp *data);272void273ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,274 u64 *prev_stat, u64 *cur_stat);275void276ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,277 u64 *prev_stat, u64 *cur_stat);278bool ice_is_e810t(struct ice_hw *hw);279bool ice_is_e822(struct ice_hw *hw);280bool ice_is_e823(struct ice_hw *hw);281bool ice_is_e825c(struct ice_hw *hw);282int283ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,284 struct ice_aqc_txsched_elem_data *buf);285int286ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,287 struct ice_sq_cd *cd);288int289ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,290 bool *value, struct ice_sq_cd *cd);291bool ice_is_100m_speed_supported(struct ice_hw *hw);292u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high);293int294ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,295 struct ice_sq_cd *cd);296bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);297int298ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);299int ice_lldp_execute_pending_mib(struct ice_hw *hw);300int301ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,302 u16 bus_addr, __le16 addr, u8 params, u8 *data,303 struct ice_sq_cd *cd);304int305ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,306 u16 bus_addr, __le16 addr, u8 params, const u8 *data,307 struct ice_sq_cd *cd);308bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);309#endif /* _ICE_COMMON_H_ */310